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schoeffelbe82781/signal_processing_vorlage
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signal_processing_vorlage/hardware/signal_processing
History
Bernhard Schoeffel 445805e5c0 merge upstream
2025-08-05 18:52:41 +00:00
..
.sine.vhd.swo
Added Rand Software, started Rand Hardware, Fixed error in Task
2024-11-27 11:28:35 +01:00
add.vhd
Implemented Task Add in c an vhdl. Still testing
2024-11-13 09:58:47 +01:00
crc.vhd
Initial commit
2023-10-31 07:47:27 +01:00
fft.vhd
New FFT.vhd Template and Fix FFT TB (expected values)
2025-05-30 11:33:35 +02:00
rand.vhd
Finished Task Rand in vhdl
2024-12-04 09:37:28 +01:00
signal_processing.vhd
Initial commit
2023-10-31 07:47:27 +01:00
sine.vhd
Finished VHDL for Sine Task
2024-11-20 10:02:38 +01:00
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