signal_processing_vorlage/hardware/system/hardware_timestamp.cmp.vhd

entity timer is
    port (
        clk : in std_logic;
        reset : in std_logic;

        address : in std_logic_vector( 3 downto 0 );
        read : in std_logic;
        readdata : out std_logic_vector( 31 downto 0 );
        write : in std_logic;
        writedata : in std_logic_vector( 31 downto 0 )
    );
end entity timer;