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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
-
- library work;
- use work.reg32.all;
- use work.task.all;
-
- entity rand is
- port (
- clk : in std_logic;
- reset : in std_logic;
-
- task_start : in std_logic;
- task_state : out work.task.State;
- seed : in work.reg32.word;
-
- signal_write : out std_logic;
- signal_writedata : out std_logic_vector( 31 downto 0 )
- );
- end entity rand;
-
- architecture rtl of rand is
-
- signal current_task_state : work.task.State;
- signal next_task_state : work.task.State;
- signal index : integer range 0 to work.task.STREAM_LEN;
-
- type CalcState is (
- CALC_IDLE,
- CALC_WRITE
- );
- signal Calc_State : CalcState;
-
- signal lsfr : SIGNED( 31 downto 0 );
- signal lsfr_std_logic : std_logic_vector( 31 downto 0 );
- signal POLYNOM : std_logic_vector (31 downto 0);
-
- signal lsfr_dump : SIGNED( 31 downto 0 );
-
-
- begin
- task_state_transitions : process ( current_task_state, task_start, index ) is
- begin
- next_task_state <= current_task_state;
- case current_task_state is
- when work.task.TASK_IDLE =>
- if ( task_start = '1' ) then
- next_task_state <= work.task.TASK_RUNNING;
- end if;
- when work.task.TASK_RUNNING =>
- if ( index = work.task.STREAM_LEN - 1 ) then
- next_task_state <= work.task.TASK_DONE;
- end if;
- when work.task.TASK_DONE =>
- if ( task_start = '1' ) then
- next_task_state <= work.task.TASK_RUNNING;
- end if;
- end case;
- end process task_state_transitions;
-
- sync : process ( clk, reset ) is
- begin
- if ( reset = '1' ) then
- current_task_state <= work.task.TASK_IDLE;
- Calc_State <= CALC_IDLE;
- lsfr <= SIGNED(seed);
- lsfr_std_logic <= seed;
- POLYNOM <= (others => '0');
- POLYNOM(31) <= '1';
- POLYNOM(21) <= '1';
- POLYNOM(1) <= '1';
- POLYNOM(0) <= '1';
- index <= 0;
-
- elsif ( rising_edge( clk ) ) then
- current_task_state <= next_task_state;
- case next_task_state is
- when work.task.TASK_IDLE =>
- index <= 0;
- lsfr <= SIGNED(seed);
- signal_write <= '0';
-
- when work.task.TASK_RUNNING =>
- case Calc_State is
- when CALC_IDLE =>
- signal_write <= '0';
- lsfr_std_logic <= STD_LOGIC_VECTOR(lsfr);
- if(lsfr_std_logic(0) = '1') then
- lsfr <= SIGNED(lsfr_std_logic srl 1);
- lsfr <= SIGNED(lsfr_std_logic XOR POLYNOM);
- else
- lsfr <= SIGNED(lsfr_std_logic srl 1);
- end if;
- lsfr <= SIGNED(lsfr_std_logic);
- lsfr_dump <= lsfr;
-
- if(lsfr_std_logic(30) = '1') then
- lsfr <= lsfr(31 downto 31) & "1000000" & lsfr(23 downto 0);
- else
- lsfr <= lsfr(31 downto 31) & "011111" & lsfr(24 downto 0);
- end if;
- Calc_State <= CALC_WRITE;
- when CALC_WRITE =>
- signal_write <= '1';
- index <= index + 1;
- Calc_State <= CALC_IDLE;
- end case;
-
- when work.task.TASK_DONE =>
- index <= 0;
- signal_write <= '0';
- end case;
- end if;
- end process sync;
-
- task_state <= current_task_state;
- signal_writedata <= STD_LOGIC_VECTOR(lsfr);
-
- end architecture rtl;
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