90 lines
2.7 KiB
VHDL
90 lines
2.7 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.avalon_slave.all;
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entity avalon_slave_transitions is
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generic (
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REG_COUNT : natural;
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REG_ACCESS_TYPES : work.reg32.AccessArray
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);
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port (
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address : in std_logic_vector( 3 downto 0 );
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read : in std_logic;
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write : in std_logic;
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current_state : in work.avalon_slave.State;
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next_state : out work.avalon_slave.State;
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reg_index : out integer range 0 to REG_COUNT - 1
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);
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end entity avalon_slave_transitions;
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architecture rtl of avalon_slave_transitions is
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signal is_access : boolean;
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signal is_read : boolean;
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signal is_write : boolean;
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signal address_index : integer range 0 to 2 ** address'high - 1;
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signal is_valid_reg_index : boolean;
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signal access_type : work.reg32.AccessType;
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signal is_valid_access : boolean;
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signal is_valid_access_type : boolean;
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signal index : integer range 0 to REG_COUNT - 1;
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begin
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c_is_access: is_access <= ( read or write ) = '1';
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c_is_read: is_read <= read = '1';
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c_is_write: is_write <= write = '1' and not is_read;
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c_address_index: address_index <= to_integer( unsigned( address ) );
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c_is_valid_reg_index: is_valid_reg_index <= address_index <= ( REG_COUNT - 1 );
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c_index: index <= address_index when is_valid_reg_index else 0;
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c_reg_index: reg_index <= index;
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c_access_type: access_type <= REG_ACCESS_TYPES( index );
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c_is_valid_access_type: is_valid_access_type <= true when
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( is_read and work.reg32.allows_read( access_type ) ) or
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( is_write and work.reg32.allows_write( access_type ) )
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else false;
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c_is_valid_access: is_valid_access <= is_access and is_valid_reg_index and
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is_valid_access_type;
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transition : process( all ) is
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begin
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case current_state is
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when SLAVE_IDLE =>
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if ( is_valid_access and is_read ) then
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next_state <= SLAVE_READ;
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elsif ( is_valid_access and is_write ) then
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next_state <= SLAVE_WRITE;
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else
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next_state <= SLAVE_IDLE;
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end if;
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when SLAVE_READ =>
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next_state <= SLAVE_READ_DATA;
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when SLAVE_READ_DATA =>
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if ( is_valid_access and is_read ) then
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next_state <= SLAVE_READ;
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elsif ( is_valid_access and is_write ) then
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next_state <= SLAVE_WRITE;
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else
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next_state <= SLAVE_IDLE;
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end if;
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when SLAVE_WRITE =>
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next_state <= SLAVE_IDLE;
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end case;
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end process transition;
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end architecture rtl;
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