181 lines
6.6 KiB
VHDL
181 lines
6.6 KiB
VHDL
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------------------------------------------------------------------------
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-- fft_magnitude_calc
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--
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-- calculation of FFT magnitude sqrt(real_part²+im_part²)
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-- Inputs:
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-- input_re in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K)
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-- input_im in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K)
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-- input_valid: high = inputs are valid for data processing
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-- Outputs
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-- output_magnitude: Fixpoint 0.5=0x40000000 (always positive)
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-- output_valid: high = magnitude data is valid
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.task.all;
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use work.float.all;
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entity fft_magnitude_calc is
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port (
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clk : in std_logic;
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reset : in std_logic;
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input_valid: in std_logic;
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input_re : in std_logic_vector( 31 downto 0 ); -- in Fixpoint
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input_im : in std_logic_vector( 31 downto 0 ); -- in Fixpoint
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output_valid : out std_logic;
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output_magnitude : out std_logic_vector( 31 downto 0 )
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);
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end entity fft_magnitude_calc;
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architecture rtl of fft_magnitude_calc is
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subtype Word_64 is std_logic_vector( 63 downto 0 );
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type Array_64 is array ( natural range <> ) of Word_64;
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subtype Word_32 is std_logic_vector( 31 downto 0 );
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type Array_32 is array ( natural range <> ) of Word_32;
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subtype Word_16 is std_logic_vector( 15 downto 0 );
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type Array_16 is array ( natural range <> ) of Word_16;
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signal input_valid_stage1 : std_logic;
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signal re_multiply_re_stage1 : signed(63 downto 0);
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signal im_multiply_re_stage1 : signed(63 downto 0);
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signal input_valid_stage2 : std_logic;
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signal re2_add_im2 : signed(63 downto 0);
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signal input_valid_stage3 : std_logic;
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signal input_sqrt : Array_32( 0 to 16 );
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signal output_sqrt: Array_16( 0 to 16 );
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signal output_delay_sqrt: std_logic_vector(15 downto 0);
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signal data_memory : work.reg32.RegArray( 0 to 1023 );
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signal index_sqrt : integer range 0 to 16;
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begin
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-- calculation of real_part² and im_part²
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p_pow2_stage1: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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input_valid_stage1 <= '0';
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re_multiply_re_stage1 <= (others => '0');
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im_multiply_re_stage1 <= (others => '0');
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elsif ( rising_edge( clk ) ) then
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input_valid_stage1 <= input_valid;
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if input_valid = '1' then
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re_multiply_re_stage1 <= signed(input_re) * signed(input_re);
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im_multiply_re_stage1 <= signed(input_im) * signed(input_im);
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end if;
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end if;
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end process p_pow2_stage1;
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-- calculation of real_part²*+im_part²
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p_add_stage2: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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input_valid_stage2 <= '0';
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re2_add_im2 <= (others => '0');
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elsif ( rising_edge( clk ) ) then
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input_valid_stage2 <= input_valid_stage1;
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re2_add_im2 <= re_multiply_re_stage1 + im_multiply_re_stage1;
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end if;
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end process p_add_stage2;
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-- calculation of sqrt (one sqrt caluation needs 16 clks with G_DATA_W => 32
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-- for continous stream 17 sqrt instances are needed
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p_sqrt_stage3: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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input_valid_stage3 <= '0';
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index_sqrt <= 0;
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input_sqrt(0) <= (others => '0');
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input_sqrt(1) <= (others => '0');
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input_sqrt(2) <= (others => '0');
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input_sqrt(3) <= (others => '0');
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input_sqrt(4) <= (others => '0');
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input_sqrt(5) <= (others => '0');
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input_sqrt(6) <= (others => '0');
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input_sqrt(7) <= (others => '0');
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input_sqrt(8) <= (others => '0');
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input_sqrt(9) <= (others => '0');
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input_sqrt(10) <= (others => '0');
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input_sqrt(11) <= (others => '0');
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input_sqrt(12) <= (others => '0');
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input_sqrt(13) <= (others => '0');
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input_sqrt(14) <= (others => '0');
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input_sqrt(15) <= (others => '0');
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input_sqrt(16) <= (others => '0');
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elsif ( rising_edge( clk ) ) then
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input_valid_stage3 <= input_valid_stage2;
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if input_valid_stage2 = '1' then
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if index_sqrt = 16 then
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index_sqrt <= 0;
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else
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index_sqrt <= index_sqrt +1;
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end if;
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end if;
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case index_sqrt is
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when 16 => input_sqrt(16) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 15 => input_sqrt(15) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 14 => input_sqrt(14) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 13 => input_sqrt(13) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 12 => input_sqrt(12) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 11 => input_sqrt(11) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 10 => input_sqrt(10) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 9 => input_sqrt(9) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 8 => input_sqrt(8) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 7 => input_sqrt(7) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 6 => input_sqrt(6) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 5 => input_sqrt(5) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 4 => input_sqrt(4) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 3 => input_sqrt(3) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 2 => input_sqrt(2) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 1 => input_sqrt(1) <= std_logic_vector(re2_add_im2(63 downto 32));
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when 0 => input_sqrt(0) <= std_logic_vector(re2_add_im2(63 downto 32));
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when others => null;
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end case;
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end if;
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end process p_sqrt_stage3;
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-- generate sqrt instances for continous data stream
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gen_sqrt_array: for i in 0 to 16 generate
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sqrt_module : entity work.squareRoot_pipe
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generic map (
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G_DATA_W => 32
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)
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port map (
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clk => clk,
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rst => reset,
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iv_data => input_sqrt(i),
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ov_res => output_sqrt(i)
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);
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end generate gen_sqrt_array;
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-- output assignment
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p_output_stage4: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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output_valid <= '0';
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output_magnitude <= (others => '0');
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output_delay_sqrt <= (others => '0');
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elsif ( rising_edge( clk ) ) then
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output_delay_sqrt <= output_delay_sqrt(14 downto 0) & input_valid_stage3;
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output_valid <= output_delay_sqrt(15);
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output_magnitude <= std_logic_vector(output_sqrt(index_sqrt)) & x"0000";
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end if;
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end process p_output_stage4;
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end architecture rtl;
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