# External clock clk_50 has a frequency of 50 MHz create_clock -period 20 [get_ports clk_input] derive_pll_clocks set clk_main u_pll_200|pll_200|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk # Input delays for singals in 50 MHz domain set_input_delay \ -clock { clk_input } \ 2 \ [get_ports {reset_n}] # Input delays for singals in 200 MHz domain set_false_path \ -from \ [get_ports {key_start}] # Output delays for singals in 200 MHz domain set_false_path \ -to \ [get_ports { \ leds[0] \ leds[1] \ leds[2] \ leds[3] \ leds[4] \ leds[5] \ leds[6] \ leds[7] \ }]