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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.03.2022 20:07:22
-- Design Name: 
-- Module Name: pwm_test_db - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pwm_test_db is
--  Port ( );
end pwm_test_db;

architecture Behavioral of pwm_test_db is

component pwm_test is
    Port ( clk : in STD_LOGIC;
           led : out STD_LOGIC);
end component;

signal clk, led : std_logic := '0';

begin

uut: pwm_test PORT MAP (
    clk => clk,
    led => led
);

--generate clock
clk <= not clk after 10 ns;


process 
begin


    wait;

end process;


end Behavioral;
