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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.03.2022 19:12:30
-- Design Name: 
-- Module Name: pwm_test - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pwm_test is
    Port ( clk : in STD_LOGIC;
           led : out STD_LOGIC);
end pwm_test;

architecture Behavioral of pwm_test is

constant pwm_duty : integer := 50;  --Duty 
constant counter_max : integer := 125000000; --100000000 geht, 125000000 geht nicht ?!


signal count : integer := 0;

begin

process(clk)
    begin
        if rising_edge(clk) then
            count <= count +1;
        end if;
        
        if(count >= counter_max)then
                count <= 0;
                led <= '0';
        elsif (count >= counter_max/100*pwm_duty) then
                led <= '1';
        end if;
   
end process;

--test
    
end Behavioral;
