diff --git a/Bibliotheken/digilent-xdc-master/Arty-A7-100-Master.xdc b/Bibliotheken/digilent-xdc-master/Arty-A7-100-Master.xdc
new file mode 100644
index 0000000..37d93e1
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Arty-A7-100-Master.xdc
@@ -0,0 +1,216 @@
+## This file is a general .xdc for the Arty A7-100 Rev. D
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
+
+## Switches
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
+#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
+#set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
+#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
+#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
+#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
+#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
+#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
+#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
+#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
+
+## LEDs
+#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
+#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
+#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
+
+## Pmod Header JC
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
+
+## Pmod Header JD
+#set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
+
+## USB-UART Interface
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io1  }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_io2  }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io3  }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { ck_io4  }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io5  }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io6  }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io7  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ck_io8  }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ck_io9  }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
+
+## ChipKit Inner Digital Header
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
+#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { vaux4_n  }]; #IO_L1N_T0_AD4N_35 	   Sch=ck_an_n[0] ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { vaux4_p  }]; #IO_L1P_T0_AD4P_35 	   Sch=ck_an_p[0] ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { vaux5_n  }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { vaux5_p  }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_n  }]; #IO_L7N_T1_AD6N_35 	   Sch=ck_an_n[2] ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_p  }]; #IO_L7P_T1_AD6P_35 	   Sch=ck_an_p[2] ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_n  }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_p  }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35   Sch=ck_an_n[4] ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35   Sch=ck_an_p[4] ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_15 	   Sch=ck_an_n[5] ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_15 	   Sch=ck_an_p[5] ChipKit pin=A5
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
+
+## ChipKit SPI
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
+
+## Misc. ChipKit Ports
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
+
+## SMSC Ethernet PHY
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
+
+## Quad SPI Flash
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+## Power Measurements 
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
diff --git a/Bibliotheken/digilent-xdc-master/Arty-A7-35-Master.xdc b/Bibliotheken/digilent-xdc-master/Arty-A7-35-Master.xdc
new file mode 100644
index 0000000..b9a906d
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Arty-A7-35-Master.xdc
@@ -0,0 +1,216 @@
+## This file is a general .xdc for the Arty A7-35 Rev. D
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
+
+## Switches
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
+#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
+#set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
+#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
+#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
+#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
+#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
+#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
+#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
+#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
+
+## LEDs
+#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
+#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
+#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
+
+## Pmod Header JC
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
+
+## Pmod Header JD
+#set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
+
+## USB-UART Interface
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L16P_T2_CSI_B_14          Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io1  }]; #IO_L18P_T2_A12_D28_14        Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_io2  }]; #IO_L8N_T1_D12_14             Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io3  }]; #IO_L19P_T3_A10_D26_14        Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { ck_io4  }]; #IO_L5P_T0_D06_14             Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io5  }]; #IO_L14P_T2_SRCC_14           Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io6  }]; #IO_L14N_T2_SRCC_14           Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io7  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ck_io8  }]; #IO_L11P_T1_SRCC_14           Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ck_io9  }]; #IO_L10P_T1_D14_14            Sch=ck_io[9]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14        Sch=ck_io[10]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14        Sch=ck_io[11]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14           Sch=ck_io[12]
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14           Sch=ck_io[13]
+
+## ChipKit Inner Digital Header
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 	Sch=ck_io[26]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 		Sch=ck_io[27]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 		Sch=ck_io[28]
+#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 		 			Sch=ck_io[29]
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14  		 			Sch=ck_io[30]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 			Sch=ck_io[31]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 			Sch=ck_io[32]
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 			Sch=ck_io[33]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 	Sch=ck_io[34]
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 			Sch=ck_io[35]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 			Sch=ck_io[36]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 		Sch=ck_io[37]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 			Sch=ck_io[38]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 			Sch=ck_io[39]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 		Sch=ck_io[40]
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 			Sch=ck_io[41]
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { vaux4_n  }]; #IO_L1N_T0_AD4N_35 		Sch=ck_an_n[0]	ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { vaux4_p  }]; #IO_L1P_T0_AD4P_35 		Sch=ck_an_p[0]	ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { vaux5_n  }]; #IO_L3N_T0_DQS_AD5N_35 	Sch=ck_an_n[1]	ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { vaux5_p  }]; #IO_L3P_T0_DQS_AD5P_35 	Sch=ck_an_p[1]	ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_n  }]; #IO_L7N_T1_AD6N_35 		Sch=ck_an_n[2]	ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_p  }]; #IO_L7P_T1_AD6P_35 		Sch=ck_an_p[2]	ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_n  }]; #IO_L9N_T1_DQS_AD7N_35 	Sch=ck_an_n[3]	ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_p  }]; #IO_L9P_T1_DQS_AD7P_35 	Sch=ck_an_p[3]	ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 	Sch=ck_an_n[4]	ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 	Sch=ck_an_p[4]	ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_15 		Sch=ck_an_n[5]	ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_15 		Sch=ck_an_p[5]	ChipKit pin=A5
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: the following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35           	Sch=ck_a[0]		ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35      	Sch=ck_a[1]		ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35      	Sch=ck_a[2]		ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35      	Sch=ck_a[3]		ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 	Sch=ck_a[4]		ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35	Sch=ck_a[5]		ChipKit pin=A5
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit Analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35	Sch=ad_p[12]	ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35	Sch=ad_n[12]	ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35	Sch=ad_p[13]	ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35	Sch=ad_n[13]	ChipKit pin=A9
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35	Sch=ad_p[14]	ChipKit pin=A10
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35	Sch=ad_n[14]	ChipKit pin=A11
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: the following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { ck_io20 }]; #IO_L2P_T0_AD12P_35	Sch=ad_p[12]	ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { ck_io21 }]; #IO_L2N_T0_AD12N_35	Sch=ad_n[12]	ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { ck_io22 }]; #IO_L5P_T0_AD13P_35	Sch=ad_p[13]	ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { ck_io23 }]; #IO_L5N_T0_AD13N_35	Sch=ad_n[13]	ChipKit pin=A9
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { ck_io24 }]; #IO_L8P_T1_AD14P_35	Sch=ad_p[14]	ChipKit pin=A10
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { ck_io25 }]; #IO_L8N_T1_AD14N_35	Sch=ad_n[14]	ChipKit pin=A11
+
+## ChipKit SPI
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
+
+## Misc. ChipKit Ports
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
+
+## SMSC Ethernet PHY
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
+
+## Quad SPI Flash
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+## Power Measurements 
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
diff --git a/Bibliotheken/digilent-xdc-master/Arty-Master.xdc b/Bibliotheken/digilent-xdc-master/Arty-Master.xdc
new file mode 100644
index 0000000..fe6829d
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Arty-Master.xdc
@@ -0,0 +1,216 @@
+## This file is a general .xdc for the ARTY Rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signal
+#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
+
+## Switches
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
+#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
+#set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
+#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
+#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
+#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
+#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
+#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
+#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
+#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
+
+## LEDs
+#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
+#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
+#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
+
+## Pmod Header JC
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
+
+## Pmod Header JD
+#set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
+
+## USB-UART Interface
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L16P_T2_CSI_B_14          Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io1  }]; #IO_L18P_T2_A12_D28_14        Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_io2  }]; #IO_L8N_T1_D12_14             Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io3  }]; #IO_L19P_T3_A10_D26_14        Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { ck_io4  }]; #IO_L5P_T0_D06_14             Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io5  }]; #IO_L14P_T2_SRCC_14           Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io6  }]; #IO_L14N_T2_SRCC_14           Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io7  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ck_io8  }]; #IO_L11P_T1_SRCC_14           Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ck_io9  }]; #IO_L10P_T1_D14_14            Sch=ck_io[9]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14        Sch=ck_io[10]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14        Sch=ck_io[11]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14           Sch=ck_io[12]
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14           Sch=ck_io[13]
+
+## ChipKit Inner Digital Header
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
+#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { vaux4_n  }]; #IO_L1N_T0_AD4N_35     Sch=ck_an_n[0] ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { vaux4_p  }]; #IO_L1P_T0_AD4P_35     Sch=ck_an_p[0] ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { vaux5_n  }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { vaux5_p  }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_n  }]; #IO_L7N_T1_AD6N_35     Sch=ck_an_n[2] ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_p  }]; #IO_L7P_T1_AD6P_35     Sch=ck_an_p[2] ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_n  }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_p  }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35   Sch=ck_an_n[4] ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35   Sch=ck_an_p[4] ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_15     Sch=ck_an_n[5] ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_15     Sch=ck_an_p[5] ChipKit pin=A5
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35            Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35       Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35       Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35       Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35  Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
+
+## ChipKit SPI
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
+
+## Misc. ChipKit Ports
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
+
+## SMSC Ethernet PHY
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
+
+## Quad SPI Flash
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+## Power Measurements 
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
diff --git a/Bibliotheken/digilent-xdc-master/Arty-S7-25-Master.xdc b/Bibliotheken/digilent-xdc-master/Arty-S7-25-Master.xdc
new file mode 100644
index 0000000..27e0b18
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Arty-S7-25-Master.xdc
@@ -0,0 +1,195 @@
+## This file is a general .xdc for the Arty S7-25 Rev. E
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signals
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { CLK12MHZ }]; #IO_L13P_T2_MRCC_15 Sch=uclk
+#create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { CLK12MHZ }];
+#set_property -dict { PACKAGE_PIN R2    IOSTANDARD SSTL135 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
+#create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000}  [get_ports { CLK100MHZ }];
+
+## Switches
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN M5    IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L14N_T2_SRCC_15 Sch=led0_g
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L13N_T2_MRCC_15 Sch=led0_b
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L16P_T2_A28_15 Sch=led1_g
+#set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L15P_T2_DQS_15 Sch=led1_b
+
+## LEDs
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3]
+#set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4]
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN H13   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L4P_T0_D04_14 Sch=ja_p[1]
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja_n[1]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L5P_T0_D06_14 Sch=ja_p[2]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L5N_T0_D07_14 Sch=ja_n[2]
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L7P_T1_D09_14 Sch=ja_p[3]
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L7N_T1_D10_14 Sch=ja_n[3]
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja_p[4]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja_n[4]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L9P_T1_DQS_14 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_D14_14 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L10N_T1_D15_14 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11P_T1_SRCC_14 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L11N_T1_SRCC_14 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L12P_T1_MRCC_14 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L12N_T1_MRCC_14 Sch=jb_n[4]
+
+## Pmod Header JC
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
+#set_property -dict { PACKAGE_PIN P13   IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
+
+## Pmod Header JD
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
+
+## USB-UART Interface
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_0_14 Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN N13   IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[9]
+
+## ChipKit SPI Header
+## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss   }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck  }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck
+
+## ChipKit Inner Digital Header
+## NOTE: these pins are shared with PMOD Headers JC and JD and cannot be used at the same time as the applicable PMOD interface(s)
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L24P_T3_A01_D17_14        Sch=jd10/ck_io[26]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L23N_T3_A02_D18_14        Sch=jd9/ck_io[27]
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L23P_T3_A03_D19_14        Sch=jd8/ck_io[28]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L22N_T3_A04_D20_14        Sch=jd7/ck_io[29]
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A05_D21_14        Sch=jd4/ck_io[30]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L21N_T3_DQS_A06_D22_14    Sch=jd3/ck_io[31]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L21P_T3_DQS_14            Sch=jd2/ck_io[32]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_A07_D23_14        Sch=jd1/ck_io[33]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L20P_T3_A08_D24_14        Sch=jc10/ck_io[34]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19N_T3_A09_D25_VREF_14   Sch=jc9/ck_io[35]
+#set_property -dict { PACKAGE_PIN P13   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L19P_T3_A10_D26_14        Sch=jc8/ck_io[36]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L16P_T2_CSI_B_14          Sch=jc7/ck_io[37]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L15P_T2_DQS_RDWR_B_14     Sch=jc3/ck_io[39]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L18N_T2_A11_D27_14        Sch=jc2/ck_io[40]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18P_T2_A12_D28_14        Sch=jc1/ck_io[41]
+
+## Dedicated Analog Inputs
+#set_property -dict { PACKAGE_PIN J10   } [get_ports { vp_in }]; #IO_L1P_T0_AD4P_35 Sch=v_p
+#set_property -dict { PACKAGE_PIN K9    } [get_ports { vn_in }]; #IO_L1N_T0_AD4N_35 Sch=v_n
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_15     Sch=ck_an_p[0]   ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_15     Sch=ck_an_n[0]   ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p  }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[1]   ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n  }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[1]   ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN E12   IOSTANDARD LVCMOS33 } [get_ports { vaux2_p  }]; #IO_L5P_T0_AD9P_15     Sch=ck_an_p[2]   ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { vaux2_n  }]; #IO_L5N_T0_AD9N_15     Sch=ck_an_n[2]   ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L7P_T1_AD2P_15     Sch=ck_an_p[3]   ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L7N_T1_AD2N_15     Sch=ck_an_n[3]   ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { vaux3_p  }]; #IO_L8P_T1_AD10P_15    Sch=ck_an_p[4]   ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { vaux3_n  }]; #IO_L8N_T1_AD10N_15    Sch=ck_an_n[4]   ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { vaux4_p  }]; #IO_L10P_T1_AD11P_15   Sch=ck_an_p[5]   ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux4_n  }]; #IO_L10N_T1_AD11N_15   Sch=ck_an_n[5]   ChipKit pin=A5
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_15            Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_15       Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_15       Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN C13   IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_15       Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_15  Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_15 Sch=ck_a[5]
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p  }]; #IO_L2P_T0_AD8P_15     Sch=ad_p[8]   ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n  }]; #IO_L2N_T0_AD8N_15     Sch=ad_n[8]   ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3]   ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3]   ChipKit pin=A9
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L2P_T0_AD8P_15     Sch=ad_p[8]
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L2N_T0_AD8N_15     Sch=ad_n[8]
+#set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3]
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3]
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L12P_T1_MRCC_15    Sch=ck_a10_r   (Cannot be used as an analog input)
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L12N_T1_MRCC_15    Sch=ck_a11_r   (Cannot be used as an analog input)
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda
+
+## Misc. ChipKit Ports
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa
+#set_property -dict { PACKAGE_PIN C18   IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L11N_T1_SRCC_15
+
+## Quad SPI Flash
+## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+## Configuration options, can be used for all designs
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
+## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
+## and to be able to use this pin as an ordinary I/O the following property must
+## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
+## used the internal reference is set to half that value (i.e. 0.675v). Note that
+## this property must be set even if SW3 is not used in the design.
+set_property INTERNAL_VREF 0.675 [get_iobanks 34]
diff --git a/Bibliotheken/digilent-xdc-master/Arty-S7-50-Master.xdc b/Bibliotheken/digilent-xdc-master/Arty-S7-50-Master.xdc
new file mode 100644
index 0000000..3ea3818
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Arty-S7-50-Master.xdc
@@ -0,0 +1,195 @@
+## This file is a general .xdc for the Arty S7-50 Rev. E
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signals
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { CLK12MHZ }]; #IO_L13P_T2_MRCC_15 Sch=uclk
+#create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { CLK12MHZ }];
+#set_property -dict { PACKAGE_PIN R2    IOSTANDARD SSTL135 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
+#create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000}  [get_ports { CLK100MHZ }];
+
+## Switches
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN M5    IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L14N_T2_SRCC_15 Sch=led0_g
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L13N_T2_MRCC_15 Sch=led0_b
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L16P_T2_A28_15 Sch=led1_g
+#set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L15P_T2_DQS_15 Sch=led1_b
+
+## LEDs
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3]
+#set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4]
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN H13   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L4P_T0_D04_14 Sch=ja_p[1]
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja_n[1]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L5P_T0_D06_14 Sch=ja_p[2]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L5N_T0_D07_14 Sch=ja_n[2]
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L7P_T1_D09_14 Sch=ja_p[3]
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L7N_T1_D10_14 Sch=ja_n[3]
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja_p[4]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja_n[4]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L9P_T1_DQS_14 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_D14_14 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L10N_T1_D15_14 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11P_T1_SRCC_14 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L11N_T1_SRCC_14 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L12P_T1_MRCC_14 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L12N_T1_MRCC_14 Sch=jb_n[4]
+
+## Pmod Header JC
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
+#set_property -dict { PACKAGE_PIN P13   IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
+
+## Pmod Header JD
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
+
+## USB-UART Interface
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_0_14 Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN N13   IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L6N_T0_D08_VREF_14   Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L13P_T2_MRCC_14      Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L13N_T2_MRCC_14      Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14      Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14      Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L16N_T2_A15_D31_14   Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L17P_T2_A14_D30_14   Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L17N_T2_A13_D29_14   Sch=ck_io[9]
+
+## ChipKit SPI Header
+## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss   }]; #IO_L22P_T3_A17_15   Sch=ck_io10_ss
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15   Sch=ck_io11_mosi
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck  }]; #IO_L14P_T2_SRCC_15  Sch=ck_io13_sck
+
+## ChipKit Inner Digital Header
+## Note: these pins are shared with PMOD Headers JC and JD and cannot be used at the same time as the applicable PMOD interface(s)
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L24P_T3_A01_D17_14        Sch=jd10/ck_io[26]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L23N_T3_A02_D18_14        Sch=jd9/ck_io[27]
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L23P_T3_A03_D19_14        Sch=jd8/ck_io[28]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L22N_T3_A04_D20_14        Sch=jd7/ck_io[29]
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A05_D21_14        Sch=jd4/ck_io[30]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L21N_T3_DQS_A06_D22_14    Sch=jd3/ck_io[31]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L21P_T3_DQS_14            Sch=jd2/ck_io[32]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_A07_D23_14        Sch=jd1/ck_io[33]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L20P_T3_A08_D24_14        Sch=jc10/ck_io[34]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19N_T3_A09_D25_VREF_14   Sch=jc9/ck_io[35]
+#set_property -dict { PACKAGE_PIN P13   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L19P_T3_A10_D26_14        Sch=jc8/ck_io[36]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L16P_T2_CSI_B_14          Sch=jc7/ck_io[37]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L15P_T2_DQS_RDWR_B_14     Sch=jc3/ck_io[39]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L18N_T2_A11_D27_14        Sch=jc2/ck_io[40]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18P_T2_A12_D28_14        Sch=jc1/ck_io[41]
+
+## Dedicated Analog Inputs
+#set_property -dict { PACKAGE_PIN J10   } [get_ports { vp_in }]; #IO_L1P_T0_AD4P_35 Sch=v_p
+#set_property -dict { PACKAGE_PIN K9    } [get_ports { vn_in }]; #IO_L1N_T0_AD4N_35 Sch=v_n
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_15     Sch=ck_an_p[0]   ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_15     Sch=ck_an_n[0]   ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p  }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[1]   ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n  }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[1]   ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN E12   IOSTANDARD LVCMOS33 } [get_ports { vaux9_p  }]; #IO_L5P_T0_AD9P_15     Sch=ck_an_p[2]   ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { vaux9_n  }]; #IO_L5N_T0_AD9N_15     Sch=ck_an_n[2]   ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { vaux2_p  }]; #IO_L7P_T1_AD2P_15     Sch=ck_an_p[3]   ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { vaux2_n  }]; #IO_L7N_T1_AD2N_15     Sch=ck_an_n[3]   ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L8P_T1_AD10P_15    Sch=ck_an_p[4]   ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L8N_T1_AD10N_15    Sch=ck_an_n[4]   ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L10P_T1_AD11P_15   Sch=ck_an_p[5]   ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L10N_T1_AD11N_15   Sch=ck_an_n[5]   ChipKit pin=A5
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_15            Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_15       Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_15       Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN C13   IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_15       Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_15  Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_15 Sch=ck_a[5]
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15     Sch=ad_p[8]   ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15     Sch=ad_n[8]   ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3]   ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3]   ChipKit pin=A9
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L2P_T0_AD8P_15     Sch=ad_p[8]
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L2N_T0_AD8N_15     Sch=ad_n[8]
+#set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3]
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3]
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L12P_T1_MRCC_15    Sch=ck_a10_r   (Cannot be used as an analog input)
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L12N_T1_MRCC_15    Sch=ck_a11_r   (Cannot be used as an analog input)
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda
+
+## Misc. ChipKit Ports
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa
+#set_property -dict { PACKAGE_PIN C18   IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L11N_T1_SRCC_15
+
+## Quad SPI Flash
+## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+## Configuration options, can be used for all designs
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
+## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
+## and to be able to use this pin as an ordinary I/O the following property must
+## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
+## used the internal reference is set to half that value (i.e. 0.675v). Note that
+## this property must be set even if SW3 is not used in the design.
+set_property INTERNAL_VREF 0.675 [get_iobanks 34]
diff --git a/Bibliotheken/digilent-xdc-master/Arty-Z7-10-Master.xdc b/Bibliotheken/digilent-xdc-master/Arty-Z7-10-Master.xdc
new file mode 100644
index 0000000..c39b336
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Arty-Z7-10-Master.xdc
@@ -0,0 +1,154 @@
+## This file is a general .xdc for the ARTY Z7-10 Rev.B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signal
+#set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
+
+## Switches
+#set_property -dict { PACKAGE_PIN M20  IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=SW0
+#set_property -dict { PACKAGE_PIN M19  IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=SW1
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN L15    IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7P_35 Sch=LED4_B
+#set_property -dict { PACKAGE_PIN G17    IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=LED4_G
+#set_property -dict { PACKAGE_PIN N15    IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=LED4_R
+#set_property -dict { PACKAGE_PIN G14    IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=LED5_B
+#set_property -dict { PACKAGE_PIN L14    IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=LED5_G
+#set_property -dict { PACKAGE_PIN M15    IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=LED5_R
+
+## LEDs
+#set_property -dict { PACKAGE_PIN R14    IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=LED0
+#set_property -dict { PACKAGE_PIN P14    IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=LED1
+#set_property -dict { PACKAGE_PIN N16    IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=LED2
+#set_property -dict { PACKAGE_PIN M14    IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=LED3
+
+## Buttons
+#set_property -dict { PACKAGE_PIN D19    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=BTN0
+#set_property -dict { PACKAGE_PIN D20    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=BTN1
+#set_property -dict { PACKAGE_PIN L20    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=BTN2
+#set_property -dict { PACKAGE_PIN L19    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=BTN3
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P (Pin 1)
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N (Pin 2)
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P (Pin 3)
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N (Pin 4)
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P (Pin 7)
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N (Pin 8)
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P (Pin 9)
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N (Pin 10)
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L8P_T1_34 Sch=JB1_P (Pin 1)
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L8N_T1_34 Sch=JB1_N (Pin 2)
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L1P_T0_34 Sch=JB2_P (Pin 3)
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L1N_T0_34 Sch=JB2_N (Pin 4)
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L18P_T2_34 Sch=JB3_P (Pin 7)
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L18N_T2_34 Sch=JB3_N (Pin 8)
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jb_p[4] }]; #IO_L4P_T0_34 Sch=JB4_P (Pin 9)
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { jb_n[4] }]; #IO_L4N_T0_34 Sch=JB4_N (Pin 10)
+
+## Audio Out
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=AUD_PWM
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=AUD_SD
+
+## Crypto SDA 
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=CRYPTO_SDA
+
+## HDMI RX Signals
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=HDMI_RX_HPD
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA
+
+## HDMI TX Signals
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=HDMI_TX_HDPN
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=HDMI_TX_SCL
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=HDMI_TX_SDA
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L5P_T0_34            Sch=CK_IO0
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { ck_io1  }]; #IO_L2N_T0_34            Sch=CK_IO1
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { ck_io2  }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=CK_IO2
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { ck_io3  }]; #IO_L3N_T0_DQS_34        Sch=CK_IO3
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io4  }]; #IO_L10P_T1_34           Sch=CK_IO4
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io5  }]; #IO_L5N_T0_34            Sch=CK_IO5
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io6  }]; #IO_L19P_T3_34           Sch=CK_IO6
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io7  }]; #IO_L9N_T1_DQS_34        Sch=CK_IO7
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io8  }]; #IO_L21P_T3_DQS_34       Sch=CK_IO8
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { ck_io9  }]; #IO_L21N_T3_DQS_34       Sch=CK_IO9
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L9P_T1_DQS_34        Sch=CK_IO10
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L19N_T3_VREF_34      Sch=CK_IO11
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L23N_T3_34           Sch=CK_IO12
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L23P_T3_34           Sch=CK_IO13
+
+## ChipKit Inner Digital Header
+## Not Connected on Z7-10 Variant
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports should be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) with the XADC IP core.
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n  }]; #IO_L3N_T0_DQS_AD1N_35 Sch=CK_AN0_N   ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p  }]; #IO_L3P_T0_DQS_AD1P_35 Sch=CK_AN0_P   ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { vaux9_n  }]; #IO_L5N_T0_AD9N_35     Sch=CK_AN1_N   ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { vaux9_p  }]; #IO_L5P_T0_AD9P_35     Sch=CK_AN1_P   ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_n  }]; #IO_L20N_T3_AD6N_35    Sch=CK_AN2_N   ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_p  }]; #IO_L20P_T3_AD6P_35    Sch=CK_AN2_P   ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35   Sch=CK_AN3_N   ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35   Sch=CK_AN3_P   ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_n  }]; #IO_L17N_T2_AD5N_35    Sch=CK_AN4_N   ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_p  }]; #IO_L17P_T2_AD5P_35    Sch=CK_AN4_P   ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35   Sch=CK_AN5_N   ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35   Sch=CK_AN5_P   ChipKit pin=A5
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P   ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N   ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_35       Sch=AD0_P    ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_35       Sch=AD0_N    ChipKit pin=A9
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p  }]; #IO_L2P_T0_AD8P_35       Sch=AD8_P    ChipKit pin=A10
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n  }]; #IO_L2N_T0_AD8N_35       Sch=AD8_N    ChipKit pin=A11
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L1P_T0_AD0P_35       Sch=AD0_P
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L1N_T0_AD0N_35       Sch=AD0_N
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35       Sch=AD8_P
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35       Sch=AD8_N
+
+## ChipKit SPI
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=CK_MISO
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34  Sch=CK_MISO
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { ck_sck  }]; #IO_L19P_T3_35 Sch=CK_SCK
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { ck_ss   }]; #IO_L6P_T0_35  Sch=CK_SS
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA
+
+## Not Connected Pins
+#set_property PACKAGE_PIN F17 [get_ports {netic20_f17}]; #IO_L6N_T0_VREF_35
+#set_property PACKAGE_PIN G18 [get_ports {netic20_g18}]; #IO_L16N_T2_35
\ No newline at end of file
diff --git a/Bibliotheken/digilent-xdc-master/Arty-Z7-20-Master.xdc b/Bibliotheken/digilent-xdc-master/Arty-Z7-20-Master.xdc
new file mode 100644
index 0000000..1e965d0
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Arty-Z7-20-Master.xdc
@@ -0,0 +1,185 @@
+## This file is a general .xdc for the ARTY Z7-20 Rev.B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signal
+#set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
+
+## Switches
+#set_property -dict { PACKAGE_PIN M20    IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=SW0
+#set_property -dict { PACKAGE_PIN M19    IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=SW1
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN L15    IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7P_35 Sch=LED4_B
+#set_property -dict { PACKAGE_PIN G17    IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=LED4_G
+#set_property -dict { PACKAGE_PIN N15    IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=LED4_R
+#set_property -dict { PACKAGE_PIN G14    IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=LED5_B
+#set_property -dict { PACKAGE_PIN L14    IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=LED5_G
+#set_property -dict { PACKAGE_PIN M15    IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=LED5_R
+
+## LEDs
+#set_property -dict { PACKAGE_PIN R14    IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=LED0
+#set_property -dict { PACKAGE_PIN P14    IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=LED1
+#set_property -dict { PACKAGE_PIN N16    IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=LED2
+#set_property -dict { PACKAGE_PIN M14    IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=LED3
+
+## Buttons
+#set_property -dict { PACKAGE_PIN D19    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=BTN0
+#set_property -dict { PACKAGE_PIN D20    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=BTN1
+#set_property -dict { PACKAGE_PIN L20    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=BTN2
+#set_property -dict { PACKAGE_PIN L19    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=BTN3
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P (Pin 1)
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N (Pin 2)
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P (Pin 3)
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N (Pin 4)
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P (Pin 7)
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N (Pin 8)
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P (Pin 9)
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N (Pin 10)
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L8P_T1_34 Sch=JB1_P (Pin 1)
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L8N_T1_34 Sch=JB1_N (Pin 2)
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L1P_T0_34 Sch=JB2_P (Pin 3)
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L1N_T0_34 Sch=JB2_N (Pin 4)
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L18P_T2_34 Sch=JB3_P (Pin 7)
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L18N_T2_34 Sch=JB3_N (Pin 8)
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jb_p[4] }]; #IO_L4P_T0_34 Sch=JB4_P (Pin 9)
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { jb_n[4] }]; #IO_L4N_T0_34 Sch=JB4_N (Pin 10)
+
+## Audio Out
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=AUD_PWM
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=AUD_SD
+
+## Crypto SDA 
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=CRYPTO_SDA
+
+## HDMI RX Signals
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=HDMI_RX_HPD
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA
+
+## HDMI TX Signals
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=HDMI_TX_HDPN
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=HDMI_TX_SCL
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=HDMI_TX_SDA
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L5P_T0_34            Sch=CK_IO0
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { ck_io1  }]; #IO_L2N_T0_34            Sch=CK_IO1
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { ck_io2  }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=CK_IO2
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { ck_io3  }]; #IO_L3N_T0_DQS_34        Sch=CK_IO3
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io4  }]; #IO_L10P_T1_34           Sch=CK_IO4
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io5  }]; #IO_L5N_T0_34            Sch=CK_IO5
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io6  }]; #IO_L19P_T3_34           Sch=CK_IO6
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io7  }]; #IO_L9N_T1_DQS_34        Sch=CK_IO7
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io8  }]; #IO_L21P_T3_DQS_34       Sch=CK_IO8
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { ck_io9  }]; #IO_L21N_T3_DQS_34       Sch=CK_IO9
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L9P_T1_DQS_34        Sch=CK_IO10
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L19N_T3_VREF_34      Sch=CK_IO11
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L23N_T3_34           Sch=CK_IO12
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L23P_T3_34           Sch=CK_IO13
+
+## ChipKit Inner Digital Header
+#set_property -dict { PACKAGE_PIN U5    IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_VREF_13  Sch=CK_IO26
+#set_property -dict { PACKAGE_PIN V5    IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L6N_T0_VREF_13   Sch=CK_IO27
+#set_property -dict { PACKAGE_PIN V6    IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L22P_T3_13       Sch=CK_IO28
+#set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L11P_T1_SRCC_13  Sch=CK_IO29
+#set_property -dict { PACKAGE_PIN V7    IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L11N_T1_SRCC_13  Sch=CK_IO30
+#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L17N_T2_13       Sch=CK_IO31
+#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L15P_T2_DQS_13   Sch=CK_IO32
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L21N_T3_DQS_13   Sch=CK_IO33
+#set_property -dict { PACKAGE_PIN W10   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L16P_T2_13       Sch=CK_IO34
+#set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L22N_T3_13       Sch=CK_IO35
+#set_property -dict { PACKAGE_PIN Y6    IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L13N_T2_MRCC_13  Sch=CK_IO36
+#set_property -dict { PACKAGE_PIN Y7    IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L13P_T2_MRCC_13  Sch=cCK_IO37
+#set_property -dict { PACKAGE_PIN W8    IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_13   Sch=CK_IO38
+#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_SRCC_13  Sch=CK_IO39
+#set_property -dict { PACKAGE_PIN W9    IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_13       Sch=CK_IO40
+#set_property -dict { PACKAGE_PIN Y9    IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L14P_T2_SRCC_13  Sch=CK_IO41
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n  }]; #IO_L3N_T0_DQS_AD1N_35 Sch=CK_AN0_N   ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p  }]; #IO_L3P_T0_DQS_AD1P_35 Sch=CK_AN0_P   ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { vaux9_n  }]; #IO_L5N_T0_AD9N_35     Sch=CK_AN1_N   ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { vaux9_p  }]; #IO_L5P_T0_AD9P_35     Sch=CK_AN1_P   ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_n  }]; #IO_L20N_T3_AD6N_35    Sch=CK_AN2_N   ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_p  }]; #IO_L20P_T3_AD6P_35    Sch=CK_AN2_P   ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35   Sch=CK_AN3_N   ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35   Sch=CK_AN3_P   ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_n  }]; #IO_L17N_T2_AD5N_35    Sch=CK_AN4_N   ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_p  }]; #IO_L17P_T2_AD5P_35    Sch=CK_AN4_P   ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35   Sch=CK_AN5_N   ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35   Sch=CK_AN5_P   ChipKit pin=A5
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN Y11   IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L18N_T2_13      Sch=CK_A0
+#set_property -dict { PACKAGE_PIN Y12   IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L20P_T3_13      Sch=CK_A1
+#set_property -dict { PACKAGE_PIN W11   IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L18P_T2_13      Sch=CK_A2
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L21P_T3_DQS_13  Sch=CK_A3
+#set_property -dict { PACKAGE_PIN T5    IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L19P_T3_13      Sch=CK_A4
+#set_property -dict { PACKAGE_PIN U10   IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L12N_T1_MRCC_13 Sch=CK_A5
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P   ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N   ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_35       Sch=AD0_P    ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_35       Sch=AD0_N    ChipKit pin=A9
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p  }]; #IO_L2P_T0_AD8P_35       Sch=AD8_P    ChipKit pin=A10
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n  }]; #IO_L2N_T0_AD8N_35       Sch=AD8_N    ChipKit pin=A11
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L1P_T0_AD0P_35       Sch=AD0_P
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L1N_T0_AD0N_35       Sch=AD0_N
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35       Sch=AD8_P
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35       Sch=AD8_N
+
+## ChipKit SPI
+## NOTE: The ChipKit SPI header ports can also be used as digital I/O
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=CK_MISO
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=CK_MISO
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { ck_sck  }]; #IO_L19P_T3_35 Sch=CK_SCK
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { ck_ss   }]; #IO_L6P_T0_35 Sch=CK_SS
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA
+
+## Misc. ChipKit Ports
+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L20N_T3_13 Sch=CK_IOA
+
+## Not Connected Pins
+#set_property PACKAGE_PIN F17 [get_ports {netic20_f17}]; #IO_L6N_T0_VREF_35
+#set_property PACKAGE_PIN G18 [get_ports {netic20_g18}]; #IO_L16N_T2_35
+#set_property PACKAGE_PIN T9 [get_ports {netic20_t9}]; #IO_L12P_T1_MRCC_13
+#set_property PACKAGE_PIN U9 [get_ports {netic20_u9}]; #IO_L17P_T2_13
diff --git a/Bibliotheken/digilent-xdc-master/Basys-3-Master.xdc b/Bibliotheken/digilent-xdc-master/Basys-3-Master.xdc
new file mode 100644
index 0000000..23768f9
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Basys-3-Master.xdc
@@ -0,0 +1,154 @@
+## This file is a general .xdc for the Basys3 rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+#set_property -dict { PACKAGE_PIN W5   IOSTANDARD LVCMOS33 } [get_ports clk]
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+
+
+## Switches
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports {sw[0]}]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports {sw[1]}]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
+#set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
+#set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
+#set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
+#set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
+#set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
+#set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
+#set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
+#set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
+#set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
+
+
+## LEDs
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
+#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports {led[4]}]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports {led[5]}]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports {led[6]}]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports {led[7]}]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports {led[8]}]
+#set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports {led[9]}]
+#set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports {led[10]}]
+#set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports {led[11]}]
+#set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports {led[12]}]
+#set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports {led[13]}]
+#set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
+#set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports {led[15]}]
+
+
+##7 Segment Display
+#set_property -dict { PACKAGE_PIN W7   IOSTANDARD LVCMOS33 } [get_ports {seg[0]}]
+#set_property -dict { PACKAGE_PIN W6   IOSTANDARD LVCMOS33 } [get_ports {seg[1]}]
+#set_property -dict { PACKAGE_PIN U8   IOSTANDARD LVCMOS33 } [get_ports {seg[2]}]
+#set_property -dict { PACKAGE_PIN V8   IOSTANDARD LVCMOS33 } [get_ports {seg[3]}]
+#set_property -dict { PACKAGE_PIN U5   IOSTANDARD LVCMOS33 } [get_ports {seg[4]}]
+#set_property -dict { PACKAGE_PIN V5   IOSTANDARD LVCMOS33 } [get_ports {seg[5]}]
+#set_property -dict { PACKAGE_PIN U7   IOSTANDARD LVCMOS33 } [get_ports {seg[6]}]
+
+#set_property -dict { PACKAGE_PIN V7   IOSTANDARD LVCMOS33 } [get_ports dp]
+
+#set_property -dict { PACKAGE_PIN U2   IOSTANDARD LVCMOS33 } [get_ports {an[0]}]
+#set_property -dict { PACKAGE_PIN U4   IOSTANDARD LVCMOS33 } [get_ports {an[1]}]
+#set_property -dict { PACKAGE_PIN V4   IOSTANDARD LVCMOS33 } [get_ports {an[2]}]
+#set_property -dict { PACKAGE_PIN W4   IOSTANDARD LVCMOS33 } [get_ports {an[3]}]
+
+
+##Buttons
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports btnC]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports btnU]
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports btnL]
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports btnR]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports btnD]
+
+
+##Pmod Header JA
+#set_property -dict { PACKAGE_PIN J1   IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1
+#set_property -dict { PACKAGE_PIN L2   IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2
+#set_property -dict { PACKAGE_PIN J2   IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3
+#set_property -dict { PACKAGE_PIN G2   IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4
+#set_property -dict { PACKAGE_PIN H1   IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7
+#set_property -dict { PACKAGE_PIN K2   IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8
+#set_property -dict { PACKAGE_PIN H2   IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9
+#set_property -dict { PACKAGE_PIN G3   IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7
+#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10
+
+##Pmod Header JXADC
+#set_property -dict { PACKAGE_PIN J3   IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P
+#set_property -dict { PACKAGE_PIN L3   IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P
+#set_property -dict { PACKAGE_PIN M2   IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P
+#set_property -dict { PACKAGE_PIN N2   IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P
+#set_property -dict { PACKAGE_PIN K3   IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N
+#set_property -dict { PACKAGE_PIN M3   IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N
+#set_property -dict { PACKAGE_PIN M1   IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N
+#set_property -dict { PACKAGE_PIN N1   IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N
+
+
+##VGA Connector
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
+#set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
+#set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports Hsync]
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports Vsync]
+
+
+##USB-RS232 Interface
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports RsRx]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports RsTx]
+
+
+##USB HID (PS/2)
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33   PULLUP true } [get_ports PS2Clk]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33   PULLUP true } [get_ports PS2Data]
+
+
+##Quad SPI Flash
+##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
+##STARTUPE2 primitive.
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports QspiCSn]
+
+
+## Configuration options, can be used for all designs
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
diff --git a/Bibliotheken/digilent-xdc-master/Cmod-A7-Master.xdc b/Bibliotheken/digilent-xdc-master/Cmod-A7-Master.xdc
new file mode 100644
index 0000000..b5df8d5
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Cmod-A7-Master.xdc
@@ -0,0 +1,132 @@
+## This file is a general .xdc for the CmodA7 rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## 12 MHz Clock Signal
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
+#create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
+
+## LEDs
+#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
+
+## RGB LED
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L14N_T2_SRCC_16 Sch=led0_b
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L14P_T2_SRCC_16 Sch=led0_r
+
+## Buttons
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L5N_T0_D07_14 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L9P_T1_DQS_14 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L8P_T1_D11_14 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L4P_T0_D04_14 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L6N_T0_D08_VREF_14 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja[10]
+
+## Analog XADC Pins
+## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
+
+## GPIO Pins
+## Pins 15 and 16 should remain commented if using them as analog inputs
+#set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { pio1  }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
+#set_property -dict { PACKAGE_PIN L3    IOSTANDARD LVCMOS33 } [get_ports { pio2  }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { pio3  }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
+#set_property -dict { PACKAGE_PIN K3    IOSTANDARD LVCMOS33 } [get_ports { pio4  }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { pio5  }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { pio6  }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { pio7  }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { pio8  }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { pio9  }]; #IO_L6P_T0_16 Sch=pio[09]
+#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { pio10 }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
+#set_property -dict { PACKAGE_PIN J1    IOSTANDARD LVCMOS33 } [get_ports { pio11 }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
+#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { pio12 }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
+#set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports { pio13 }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
+#set_property -dict { PACKAGE_PIN L2    IOSTANDARD LVCMOS33 } [get_ports { pio14 }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
+#set_property -dict { PACKAGE_PIN M1    IOSTANDARD LVCMOS33 } [get_ports { pio17 }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
+#set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports { pio18 }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
+#set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { pio19 }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
+#set_property -dict { PACKAGE_PIN M2    IOSTANDARD LVCMOS33 } [get_ports { pio20 }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
+#set_property -dict { PACKAGE_PIN N1    IOSTANDARD LVCMOS33 } [get_ports { pio21 }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
+#set_property -dict { PACKAGE_PIN N2    IOSTANDARD LVCMOS33 } [get_ports { pio22 }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
+#set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { pio23 }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
+#set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { pio26 }]; #IO_L2P_T0_34 Sch=pio[26]
+#set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports { pio27 }]; #IO_L2N_T0_34 Sch=pio[27]
+#set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { pio28 }]; #IO_L1P_T0_34 Sch=pio[28]
+#set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports { pio29 }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
+#set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports { pio30 }]; #IO_L1N_T0_34 Sch=pio[30]
+#set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports { pio31 }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
+#set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports { pio32 }]; #IO_L5N_T0_34 Sch=pio[32]
+#set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports { pio33 }]; #IO_L5P_T0_34 Sch=pio[33]
+#set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports { pio34 }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
+#set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { pio35 }]; #IO_L6P_T0_34 Sch=pio[35]
+#set_property -dict { PACKAGE_PIN W5    IOSTANDARD LVCMOS33 } [get_ports { pio36 }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
+#set_property -dict { PACKAGE_PIN V4    IOSTANDARD LVCMOS33 } [get_ports { pio37 }]; #IO_L11N_T1_SRCC_34 Sch=pio[37]
+#set_property -dict { PACKAGE_PIN U4    IOSTANDARD LVCMOS33 } [get_ports { pio38 }]; #IO_L11P_T1_SRCC_34 Sch=pio[38]
+#set_property -dict { PACKAGE_PIN V5    IOSTANDARD LVCMOS33 } [get_ports { pio39 }]; #IO_L16N_T2_34 Sch=pio[39]
+#set_property -dict { PACKAGE_PIN W4    IOSTANDARD LVCMOS33 } [get_ports { pio40 }]; #IO_L12N_T1_MRCC_34 Sch=pio[40]
+#set_property -dict { PACKAGE_PIN U5    IOSTANDARD LVCMOS33 } [get_ports { pio41 }]; #IO_L16P_T2_34 Sch=pio[41]
+#set_property -dict { PACKAGE_PIN U2    IOSTANDARD LVCMOS33 } [get_ports { pio42 }]; #IO_L9N_T1_DQS_34 Sch=pio[42]
+#set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33 } [get_ports { pio43 }]; #IO_L13N_T2_MRCC_34 Sch=pio[43]
+#set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { pio44 }]; #IO_L9P_T1_DQS_34 Sch=pio[44]
+#set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33 } [get_ports { pio45 }]; #IO_L19P_T3_34 Sch=pio[45]
+#set_property -dict { PACKAGE_PIN W7    IOSTANDARD LVCMOS33 } [get_ports { pio46 }]; #IO_L13P_T2_MRCC_34 Sch=pio[46]
+#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS33 } [get_ports { pio47 }]; #IO_L14P_T2_SRCC_34 Sch=pio[47]
+#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33 } [get_ports { pio48 }]; #IO_L14N_T2_SRCC_34 Sch=pio[48]
+
+## UART
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in  }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
+
+## Crypto 1 Wire Interface
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_0_14 Sch=crypto_sda
+
+## QSPI
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs    }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+## Cellular RAM
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[0]  }]; #IO_L11P_T1_SRCC_14 Sch=sram- a[0]
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[1]  }]; #IO_L11N_T1_SRCC_14 Sch=sram- a[1]
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[2]  }]; #IO_L12N_T1_MRCC_14 Sch=sram- a[2]
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[3]  }]; #IO_L13P_T2_MRCC_14 Sch=sram- a[3]
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[4]  }]; #IO_L13N_T2_MRCC_14 Sch=sram- a[4]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[5]  }]; #IO_L14P_T2_SRCC_14 Sch=sram- a[5]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[6]  }]; #IO_L14N_T2_SRCC_14 Sch=sram- a[6]
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[7]  }]; #IO_L16N_T2_A15_D31_14 Sch=sram- a[7]
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[8]  }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram- a[8]
+#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[9]  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram- a[9]
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[10] }]; #IO_L16P_T2_CSI_B_14 Sch=sram- a[10]
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[11] }]; #IO_L17P_T2_A14_D30_14 Sch=sram- a[11]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[12] }]; #IO_L17N_T2_A13_D29_14 Sch=sram- a[12]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[13] }]; #IO_L18P_T2_A12_D28_14 Sch=sram- a[13]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[14] }]; #IO_L18N_T2_A11_D27_14 Sch=sram- a[14]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[15] }]; #IO_L19P_T3_A10_D26_14 Sch=sram- a[15]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[16] }]; #IO_L20P_T3_A08_D24_14 Sch=sram- a[16]
+#set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[17] }]; #IO_L20N_T3_A07_D23_14 Sch=sram- a[17]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[18] }]; #IO_L21P_T3_DQS_14 Sch=sram- a[18]
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[0]   }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram-dq[0]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[1]   }]; #IO_L22P_T3_A05_D21_14 Sch=sram-dq[1]
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[2]   }]; #IO_L22N_T3_A04_D20_14 Sch=sram-dq[2]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[3]   }]; #IO_L23P_T3_A03_D19_14 Sch=sram-dq[3]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { MemDB[4]   }]; #IO_L23N_T3_A02_D18_14 Sch=sram-dq[4]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[5]   }]; #IO_L24P_T3_A01_D17_14 Sch=sram-dq[5]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[6]   }]; #IO_L24N_T3_A00_D16_14 Sch=sram-dq[6]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[7]   }]; #IO_25_14 Sch=sram-dq[7]
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { RamOEn     }]; #IO_L10P_T1_D14_14 Sch=sram-oe
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { RamWEn     }]; #IO_L10N_T1_D15_14 Sch=sram-we
+#set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS33 } [get_ports { RamCEn     }]; #IO_L9N_T1_DQS_D13_14 Sch=sram-ce
+
diff --git a/Bibliotheken/digilent-xdc-master/Cmod-S7-25-Master.xdc b/Bibliotheken/digilent-xdc-master/Cmod-S7-25-Master.xdc
new file mode 100644
index 0000000..237c893
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Cmod-S7-25-Master.xdc
@@ -0,0 +1,90 @@
+## This file is a general .xdc for the Cmod S7-25 Rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## 12 MHz System Clock
+#set_property -dict { PACKAGE_PIN M9    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_14 Sch=gclk
+#create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { clk }];
+
+## Push Buttons
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6P_T0_34 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN D1    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L6N_T0_VREF_34 Sch=btn[1]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L10N_T1_34 Sch=led0_b
+#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L9N_T1_DQS_34 Sch=led0_g
+#set_property -dict { PACKAGE_PIN F2    IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L10P_T1_34 Sch=led0_r
+
+## 4 LEDs
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L8P_T1_34 Sch=led[1]
+#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L16P_T2_34 Sch=led[2]
+#set_property -dict { PACKAGE_PIN J1    IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L16N_T2_34 Sch=led[3]
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8N_T1_34 Sch=led[4]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L14P_T2_SRCC_34 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L14N_T2_SRCC_34 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L13P_T2_MRCC_34 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L11N_T1_SRCC_34 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN H3    IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L13N_T2_MRCC_34 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12P_T1_MRCC_34 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L12N_T1_MRCC_34 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L11P_T1_SRCC_34 Sch=ja[10]
+
+## USB UART
+## Note: Port names are from the perspoctive of the FPGA.
+#set_property -dict { PACKAGE_PIN L12   IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L6N_T0_D08_VREF_14 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { uart_rx }]; #IO_L5N_T0_D07_14 Sch=uart_txd_in
+
+## Analog Inputs on PIO Pins 32 and 33
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=ain_p[32]
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=ain_n[32]
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=ain_p[33]
+#set_property -dict { PACKAGE_PIN A12   IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=ain_n[33]
+
+## Dedicated Digital I/O on the PIO Headers
+#set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports { pio1 }]; #IO_L18N_T2_34 Sch=pio[01]
+#set_property -dict { PACKAGE_PIN M4    IOSTANDARD LVCMOS33 } [get_ports { pio2 }]; #IO_L19P_T3_34 Sch=pio[02]
+#set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { pio3 }]; #IO_L19N_T3_VREF_34 Sch=pio[03]
+#set_property -dict { PACKAGE_PIN N2    IOSTANDARD LVCMOS33 } [get_ports { pio4 }]; #IO_L20P_T3_34 Sch=pio[04]
+#set_property -dict { PACKAGE_PIN M2    IOSTANDARD LVCMOS33 } [get_ports { pio5 }]; #IO_L20N_T3_34 Sch=pio[05]
+#set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { pio6 }]; #IO_L21P_T3_DQS_34 Sch=pio[06]
+#set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports { pio7 }]; #IO_L21N_T3_DQS_34 Sch=pio[07]
+#set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { pio8 }]; #IO_L22P_T3_34 Sch=pio[08]
+#set_property -dict { PACKAGE_PIN N1    IOSTANDARD LVCMOS33 } [get_ports { pio9 }]; #IO_L22N_T3_34 Sch=pio[09]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { pio16 }]; #IO_L11P_T1_SRCC_14 Sch=pio[16]
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { pio17 }]; #IO_L11N_T1_SRCC_14 Sch=pio[17]
+#set_property -dict { PACKAGE_PIN N13   IOSTANDARD LVCMOS33 } [get_ports { pio18 }]; #IO_L8N_T1_D12_14 Sch=pio[18]
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { pio19 }]; #IO_L10N_T1_D15_14 Sch=pio[19]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { pio20 }]; #IO_L10P_T1_D14_14 Sch=pio[20]
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { pio21 }]; #IO_L9N_T1_DQS_D13_14 Sch=pio[21]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { pio22 }]; #IO_L9P_T1_DQS_14 Sch=pio[22]
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { pio23 }]; #IO_L4N_T0_D05_14 Sch=pio[23]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { pio26 }]; #IO_L7N_T1_D10_14 Sch=pio[26]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { pio27 }]; #IO_L4P_T0_D04_14 Sch=pio[27]
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { pio28 }]; #IO_L5P_T0_D06_14 Sch=pio[28]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { pio29 }]; #IO_L7P_T1_D09_14 Sch=pio[29]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { pio30 }]; #IO_L8P_T1_D11_14 Sch=pio[30]
+#set_property -dict { PACKAGE_PIN J11   IOSTANDARD LVCMOS33 } [get_ports { pio31 }]; #IO_0_14 Sch=pio[31]
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { pio40 }]; #IO_L5P_T0_34 Sch=pio[40]
+#set_property -dict { PACKAGE_PIN A2    IOSTANDARD LVCMOS33 } [get_ports { pio41 }]; #IO_L2N_T0_34 Sch=pio[41]
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { pio42 }]; #IO_L2P_T0_34 Sch=pio[42]
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { pio43 }]; #IO_L4N_T0_34 Sch=pio[43]
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { pio44 }]; #IO_L4P_T0_34 Sch=pio[44]
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { pio45 }]; #IO_L3N_T0_DQS_34 Sch=pio[45]
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { pio46 }]; #IO_L3P_T0_DQS_34 Sch=pio[46]
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { pio47 }]; #IO_L1N_T0_34 Sch=pio[47]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { pio48 }]; #IO_L1P_T0_34 Sch=pio[48]
+
+## Quad SPI Flash
+## Note: QSPI clock can only be accessed through the STARTUPE2 primitive
+#set_property -dict { PACKAGE_PIN L11   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN J12   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
\ No newline at end of file
diff --git a/Bibliotheken/digilent-xdc-master/Cora-Z7-07S-Master.xdc b/Bibliotheken/digilent-xdc-master/Cora-Z7-07S-Master.xdc
new file mode 100644
index 0000000..5bdc893
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Cora-Z7-07S-Master.xdc
@@ -0,0 +1,150 @@
+## This file is a general .xdc for the Cora Z7-07S Rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## PL System Clock
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_0_35 Sch=led1_b
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r
+
+## Buttons
+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L17P_T2_34 Sch=ja_p[1]
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L17N_T2_34 Sch=ja_n[1]
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L7P_T1_34 Sch=ja_p[2]
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L7N_T1_34 Sch=ja_n[2]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4]
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
+
+## Crypto SDA 
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }];
+
+## Dedicated Analog Inputs
+#set_property -dict { PACKAGE_PIN K9    IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p
+#set_property -dict { PACKAGE_PIN L10   IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L10N_T1_AD11N_35 Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L12P_T1_MRCC_35 Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L6P_T0_34 Sch=ck_a[5]
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L5P_T0_34 Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L5N_T0_34 Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L21P_T3_DQS_34 Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L21N_T3_DQS_34 Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19N_T3_VREF_34 Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L19N_T3_VREF_35 Sch=ck_io[13]
+
+## ChipKit Inner Digital Header
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19P_T3_34 Sch=ck_io[26]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L2N_T0_34 Sch=ck_io[27]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[28]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L10P_T1_34 Sch=ck_io[29]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L9P_T1_DQS_34 Sch=ck_io[30]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L9N_T1_DQS_34 Sch=ck_io[31]
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L20P_T3_34 Sch=ck_io[32]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_34 Sch=ck_io[33]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L23N_T3_34 Sch=ck_io[34]
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L23P_T3_34 Sch=ck_io[35]
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_AD10P_35 Sch=ck_io[36]
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L11N_T1_SRCC_35 Sch=ck_io[37]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L13N_T2_MRCC_35 Sch=ck_io[38]
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=ck_io[39]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_35 Sch=ck_io[40]
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9N_T1_DQS_AD3N_35 Sch=ck_io[41]
+
+## ChipKit SPI
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda
+
+##Misc. ChipKit signals
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L7N_T1_AD2N_35 Sch=ck_ioa
+
+## User Digital I/O Header J1
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[1] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=user_dio[1]
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[2] }]; #IO_L7P_T1_AD2P_35 Sch=user_dio[2]
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[3] }]; #IO_L14P_T2_SRCC_34 Sch=user_dio[3]
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[4] }]; #IO_L14N_T2_SRCC_34 Sch=user_dio[4]
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[5] }]; #IO_L13N_T2_MRCC_34 Sch=user_dio[5]
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[6] }]; #IO_0_34 Sch=user_dio[6]
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[7] }]; #IO_L15P_T2_DQS_34 Sch=user_dio[7]
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[8] }]; #IO_25_34 Sch=user_dio[8]
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[9] }]; #IO_L15N_T2_DQS_34 Sch=user_dio[9]
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[10] }]; #IO_L16P_T2_34 Sch=user_dio[10]
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[11] }]; #IO_L16N_T2_34 Sch=user_dio[11]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[12] }]; #IO_L10P_T1_AD11P_35 Sch=user_dio[12]
diff --git a/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc b/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc
new file mode 100644
index 0000000..92a00af
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc
@@ -0,0 +1,152 @@
+## This file is a general .xdc for the Cora Z7-10 Rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## PL System Clock
+set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk]
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
+
+## RGB LEDs
+set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
+set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g
+set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
+set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports led]
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_0_35 Sch=led1_b
+set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g
+set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r
+
+## Buttons
+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L17P_T2_34 Sch=ja_p[1]
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L17N_T2_34 Sch=ja_n[1]
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L7P_T1_34 Sch=ja_p[2]
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L7N_T1_34 Sch=ja_n[2]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4]
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
+
+## Crypto SDA
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }];
+
+## Dedicated Analog Inputs
+#set_property -dict { PACKAGE_PIN K9    IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p
+#set_property -dict { PACKAGE_PIN L10   IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L10N_T1_AD11N_35 Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L12P_T1_MRCC_35 Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L6P_T0_34 Sch=ck_a[5]
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L5P_T0_34 Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L5N_T0_34 Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L21P_T3_DQS_34 Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L21N_T3_DQS_34 Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19N_T3_VREF_34 Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L19N_T3_VREF_35 Sch=ck_io[13]
+
+## ChipKit Inner Digital Header
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19P_T3_34 Sch=ck_io[26]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L2N_T0_34 Sch=ck_io[27]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[28]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L10P_T1_34 Sch=ck_io[29]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L9P_T1_DQS_34 Sch=ck_io[30]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L9N_T1_DQS_34 Sch=ck_io[31]
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L20P_T3_34 Sch=ck_io[32]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_34 Sch=ck_io[33]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L23N_T3_34 Sch=ck_io[34]
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L23P_T3_34 Sch=ck_io[35]
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_AD10P_35 Sch=ck_io[36]
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L11N_T1_SRCC_35 Sch=ck_io[37]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L13N_T2_MRCC_35 Sch=ck_io[38]
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=ck_io[39]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_35 Sch=ck_io[40]
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9N_T1_DQS_AD3N_35 Sch=ck_io[41]
+
+## ChipKit SPI
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda
+
+##Misc. ChipKit signals
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L7N_T1_AD2N_35 Sch=ck_ioa
+
+## User Digital I/O Header J1
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[1] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=user_dio[1]
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[2] }]; #IO_L7P_T1_AD2P_35 Sch=user_dio[2]
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[3] }]; #IO_L14P_T2_SRCC_34 Sch=user_dio[3]
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[4] }]; #IO_L14N_T2_SRCC_34 Sch=user_dio[4]
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[5] }]; #IO_L13N_T2_MRCC_34 Sch=user_dio[5]
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[6] }]; #IO_0_34 Sch=user_dio[6]
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[7] }]; #IO_L15P_T2_DQS_34 Sch=user_dio[7]
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[8] }]; #IO_25_34 Sch=user_dio[8]
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[9] }]; #IO_L15N_T2_DQS_34 Sch=user_dio[9]
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[10] }]; #IO_L16P_T2_34 Sch=user_dio[10]
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[11] }]; #IO_L16N_T2_34 Sch=user_dio[11]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[12] }]; #IO_L10P_T1_AD11P_35 Sch=user_dio[12]
+
diff --git a/Bibliotheken/digilent-xdc-master/Eclypse-Z7-Master.xdc b/Bibliotheken/digilent-xdc-master/Eclypse-Z7-Master.xdc
new file mode 100644
index 0000000..80b6ac2
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Eclypse-Z7-Master.xdc
@@ -0,0 +1,115 @@
+## This file is a general .xdc for the Eclypse Z7 Rev. B.0
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## 125MHz Clock from Ethernet PHY
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
+
+## Buttons
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L11P_T1_SRCC Sch=btn[0]
+#set_property -dict { PACKAGE_PIN C18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11N_T1_SRCC Sch=btn[1]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L9N_T1_DQS_AD3N Sch=led0_b
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L8P_T1_AD10P Sch=led0_g
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L8N_T1_AD10N Sch=led0_r
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L9P_T1_DQS_AD3P Sch=led1_b
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L10P_T1_AD11P Sch=led1_g
+#set_property -dict { PACKAGE_PIN A19   IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L10N_T1_AD11N Sch=led1_r
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0 Sch=ja1_fpga
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_25 Sch=ja2_fpga
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L1N_T0_AD0N Sch=ja3_fpga
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L1P_T0_AD0P Sch=ja4_fpga
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L2N_T0_AD8N Sch=ja7_fpga
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L2P_T0_AD8P Sch=ja8_fpga
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L3N_T0_DQS_AD1N Sch=ja9_fpga
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L3P_T0_DQS_AD1P Sch=ja10_fpga
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L4N_T0 Sch=jb1_fpga
+#set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L4P_T0 Sch=jb2_fpga
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L5N_T0_AD9N Sch=jb3_fpga
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L5P_T0_AD9P Sch=jb4_fpga
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6N_T0_VREF Sch=jb7_fpga
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L6P_T0 Sch=jb8_fpga
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L7N_T1_AD2N Sch=jb9_fpga
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L7P_T1_AD2P Sch=jb10_fpga
+
+## Syzygy Port A
+#set_property -dict { PACKAGE_PIN N20  } [get_ports { syzygy_a_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
+#set_property -dict { PACKAGE_PIN N19  } [get_ports { syzygy_a_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
+#set_property -dict { PACKAGE_PIN T17  } [get_ports { syzygy_a_d_n[0] }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
+#set_property -dict { PACKAGE_PIN T16  } [get_ports { syzygy_a_d_p[0] }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
+#set_property -dict { PACKAGE_PIN T19  } [get_ports { syzygy_a_d_n[1] }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
+#set_property -dict { PACKAGE_PIN R19  } [get_ports { syzygy_a_d_p[1] }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
+#set_property -dict { PACKAGE_PIN T18  } [get_ports { syzygy_a_d_n[2] }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
+#set_property -dict { PACKAGE_PIN R18  } [get_ports { syzygy_a_d_p[2] }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
+#set_property -dict { PACKAGE_PIN P18  } [get_ports { syzygy_a_d_n[3] }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
+#set_property -dict { PACKAGE_PIN P17  } [get_ports { syzygy_a_d_p[3] }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
+#set_property -dict { PACKAGE_PIN R16  } [get_ports { syzygy_a_d_n[4] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
+#set_property -dict { PACKAGE_PIN P16  } [get_ports { syzygy_a_d_p[4] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
+#set_property -dict { PACKAGE_PIN P15  } [get_ports { syzygy_a_d_n[5] }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
+#set_property -dict { PACKAGE_PIN N15  } [get_ports { syzygy_a_d_p[5] }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
+#set_property -dict { PACKAGE_PIN K18  } [get_ports { syzygy_a_d_n[6] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
+#set_property -dict { PACKAGE_PIN J18  } [get_ports { syzygy_a_d_p[6] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
+#set_property -dict { PACKAGE_PIN K21  } [get_ports { syzygy_a_d_n[7] }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
+#set_property -dict { PACKAGE_PIN J20  } [get_ports { syzygy_a_d_p[7] }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]
+#set_property -dict { PACKAGE_PIN M20  } [get_ports { syzygy_a_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n
+#set_property -dict { PACKAGE_PIN M19  } [get_ports { syzygy_a_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
+#set_property -dict { PACKAGE_PIN L19  } [get_ports { syzygy_a_s[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
+#set_property -dict { PACKAGE_PIN K20  } [get_ports { syzygy_a_s[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
+#set_property -dict { PACKAGE_PIN L18  } [get_ports { syzygy_a_s[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
+#set_property -dict { PACKAGE_PIN K19  } [get_ports { syzygy_a_s[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
+#set_property -dict { PACKAGE_PIN L22  } [get_ports { syzygy_a_s[20] }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
+#set_property -dict { PACKAGE_PIN J22  } [get_ports { syzygy_a_s[21] }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
+#set_property -dict { PACKAGE_PIN L21  } [get_ports { syzygy_a_s[22] }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
+#set_property -dict { PACKAGE_PIN J21  } [get_ports { syzygy_a_s[23] }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
+#set_property -dict { PACKAGE_PIN N22  } [get_ports { syzygy_a_s[24] }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
+#set_property -dict { PACKAGE_PIN P22  } [get_ports { syzygy_a_s[25] }]; #IO_L16N_T2 Sch=syzygy_a_s[25]
+#set_property -dict { PACKAGE_PIN M21  } [get_ports { syzygy_a_s[26] }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]
+#set_property -dict { PACKAGE_PIN M22  } [get_ports { syzygy_a_s[27] }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]
+
+## Syzygy Port B
+#set_property -dict { PACKAGE_PIN Y16  } [get_ports { syzygy_b_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_b_c2p_clk_n
+#set_property -dict { PACKAGE_PIN W16  } [get_ports { syzygy_b_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_b_c2p_clk_p
+#set_property -dict { PACKAGE_PIN Y15  } [get_ports { syzygy_b_d_n[0] }]; #IO_L21N_T3_DQS Sch=syzygy_b_d_n[0]
+#set_property -dict { PACKAGE_PIN W15  } [get_ports { syzygy_b_d_p[0] }]; #IO_L21P_T3_DQS Sch=syzygy_b_d_p[0]
+#set_property -dict { PACKAGE_PIN W13  } [get_ports { syzygy_b_d_n[1] }]; #IO_L20N_T3 Sch=syzygy_b_d_n[1]
+#set_property -dict { PACKAGE_PIN V13  } [get_ports { syzygy_b_d_p[1] }]; #IO_L20P_T3 Sch=syzygy_b_d_p[1]
+#set_property -dict { PACKAGE_PIN AA13 } [get_ports { syzygy_b_d_n[2] }]; #IO_L23N_T3 Sch=syzygy_b_d_n[2]
+#set_property -dict { PACKAGE_PIN Y13  } [get_ports { syzygy_b_d_p[2] }]; #IO_L23P_T3 Sch=syzygy_b_d_p[2]
+#set_property -dict { PACKAGE_PIN AB15 } [get_ports { syzygy_b_d_n[3] }]; #IO_L24N_T3 Sch=syzygy_b_d_n[3]
+#set_property -dict { PACKAGE_PIN AB14 } [get_ports { syzygy_b_d_p[3] }]; #IO_L24P_T3 Sch=syzygy_b_d_p[3]
+#set_property -dict { PACKAGE_PIN AA14 } [get_ports { syzygy_b_d_n[4] }]; #IO_L22N_T3 Sch=syzygy_b_d_n[4]
+#set_property -dict { PACKAGE_PIN Y14  } [get_ports { syzygy_b_d_p[4] }]; #IO_L22P_T3 Sch=syzygy_b_d_p[4]
+#set_property -dict { PACKAGE_PIN V15  } [get_ports { syzygy_b_d_n[5] }]; #IO_L19N_T3_VREF Sch=syzygy_b_d_n[5]
+#set_property -dict { PACKAGE_PIN V14  } [get_ports { syzygy_b_d_p[5] }]; #IO_L19P_T3 Sch=syzygy_b_d_p[5]
+#set_property -dict { PACKAGE_PIN AB22 } [get_ports { syzygy_b_d_n[6] }]; #IO_L7N_T1 Sch=syzygy_b_d_n[6]
+#set_property -dict { PACKAGE_PIN AA22 } [get_ports { syzygy_b_d_p[6] }]; #IO_L7P_T1 Sch=syzygy_b_d_p[6]
+#set_property -dict { PACKAGE_PIN Y21  } [get_ports { syzygy_b_d_n[7] }]; #IO_L9N_T1_DQS Sch=syzygy_b_d_n[7]
+#set_property -dict { PACKAGE_PIN Y20  } [get_ports { syzygy_b_d_p[7] }]; #IO_L9P_T1_DQS Sch=syzygy_b_d_p[7]
+#set_property -dict { PACKAGE_PIN W18  } [get_ports { syzygy_b_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_b_p2c_clk_n
+#set_property -dict { PACKAGE_PIN W17  } [get_ports { syzygy_b_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_b_p2c_clk_p
+#set_property -dict { PACKAGE_PIN AA18 } [get_ports { syzygy_b_s[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_b_s[16]
+#set_property -dict { PACKAGE_PIN AA19 } [get_ports { syzygy_b_s[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_b_s[17]
+#set_property -dict { PACKAGE_PIN Y18  } [get_ports { syzygy_b_s[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_b_s[18]
+#set_property -dict { PACKAGE_PIN Y19  } [get_ports { syzygy_b_s[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_b_s[19]
+#set_property -dict { PACKAGE_PIN AB20 } [get_ports { syzygy_b_s[20] }]; #IO_L10N_T1 Sch=syzygy_b_s[20]
+#set_property -dict { PACKAGE_PIN AB21 } [get_ports { syzygy_b_s[21] }]; #IO_L8N_T1 Sch=syzygy_b_s[21]
+#set_property -dict { PACKAGE_PIN AB19 } [get_ports { syzygy_b_s[22] }]; #IO_L10P_T1 Sch=syzygy_b_s[22]
+#set_property -dict { PACKAGE_PIN AA21 } [get_ports { syzygy_b_s[23] }]; #IO_L8P_T1 Sch=syzygy_b_s[23]
+#set_property -dict { PACKAGE_PIN U16  } [get_ports { syzygy_b_s[24] }]; #IO_L15N_T2_DQS Sch=syzygy_b_s[24]
+#set_property -dict { PACKAGE_PIN U15  } [get_ports { syzygy_b_s[25] }]; #IO_L15P_T2_DQS Sch=syzygy_b_s[25]
+#set_property -dict { PACKAGE_PIN V17  } [get_ports { syzygy_b_s[26] }]; #IO_L16N_T2 Sch=syzygy_b_s[26]
+#set_property -dict { PACKAGE_PIN U17  } [get_ports { syzygy_b_s[27] }]; #IO_L16P_T2 Sch=syzygy_b_s[27]
+
+## Crypto SDA 
+#set_property -dict { PACKAGE_PIN D22   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L16P_T2 Sch=crypto_sda
+
+## Miscellaneous
+#set_property -dict { PACKAGE_PIN B22   IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[0] }]; #IO_L18N_T2_AD13N Sch=mcu_rsvd[1]
+#set_property -dict { PACKAGE_PIN B21   IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[1] }]; #IO_L18P_T2_AD13P Sch=mcu_rsvd[2]
diff --git a/Bibliotheken/digilent-xdc-master/Genesys-2-Master.xdc b/Bibliotheken/digilent-xdc-master/Genesys-2-Master.xdc
new file mode 100644
index 0000000..7f97646
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Genesys-2-Master.xdc
@@ -0,0 +1,437 @@
+#### This file is a general .xdc for the Genesys 2 Rev. H
+#### To use it in a project:
+#### - uncomment the lines corresponding to used pins
+#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signal
+#set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+#set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+
+## Buttons
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_0_15 Sch=btnd
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L6P_T0_15 Sch=btnl
+#set_property -dict { PACKAGE_PIN C19   IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L24P_T3_17 Sch=btnr
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_L24N_T3_17 Sch=btnu
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_0_14 Sch=cpu_resetn
+
+## LEDs
+#set_property -dict { PACKAGE_PIN T28   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
+#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
+#set_property -dict { PACKAGE_PIN U30   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
+#set_property -dict { PACKAGE_PIN U29   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
+#set_property -dict { PACKAGE_PIN V26   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
+#set_property -dict { PACKAGE_PIN W24   IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN W23   IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7]
+
+## Switches
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS12 } [get_ports { sw[0] }]; #IO_0_17 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN G25   IOSTANDARD LVCMOS12 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN H24   IOSTANDARD LVCMOS12 } [get_ports { sw[2] }]; #IO_L19P_T3_16 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS12 } [get_ports { sw[3] }]; #IO_L6P_T0_17 Sch=sw[3]
+#set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS12 } [get_ports { sw[4] }]; #IO_L19P_T3_A22_15 Sch=sw[4]
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS12 } [get_ports { sw[5] }]; #IO_25_15 Sch=sw[5]
+#set_property -dict { PACKAGE_PIN P26   IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6]
+#set_property -dict { PACKAGE_PIN P27   IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L8P_T1_D11_14 Sch=sw[7]
+
+## USB HIDs For Both Mouse and Keyboard
+#set_property -dict { PACKAGE_PIN AD23  IOSTANDARD LVCMOS33  PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0]
+#set_property -dict { PACKAGE_PIN AE20  IOSTANDARD LVCMOS33  PULLUP true } [get_ports { ps2_data_0 }]; #IO_25_12 Sch=ps2_data[0]
+
+## UART
+#set_property -dict { PACKAGE_PIN Y23   IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }]; #IO_L1P_T0_12 Sch=uart_rx_out
+#set_property -dict { PACKAGE_PIN Y20   IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }]; #IO_0_12 Sch=uart_tx_in
+
+## SD Card
+#set_property -dict { PACKAGE_PIN P28   IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN R29   IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN R26   IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
+#set_property -dict { PACKAGE_PIN R30   IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
+#set_property -dict { PACKAGE_PIN P29   IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
+#set_property -dict { PACKAGE_PIN T30   IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
+#set_property -dict { PACKAGE_PIN AE24  IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
+#set_property -dict { PACKAGE_PIN R28   IOSTANDARD LVCMOS33 } [get_ports { sd_sclk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
+
+## Audio Codec
+#set_property -dict { PACKAGE_PIN AH19  IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L8N_T1_32 Sch=aud_adc_sdata
+#set_property -dict { PACKAGE_PIN AD19  IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L10P_T1_32 Sch=aud_adr[0]
+#set_property -dict { PACKAGE_PIN AG19  IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L8P_T1_32 Sch=aud_adr[1]
+#set_property -dict { PACKAGE_PIN AG18  IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L11N_T1_SRCC_32 Sch=aud_bclk
+#set_property -dict { PACKAGE_PIN AJ19  IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L7P_T1_32 Sch=aud_dac_sdata
+#set_property -dict { PACKAGE_PIN AJ18  IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L9P_T1_DQS_32 Sch=aud_lrclk
+#set_property -dict { PACKAGE_PIN AK19  IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L7N_T1_32 Sch=aud_mclk
+#set_property -dict { PACKAGE_PIN AE19  IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L10N_T1_32 Sch=aud_scl
+#set_property -dict { PACKAGE_PIN AF18  IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_L11P_T1_SRCC_32 Sch=aud_sda
+
+## Ethernet
+#set_property -dict { PACKAGE_PIN AK16  IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
+#set_property -dict { PACKAGE_PIN AF12  IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN AG12  IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN AH24  IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
+#set_property -dict { PACKAGE_PIN AK15  IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
+#set_property -dict { PACKAGE_PIN AG10  IOSTANDARD LVCMOS15 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
+#set_property -dict { PACKAGE_PIN AH11  IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
+#set_property -dict { PACKAGE_PIN AJ14  IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
+#set_property -dict { PACKAGE_PIN AH14  IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
+#set_property -dict { PACKAGE_PIN AK13  IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
+#set_property -dict { PACKAGE_PIN AJ13  IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
+#set_property -dict { PACKAGE_PIN AE10  IOSTANDARD LVCMOS15 } [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
+#set_property -dict { PACKAGE_PIN AJ12  IOSTANDARD LVCMOS15 } [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
+#set_property -dict { PACKAGE_PIN AK11  IOSTANDARD LVCMOS15 } [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
+#set_property -dict { PACKAGE_PIN AJ11  IOSTANDARD LVCMOS15 } [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
+#set_property -dict { PACKAGE_PIN AK10  IOSTANDARD LVCMOS15 } [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
+#set_property -dict { PACKAGE_PIN AK14  IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en
+
+## VGA Connector
+#set_property -dict { PACKAGE_PIN AH20  IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3]
+#set_property -dict { PACKAGE_PIN AG20  IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4]
+#set_property -dict { PACKAGE_PIN AF21  IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5]
+#set_property -dict { PACKAGE_PIN AK20  IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6]
+#set_property -dict { PACKAGE_PIN AG22  IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7]
+
+#set_property -dict { PACKAGE_PIN AJ23  IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2]
+#set_property -dict { PACKAGE_PIN AJ22  IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3]
+#set_property -dict { PACKAGE_PIN AH22  IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4]
+#set_property -dict { PACKAGE_PIN AK21  IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5]
+#set_property -dict { PACKAGE_PIN AJ21  IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6]
+#set_property -dict { PACKAGE_PIN AK23  IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7]
+
+#set_property -dict { PACKAGE_PIN AK25  IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3]
+#set_property -dict { PACKAGE_PIN AG25  IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4]
+#set_property -dict { PACKAGE_PIN AH25  IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5]
+#set_property -dict { PACKAGE_PIN AK24  IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6]
+#set_property -dict { PACKAGE_PIN AJ24  IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7]
+
+#set_property -dict { PACKAGE_PIN AF20  IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs
+#set_property -dict { PACKAGE_PIN AG23  IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs
+
+## HDMI in
+#set_property -dict { PACKAGE_PIN Y21   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L2P_T0_12 Sch=hdmi_rx_cec
+#set_property -dict { PACKAGE_PIN AF28  IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_n }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN AE28  IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_p }]; #IO_L14P_T2_SRCC_13 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN AH29  IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_hpa
+#set_property -dict { PACKAGE_PIN AJ28  IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17P_T2_13 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN AJ29  IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_13 Sch=hdmi_rx_sda
+#set_property -dict { PACKAGE_PIN AK26  IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN AJ26  IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN AG28  IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[1] }]; #IO_L21N_T3_DQS_13 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN AG27  IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[1] }]; #IO_L21P_T3_DQS_13 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN AH27  IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[2] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN AH26  IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[2] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[2]
+
+## HDMI out
+#set_property -dict { PACKAGE_PIN Y24   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L1N_T0_12 Sch=hdmi_tx_cec
+#set_property -dict { PACKAGE_PIN AB20  IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_n }]; #IO_L6N_T0_VREF_12 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN AA20  IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_p }]; #IO_L6P_T0_12 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN AG29  IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN AF27  IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L23N_T3_13 Sch=hdmi_tx_scl
+#set_property -dict { PACKAGE_PIN AF26  IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L23P_T3_13 Sch=hdmi_tx_sda
+#set_property -dict { PACKAGE_PIN AC21  IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_12 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN AC20  IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_12 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN AA23  IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[1] }]; #IO_L4N_T0_12 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN AA22  IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[1] }]; #IO_L4P_T0_12 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN AC25  IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[2] }]; #IO_L7N_T1_12 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN AB24  IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[2] }]; #IO_L7P_T1_12 Sch=hdmi_tx_p[2]
+
+## OLED Display
+#set_property -dict { PACKAGE_PIN AC17  IOSTANDARD LVCMOS18 } [get_ports { oled_dc }]; #IO_L18N_T2_32 Sch=oled_dc
+#set_property -dict { PACKAGE_PIN AB17  IOSTANDARD LVCMOS18 } [get_ports { oled_res }]; #IO_L18P_T2_32 Sch=oled_res
+#set_property -dict { PACKAGE_PIN AF17  IOSTANDARD LVCMOS18 } [get_ports { oled_sclk }]; #IO_L12P_T1_MRCC_32 Sch=oled_sclk
+#set_property -dict { PACKAGE_PIN Y15   IOSTANDARD LVCMOS18 } [get_ports { oled_sdin }]; #IO_L24N_T3_32 Sch=oled_sdin
+#set_property -dict { PACKAGE_PIN AB22  IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_L3P_T0_DQS_12 Sch=oled_vbat
+#set_property -dict { PACKAGE_PIN AG17  IOSTANDARD LVCMOS18 } [get_ports { oled_vdd }]; #IO_L12N_T1_MRCC_32 Sch=oled_vdd
+
+## PMOD Header JA
+#set_property -dict { PACKAGE_PIN U27   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1]
+#set_property -dict { PACKAGE_PIN U28   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1]
+#set_property -dict { PACKAGE_PIN T26   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2]
+#set_property -dict { PACKAGE_PIN T27   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2]
+#set_property -dict { PACKAGE_PIN T22   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]
+#set_property -dict { PACKAGE_PIN T23   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3]
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4]
+#set_property -dict { PACKAGE_PIN T21   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4]
+
+## PMOD Header JB
+#set_property -dict { PACKAGE_PIN V29   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L17P_T2_A14_D30_14 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN V30   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L17N_T2_A13_D29_14 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN V25   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L18P_T2_A12_D28_14 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN W26   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L18N_T2_A11_D27_14 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN T25   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L14P_T2_SRCC_14 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN U25   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L14N_T2_SRCC_14 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN U22   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L21P_T3_DQS_14 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN U23   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4]
+
+## PMOD Header JC
+#set_property -dict { PACKAGE_PIN AC26  IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L19P_T3_13 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN AJ27  IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20P_T3_13 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN AH30  IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L18N_T2_13 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN AK29  IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15P_T2_DQS_13 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN AD26  IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L19N_T3_VREF_13 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN AG30  IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L18P_T2_13 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN AK30  IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L15N_T2_DQS_13 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN AK28  IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_13 Sch=jc[10]
+
+## PMOD Header JD
+#set_property -dict { PACKAGE_PIN V27   IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN Y30   IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L8P_T1_13 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN V24   IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN W22   IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN U24   IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L23P_T3_A03_D19_14 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN Y26   IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L1P_T0_13 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN V22   IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L22N_T3_A04_D20_14 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN W21   IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd[10]
+
+## XADC Header
+#set_property -dict { PACKAGE_PIN J24   IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD0N_15 Sch=xadc0r_n
+#set_property -dict { PACKAGE_PIN J23   IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD0P_15 Sch=xadc0r_p
+#set_property -dict { PACKAGE_PIN K24   IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xadc1r_n
+#set_property -dict { PACKAGE_PIN K23   IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xadc1r_p
+#set_property -dict { PACKAGE_PIN L23   IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xadc8r_n
+#set_property -dict { PACKAGE_PIN L22   IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xadc8r_p
+#set_property -dict { PACKAGE_PIN K21   IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L4N_T0_AD9N_15 Sch=xadc9r_n
+#set_property -dict { PACKAGE_PIN L21   IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L4P_T0_AD9P_15 Sch=xadc9r_p
+
+## FMC
+#set_property -dict { PACKAGE_PIN AB30  IOSTANDARD LVCMOS33 } [get_ports { FMC_CLK_DIR }]; #IO_L10N_T1_13 Sch=fmc_clk_dir
+#set_property -dict { PACKAGE_PIN E20   IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_17 Sch=fmc_clk0_m2c_n
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_17 Sch=fmc_clk0_m2c_p
+#set_property -dict { PACKAGE_PIN D28   IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L14N_T2_SRCC_16 Sch=fmc_clk1_m2c_n
+#set_property -dict { PACKAGE_PIN E28   IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L14P_T2_SRCC_16 Sch=fmc_clk1_m2c_p
+#set_property -dict { PACKAGE_PIN K25   IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_N[2] }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=fmc_clk_n[2]
+#set_property -dict { PACKAGE_PIN L25   IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_P[2] }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=fmc_clk_p[2]
+#set_property -dict { PACKAGE_PIN K29   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[00] }]; #IO_L13N_T2_MRCC_15 Sch=fmc_ha_n[00]
+#set_property -dict { PACKAGE_PIN K28   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[00] }]; #IO_L13P_T2_MRCC_15 Sch=fmc_ha_p[00]
+#set_property -dict { PACKAGE_PIN L28   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[01] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_ha_n[01]
+#set_property -dict { PACKAGE_PIN M28   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[01] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_ha_p[01]
+#set_property -dict { PACKAGE_PIN P22   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[02] }]; #IO_L22N_T3_A16_15 Sch=fmc_ha_n[02]
+#set_property -dict { PACKAGE_PIN P21   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[02] }]; #IO_L22P_T3_A17_15 Sch=fmc_ha_p[02]
+#set_property -dict { PACKAGE_PIN N26   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[03] }]; #IO_L18N_T2_A23_15 Sch=fmc_ha_n[03]
+#set_property -dict { PACKAGE_PIN N25   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[03] }]; #IO_L18P_T2_A24_15 Sch=fmc_ha_p[03]
+#set_property -dict { PACKAGE_PIN M25   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[04] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_ha_n[04]
+#set_property -dict { PACKAGE_PIN M24   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[04] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_ha_p[04]
+#set_property -dict { PACKAGE_PIN H29   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[05] }]; #IO_L7N_T1_AD10N_15 Sch=fmc_ha_n[05]
+#set_property -dict { PACKAGE_PIN J29   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[05] }]; #IO_L7P_T1_AD10P_15 Sch=fmc_ha_p[05]
+#set_property -dict { PACKAGE_PIN N30   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[06] }]; #IO_L17N_T2_A25_15 Sch=fmc_ha_n[06]
+#set_property -dict { PACKAGE_PIN N29   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[06] }]; #IO_L17P_T2_A26_15 Sch=fmc_ha_p[06]
+#set_property -dict { PACKAGE_PIN M30   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[07] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_ha_n[07]
+#set_property -dict { PACKAGE_PIN M29   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[07] }]; #IO_L15P_T2_DQS_15 Sch=fmc_ha_p[07]
+#set_property -dict { PACKAGE_PIN J28   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[08] }]; #IO_L8N_T1_AD3N_15 Sch=fmc_ha_n[08]
+#set_property -dict { PACKAGE_PIN J27   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[08] }]; #IO_L8P_T1_AD3P_15 Sch=fmc_ha_p[08]
+#set_property -dict { PACKAGE_PIN K30   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[09] }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fmc_ha_n[09]
+#set_property -dict { PACKAGE_PIN L30   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[09] }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fmc_ha_p[09]
+#set_property -dict { PACKAGE_PIN N22   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[10] }]; #IO_L20N_T3_A19_15 Sch=fmc_ha_n[10]
+#set_property -dict { PACKAGE_PIN N21   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[10] }]; #IO_L20P_T3_A20_15 Sch=fmc_ha_p[10]
+#set_property -dict { PACKAGE_PIN N24   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[11] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_ha_n[11]
+#set_property -dict { PACKAGE_PIN P23   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[11] }]; #IO_L21P_T3_DQS_15 Sch=fmc_ha_p[11]
+#set_property -dict { PACKAGE_PIN L27   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[12] }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=fmc_ha_n[12]
+#set_property -dict { PACKAGE_PIN L26   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[12] }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=fmc_ha_p[12]
+#set_property -dict { PACKAGE_PIN J26   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[13] }]; #IO_L10N_T1_AD4N_15 Sch=fmc_ha_n[13]
+#set_property -dict { PACKAGE_PIN K26   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[13] }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13]
+#set_property -dict { PACKAGE_PIN M27   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[14] }]; #IO_L16N_T2_A27_15 Sch=fmc_ha_n[14]
+#set_property -dict { PACKAGE_PIN N27   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[14] }]; #IO_L16P_T2_A28_15 Sch=fmc_ha_p[14]
+#set_property -dict { PACKAGE_PIN J22   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[15] }]; #IO_L5N_T0_AD2N_15 Sch=fmc_ha_n[15]
+#set_property -dict { PACKAGE_PIN J21   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[15] }]; #IO_L5P_T0_AD2P_15 Sch=fmc_ha_p[15]
+#set_property -dict { PACKAGE_PIN M23   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[16] }]; #IO_L24N_T3_RS0_15 Sch=fmc_ha_n[16]
+#set_property -dict { PACKAGE_PIN M22   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[16] }]; #IO_L24P_T3_RS1_15 Sch=fmc_ha_p[16]
+#set_property -dict { PACKAGE_PIN B25   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[17] }]; #IO_L12N_T1_MRCC_16 Sch=fmc_ha_n[17]
+#set_property -dict { PACKAGE_PIN C25   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[17] }]; #IO_L12P_T1_MRCC_16 Sch=fmc_ha_p[17]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[18] }]; #IO_L14N_T2_SRCC_17 Sch=fmc_ha_n[18]
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[18] }]; #IO_L14P_T2_SRCC_17 Sch=fmc_ha_p[18]
+#set_property -dict { PACKAGE_PIN F30   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[19] }]; #IO_L22N_T3_16 Sch=fmc_ha_n[19]
+#set_property -dict { PACKAGE_PIN G29   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[19] }]; #IO_L22P_T3_16 Sch=fmc_ha_p[19]
+#set_property -dict { PACKAGE_PIN F27   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[20] }]; #IO_L21N_T3_DQS_16 Sch=fmc_ha_n[20]
+#set_property -dict { PACKAGE_PIN G27   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[20] }]; #IO_L21P_T3_DQS_16 Sch=fmc_ha_p[20]
+#set_property -dict { PACKAGE_PIN F28   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[21] }]; #IO_L20N_T3_16 Sch=fmc_ha_n[21]
+#set_property -dict { PACKAGE_PIN G28   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[21] }]; #IO_L20P_T3_16 Sch=fmc_ha_p[21]
+#set_property -dict { PACKAGE_PIN C21   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[22] }]; #IO_L8N_T1_17 Sch=fmc_ha_n[22]
+#set_property -dict { PACKAGE_PIN D21   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[22] }]; #IO_L8P_T1_17 Sch=fmc_ha_p[22]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[23] }]; #IO_L16N_T2_17 Sch=fmc_ha_n[23]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[23] }]; #IO_L16P_T2_17 Sch=fmc_ha_p[23]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[00] }]; #IO_L12N_T1_MRCC_18 Sch=fmc_hb_n[00]
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[00] }]; #IO_L12P_T1_MRCC_18 Sch=fmc_hb_p[00]
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[01] }]; #IO_L7N_T1_18 Sch=fmc_hb_n[01]
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[01] }]; #IO_L7P_T1_18 Sch=fmc_hb_p[01]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[02] }]; #IO_L2N_T0_18 Sch=fmc_hb_n[02]
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[02] }]; #IO_L2P_T0_18 Sch=fmc_hb_p[02]
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[03] }]; #IO_L11N_T1_SRCC_18 Sch=fmc_hb_n[03]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[03] }]; #IO_L11P_T1_SRCC_18 Sch=fmc_hb_p[03]
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[04] }]; #IO_L9N_T1_DQS_18 Sch=fmc_hb_n[04]
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[04] }]; #IO_L9P_T1_DQS_18 Sch=fmc_hb_p[04]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[05] }]; #IO_L1N_T0_18 Sch=fmc_hb_n[05]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[05] }]; #IO_L1P_T0_18 Sch=fmc_hb_p[05]
+#set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[06] }]; #IO_L14N_T2_SRCC_18 Sch=fmc_hb_n[06]
+#set_property -dict { PACKAGE_PIN F12   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[06] }]; #IO_L14P_T2_SRCC_18 Sch=fmc_hb_p[06]
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[07] }]; #IO_L22N_T3_18 Sch=fmc_hb_n[07]
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[07] }]; #IO_L22P_T3_18 Sch=fmc_hb_p[07]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[08] }]; #IO_L5N_T0_18 Sch=fmc_hb_n[08]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[08] }]; #IO_L5P_T0_18 Sch=fmc_hb_p[08]
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[09] }]; #IO_L23N_T3_18 Sch=fmc_hb_n[09]
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[09] }]; #IO_L23P_T3_18 Sch=fmc_hb_p[09]
+#set_property -dict { PACKAGE_PIN J12   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[10] }]; #IO_L8N_T1_18 Sch=fmc_hb_n[10]
+#set_property -dict { PACKAGE_PIN J11   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[10] }]; #IO_L8P_T1_18 Sch=fmc_hb_p[10]
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[11] }]; #IO_L18N_T2_18 Sch=fmc_hb_n[11]
+#set_property -dict { PACKAGE_PIN D11   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[11] }]; #IO_L18P_T2_18 Sch=fmc_hb_p[11]
+#set_property -dict { PACKAGE_PIN A12   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[12] }]; #IO_L17N_T2_18 Sch=fmc_hb_n[12]
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[12] }]; #IO_L17P_T2_18 Sch=fmc_hb_p[12]
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[13] }]; #IO_L15N_T2_DQS_18 Sch=fmc_hb_n[13]
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[13] }]; #IO_L15P_T2_DQS_18 Sch=fmc_hb_p[13]
+#set_property -dict { PACKAGE_PIN H12   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[14] }]; #IO_L10N_T1_18 Sch=fmc_hb_n[14]
+#set_property -dict { PACKAGE_PIN H11   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[14] }]; #IO_L10P_T1_18 Sch=fmc_hb_p[14]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[15] }]; #IO_L3N_T0_DQS_18 Sch=fmc_hb_n[15]
+#set_property -dict { PACKAGE_PIN L12   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[15] }]; #IO_L3P_T0_DQS_18 Sch=fmc_hb_p[15]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[16] }]; #IO_L4N_T0_18 Sch=fmc_hb_n[16]
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[16] }]; #IO_L4P_T0_18 Sch=fmc_hb_p[16]
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[17] }]; #IO_L13N_T2_MRCC_18 Sch=fmc_hb_n[17]
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[17] }]; #IO_L13P_T2_MRCC_18 Sch=fmc_hb_p[17]
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[18] }]; #IO_L20N_T3_18 Sch=fmc_hb_n[18]
+#set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[18] }]; #IO_L20P_T3_18 Sch=fmc_hb_p[18]
+#set_property -dict { PACKAGE_PIN E11   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[19] }]; #IO_L16N_T2_18 Sch=fmc_hb_n[19]
+#set_property -dict { PACKAGE_PIN F11   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[19] }]; #IO_L16P_T2_18 Sch=fmc_hb_p[19]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[20] }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20]
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[20] }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20]
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[21] }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21]
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[21] }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21]
+#set_property -dict { PACKAGE_PIN C27   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[00] }]; #IO_L13N_T2_MRCC_16 Sch=fmc_la_n[00]
+#set_property -dict { PACKAGE_PIN D27   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[00] }]; #IO_L13P_T2_MRCC_16 Sch=fmc_la_p[00]
+#set_property -dict { PACKAGE_PIN C26   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[01] }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la_n[01]
+#set_property -dict { PACKAGE_PIN D26   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[01] }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la_p[01]
+#set_property -dict { PACKAGE_PIN G30   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L24N_T3_16 Sch=fmc_la_n[02]
+#set_property -dict { PACKAGE_PIN H30   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L24P_T3_16 Sch=fmc_la_p[02]
+#set_property -dict { PACKAGE_PIN E30   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L18N_T2_16 Sch=fmc_la_n[03]
+#set_property -dict { PACKAGE_PIN E29   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L18P_T2_16 Sch=fmc_la_p[03]
+#set_property -dict { PACKAGE_PIN H27   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L23N_T3_16 Sch=fmc_la_n[04]
+#set_property -dict { PACKAGE_PIN H26   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L23P_T3_16 Sch=fmc_la_p[04]
+#set_property -dict { PACKAGE_PIN A30   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L17N_T2_16 Sch=fmc_la_n[05]
+#set_property -dict { PACKAGE_PIN B30   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L17P_T2_16 Sch=fmc_la_p[05]
+#set_property -dict { PACKAGE_PIN C30   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L16N_T2_16 Sch=fmc_la_n[06]
+#set_property -dict { PACKAGE_PIN D29   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L16P_T2_16 Sch=fmc_la_p[06]
+#set_property -dict { PACKAGE_PIN E25   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[07]
+#set_property -dict { PACKAGE_PIN F25   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[07]
+#set_property -dict { PACKAGE_PIN B29   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[08]
+#set_property -dict { PACKAGE_PIN C29   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[08]
+#set_property -dict { PACKAGE_PIN A28   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[09]
+#set_property -dict { PACKAGE_PIN B28   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[09]
+#set_property -dict { PACKAGE_PIN A27   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L7N_T1_16 Sch=fmc_la_n[10]
+#set_property -dict { PACKAGE_PIN B27   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L7P_T1_16 Sch=fmc_la_p[10]
+#set_property -dict { PACKAGE_PIN A26   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L10N_T1_16 Sch=fmc_la_n[11]
+#set_property -dict { PACKAGE_PIN A25   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L10P_T1_16 Sch=fmc_la_p[11]
+#set_property -dict { PACKAGE_PIN E26   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L5N_T0_16 Sch=fmc_la_n[12]
+#set_property -dict { PACKAGE_PIN F26   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L5P_T0_16 Sch=fmc_la_p[12]
+#set_property -dict { PACKAGE_PIN D24   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L4N_T0_16 Sch=fmc_la_n[13]
+#set_property -dict { PACKAGE_PIN E24   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L4P_T0_16 Sch=fmc_la_p[13]
+#set_property -dict { PACKAGE_PIN B24   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L8N_T1_16 Sch=fmc_la_n[14]
+#set_property -dict { PACKAGE_PIN C24   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L8P_T1_16 Sch=fmc_la_p[14]
+#set_property -dict { PACKAGE_PIN A23   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L1N_T0_16 Sch=fmc_la_n[15]
+#set_property -dict { PACKAGE_PIN B23   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L1P_T0_16 Sch=fmc_la_p[15]
+#set_property -dict { PACKAGE_PIN D23   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L2N_T0_16 Sch=fmc_la_n[16]
+#set_property -dict { PACKAGE_PIN E23   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L2P_T0_16 Sch=fmc_la_p[16]
+#set_property -dict { PACKAGE_PIN E21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[17] }]; #IO_L11N_T1_SRCC_17 Sch=fmc_la_n[17]
+#set_property -dict { PACKAGE_PIN F21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[17] }]; #IO_L11P_T1_SRCC_17 Sch=fmc_la_p[17]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[18] }]; #IO_L13N_T2_MRCC_17 Sch=fmc_la_n[18]
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[18] }]; #IO_L13P_T2_MRCC_17 Sch=fmc_la_p[18]
+#set_property -dict { PACKAGE_PIN H22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L7N_T1_17 Sch=fmc_la_n[19]
+#set_property -dict { PACKAGE_PIN H21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L7P_T1_17 Sch=fmc_la_p[19]
+#set_property -dict { PACKAGE_PIN F22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L9N_T1_DQS_17 Sch=fmc_la_n[20]
+#set_property -dict { PACKAGE_PIN G22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L9P_T1_DQS_17 Sch=fmc_la_p[20]
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L5N_T0_17 Sch=fmc_la_n[21]
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L5P_T0_17 Sch=fmc_la_p[21]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0_DQS_17 Sch=fmc_la_n[22]
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0_DQS_17 Sch=fmc_la_p[22]
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L18N_T2_17 Sch=fmc_la_n[23]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L18P_T2_17 Sch=fmc_la_p[23]
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L2N_T0_17 Sch=fmc_la_n[24]
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L2P_T0_17 Sch=fmc_la_p[24]
+#set_property -dict { PACKAGE_PIN C22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L10N_T1_17 Sch=fmc_la_n[25]
+#set_property -dict { PACKAGE_PIN D22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L10P_T1_17 Sch=fmc_la_p[25]
+#set_property -dict { PACKAGE_PIN A22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L23N_T3_17 Sch=fmc_la_n[26]
+#set_property -dict { PACKAGE_PIN B22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L23P_T3_17 Sch=fmc_la_p[26]
+#set_property -dict { PACKAGE_PIN A21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L21N_T3_DQS_17 Sch=fmc_la_n[27]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L21P_T3_DQS_17 Sch=fmc_la_p[27]
+#set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L4N_T0_17 Sch=fmc_la_n[28]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L4P_T0_17 Sch=fmc_la_p[28]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L22N_T3_17 Sch=fmc_la_n[29]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L22P_T3_17 Sch=fmc_la_p[29]
+#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L20N_T3_17 Sch=fmc_la_n[30]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L20P_T3_17 Sch=fmc_la_p[30]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L17N_T2_17 Sch=fmc_la_n[31]
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L17P_T2_17 Sch=fmc_la_p[31]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L1N_T0_17 Sch=fmc_la_n[32]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L1P_T0_17 Sch=fmc_la_p[32]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L15N_T2_DQS_17 Sch=fmc_la_n[33]
+#set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L15P_T2_DQS_17 Sch=fmc_la_p[33]
+#set_property -dict { PACKAGE_PIN AC24  IOSTANDARD LVCMOS33 } [get_ports { FMC_SCL }]; #IO_L9P_T1_DQS_12 Sch=fmc_scl
+#set_property -dict { PACKAGE_PIN AD24  IOSTANDARD LVCMOS33 } [get_ports { FMC_SDA }]; #IO_L9N_T1_DQS_12 Sch=fmc_sda
+
+## Fan Control
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { FAN_PWM }]; #IO_25_14 Sch=fan_pwm
+#set_property -dict { PACKAGE_PIN V21   IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tach
+
+## DPTI
+## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins.
+#set_property -dict { PACKAGE_PIN AB27  IOSTANDARD LVCMOS33 } [get_ports { PROG_CLKO }]; #IO_L12P_T1_MRCC_13 Sch=prog_clko
+#set_property -dict { PACKAGE_PIN AD27  IOSTANDARD LVCMOS33 } [get_ports { PROG_D[0] }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck
+#set_property -dict { PACKAGE_PIN W27   IOSTANDARD LVCMOS33 } [get_ports { PROG_D[1] }]; #IO_L2P_T0_13 Sch=prog_d1/mosi
+#set_property -dict { PACKAGE_PIN W28   IOSTANDARD LVCMOS33 } [get_ports { PROG_D[2] }]; #IO_L2N_T0_13 Sch=prog_d2/miso
+#set_property -dict { PACKAGE_PIN W29   IOSTANDARD LVCMOS33 } [get_ports { PROG_D[3] }]; #IO_L4P_T0_13 Sch=prog_d3/ss
+#set_property -dict { PACKAGE_PIN Y29   IOSTANDARD LVCMOS33 } [get_ports { PROG_D[4] }]; #IO_L4N_T0_13 Sch=prog_d[4]
+#set_property -dict { PACKAGE_PIN Y28   IOSTANDARD LVCMOS33 } [get_ports { PROG_D[5] }]; #IO_L3P_T0_DQS_13 Sch=prog_d[5]
+#set_property -dict { PACKAGE_PIN AA28  IOSTANDARD LVCMOS33 } [get_ports { PROG_D[6] }]; #IO_L3N_T0_DQS_13 Sch=prog_d[6]
+#set_property -dict { PACKAGE_PIN AA26  IOSTANDARD LVCMOS33 } [get_ports { PROG_D[7] }]; #IO_L1N_T0_13 Sch=prog_d[7]
+#set_property -dict { PACKAGE_PIN AC30  IOSTANDARD LVCMOS33 } [get_ports { PROG_OEN }]; #IO_L7N_T1_13 Sch=prog_oen
+#set_property -dict { PACKAGE_PIN AB25  IOSTANDARD LVCMOS33 } [get_ports { PROG_RDN }]; #IO_L6N_T0_VREF_13 Sch=prog_rdn
+#set_property -dict { PACKAGE_PIN AB29  IOSTANDARD LVCMOS33 } [get_ports { PROG_RXFN }]; #IO_L10P_T1_13 Sch=prog_rxfn
+#set_property -dict { PACKAGE_PIN AB28  IOSTANDARD LVCMOS33 } [get_ports { PROG_SIWUN }]; #IO_L5N_T0_13 Sch=prog_siwun
+#set_property -dict { PACKAGE_PIN AD29  IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien
+#set_property -dict { PACKAGE_PIN AA25  IOSTANDARD LVCMOS33 } [get_ports { PROG_TXEN }]; #IO_L6P_T0_13 Sch=prog_txen
+#set_property -dict { PACKAGE_PIN AC27  IOSTANDARD LVCMOS33 } [get_ports { PROG_WRN }]; #IO_L12N_T1_MRCC_13 Sch=prog_wrn
+
+## DSPI
+## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins.
+#set_property -dict { PACKAGE_PIN AD29  IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien
+#set_property -dict { PACKAGE_PIN AD27  IOSTANDARD LVCMOS33 } [get_ports { PROG_SCK }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck
+#set_property -dict { PACKAGE_PIN W27   IOSTANDARD LVCMOS33 } [get_ports { PROG_MOSI }]; #IO_L2P_T0_13 Sch=prog_d1/mosi
+#set_property -dict { PACKAGE_PIN W28   IOSTANDARD LVCMOS33 } [get_ports { PROG_MISO }]; #IO_L2N_T0_13 Sch=prog_d2/miso
+#set_property -dict { PACKAGE_PIN W29   IOSTANDARD LVCMOS33 } [get_ports { PROG_SS }]; #IO_L4P_T0_13 Sch=prog_d3/ss
+
+## QSPI
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
+#set_property -dict { PACKAGE_PIN P24   IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0]
+#set_property -dict { PACKAGE_PIN R25   IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1]
+#set_property -dict { PACKAGE_PIN R20   IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2]
+#set_property -dict { PACKAGE_PIN R21   IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3]
+
+## IIC Bus
+#set_property -dict { PACKAGE_PIN AE30  IOSTANDARD LVCMOS33 } [get_ports { SYS_SCL }]; #IO_L16P_T2_13 Sch=sys_scl
+#set_property -dict { PACKAGE_PIN AF30  IOSTANDARD LVCMOS33 } [get_ports { SYS_SDA }]; #IO_L16N_T2_13 Sch=sys_sda
+
+## Display Port IN
+#set_property -dict { PACKAGE_PIN AC19  IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_N }]; #IO_L17N_T2_32 Sch=rx_aux_ch_n
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_N }]; #IO_L15N_T2_DQS_32 Sch=rx_aux_ch_n
+#set_property -dict { PACKAGE_PIN AB19  IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_P }]; #IO_L17P_T2_32 Sch=rx_aux_ch_p
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_P }]; #IO_L15P_T2_DQS_32 Sch=rx_aux_ch_p
+#set_property -dict { PACKAGE_PIN AE21  IOSTANDARD LVCMOS33 } [get_ports { RX_HPD }]; #IO_L10N_T1_12 Sch=rx_hpd
+
+## Display Port OUT
+#set_property -dict { PACKAGE_PIN AD16  IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_N }]; #IO_L14N_T2_SRCC_32 Sch=tx_aux_ch_n
+#set_property -dict { PACKAGE_PIN AB18  IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_N }]; #IO_L16N_T2_32 Sch=tx_aux_ch_n
+#set_property -dict { PACKAGE_PIN AA18  IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_P }]; #IO_L16P_T2_32 Sch=tx_aux_ch_p
+#set_property -dict { PACKAGE_PIN AD17  IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_P }]; #IO_L14P_T2_SRCC_32 Sch=tx_aux_ch_p
+#set_property -dict { PACKAGE_PIN AD21  IOSTANDARD LVCMOS33 } [get_ports { TX_HPD }]; #IO_L10P_T1_12 Sch=tx_hpd
+
+## USB
+#set_property -dict { PACKAGE_PIN AD18  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_CLK }]; #IO_L13P_T2_MRCC_32 Sch=usb_otg_clk
+#set_property -dict { PACKAGE_PIN AE14  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[0] }]; #IO_L19N_T3_VREF_32 Sch=usb_otg_d[0]
+#set_property -dict { PACKAGE_PIN AE15  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[1] }]; #IO_L19P_T3_32 Sch=usb_otg_d[1]
+#set_property -dict { PACKAGE_PIN AC15  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[2] }]; #IO_L21N_T3_DQS_32 Sch=usb_otg_d[2]
+#set_property -dict { PACKAGE_PIN AC16  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[3] }]; #IO_L21P_T3_DQS_32 Sch=usb_otg_d[3]
+#set_property -dict { PACKAGE_PIN AB15  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[4] }]; #IO_L20N_T3_32 Sch=usb_otg_d[4]
+#set_property -dict { PACKAGE_PIN AA15  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[5] }]; #IO_L20P_T3_32 Sch=usb_otg_d[5]
+#set_property -dict { PACKAGE_PIN AD14  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[6] }]; #IO_L22N_T3_32 Sch=usb_otg_d[6]
+#set_property -dict { PACKAGE_PIN AC14  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[7] }]; #IO_L22P_T3_32 Sch=usb_otg_d[7]
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_DIR }]; #IO_L24P_T3_32 Sch=usb_otg_dir
+#set_property -dict { PACKAGE_PIN AA16  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_NXT }]; #IO_L23N_T3_32 Sch=usb_otg_nxt
+#set_property -dict { PACKAGE_PIN AB14  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_RESETB }]; #IO_25_VRP_32 Sch=usb_otg_resetb
+#set_property -dict { PACKAGE_PIN AA17  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_STP }]; #IO_L23P_T3_32 Sch=usb_otg_stp
+#set_property -dict { PACKAGE_PIN AF16  IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_VBUSOC }]; #IO_L6N_T0_VREF_32 Sch=usb_otg_vbusoc
+
diff --git a/Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-D-Master.xdc b/Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-D-Master.xdc
new file mode 100644
index 0000000..e08cf29
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-D-Master.xdc
@@ -0,0 +1,272 @@
+#### This file is a general .xdc for the Genesys ZU-3EG Rev. D
+#### To use it in a project:
+#### - uncomment the lines corresponding to used pins
+#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+#set_property DCI_CASCADE {64} [get_iobanks 65]
+
+## Crypto
+#set_property -dict { PACKAGE_PIN AD15  IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
+
+# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
+# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
+# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
+# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
+# Might need CLOCK_DEDICATED_ROUTE FALSE
+#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
+
+## MIPI A Port
+#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
+## Commented, since it will be defined in IP XDC.
+##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
+##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
+##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
+
+## MIPI B Port
+#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
+## Commented, since it will be defined in IP XDC.
+##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
+##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
+##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
+
+## Audio CODEC I2S, I2C
+#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
+#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
+#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
+#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
+#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
+#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
+#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
+
+## PMOD XADC
+## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
+#set_property -dict { PACKAGE_PIN Y10   IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
+#set_property -dict { PACKAGE_PIN W10   IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
+#set_property -dict { PACKAGE_PIN AA10  IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
+#set_property -dict { PACKAGE_PIN AA11  IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
+#set_property -dict { PACKAGE_PIN AB9   IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
+#set_property -dict { PACKAGE_PIN AB10  IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
+#set_property -dict { PACKAGE_PIN AA8   IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
+#set_property -dict { PACKAGE_PIN Y9    IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
+
+## Platform MCU signals
+#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
+#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
+#set_property -dict { PACKAGE_PIN G10  IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
+#set_property -dict { PACKAGE_PIN H11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
+
+##DisplayPort AUX channel over EMIO
+#set_property -dict { PACKAGE_PIN K12  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
+#set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
+#set_property -dict { PACKAGE_PIN J11  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
+#set_property -dict { PACKAGE_PIN J10  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
+
+## Mini PCIe Auxiliary
+#set_property -dict { PACKAGE_PIN Y12  IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
+#set_property -dict { PACKAGE_PIN B3  IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }];  #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
+
+## USB 2.0 Overcurrent EMIO
+#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
+
+## Ethernet JTAG
+#set_property -dict { PACKAGE_PIN F7  LVCMOS12  } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
+#set_property -dict { PACKAGE_PIN F8  LVCMOS12  } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
+#set_property -dict { PACKAGE_PIN E8  LVCMOS12  } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
+#set_property -dict { PACKAGE_PIN E9  LVCMOS12  } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
+
+## PMOD JB
+#set_property -dict { PACKAGE_PIN AE13  IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN AG14  IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN AH14  IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN AG13  IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN AE14  IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN AF13  IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN AE15  IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
+#set_property -dict { PACKAGE_PIN AH13  IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
+
+## PMOD JC
+#set_property -dict { PACKAGE_PIN E13  IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN G13  IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN B13  IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN D14  IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN F13  IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN C13  IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN C14  IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN A13  IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
+
+## PMOD JD
+#set_property -dict {PACKAGE_PIN E15  IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
+#set_property -dict {PACKAGE_PIN A14  IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
+#set_property -dict {PACKAGE_PIN B15  IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
+#set_property -dict {PACKAGE_PIN F15  IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
+#set_property -dict {PACKAGE_PIN E14  IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
+#set_property -dict {PACKAGE_PIN B14  IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
+#set_property -dict {PACKAGE_PIN D15  IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
+#set_property -dict {PACKAGE_PIN A15  IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN B10  IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN H12  IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
+#set_property -dict { PACKAGE_PIN J12  IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
+#set_property -dict { PACKAGE_PIN F12  IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
+#set_property -dict { PACKAGE_PIN A12  IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
+
+## Switches
+#set_property -dict { PACKAGE_PIN AB14  IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN W12   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN AB15  IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
+
+## LED
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
+
+## RGB LED
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
+
+## GTH reference clock jitter filter auxiliary
+#set_property -dict { PACKAGE_PIN C4  IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
+#set_property -dict { PACKAGE_PIN D6  IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
+#set_property -dict { PACKAGE_PIN G8  IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
+
+## MUX I2C
+#set_property -dict { PACKAGE_PIN F6   IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
+#set_property -dict { PACKAGE_PIN G15  IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
+#set_property -dict { PACKAGE_PIN G14  IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
+
+## SYZYGY
+#set_property -dict { PACKAGE_PIN AB1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
+#set_property -dict { PACKAGE_PIN AE2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
+#set_property -dict { PACKAGE_PIN AE3  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
+#set_property -dict { PACKAGE_PIN AE5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
+#set_property -dict { PACKAGE_PIN AD7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
+#set_property -dict { PACKAGE_PIN AG6  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
+#set_property -dict { PACKAGE_PIN U8   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }];  #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
+#set_property -dict { PACKAGE_PIN U9   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
+#set_property -dict { PACKAGE_PIN AC1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
+#set_property -dict { PACKAGE_PIN AF2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
+#set_property -dict { PACKAGE_PIN AF3  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
+#set_property -dict { PACKAGE_PIN AF5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
+#set_property -dict { PACKAGE_PIN AE7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
+#set_property -dict { PACKAGE_PIN AG5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
+#set_property -dict { PACKAGE_PIN V8   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }];  #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
+#set_property -dict { PACKAGE_PIN V9   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
+#set_property -dict { PACKAGE_PIN AE10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
+#set_property -dict { PACKAGE_PIN AC12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
+#set_property -dict { PACKAGE_PIN AF10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
+#set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
+#set_property -dict { PACKAGE_PIN AF11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
+#set_property -dict { PACKAGE_PIN AE12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
+#set_property -dict { PACKAGE_PIN AF12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
+#set_property -dict { PACKAGE_PIN AH12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
+#set_property -dict { PACKAGE_PIN AG11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
+#set_property -dict { PACKAGE_PIN AG10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
+#set_property -dict { PACKAGE_PIN AH11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
+#set_property -dict { PACKAGE_PIN AH10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
+#set_property -dict { PACKAGE_PIN AD4   IOSTANDARD LVDS   DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
+#set_property -dict { PACKAGE_PIN AD5   IOSTANDARD LVDS   DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
+#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
+#set_property -dict { PACKAGE_PIN W8    IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
+
+## FMC connector
+#set_property -dict { PACKAGE_PIN M6   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
+#set_property -dict { PACKAGE_PIN L3   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
+#set_property -dict { PACKAGE_PIN L6   IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
+#set_property -dict { PACKAGE_PIN L7   IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
+#set_property -dict { PACKAGE_PIN H3   IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
+#set_property -dict { PACKAGE_PIN H4   IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
+#set_property -dict { PACKAGE_PIN H6   IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
+#set_property -dict { PACKAGE_PIN J6   IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
+#set_property -dict { PACKAGE_PIN K3   IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
+#set_property -dict { PACKAGE_PIN K4   IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
+#set_property -dict { PACKAGE_PIN J2   IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
+#set_property -dict { PACKAGE_PIN K2   IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
+#set_property -dict { PACKAGE_PIN T6   IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
+#set_property -dict { PACKAGE_PIN R6   IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
+#set_property -dict { PACKAGE_PIN K1   IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
+#set_property -dict { PACKAGE_PIN L1   IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
+#set_property -dict { PACKAGE_PIN J9   IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
+#set_property -dict { PACKAGE_PIN K9   IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
+#set_property -dict { PACKAGE_PIN T7   IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
+#set_property -dict { PACKAGE_PIN R7   IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
+#set_property -dict { PACKAGE_PIN L8   IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
+#set_property -dict { PACKAGE_PIN M8   IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
+#set_property -dict { PACKAGE_PIN H1   IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
+#set_property -dict { PACKAGE_PIN J1   IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
+#set_property -dict { PACKAGE_PIN J4   IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
+#set_property -dict { PACKAGE_PIN J5   IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
+#set_property -dict { PACKAGE_PIN H7   IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
+#set_property -dict { PACKAGE_PIN J7   IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
+#set_property -dict { PACKAGE_PIN N6   IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
+#set_property -dict { PACKAGE_PIN N7   IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
+#set_property -dict { PACKAGE_PIN P6   IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
+#set_property -dict { PACKAGE_PIN P7   IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
+#set_property -dict { PACKAGE_PIN T8   IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
+#set_property -dict { PACKAGE_PIN R8   IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
+#set_property -dict { PACKAGE_PIN K7   IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
+#set_property -dict { PACKAGE_PIN K8   IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
+#set_property -dict { PACKAGE_PIN AD1  IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
+#set_property -dict { PACKAGE_PIN AD2  IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
+#set_property -dict { PACKAGE_PIN AH9  IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
+#set_property -dict { PACKAGE_PIN AG9  IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
+#set_property -dict { PACKAGE_PIN AC3  IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
+#set_property -dict { PACKAGE_PIN AC4  IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
+#set_property -dict { PACKAGE_PIN AB3  IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
+#set_property -dict { PACKAGE_PIN AB4  IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
+#set_property -dict { PACKAGE_PIN AG1  IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
+#set_property -dict { PACKAGE_PIN AF1  IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
+#set_property -dict { PACKAGE_PIN AC8  IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
+#set_property -dict { PACKAGE_PIN AB8  IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
+#set_property -dict { PACKAGE_PIN AH1  IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
+#set_property -dict { PACKAGE_PIN AH2  IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
+#set_property -dict { PACKAGE_PIN AF6  IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
+#set_property -dict { PACKAGE_PIN AF7  IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
+#set_property -dict { PACKAGE_PIN AH3  IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
+#set_property -dict { PACKAGE_PIN AG3  IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
+#set_property -dict { PACKAGE_PIN AD9  IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
+#set_property -dict { PACKAGE_PIN AC9  IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
+#set_property -dict { PACKAGE_PIN AH4  IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
+#set_property -dict { PACKAGE_PIN AG4  IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
+#set_property -dict { PACKAGE_PIN AE8  IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
+#set_property -dict { PACKAGE_PIN AE9  IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
+#set_property -dict { PACKAGE_PIN AH7  IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
+#set_property -dict { PACKAGE_PIN AH8  IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
+#set_property -dict { PACKAGE_PIN AC7  IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
+#set_property -dict { PACKAGE_PIN AB7  IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
+#set_property -dict { PACKAGE_PIN AG8  IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
+#set_property -dict { PACKAGE_PIN AF8  IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
+#set_property -dict { PACKAGE_PIN AC2  IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
+#set_property -dict { PACKAGE_PIN AB2  IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
+#set_property -dict { PACKAGE_PIN AC6  IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
+#set_property -dict { PACKAGE_PIN AB6  IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
+
+#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
+
+## Power-good input for VADJ supply rail
+#set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33 } [get_ports { pg_vadj_r }]; #IO_L12N_AD8N_44/24 Sch=pg_vadj_r
+
+#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
+#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
+
+#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
+
+
+
+
diff --git a/Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-Master.xdc b/Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-Master.xdc
new file mode 100644
index 0000000..09d6462
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-Master.xdc
@@ -0,0 +1,269 @@
+#### This file is a general .xdc for the Genesys ZU-3EG Rev. B
+#### To use it in a project:
+#### - uncomment the lines corresponding to used pins
+#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+#set_property DCI_CASCADE {64} [get_iobanks 65]
+
+## Crypto
+#set_property -dict { PACKAGE_PIN AD15  IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
+
+# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
+# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
+# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
+# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
+# Might need CLOCK_DEDICATED_ROUTE FALSE
+#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
+
+## MIPI A Port
+#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
+## Commented, since it will be defined in IP XDC.
+##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
+##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
+##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
+
+## MIPI B Port
+#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
+## Commented, since it will be defined in IP XDC.
+##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
+##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
+##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
+
+## Audio CODEC I2S, I2C
+#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
+#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
+#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
+#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
+#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
+#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
+#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
+
+## PMOD XADC
+## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
+#set_property -dict { PACKAGE_PIN Y10   IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
+#set_property -dict { PACKAGE_PIN W10   IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
+#set_property -dict { PACKAGE_PIN AA10  IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
+#set_property -dict { PACKAGE_PIN AA11  IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
+#set_property -dict { PACKAGE_PIN AB9   IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
+#set_property -dict { PACKAGE_PIN AB10  IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
+#set_property -dict { PACKAGE_PIN AA8   IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
+#set_property -dict { PACKAGE_PIN Y9    IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
+
+## Platform MCU signals
+#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
+#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
+#set_property -dict { PACKAGE_PIN G10  IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
+#set_property -dict { PACKAGE_PIN H11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
+
+##DisplayPort AUX channel over EMIO
+#set_property -dict { PACKAGE_PIN K12  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
+#set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
+#set_property -dict { PACKAGE_PIN J11  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
+#set_property -dict { PACKAGE_PIN J10  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
+
+## Mini PCIe Auxiliary
+#set_property -dict { PACKAGE_PIN Y12  IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
+#set_property -dict { PACKAGE_PIN B3  IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }];  #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
+
+## USB 2.0 Overcurrent EMIO
+#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
+
+## Ethernet JTAG
+#set_property -dict { PACKAGE_PIN F7  LVCMOS12  } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
+#set_property -dict { PACKAGE_PIN F8  LVCMOS12  } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
+#set_property -dict { PACKAGE_PIN E8  LVCMOS12  } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
+#set_property -dict { PACKAGE_PIN E9  LVCMOS12  } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
+
+## PMOD JB
+#set_property -dict { PACKAGE_PIN AE13  IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN AG14  IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN AH14  IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN AG13  IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN AE14  IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN AF13  IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN AE15  IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
+#set_property -dict { PACKAGE_PIN AH13  IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
+
+## PMOD JC
+#set_property -dict { PACKAGE_PIN E13  IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN G13  IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN B13  IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN D14  IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN F13  IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN C13  IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN C14  IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN A13  IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
+
+## PMOD JD
+#set_property -dict {PACKAGE_PIN E15  IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
+#set_property -dict {PACKAGE_PIN A14  IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
+#set_property -dict {PACKAGE_PIN B15  IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
+#set_property -dict {PACKAGE_PIN F15  IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
+#set_property -dict {PACKAGE_PIN E14  IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
+#set_property -dict {PACKAGE_PIN B14  IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
+#set_property -dict {PACKAGE_PIN D15  IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
+#set_property -dict {PACKAGE_PIN A15  IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN B10  IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN H12  IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
+#set_property -dict { PACKAGE_PIN J12  IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
+#set_property -dict { PACKAGE_PIN F12  IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
+#set_property -dict { PACKAGE_PIN A12  IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
+
+## Switches
+#set_property -dict { PACKAGE_PIN AB14  IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN W12   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN AB15  IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
+
+## LED
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
+
+## RGB LED
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
+
+## GTH reference clock jitter filter auxiliary
+#set_property -dict { PACKAGE_PIN C4  IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
+#set_property -dict { PACKAGE_PIN D6  IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
+#set_property -dict { PACKAGE_PIN G8  IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
+
+## MUX I2C
+#set_property -dict { PACKAGE_PIN F6   IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
+#set_property -dict { PACKAGE_PIN G15  IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
+#set_property -dict { PACKAGE_PIN G14  IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
+
+## SYZYGY
+#set_property -dict { PACKAGE_PIN AB1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
+#set_property -dict { PACKAGE_PIN AE2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
+#set_property -dict { PACKAGE_PIN AE3  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
+#set_property -dict { PACKAGE_PIN AE5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
+#set_property -dict { PACKAGE_PIN AD7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
+#set_property -dict { PACKAGE_PIN AG6  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
+#set_property -dict { PACKAGE_PIN U8   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }];  #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
+#set_property -dict { PACKAGE_PIN U9   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
+#set_property -dict { PACKAGE_PIN AC1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
+#set_property -dict { PACKAGE_PIN AF2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
+#set_property -dict { PACKAGE_PIN AF3  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
+#set_property -dict { PACKAGE_PIN AF5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
+#set_property -dict { PACKAGE_PIN AE7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
+#set_property -dict { PACKAGE_PIN AG5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
+#set_property -dict { PACKAGE_PIN V8   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }];  #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
+#set_property -dict { PACKAGE_PIN V9   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
+#set_property -dict { PACKAGE_PIN AE10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
+#set_property -dict { PACKAGE_PIN AC12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
+#set_property -dict { PACKAGE_PIN AF10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
+#set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
+#set_property -dict { PACKAGE_PIN AF11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
+#set_property -dict { PACKAGE_PIN AE12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
+#set_property -dict { PACKAGE_PIN AF12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
+#set_property -dict { PACKAGE_PIN AH12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
+#set_property -dict { PACKAGE_PIN AG11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
+#set_property -dict { PACKAGE_PIN AG10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
+#set_property -dict { PACKAGE_PIN AH11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
+#set_property -dict { PACKAGE_PIN AH10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
+#set_property -dict { PACKAGE_PIN AD4   IOSTANDARD LVDS   DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
+#set_property -dict { PACKAGE_PIN AD5   IOSTANDARD LVDS   DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
+#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
+#set_property -dict { PACKAGE_PIN W8    IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
+
+## FMC connector
+#set_property -dict { PACKAGE_PIN M6   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
+#set_property -dict { PACKAGE_PIN L3   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
+#set_property -dict { PACKAGE_PIN L6   IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
+#set_property -dict { PACKAGE_PIN L7   IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
+#set_property -dict { PACKAGE_PIN H3   IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
+#set_property -dict { PACKAGE_PIN H4   IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
+#set_property -dict { PACKAGE_PIN H6   IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
+#set_property -dict { PACKAGE_PIN J6   IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
+#set_property -dict { PACKAGE_PIN K3   IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
+#set_property -dict { PACKAGE_PIN K4   IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
+#set_property -dict { PACKAGE_PIN J2   IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
+#set_property -dict { PACKAGE_PIN K2   IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
+#set_property -dict { PACKAGE_PIN T6   IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
+#set_property -dict { PACKAGE_PIN R6   IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
+#set_property -dict { PACKAGE_PIN K1   IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
+#set_property -dict { PACKAGE_PIN L1   IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
+#set_property -dict { PACKAGE_PIN J9   IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
+#set_property -dict { PACKAGE_PIN K9   IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
+#set_property -dict { PACKAGE_PIN T7   IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
+#set_property -dict { PACKAGE_PIN R7   IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
+#set_property -dict { PACKAGE_PIN L8   IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
+#set_property -dict { PACKAGE_PIN M8   IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
+#set_property -dict { PACKAGE_PIN H1   IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
+#set_property -dict { PACKAGE_PIN J1   IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
+#set_property -dict { PACKAGE_PIN J4   IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
+#set_property -dict { PACKAGE_PIN J5   IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
+#set_property -dict { PACKAGE_PIN H7   IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
+#set_property -dict { PACKAGE_PIN J7   IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
+#set_property -dict { PACKAGE_PIN N6   IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
+#set_property -dict { PACKAGE_PIN N7   IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
+#set_property -dict { PACKAGE_PIN P6   IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
+#set_property -dict { PACKAGE_PIN P7   IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
+#set_property -dict { PACKAGE_PIN T8   IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
+#set_property -dict { PACKAGE_PIN R8   IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
+#set_property -dict { PACKAGE_PIN K7   IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
+#set_property -dict { PACKAGE_PIN K8   IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
+#set_property -dict { PACKAGE_PIN AD1  IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
+#set_property -dict { PACKAGE_PIN AD2  IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
+#set_property -dict { PACKAGE_PIN AH9  IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
+#set_property -dict { PACKAGE_PIN AG9  IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
+#set_property -dict { PACKAGE_PIN AC3  IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
+#set_property -dict { PACKAGE_PIN AC4  IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
+#set_property -dict { PACKAGE_PIN AB3  IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
+#set_property -dict { PACKAGE_PIN AB4  IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
+#set_property -dict { PACKAGE_PIN AG1  IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
+#set_property -dict { PACKAGE_PIN AF1  IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
+#set_property -dict { PACKAGE_PIN AC8  IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
+#set_property -dict { PACKAGE_PIN AB8  IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
+#set_property -dict { PACKAGE_PIN AH1  IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
+#set_property -dict { PACKAGE_PIN AH2  IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
+#set_property -dict { PACKAGE_PIN AF6  IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
+#set_property -dict { PACKAGE_PIN AF7  IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
+#set_property -dict { PACKAGE_PIN AH3  IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
+#set_property -dict { PACKAGE_PIN AG3  IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
+#set_property -dict { PACKAGE_PIN AD9  IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
+#set_property -dict { PACKAGE_PIN AC9  IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
+#set_property -dict { PACKAGE_PIN AH4  IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
+#set_property -dict { PACKAGE_PIN AG4  IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
+#set_property -dict { PACKAGE_PIN AE8  IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
+#set_property -dict { PACKAGE_PIN AE9  IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
+#set_property -dict { PACKAGE_PIN AH7  IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
+#set_property -dict { PACKAGE_PIN AH8  IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
+#set_property -dict { PACKAGE_PIN AC7  IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
+#set_property -dict { PACKAGE_PIN AB7  IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
+#set_property -dict { PACKAGE_PIN AG8  IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
+#set_property -dict { PACKAGE_PIN AF8  IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
+#set_property -dict { PACKAGE_PIN AC2  IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
+#set_property -dict { PACKAGE_PIN AB2  IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
+#set_property -dict { PACKAGE_PIN AC6  IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
+#set_property -dict { PACKAGE_PIN AB6  IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
+
+#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
+
+#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
+#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
+
+#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
+
+
+
+
diff --git a/Bibliotheken/digilent-xdc-master/Genesys-ZU-5EV-D-Master.xdc b/Bibliotheken/digilent-xdc-master/Genesys-ZU-5EV-D-Master.xdc
new file mode 100644
index 0000000..62fd046
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Genesys-ZU-5EV-D-Master.xdc
@@ -0,0 +1,272 @@
+#### This file is a general .xdc for the Genesys ZU-5EV Rev. D
+#### To use it in a project:
+#### - uncomment the lines corresponding to used pins
+#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+#set_property DCI_CASCADE {64} [get_iobanks 65]
+
+## Crypto
+#set_property -dict { PACKAGE_PIN AD15  IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
+
+# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
+# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
+# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
+# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
+# Might need CLOCK_DEDICATED_ROUTE FALSE
+#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
+
+## MIPI A Port
+#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
+## Commented, since it will be defined in IP XDC.
+##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
+##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
+##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
+
+## MIPI B Port
+#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
+## Commented, since it will be defined in IP XDC.
+##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
+##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
+##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
+##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
+
+## Audio CODEC I2S, I2C
+#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
+#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
+#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
+#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
+#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
+#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
+#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
+
+## PMOD XADC
+## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
+#set_property -dict { PACKAGE_PIN Y10   IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
+#set_property -dict { PACKAGE_PIN W10   IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
+#set_property -dict { PACKAGE_PIN AA10  IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
+#set_property -dict { PACKAGE_PIN AA11  IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
+#set_property -dict { PACKAGE_PIN AB9   IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
+#set_property -dict { PACKAGE_PIN AB10  IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
+#set_property -dict { PACKAGE_PIN AA8   IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
+#set_property -dict { PACKAGE_PIN Y9    IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
+
+## Platform MCU signals
+#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
+#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
+#set_property -dict { PACKAGE_PIN G10  IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
+#set_property -dict { PACKAGE_PIN H11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
+
+##DisplayPort AUX channel over EMIO
+#set_property -dict { PACKAGE_PIN K12  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
+#set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
+#set_property -dict { PACKAGE_PIN J11  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
+#set_property -dict { PACKAGE_PIN J10  IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
+
+## Mini PCIe Auxiliary
+#set_property -dict { PACKAGE_PIN Y12  IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
+#set_property -dict { PACKAGE_PIN B3  IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }];  #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
+
+## USB 2.0 Overcurrent EMIO
+#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
+
+## Ethernet JTAG
+#set_property -dict { PACKAGE_PIN F7  LVCMOS12  } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
+#set_property -dict { PACKAGE_PIN F8  LVCMOS12  } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
+#set_property -dict { PACKAGE_PIN E8  LVCMOS12  } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
+#set_property -dict { PACKAGE_PIN E9  LVCMOS12  } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
+
+## PMOD JB
+#set_property -dict { PACKAGE_PIN AE13  IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN AG14  IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN AH14  IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN AG13  IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN AE14  IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN AF13  IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN AE15  IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
+#set_property -dict { PACKAGE_PIN AH13  IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
+
+## PMOD JC
+#set_property -dict { PACKAGE_PIN E13  IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN G13  IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN B13  IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN D14  IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN F13  IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN C13  IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN C14  IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN A13  IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
+
+## PMOD JD
+#set_property -dict {PACKAGE_PIN E15  IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
+#set_property -dict {PACKAGE_PIN A14  IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
+#set_property -dict {PACKAGE_PIN B15  IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
+#set_property -dict {PACKAGE_PIN F15  IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
+#set_property -dict {PACKAGE_PIN E14  IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
+#set_property -dict {PACKAGE_PIN B14  IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
+#set_property -dict {PACKAGE_PIN D15  IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
+#set_property -dict {PACKAGE_PIN A15  IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN B10  IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN H12  IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
+#set_property -dict { PACKAGE_PIN J12  IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
+#set_property -dict { PACKAGE_PIN F12  IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
+#set_property -dict { PACKAGE_PIN A12  IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
+
+## Switches
+#set_property -dict { PACKAGE_PIN AB14  IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN W12   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN AB15  IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
+
+## LED
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
+
+## RGB LED
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
+
+## GTH reference clock jitter filter auxiliary
+#set_property -dict { PACKAGE_PIN C4  IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
+#set_property -dict { PACKAGE_PIN D6  IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
+#set_property -dict { PACKAGE_PIN G8  IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
+
+## MUX I2C
+#set_property -dict { PACKAGE_PIN F6   IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
+#set_property -dict { PACKAGE_PIN G15  IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
+#set_property -dict { PACKAGE_PIN G14  IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
+
+## SYZYGY
+#set_property -dict { PACKAGE_PIN AB1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
+#set_property -dict { PACKAGE_PIN AE2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
+#set_property -dict { PACKAGE_PIN AE3  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
+#set_property -dict { PACKAGE_PIN AE5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
+#set_property -dict { PACKAGE_PIN AD7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
+#set_property -dict { PACKAGE_PIN AG6  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
+#set_property -dict { PACKAGE_PIN U8   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }];  #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
+#set_property -dict { PACKAGE_PIN U9   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
+#set_property -dict { PACKAGE_PIN AC1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
+#set_property -dict { PACKAGE_PIN AF2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
+#set_property -dict { PACKAGE_PIN AF3  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
+#set_property -dict { PACKAGE_PIN AF5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
+#set_property -dict { PACKAGE_PIN AE7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
+#set_property -dict { PACKAGE_PIN AG5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
+#set_property -dict { PACKAGE_PIN V8   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }];  #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
+#set_property -dict { PACKAGE_PIN V9   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
+#set_property -dict { PACKAGE_PIN AE10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
+#set_property -dict { PACKAGE_PIN AC12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
+#set_property -dict { PACKAGE_PIN AF10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
+#set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
+#set_property -dict { PACKAGE_PIN AF11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
+#set_property -dict { PACKAGE_PIN AE12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
+#set_property -dict { PACKAGE_PIN AF12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
+#set_property -dict { PACKAGE_PIN AH12  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
+#set_property -dict { PACKAGE_PIN AG11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
+#set_property -dict { PACKAGE_PIN AG10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
+#set_property -dict { PACKAGE_PIN AH11  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
+#set_property -dict { PACKAGE_PIN AH10  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
+#set_property -dict { PACKAGE_PIN AD4   IOSTANDARD LVDS   DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
+#set_property -dict { PACKAGE_PIN AD5   IOSTANDARD LVDS   DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
+#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
+#set_property -dict { PACKAGE_PIN W8    IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
+
+## FMC connector
+#set_property -dict { PACKAGE_PIN M6   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
+#set_property -dict { PACKAGE_PIN L3   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
+#set_property -dict { PACKAGE_PIN L6   IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
+#set_property -dict { PACKAGE_PIN L7   IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
+#set_property -dict { PACKAGE_PIN H3   IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
+#set_property -dict { PACKAGE_PIN H4   IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
+#set_property -dict { PACKAGE_PIN H6   IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
+#set_property -dict { PACKAGE_PIN J6   IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
+#set_property -dict { PACKAGE_PIN K3   IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
+#set_property -dict { PACKAGE_PIN K4   IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
+#set_property -dict { PACKAGE_PIN J2   IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
+#set_property -dict { PACKAGE_PIN K2   IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
+#set_property -dict { PACKAGE_PIN T6   IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
+#set_property -dict { PACKAGE_PIN R6   IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
+#set_property -dict { PACKAGE_PIN K1   IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
+#set_property -dict { PACKAGE_PIN L1   IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
+#set_property -dict { PACKAGE_PIN J9   IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
+#set_property -dict { PACKAGE_PIN K9   IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
+#set_property -dict { PACKAGE_PIN T7   IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
+#set_property -dict { PACKAGE_PIN R7   IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
+#set_property -dict { PACKAGE_PIN L8   IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
+#set_property -dict { PACKAGE_PIN M8   IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
+#set_property -dict { PACKAGE_PIN H1   IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
+#set_property -dict { PACKAGE_PIN J1   IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
+#set_property -dict { PACKAGE_PIN J4   IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
+#set_property -dict { PACKAGE_PIN J5   IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
+#set_property -dict { PACKAGE_PIN H7   IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
+#set_property -dict { PACKAGE_PIN J7   IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
+#set_property -dict { PACKAGE_PIN N6   IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
+#set_property -dict { PACKAGE_PIN N7   IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
+#set_property -dict { PACKAGE_PIN P6   IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
+#set_property -dict { PACKAGE_PIN P7   IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
+#set_property -dict { PACKAGE_PIN T8   IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
+#set_property -dict { PACKAGE_PIN R8   IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
+#set_property -dict { PACKAGE_PIN K7   IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
+#set_property -dict { PACKAGE_PIN K8   IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
+#set_property -dict { PACKAGE_PIN AD1  IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
+#set_property -dict { PACKAGE_PIN AD2  IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
+#set_property -dict { PACKAGE_PIN AH9  IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
+#set_property -dict { PACKAGE_PIN AG9  IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
+#set_property -dict { PACKAGE_PIN AC3  IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
+#set_property -dict { PACKAGE_PIN AC4  IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
+#set_property -dict { PACKAGE_PIN AB3  IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
+#set_property -dict { PACKAGE_PIN AB4  IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
+#set_property -dict { PACKAGE_PIN AG1  IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
+#set_property -dict { PACKAGE_PIN AF1  IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
+#set_property -dict { PACKAGE_PIN AC8  IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
+#set_property -dict { PACKAGE_PIN AB8  IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
+#set_property -dict { PACKAGE_PIN AH1  IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
+#set_property -dict { PACKAGE_PIN AH2  IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
+#set_property -dict { PACKAGE_PIN AF6  IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
+#set_property -dict { PACKAGE_PIN AF7  IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
+#set_property -dict { PACKAGE_PIN AH3  IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
+#set_property -dict { PACKAGE_PIN AG3  IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
+#set_property -dict { PACKAGE_PIN AD9  IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
+#set_property -dict { PACKAGE_PIN AC9  IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
+#set_property -dict { PACKAGE_PIN AH4  IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
+#set_property -dict { PACKAGE_PIN AG4  IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
+#set_property -dict { PACKAGE_PIN AE8  IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
+#set_property -dict { PACKAGE_PIN AE9  IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
+#set_property -dict { PACKAGE_PIN AH7  IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
+#set_property -dict { PACKAGE_PIN AH8  IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
+#set_property -dict { PACKAGE_PIN AC7  IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
+#set_property -dict { PACKAGE_PIN AB7  IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
+#set_property -dict { PACKAGE_PIN AG8  IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
+#set_property -dict { PACKAGE_PIN AF8  IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
+#set_property -dict { PACKAGE_PIN AC2  IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
+#set_property -dict { PACKAGE_PIN AB2  IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
+#set_property -dict { PACKAGE_PIN AC6  IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
+#set_property -dict { PACKAGE_PIN AB6  IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
+
+#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
+
+## Power-good input for VADJ supply rail
+#set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33 } [get_ports { pg_vadj_r }]; #IO_L12N_AD8N_44/24 Sch=pg_vadj_r
+
+#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
+#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
+
+#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
+
+
+
+
diff --git a/Bibliotheken/digilent-xdc-master/License.txt b/Bibliotheken/digilent-xdc-master/License.txt
new file mode 100644
index 0000000..de71801
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/License.txt
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2017 Digilent
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
\ No newline at end of file
diff --git a/Bibliotheken/digilent-xdc-master/Nexys-4-DDR-Master.xdc b/Bibliotheken/digilent-xdc-master/Nexys-4-DDR-Master.xdc
new file mode 100644
index 0000000..ecf1c90
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Nexys-4-DDR-Master.xdc
@@ -0,0 +1,265 @@
+## This file is a general .xdc for the Nexys4 DDR Rev. C
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
+
+
+##Switches
+
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
+#set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
+#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
+#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+
+
+## LEDs
+
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
+
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
+
+
+##7 segment display
+
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
+
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
+
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+
+
+##Buttons
+
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
+
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+
+
+##Pmod Headers
+
+
+##Pmod Header JA
+
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
+
+
+##Pmod Header JB
+
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
+
+
+##Pmod Header JC
+
+#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
+
+
+##Pmod Header JD
+
+#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
+
+
+##Pmod Header JXADC
+
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVDS     } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVDS     } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVDS     } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVDS     } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVDS     } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVDS     } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVDS     } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVDS     } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
+
+
+##VGA Connector
+
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
+
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
+
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
+#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
+
+#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
+
+
+##Micro SD Connector
+
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
+
+
+##Accelerometer
+
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
+
+
+##Temperature Sensor
+
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
+
+##Omnidirectional Microphone
+
+#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
+#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
+
+
+##PWM Audio Amplifier
+
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
+
+
+##USB-RS232 Interface
+
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
+#set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
+
+##USB HID (PS/2)
+
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
+
+
+##SMSC Ethernet PHY
+
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
+#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
+#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
+#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
+
+
+##Quad SPI Flash
+
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Bibliotheken/digilent-xdc-master/Nexys-4-Master.xdc b/Bibliotheken/digilent-xdc-master/Nexys-4-Master.xdc
new file mode 100644
index 0000000..bc6b983
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Nexys-4-Master.xdc
@@ -0,0 +1,722 @@
+## This file is a general .xdc for the Nexys4 rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+##Bank = 35, Pin name = IO_L12P_T1_MRCC_35,					Sch name = CLK100MHZ
+#set_property PACKAGE_PIN E3 [get_ports clk]							
+	#set_property IOSTANDARD LVCMOS33 [get_ports clk]
+	#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+ 
+## Switches
+##Bank = 34, Pin name = IO_L21P_T3_DQS_34,					Sch name = SW0
+#set_property PACKAGE_PIN U9 [get_ports {sw[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+##Bank = 34, Pin name = IO_25_34,							Sch name = SW1
+#set_property PACKAGE_PIN U8 [get_ports {sw[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+##Bank = 34, Pin name = IO_L23P_T3_34,						Sch name = SW2
+#set_property PACKAGE_PIN R7 [get_ports {sw[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+##Bank = 34, Pin name = IO_L19P_T3_34,						Sch name = SW3
+#set_property PACKAGE_PIN R6 [get_ports {sw[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
+##Bank = 34, Pin name = IO_L19N_T3_VREF_34,					Sch name = SW4
+#set_property PACKAGE_PIN R5 [get_ports {sw[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
+##Bank = 34, Pin name = IO_L20P_T3_34,						Sch name = SW5
+#set_property PACKAGE_PIN V7 [get_ports {sw[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
+##Bank = 34, Pin name = IO_L20N_T3_34,						Sch name = SW6
+#set_property PACKAGE_PIN V6 [get_ports {sw[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
+##Bank = 34, Pin name = IO_L10P_T1_34,						Sch name = SW7
+#set_property PACKAGE_PIN V5 [get_ports {sw[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
+##Bank = 34, Pin name = IO_L8P_T1-34,						Sch name = SW8
+#set_property PACKAGE_PIN U4 [get_ports {sw[8]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
+##Bank = 34, Pin name = IO_L9N_T1_DQS_34,					Sch name = SW9
+#set_property PACKAGE_PIN V2 [get_ports {sw[9]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
+##Bank = 34, Pin name = IO_L9P_T1_DQS_34,					Sch name = SW10
+#set_property PACKAGE_PIN U2 [get_ports {sw[10]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
+##Bank = 34, Pin name = IO_L11N_T1_MRCC_34,					Sch name = SW11
+#set_property PACKAGE_PIN T3 [get_ports {sw[11]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
+##Bank = 34, Pin name = IO_L17N_T2_34,						Sch name = SW12
+#set_property PACKAGE_PIN T1 [get_ports {sw[12]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
+##Bank = 34, Pin name = IO_L11P_T1_SRCC_34,					Sch name = SW13
+#set_property PACKAGE_PIN R3 [get_ports {sw[13]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
+##Bank = 34, Pin name = IO_L14N_T2_SRCC_34,					Sch name = SW14
+#set_property PACKAGE_PIN P3 [get_ports {sw[14]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
+##Bank = 34, Pin name = IO_L14P_T2_SRCC_34,					Sch name = SW15
+#set_property PACKAGE_PIN P4 [get_ports {sw[15]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
+ 
+
+
+## LEDs
+##Bank = 34, Pin name = IO_L24N_T3_34,						Sch name = LED0
+#set_property PACKAGE_PIN T8 [get_ports {led[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+##Bank = 34, Pin name = IO_L21N_T3_DQS_34,					Sch name = LED1
+#set_property PACKAGE_PIN V9 [get_ports {led[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+##Bank = 34, Pin name = IO_L24P_T3_34,						Sch name = LED2
+#set_property PACKAGE_PIN R8 [get_ports {led[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+##Bank = 34, Pin name = IO_L23N_T3_34,						Sch name = LED3
+#set_property PACKAGE_PIN T6 [get_ports {led[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+##Bank = 34, Pin name = IO_L12P_T1_MRCC_34,					Sch name = LED4
+#set_property PACKAGE_PIN T5 [get_ports {led[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
+##Bank = 34, Pin name = IO_L12N_T1_MRCC_34,					Sch	name = LED5
+#set_property PACKAGE_PIN T4 [get_ports {led[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
+##Bank = 34, Pin name = IO_L22P_T3_34,						Sch name = LED6
+#set_property PACKAGE_PIN U7 [get_ports {led[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
+##Bank = 34, Pin name = IO_L22N_T3_34,						Sch name = LED7
+#set_property PACKAGE_PIN U6 [get_ports {led[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
+##Bank = 34, Pin name = IO_L10N_T1_34,						Sch name = LED8
+#set_property PACKAGE_PIN V4 [get_ports {led[8]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
+##Bank = 34, Pin name = IO_L8N_T1_34,						Sch name = LED9
+#set_property PACKAGE_PIN U3 [get_ports {led[9]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
+##Bank = 34, Pin name = IO_L7N_T1_34,						Sch name = LED10
+#set_property PACKAGE_PIN V1 [get_ports {led[10]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
+##Bank = 34, Pin name = IO_L17P_T2_34,						Sch name = LED11
+#set_property PACKAGE_PIN R1 [get_ports {led[11]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
+##Bank = 34, Pin name = IO_L13N_T2_MRCC_34,					Sch name = LED12
+#set_property PACKAGE_PIN P5 [get_ports {led[12]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
+##Bank = 34, Pin name = IO_L7P_T1_34,						Sch name = LED13
+#set_property PACKAGE_PIN U1 [get_ports {led[13]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
+##Bank = 34, Pin name = IO_L15N_T2_DQS_34,					Sch name = LED14
+#set_property PACKAGE_PIN R2 [get_ports {led[14]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
+##Bank = 34, Pin name = IO_L15P_T2_DQS_34,					Sch name = LED15
+#set_property PACKAGE_PIN P2 [get_ports {led[15]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
+
+##Bank = 34, Pin name = IO_L5P_T0_34,						Sch name = LED16_R
+#set_property PACKAGE_PIN K5 [get_ports RGB1_Red]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Red]
+##Bank = 15, Pin name = IO_L5P_T0_AD9P_15,					Sch name = LED16_G
+#set_property PACKAGE_PIN F13 [get_ports RGB1_Green]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Green]
+##Bank = 35, Pin name = IO_L19N_T3_VREF_35,					Sch name = LED16_B
+#set_property PACKAGE_PIN F6 [get_ports RGB1_Blue]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Blue]
+##Bank = 34, Pin name = IO_0_34,								Sch name = LED17_R
+#set_property PACKAGE_PIN K6 [get_ports RGB2_Red]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Red]
+##Bank = 35, Pin name = IO_24P_T3_35,						Sch name =  LED17_G
+#set_property PACKAGE_PIN H6 [get_ports RGB2_Green]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Green]
+##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14,			Sch name = LED17_B
+#set_property PACKAGE_PIN L16 [get_ports RGB2_Blue]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Blue]
+
+
+
+##7 segment display
+##Bank = 34, Pin name = IO_L2N_T0_34,						Sch name = CA
+#set_property PACKAGE_PIN L3 [get_ports {seg[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
+##Bank = 34, Pin name = IO_L3N_T0_DQS_34,					Sch name = CB
+#set_property PACKAGE_PIN N1 [get_ports {seg[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
+##Bank = 34, Pin name = IO_L6N_T0_VREF_34,					Sch name = CC
+#set_property PACKAGE_PIN L5 [get_ports {seg[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
+##Bank = 34, Pin name = IO_L5N_T0_34,						Sch name = CD
+#set_property PACKAGE_PIN L4 [get_ports {seg[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
+##Bank = 34, Pin name = IO_L2P_T0_34,						Sch name = CE
+#set_property PACKAGE_PIN K3 [get_ports {seg[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
+##Bank = 34, Pin name = IO_L4N_T0_34,						Sch name = CF
+#set_property PACKAGE_PIN M2 [get_ports {seg[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
+##Bank = 34, Pin name = IO_L6P_T0_34,						Sch name = CG
+#set_property PACKAGE_PIN L6 [get_ports {seg[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
+
+##Bank = 34, Pin name = IO_L16P_T2_34,						Sch name = DP
+#set_property PACKAGE_PIN M4 [get_ports dp]							
+	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
+
+##Bank = 34, Pin name = IO_L18N_T2_34,						Sch name = AN0
+#set_property PACKAGE_PIN N6 [get_ports {an[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+##Bank = 34, Pin name = IO_L18P_T2_34,						Sch name = AN1
+#set_property PACKAGE_PIN M6 [get_ports {an[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+##Bank = 34, Pin name = IO_L4P_T0_34,						Sch name = AN2
+#set_property PACKAGE_PIN M3 [get_ports {an[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+##Bank = 34, Pin name = IO_L13_T2_MRCC_34,					Sch name = AN3
+#set_property PACKAGE_PIN N5 [get_ports {an[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+##Bank = 34, Pin name = IO_L3P_T0_DQS_34,					Sch name = AN4
+#set_property PACKAGE_PIN N2 [get_ports {an[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
+##Bank = 34, Pin name = IO_L16N_T2_34,						Sch name = AN5
+#set_property PACKAGE_PIN N4 [get_ports {an[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
+##Bank = 34, Pin name = IO_L1P_T0_34,						Sch name = AN6
+#set_property PACKAGE_PIN L1 [get_ports {an[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
+##Bank = 34, Pin name = IO_L1N_T034,							Sch name = AN7
+#set_property PACKAGE_PIN M1 [get_ports {an[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
+
+
+
+##Buttons
+##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15,				Sch name = CPU_RESET
+#set_property PACKAGE_PIN C12 [get_ports btnCpuReset]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset]
+##Bank = 15, Pin name = IO_L11N_T1_SRCC_15,					Sch name = BTNC
+#set_property PACKAGE_PIN E16 [get_ports btnC]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
+##Bank = 15, Pin name = IO_L14P_T2_SRCC_15,					Sch name = BTNU
+#set_property PACKAGE_PIN F15 [get_ports btnU]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
+##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14,	Sch name = BTNL
+#set_property PACKAGE_PIN T16 [get_ports btnL]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
+##Bank = 14, Pin name = IO_25_14,							Sch name = BTNR
+#set_property PACKAGE_PIN R10 [get_ports btnR]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
+##Bank = 14, Pin name = IO_L21P_T3_DQS_14,					Sch name = BTND
+#set_property PACKAGE_PIN V10 [get_ports btnD]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
+ 
+
+
+##Pmod Header JA
+##Bank = 15, Pin name = IO_L1N_T0_AD0N_15,					Sch name = JA1
+#set_property PACKAGE_PIN B13 [get_ports {JA[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
+##Bank = 15, Pin name = IO_L5N_T0_AD9N_15,					Sch name = JA2
+#set_property PACKAGE_PIN F14 [get_ports {JA[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
+##Bank = 15, Pin name = IO_L16N_T2_A27_15,					Sch name = JA3
+#set_property PACKAGE_PIN D17 [get_ports {JA[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
+##Bank = 15, Pin name = IO_L16P_T2_A28_15,					Sch name = JA4
+#set_property PACKAGE_PIN E17 [get_ports {JA[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
+##Bank = 15, Pin name = IO_0_15,								Sch name = JA7
+#set_property PACKAGE_PIN G13 [get_ports {JA[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
+##Bank = 15, Pin name = IO_L20N_T3_A19_15,					Sch name = JA8
+#set_property PACKAGE_PIN C17 [get_ports {JA[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
+##Bank = 15, Pin name = IO_L21N_T3_A17_15,					Sch name = JA9
+#set_property PACKAGE_PIN D18 [get_ports {JA[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
+##Bank = 15, Pin name = IO_L21P_T3_DQS_15,					Sch name = JA10
+#set_property PACKAGE_PIN E18 [get_ports {JA[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
+
+
+
+##Pmod Header JB
+##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15,				Sch name = JB1
+#set_property PACKAGE_PIN G14 [get_ports {JB[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
+##Bank = 14, Pin name = IO_L13P_T2_MRCC_14,					Sch name = JB2
+#set_property PACKAGE_PIN P15 [get_ports {JB[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
+##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14,			Sch name = JB3
+#set_property PACKAGE_PIN V11 [get_ports {JB[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
+##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14,				Sch name = JB4
+#set_property PACKAGE_PIN V15 [get_ports {JB[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
+##Bank = 15, Pin name = IO_25_15,							Sch name = JB7
+#set_property PACKAGE_PIN K16 [get_ports {JB[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
+##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14,			Sch name = JB8
+#set_property PACKAGE_PIN R16 [get_ports {JB[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
+##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14,				Sch name = JB9
+#set_property PACKAGE_PIN T9 [get_ports {JB[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
+##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14,			Sch name = JB10 
+#set_property PACKAGE_PIN U11 [get_ports {JB[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
+ 
+
+
+##Pmod Header JC
+##Bank = 35, Pin name = IO_L23P_T3_35,						Sch name = JC1
+#set_property PACKAGE_PIN K2 [get_ports {JC[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
+##Bank = 35, Pin name = IO_L6P_T0_35,						Sch name = JC2
+#set_property PACKAGE_PIN E7 [get_ports {JC[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
+##Bank = 35, Pin name = IO_L22P_T3_35,						Sch name = JC3
+#set_property PACKAGE_PIN J3 [get_ports {JC[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
+##Bank = 35, Pin name = IO_L21P_T3_DQS_35,					Sch name = JC4
+#set_property PACKAGE_PIN J4 [get_ports {JC[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
+##Bank = 35, Pin name = IO_L23N_T3_35,						Sch name = JC7
+#set_property PACKAGE_PIN K1 [get_ports {JC[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
+##Bank = 35, Pin name = IO_L5P_T0_AD13P_35,					Sch name = JC8
+#set_property PACKAGE_PIN E6 [get_ports {JC[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
+##Bank = 35, Pin name = IO_L22N_T3_35,						Sch name = JC9
+#set_property PACKAGE_PIN J2 [get_ports {JC[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
+##Bank = 35, Pin name = IO_L19P_T3_35,						Sch name = JC10
+#set_property PACKAGE_PIN G6 [get_ports {JC[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
+ 
+
+ 
+##Pmod Header JD
+##Bank = 35, Pin name = IO_L21N_T2_DQS_35,					Sch name = JD1
+#set_property PACKAGE_PIN H4 [get_ports {JD[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}]
+##Bank = 35, Pin name = IO_L17P_T2_35,						Sch name = JD2
+#set_property PACKAGE_PIN H1 [get_ports {JD[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}]
+##Bank = 35, Pin name = IO_L17N_T2_35,						Sch name = JD3
+#set_property PACKAGE_PIN G1 [get_ports {JD[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}]
+##Bank = 35, Pin name = IO_L20N_T3_35,						Sch name = JD4
+#set_property PACKAGE_PIN G3 [get_ports {JD[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}]
+##Bank = 35, Pin name = IO_L15P_T2_DQS_35,					Sch name = JD7
+#set_property PACKAGE_PIN H2 [get_ports {JD[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}]
+##Bank = 35, Pin name = IO_L20P_T3_35,						Sch name = JD8
+#set_property PACKAGE_PIN G4 [get_ports {JD[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}]
+##Bank = 35, Pin name = IO_L15N_T2_DQS_35,					Sch name = JD9
+#set_property PACKAGE_PIN G2 [get_ports {JD[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}]
+##Bank = 35, Pin name = IO_L13N_T2_MRCC_35,					Sch name = JD10
+#set_property PACKAGE_PIN F3 [get_ports {JD[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}]
+ 
+
+
+##Pmod Header JXADC
+##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15,				Sch name = XADC1_P -> XA1_P
+#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
+##Bank = 15, Pin name = IO_L8P_T1_AD10P_15,					Sch name = XADC2_P -> XA2_P
+#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
+##Bank = 15, Pin name = IO_L7P_T1_AD2P_15,					Sch name = XADC3_P -> XA3_P
+#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
+##Bank = 15, Pin name = IO_L10P_T1_AD11P_15,					Sch name = XADC4_P -> XA4_P
+#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
+##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15,				Sch name = XADC1_N -> XA1_N
+#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
+##Bank = 15, Pin name = IO_L8N_T1_AD10N_15,					Sch name = XADC2_N -> XA2_N
+#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
+##Bank = 15, Pin name = IO_L7N_T1_AD2N_15,					Sch name = XADC3_N -> XA3_N 
+#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
+##Bank = 15, Pin name = IO_L10N_T1_AD11N_15,					Sch name = XADC4_N -> XA4_N
+#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
+
+
+
+##VGA Connector
+##Bank = 35, Pin name = IO_L8N_T1_AD14N_35,					Sch name = VGA_R0
+#set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
+##Bank = 35, Pin name = IO_L7N_T1_AD6N_35,					Sch name = VGA_R1
+#set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
+##Bank = 35, Pin name = IO_L1N_T0_AD4N_35,					Sch name = VGA_R2
+#set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
+##Bank = 35, Pin name = IO_L8P_T1_AD14P_35,					Sch name = VGA_R3
+#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
+##Bank = 35, Pin name = IO_L2P_T0_AD12P_35,					Sch name = VGA_B0
+#set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
+##Bank = 35, Pin name = IO_L4N_T0_35,						Sch name = VGA_B1
+#set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
+##Bank = 35, Pin name = IO_L6N_T0_VREF_35,					Sch name = VGA_B2
+#set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
+##Bank = 35, Pin name = IO_L4P_T0_35,						Sch name = VGA_B3
+#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
+##Bank = 35, Pin name = IO_L1P_T0_AD4P_35,					Sch name = VGA_G0
+#set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
+##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35,				Sch name = VGA_G1
+#set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
+##Bank = 35, Pin name = IO_L2N_T0_AD12N_35,					Sch name = VGA_G2
+#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
+##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35,				Sch name = VGA_G3
+#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
+##Bank = 15, Pin name = IO_L4P_T0_15,						Sch name = VGA_HS
+#set_property PACKAGE_PIN B11 [get_ports Hsync]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
+##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15,				Sch name = VGA_VS
+#set_property PACKAGE_PIN B12 [get_ports Vsync]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
+
+
+
+##Micro SD Connector
+##Bank = 35, Pin name = IO_L14P_T2_SRCC_35,					Sch name = SD_RESET
+#set_property PACKAGE_PIN E2 [get_ports sdReset]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports sdReset]
+##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35,				Sch name = SD_CD
+#set_property PACKAGE_PIN A1 [get_ports sdCD]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports sdCD]
+##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35,				Sch name = SD_SCK
+#set_property PACKAGE_PIN B1 [get_ports sdSCK]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports sdSCK]
+##Bank = 35, Pin name = IO_L16N_T2_35,						Sch name = SD_CMD
+#set_property PACKAGE_PIN C1 [get_ports sdCmd]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports sdCmd]
+##Bank = 35, Pin name = IO_L16P_T2_35,						Sch name = SD_DAT0
+#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}]
+##Bank = 35, Pin name = IO_L18N_T2_35,						Sch name = SD_DAT1
+#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}]
+##Bank = 35, Pin name = IO_L18P_T2_35,						Sch name = SD_DAT2
+#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}]
+##Bank = 35, Pin name = IO_L14N_T2_SRCC_35,					Sch name = SD_DAT3
+#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}]
+
+
+
+##Accelerometer
+##Bank = 15, Pin name = IO_L6N_T0_VREF_15,					Sch name = ACL_MISO
+#set_property PACKAGE_PIN D13 [get_ports aclMISO]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports aclMISO]
+##Bank = 15, Pin name = IO_L2N_T0_AD8N_15,					Sch name = ACL_MOSI
+#set_property PACKAGE_PIN B14 [get_ports aclMOSI]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports aclMOSI]
+##Bank = 15, Pin name = IO_L12P_T1_MRCC_15,					Sch name = ACL_SCLK
+#set_property PACKAGE_PIN D15 [get_ports aclSCK]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports aclSCK]
+##Bank = 15, Pin name = IO_L12N_T1_MRCC_15,					Sch name = ACL_CSN
+#set_property PACKAGE_PIN C15 [get_ports aclSS]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports aclSS]
+##Bank = 15, Pin name = IO_L20P_T3_A20_15,					Sch name = ACL_INT1
+#set_property PACKAGE_PIN C16 [get_ports aclInt1]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports aclInt1]
+##Bank = 15, Pin name = IO_L11P_T1_SRCC_15,					Sch name = ACL_INT2
+#set_property PACKAGE_PIN E15 [get_ports aclInt2]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports aclInt2]
+
+
+
+##Temperature Sensor
+##Bank = 15, Pin name = IO_L14N_T2_SRCC_15,					Sch name = TMP_SCL
+#set_property PACKAGE_PIN F16 [get_ports tmpSCL]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL]
+##Bank = 15, Pin name = IO_L13N_T2_MRCC_15,					Sch name = TMP_SDA
+#set_property PACKAGE_PIN G16 [get_ports tmpSDA]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA]
+##Bank = 15, Pin name = IO_L1P_T0_AD0P_15,					Sch name = TMP_INT
+#set_property PACKAGE_PIN D14 [get_ports tmpInt]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports tmpInt]
+##Bank = 15, Pin name = IO_L1N_T0_AD0N_15,					Sch name = TMP_CT
+#set_property PACKAGE_PIN C14 [get_ports tmpCT]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports tmpCT]
+
+
+
+##Omnidirectional Microphone
+##Bank = 35, Pin name = IO_25_35,							Sch name = M_CLK
+#set_property PACKAGE_PIN J5 [get_ports micClk]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports micClk]
+##Bank = 35, Pin name = IO_L24N_T3_35,						Sch name = M_DATA
+#set_property PACKAGE_PIN H5 [get_ports micData]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports micData]
+##Bank = 35, Pin name = IO_0_35,								Sch name = M_LRSEL
+#set_property PACKAGE_PIN F5 [get_ports micLRSel]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports micLRSel]
+
+
+
+##PWM Audio Amplifier
+##Bank = 15, Pin name = IO_L4N_T0_15,						Sch name = AUD_PWM
+#set_property PACKAGE_PIN A11 [get_ports ampPWM]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports ampPWM]
+##Bank = 15, Pin name = IO_L6P_T0_15,						Sch name = AUD_SD
+#set_property PACKAGE_PIN D12 [get_ports ampSD]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports ampSD]
+
+
+##USB-RS232 Interface
+##Bank = 35, Pin name = IO_L7P_T1_AD6P_35,					Sch name = UART_TXD_IN
+#set_property PACKAGE_PIN C4 [get_ports RsRx]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
+##Bank = 35, Pin name = IO_L11N_T1_SRCC_35,					Sch name = UART_RXD_OUT
+#set_property PACKAGE_PIN D4 [get_ports RsTx]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
+##Bank = 35, Pin name = IO_L12N_T1_MRCC_35,					Sch name = UART_CTS
+#set_property PACKAGE_PIN D3 [get_ports RsCts]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsCts]
+##Bank = 35, Pin name = IO_L5N_T0_AD13N_35,					Sch name = UART_RTS
+#set_property PACKAGE_PIN E5 [get_ports RsRts]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsRts]
+
+
+
+##USB HID (PS/2)
+##Bank = 35, Pin name = IO_L13P_T2_MRCC_35,					Sch name = PS2_CLK
+#set_property PACKAGE_PIN F4 [get_ports PS2Clk]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
+	#set_property PULLUP true [get_ports PS2Clk]
+##Bank = 35, Pin name = IO_L10N_T1_AD15N_35,					Sch name = PS2_DATA
+#set_property PACKAGE_PIN B2 [get_ports PS2Data]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]	
+	#set_property PULLUP true [get_ports PS2Data]
+
+
+
+##SMSC Ethernet PHY
+##Bank = 16, Pin name = IO_L11P_T1_SRCC_16,					Sch name = ETH_MDC
+#set_property PACKAGE_PIN C9 [get_ports PhyMdc]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc]
+##Bank = 16, Pin name = IO_L14N_T2_SRCC_16,					Sch name = ETH_MDIO
+#set_property PACKAGE_PIN A9 [get_ports PhyMdio]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio]
+##Bank = 35, Pin name = IO_L10P_T1_AD15P_35,					Sch name = ETH_RSTN
+#set_property PACKAGE_PIN B3 [get_ports PhyRstn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn]
+##Bank = 16, Pin name = IO_L6N_T0_VREF_16,					Sch name = ETH_CRSDV
+#set_property PACKAGE_PIN D9 [get_ports PhyCrs]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs]
+##Bank = 16, Pin name = IO_L13N_T2_MRCC_16,					Sch name = ETH_RXERR
+#set_property PACKAGE_PIN C10 [get_ports PhyRxErr]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr]
+##Bank = 16, Pin name = IO_L19N_T3_VREF_16,					Sch name = ETH_RXD0
+#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}]
+##Bank = 16, Pin name = IO_L13P_T2_MRCC_16,					Sch name = ETH_RXD1
+#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}]
+##Bank = 16, Pin name = IO_L11N_T1_SRCC_16,					Sch name = ETH_TXEN
+#set_property PACKAGE_PIN B9 [get_ports PhyTxEn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn]
+##Bank = 16, Pin name = IO_L14P_T2_SRCC_16,					Sch name = ETH_TXD0
+#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}]
+##Bank = 16, Pin name = IO_L12N_T1_MRCC_16,					Sch name = ETH_TXD1
+#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}]
+##Bank = 35, Pin name = IO_L11P_T1_SRCC_35,					Sch name = ETH_REFCLK
+#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz]
+##Bank = 16, Pin name = IO_L12P_T1_MRCC_16,					Sch name = ETH_INTN
+#set_property PACKAGE_PIN B8 [get_ports PhyIntn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn]
+
+
+
+##Quad SPI Flash
+##Bank = CONFIG, Pin name = CCLK_0,							Sch name = QSPI_SCK
+#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}]
+##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14,			Sch name = QSPI_DQ0
+#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
+##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14,			Sch name = QSPI_DQ1
+#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
+##Bank = CONFIG, Pin name = IO_L20_T0_D02_14,				Sch name = QSPI_DQ2
+#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
+##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14,				Sch name = QSPI_DQ3
+#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
+##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14,	Sch name = QSPI_CSN
+#set_property PACKAGE_PIN L13 [get_ports QspiCSn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
+
+
+
+##Cellular RAM
+##Bank = 14, Pin name = IO_L14N_T2_SRCC_14,					Sch name = CRAM_CLK
+#set_property PACKAGE_PIN T15 [get_ports RamCLK]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamCLK]
+##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14,				Sch name = CRAM_ADVN
+#set_property PACKAGE_PIN T13 [get_ports RamADVn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamADVn]
+##Bank = 14, Pin name = IO_L4P_T0_D04_14,					Sch name = CRAM_CEN
+#set_property PACKAGE_PIN L18 [get_ports RamCEn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamCEn]
+##Bank = 15, Pin name = IO_L19P_T3_A22_15,					Sch name = CRAM_CRE
+#set_property PACKAGE_PIN J14 [get_ports RamCRE]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamCRE]
+##Bank = 15, Pin name = IO_L15P_T2_DQS_15,					Sch name = CRAM_OEN
+#set_property PACKAGE_PIN H14 [get_ports RamOEn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamOEn]
+##Bank = 14, Pin name = IO_0_14,								Sch name = CRAM_WEN
+#set_property PACKAGE_PIN R11 [get_ports RamWEn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamWEn]
+##Bank = 15, Pin name = IO_L24N_T3_RS0_15,					Sch name = CRAM_LBN
+#set_property PACKAGE_PIN J15 [get_ports RamLBn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamLBn]
+##Bank = 15, Pin name = IO_L17N_T2_A25_15,					Sch name = CRAM_UBN
+#set_property PACKAGE_PIN J13 [get_ports RamUBn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamUBn]
+##Bank = 14, Pin name = IO_L14P_T2_SRCC_14,					Sch name = CRAM_WAIT
+#set_property PACKAGE_PIN T14 [get_ports RamWait]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports RamWait]
+
+##Bank = 14, Pin name = IO_L5P_T0_DQ06_14,					Sch name = CRAM_DQ0
+#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}]
+##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14,				Sch name = CRAM_DQ1
+#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}]
+##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14,				Sch name = CRAM_DQ2
+#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}]
+##Bank = 14, Pin name = IO_L5N_T0_D07_14,					Sch name = CRAM_DQ3
+#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}]
+##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14,				Sch name = CRAM_DQ4
+#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}]
+##Bank = 14, Pin name = IO_L12N_T1_MRCC_14,					Sch name = CRAM_DQ5
+#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}]
+##Bank = 14, Pin name = IO_L7N_T1_D10_14,					Sch name = CRAM_DQ6
+#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}]
+##Bank = 14, Pin name = IO_L7P_T1_D09_14,					Sch name = CRAM_DQ7
+#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}]
+##Bank = 15, Pin name = IO_L22N_T3_A16_15,					Sch name = CRAM_DQ8
+#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}]
+##Bank = 15, Pin name = IO_L22P_T3_A17_15,					Sch name = CRAM_DQ9
+#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}]
+##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15,				Sch name = CRAM_DQ10
+#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}]
+##Bank = 14, Pin name = IO_L4N_T0_D05_14,					Sch name = CRAM_DQ11
+#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}]
+##Bank = 14, Pin name = IO_L10N_T1_D15_14,					Sch name = CRAM_DQ12
+#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}]
+##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14,				Sch name = CRAM_DQ13
+#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}]
+##Bank = 14, Pin name = IO_L9P_T1_DQS_14,					Sch name = CRAM_DQ14
+#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}]
+##Bank = 14, Pin name = IO_L12P_T1_MRCC_14,					Sch name = CRAM_DQ15
+#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}]
+
+##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15,					Sch name = CRAM_A0
+#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}]
+##Bank = 15, Pin name = IO_L18P_T2_A24_15,					Sch name = CRAM_A1
+#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}]
+##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15,				Sch name = CRAM_A2
+#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}]
+##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15,					Sch name = CRAM_A3
+#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}]
+##Bank = 15, Pin name = IO_L13P_T2_MRCC_15,					Sch name = CRAM_A4
+#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}]
+##Bank = 15, Pin name = IO_L24P_T3_RS1_15,					Sch name = CRAM_A5
+#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}]
+##Bank = 15, Pin name = IO_L17P_T2_A26_15,					Sch name = CRAM_A6
+#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}]
+##Bank = 14, Pin name = IO_L11P_T1_SRCC_14,					Sch name = CRAM_A7
+#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}]
+##Bank = 14, Pin name = IO_L16N_T2_SRCC-14,					Sch name = CRAM_A8
+#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}]
+##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14,				Sch name = CRAM_A9
+#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}]
+##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14,				Sch name = CRAM_A10
+#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}]
+##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14,				Sch name = CRAM_A11
+#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}]
+##Bank = 14, Pin name = IO_L8N_T1_D12_14,					Sch name = CRAM_A12
+#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}]
+##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14,				Sch name = CRAM_A13
+#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}]
+##Bank = 14, Pin name = IO_L13N_T2_MRCC_14,					Sch name = CRAM_A14
+#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}]
+##Bank = 14, Pin name = IO_L8P_T1_D11_14,					Sch name = CRAM_A15
+#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}]
+##Bank = 14, Pin name = IO_L11N_T1_SRCC_14,					Sch name = CRAM_A16
+#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}]
+##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14,				Sch name = CRAM_A17
+#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}]
+##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14,				Sch name = CRAM_A18
+#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}]
+##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14,				Sch name = CRAM_A19
+#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}]
+##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14,				Sch name = CRAM_A20
+#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}]
+##Bank = 14, Pin name = IO_L10P_T1_D14_14,					Sch name = CRAM_A21
+#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}]	
+##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14,				Sch name = CRAM_A22
+#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}]
+	
diff --git a/Bibliotheken/digilent-xdc-master/Nexys-A7-100T-Master.xdc b/Bibliotheken/digilent-xdc-master/Nexys-A7-100T-Master.xdc
new file mode 100644
index 0000000..705f54a
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Nexys-A7-100T-Master.xdc
@@ -0,0 +1,211 @@
+## This file is a general .xdc for the Nexys A7-100T
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
+
+
+##Switches
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
+#set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
+#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
+#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+
+## LEDs
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
+
+##7 segment display
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+
+##Buttons
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+
+
+##Pmod Headers
+##Pmod Header JA
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
+
+##Pmod Header JXADC
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
+
+##VGA Connector
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
+#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
+#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
+
+##Micro SD Connector
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
+
+##Accelerometer
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
+
+##Temperature Sensor
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
+
+##Omnidirectional Microphone
+#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
+#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
+
+##PWM Audio Amplifier
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
+
+##USB-RS232 Interface
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
+#set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
+
+##USB HID (PS/2)
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
+
+##SMSC Ethernet PHY
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
+#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
+#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
+#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
+
+##Quad SPI Flash
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
diff --git a/Bibliotheken/digilent-xdc-master/Nexys-A7-50T-Master.xdc b/Bibliotheken/digilent-xdc-master/Nexys-A7-50T-Master.xdc
new file mode 100644
index 0000000..7a5ce3f
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Nexys-A7-50T-Master.xdc
@@ -0,0 +1,211 @@
+## This file is a general .xdc for the Nexys A7-50T
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
+
+
+##Switches
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
+#set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
+#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
+#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+
+## LEDs
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
+
+##7 segment display
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+
+##Buttons
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+
+
+##Pmod Headers
+##Pmod Header JA
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
+
+##Pmod Header JXADC
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
+
+##VGA Connector
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
+#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
+#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
+
+##Micro SD Connector
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
+
+##Accelerometer
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
+
+##Temperature Sensor
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
+
+##Omnidirectional Microphone
+#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
+#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
+
+##PWM Audio Amplifier
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
+
+##USB-RS232 Interface
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
+#set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
+
+##USB HID (PS/2)
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
+
+##SMSC Ethernet PHY
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
+#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
+#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
+#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
+
+##Quad SPI Flash
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
diff --git a/Bibliotheken/digilent-xdc-master/Nexys-Video-Master.xdc b/Bibliotheken/digilent-xdc-master/Nexys-Video-Master.xdc
new file mode 100644
index 0000000..c6ff4ca
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Nexys-Video-Master.xdc
@@ -0,0 +1,312 @@
+### This file is a general .xdc for the Nexys Video Rev. A
+### To use it in a project:
+### - uncomment the lines corresponding to used pins
+### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+
+## Clock Signal
+#set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+
+## FMC Transceiver clocks (Must be set to value provided by Mezzanine card, currently set to 156.25 MHz)
+## Note: This clock is attached to a MGTREFCLK pin
+#set_property -dict { PACKAGE_PIN E6 } [get_ports { GTP_CLK_N }];
+#set_property -dict { PACKAGE_PIN F6 } [get_ports { GTP_CLK_P }];
+#create_clock -add -name gtpclk0_pin -period 6.400 -waveform {0 3.200} [get_ports {GTP_CLK_P}];
+#set_property -dict { PACKAGE_PIN E10 } [get_ports { FMC_MGT_CLK_N }];
+#set_property -dict { PACKAGE_PIN F10 } [get_ports { FMC_MGT_CLK_P }];
+#create_clock -add -name mgtclk1_pin -period 6.400 -waveform {0 3.200} [get_ports {FMC_MGT_CLK_P}];
+
+
+## LEDs
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { led[0] }]; #IO_L15P_T2_DQS_13 Sch=led[0]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS25 } [get_ports { led[1] }]; #IO_L15N_T2_DQS_13 Sch=led[1]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS25 } [get_ports { led[2] }]; #IO_L17P_T2_13 Sch=led[2]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS25 } [get_ports { led[3] }]; #IO_L17N_T2_13 Sch=led[3]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS25 } [get_ports { led[4] }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS25 } [get_ports { led[5] }]; #IO_L16N_T2_13 Sch=led[5]
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS25 } [get_ports { led[6] }]; #IO_L16P_T2_13 Sch=led[6]
+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS25 } [get_ports { led[7] }]; #IO_L5P_T0_13 Sch=led[7]
+
+
+## Buttons
+#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_L20N_T3_16 Sch=btnc
+#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_L22N_T3_16 Sch=btnd
+#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L20P_T3_16 Sch=btnl
+#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L6P_T0_16 Sch=btnr
+#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_0_16 Sch=btnu
+#set_property -dict { PACKAGE_PIN G4  IOSTANDARD LVCMOS15 } [get_ports { cpu_resetn }]; #IO_L12N_T1_MRCC_35 Sch=cpu_resetn
+
+
+## Switches
+#set_property -dict { PACKAGE_PIN E22  IOSTANDARD LVCMOS12 } [get_ports { sw[0] }]; #IO_L22P_T3_16 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN F21  IOSTANDARD LVCMOS12 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN G21  IOSTANDARD LVCMOS12 } [get_ports { sw[2] }]; #IO_L24P_T3_16 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS12 } [get_ports { sw[3] }]; #IO_L24N_T3_16 Sch=sw[3]
+#set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS12 } [get_ports { sw[4] }]; #IO_L6P_T0_15 Sch=sw[4]
+#set_property -dict { PACKAGE_PIN J16  IOSTANDARD LVCMOS12 } [get_ports { sw[5] }]; #IO_0_15 Sch=sw[5]
+#set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS12 } [get_ports { sw[6] }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+#set_property -dict { PACKAGE_PIN M17  IOSTANDARD LVCMOS12 } [get_ports { sw[7] }]; #IO_25_15 Sch=sw[7]
+
+
+## OLED Display
+#set_property -dict { PACKAGE_PIN W22   IOSTANDARD LVCMOS33 } [get_ports { oled_dc }]; #IO_L7N_T1_D10_14 Sch=oled_dc
+#set_property -dict { PACKAGE_PIN U21   IOSTANDARD LVCMOS33 } [get_ports { oled_res }]; #IO_L4N_T0_D05_14 Sch=oled_res
+#set_property -dict { PACKAGE_PIN W21   IOSTANDARD LVCMOS33 } [get_ports { oled_sclk }]; #IO_L7P_T1_D09_14 Sch=oled_sclk
+#set_property -dict { PACKAGE_PIN Y22   IOSTANDARD LVCMOS33 } [get_ports { oled_sdin }]; #IO_L9N_T1_DQS_D13_14 Sch=oled_sdin
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_0_14 Sch=oled_vbat
+#set_property -dict { PACKAGE_PIN V22   IOSTANDARD LVCMOS33 } [get_ports { oled_vdd }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=oled_vdd
+
+
+## HDMI in
+#set_property -dict { PACKAGE_PIN AA5   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
+#set_property -dict { PACKAGE_PIN W4    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN V4    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN AB12  IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
+#set_property -dict { PACKAGE_PIN Y4    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN AB5   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
+#set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
+#set_property -dict { PACKAGE_PIN AA3   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN Y3    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN Y2    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN W2    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN V2    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN U2    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]
+
+
+## HDMI out
+#set_property -dict { PACKAGE_PIN AA4   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
+#set_property -dict { PACKAGE_PIN U1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN T1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN AB13  IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rscl }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
+#set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rsda }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
+#set_property -dict { PACKAGE_PIN Y1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN W1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN AB1   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN AA1   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN AB2   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN AB3   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]
+
+
+## Display Port
+#set_property -dict { PACKAGE_PIN AB10  IOSTANDARD TMDS_33  } [get_ports { dp_tx_aux_n }]; #IO_L8N_T1_13 Sch=dp_tx_aux_n
+#set_property -dict { PACKAGE_PIN AA11  IOSTANDARD TMDS_33  } [get_ports { dp_tx_aux_n }]; #IO_L9N_T1_DQS_13 Sch=dp_tx_aux_n
+#set_property -dict { PACKAGE_PIN AA9   IOSTANDARD TMDS_33  } [get_ports { dp_tx_aux_p }]; #IO_L8P_T1_13 Sch=dp_tx_aux_p
+#set_property -dict { PACKAGE_PIN AA10  IOSTANDARD TMDS_33  } [get_ports { dp_tx_aux_p }]; #IO_L9P_T1_DQS_13 Sch=dp_tx_aux_p
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { dp_tx_hpd }]; #IO_25_14 Sch=dp_tx_hpd
+
+
+## Audio Codec
+#set_property -dict { PACKAGE_PIN T4    IOSTANDARD LVCMOS33 } [get_ports { ac_adc_sdata }]; #IO_L13N_T2_MRCC_34 Sch=ac_adc_sdata
+#set_property -dict { PACKAGE_PIN T5    IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_L14P_T2_SRCC_34 Sch=ac_bclk
+#set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33 } [get_ports { ac_dac_sdata }]; #IO_L15P_T2_DQS_34 Sch=ac_dac_sdata
+#set_property -dict { PACKAGE_PIN U5    IOSTANDARD LVCMOS33 } [get_ports { ac_lrclk }]; #IO_L14N_T2_SRCC_34 Sch=ac_lrclk
+#set_property -dict { PACKAGE_PIN U6    IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L16P_T2_34 Sch=ac_mclk
+
+
+## Pmod header JA
+#set_property -dict { PACKAGE_PIN AB22  IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L10N_T1_D15_14 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN AB21  IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L10P_T1_D14_14 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN AB20  IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN AB18  IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN Y21   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN AA21  IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L8N_T1_D12_14 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN AA20  IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN AA18  IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
+
+
+## Pmod header JB
+#set_property -dict { PACKAGE_PIN V9    IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L21P_T3_DQS_34 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN V7    IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L19P_T3_34 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN W7    IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L19N_T3_VREF_34 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN W9    IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L24P_T3_34 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN Y9    IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L24N_T3_34 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L23P_T3_34 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN Y7    IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L23N_T3_34 Sch=jb_n[4]
+
+
+## Pmod header JC
+#set_property -dict { PACKAGE_PIN Y6    IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_34 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN AA6   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_34 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN AA8   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22P_T3_34 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN AB8   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L22N_T3_34 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN R6    IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L17P_T2_34 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN T6    IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L17N_T2_34 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN AB7   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L20P_T3_34 Sch=jc_p[4]
+#set_property -dict { PACKAGE_PIN AB6   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_34 Sch=jc_n[4]
+
+
+## XADC Header
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN H13   IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L5P_T0_AD9P_15 Sch=xa_p[4]
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L5N_T0_AD9N_15 Sch=xa_n[4]
+
+
+## UART
+#set_property -dict { PACKAGE_PIN AA19  IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
+
+
+## Ethernet
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS25 } [get_ports { eth_int_b }]; #IO_L6N_T0_VREF_13 Sch=eth_int_b
+#set_property -dict { PACKAGE_PIN AA16  IOSTANDARD LVCMOS25 } [get_ports { eth_mdc }]; #IO_L1N_T0_13 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS25 } [get_ports { eth_mdio }]; #IO_L1P_T0_13 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS25 } [get_ports { eth_pme_b }]; #IO_L6P_T0_13 Sch=eth_pme_b
+#set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_25_34 Sch=eth_rst_b
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS25 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_13 Sch=eth_rxck
+#set_property -dict { PACKAGE_PIN W10   IOSTANDARD LVCMOS25 } [get_ports { eth_rxctl }]; #IO_L10N_T1_13 Sch=eth_rxctl
+#set_property -dict { PACKAGE_PIN AB16  IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[0] }]; #IO_L2P_T0_13 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN AA15  IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[1] }]; #IO_L4P_T0_13 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN AB15  IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[2] }]; #IO_L4N_T0_13 Sch=eth_rxd[2]
+#set_property -dict { PACKAGE_PIN AB11  IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[3] }]; #IO_L7P_T1_13 Sch=eth_rxd[3]
+#set_property -dict { PACKAGE_PIN AA14  IOSTANDARD LVCMOS25 } [get_ports { eth_txck }]; #IO_L5N_T0_13 Sch=eth_txck
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS25 } [get_ports { eth_txctl }]; #IO_L10P_T1_13 Sch=eth_txctl
+#set_property -dict { PACKAGE_PIN Y12   IOSTANDARD LVCMOS25 } [get_ports { eth_txd[0] }]; #IO_L11N_T1_SRCC_13 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN W12   IOSTANDARD LVCMOS25 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_13 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN W11   IOSTANDARD LVCMOS25 } [get_ports { eth_txd[2] }]; #IO_L12P_T1_MRCC_13 Sch=eth_txd[2]
+#set_property -dict { PACKAGE_PIN Y11   IOSTANDARD LVCMOS25 } [get_ports { eth_txd[3] }]; #IO_L11P_T1_SRCC_13 Sch=eth_txd[3]
+
+
+## Fan PWM
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS25 } [get_ports { fan_pwm }]; #IO_L14P_T2_SRCC_13 Sch=fan_pwm
+
+
+## DPTI/DSPI
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { prog_d[0]}]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { prog_d[1] }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/mosi
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { prog_d[2] }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/miso
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { prog_d[3]}]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { prog_d[4] }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { prog_d[5] }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { prog_d[6] }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { prog_d[7] }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { prog_oen }]; #IO_L16P_T2_CSI_B_14 Sch=prog_oen
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { prog_rdn }]; #IO_L5P_T0_D06_14 Sch=prog_rdn
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { prog_rxen }]; #IO_L21P_T3_DQS_14 Sch=prog_rxen
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { prog_siwun }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=prog_siwun
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { prog_spien }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=prog_spien
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { prog_txen }]; #IO_L13N_T2_MRCC_14 Sch=prog_txen
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { prog_wrn }]; #IO_L5N_T0_D07_14 Sch=prog_wrn
+
+
+## HID port
+#set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33   PULLUP true } [get_ports { ps2_clk }]; #IO_L16N_T2_A15_D31_14 Sch=ps2_clk
+#set_property -dict { PACKAGE_PIN N13   IOSTANDARD LVCMOS33   PULLUP true } [get_ports { ps2_data }]; #IO_L23P_T3_A03_D19_14 Sch=ps2_data
+
+
+## QSPI
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN P22   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN R22   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN P21   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN R21   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+
+## SD card
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { sd_cclk }]; #IO_L12P_T1_MRCC_14 Sch=sd_cclk
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L12N_T1_MRCC_14 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L14N_T2_SRCC_14 Sch=sd_d[0]
+#set_property -dict { PACKAGE_PIN T21   IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L4P_T0_D04_14 Sch=sd_d[1]
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sd_d[2]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L18N_T2_A11_D27_14 Sch=sd_d[3]
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L11N_T1_SRCC_14 Sch=sd_reset
+
+
+## I2C
+#set_property -dict { PACKAGE_PIN W5    IOSTANDARD LVCMOS33 } [get_ports { scl }]; #IO_L15N_T2_DQS_34 Sch=scl
+#set_property -dict { PACKAGE_PIN V5    IOSTANDARD LVCMOS33 } [get_ports { sda }]; #IO_L16N_T2_34 Sch=sda
+
+
+## Voltage Adjust
+#set_property -dict { PACKAGE_PIN AA13  IOSTANDARD LVCMOS25 } [get_ports { set_vadj[0] }]; #IO_L3P_T0_DQS_13 Sch=set_vadj[0]
+#set_property -dict { PACKAGE_PIN AB17  IOSTANDARD LVCMOS25 } [get_ports { set_vadj[1] }]; #IO_L2N_T0_13 Sch=set_vadj[1]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS25 } [get_ports { vadj_en }]; #IO_L13N_T2_MRCC_13 Sch=vadj_en
+
+
+## FMC
+#set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_15 Sch=fmc_clk0_m2c_n
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_15 Sch=fmc_clk0_m2c_p
+#set_property -dict { PACKAGE_PIN C19   IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L13N_T2_MRCC_16 Sch=fmc_clk1_m2c_n
+#set_property -dict { PACKAGE_PIN C18   IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L13P_T2_MRCC_16 Sch=fmc_clk1_m2c_p
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2_MRCC_15 Sch=fmc_la00_cc_n
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2_MRCC_15 Sch=fmc_la00_cc_p
+#set_property -dict { PACKAGE_PIN J21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la01_cc_n }]; #IO_L11N_T1_SRCC_15 Sch=fmc_la01_cc_n
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la01_cc_p }]; #IO_L11P_T1_SRCC_15 Sch=fmc_la01_cc_p
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L16N_T2_A27_15 Sch=fmc_la_n[02]
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L16P_T2_A28_15 Sch=fmc_la_p[02]
+#set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L17N_T2_A25_15 Sch=fmc_la_n[03]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L17P_T2_A26_15 Sch=fmc_la_p[03]
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L18N_T2_A23_15 Sch=fmc_la_n[04]
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L18P_T2_A24_15 Sch=fmc_la_p[04]
+#set_property -dict { PACKAGE_PIN L21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L10N_T1_AD11N_15 Sch=fmc_la_n[05]
+#set_property -dict { PACKAGE_PIN M21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L10P_T1_AD11P_15 Sch=fmc_la_p[05]
+#set_property -dict { PACKAGE_PIN M22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_la_n[06]
+#set_property -dict { PACKAGE_PIN N22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L15P_T2_DQS_15 Sch=fmc_la_p[06]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L20N_T3_A19_15 Sch=fmc_la_n[07]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L20P_T3_A20_15 Sch=fmc_la_p[07]
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L24N_T3_RS0_15 Sch=fmc_la_n[08]
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L24P_T3_RS1_15 Sch=fmc_la_p[08]
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L8N_T1_AD10N_15 Sch=fmc_la_n[09]
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L8P_T1_AD10P_15 Sch=fmc_la_p[09]
+#set_property -dict { PACKAGE_PIN K22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=fmc_la_n[10]
+#set_property -dict { PACKAGE_PIN K21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=fmc_la_p[10]
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L22N_T3_A16_15 Sch=fmc_la_n[11]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L22P_T3_A17_15 Sch=fmc_la_p[11]
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_la_n[12]
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_la_p[12]
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_la_n[13]
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L21P_T3_DQS_15 Sch=fmc_la_p[13]
+#set_property -dict { PACKAGE_PIN H22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L7N_T1_AD2N_15 Sch=fmc_la_n[14]
+#set_property -dict { PACKAGE_PIN J22   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L7P_T1_AD2P_15 Sch=fmc_la_p[14]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_la_n[15]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_la_p[15]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L4N_T0_15 Sch=fmc_la_n[16]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L4P_T0_15 Sch=fmc_la_p[16]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la17_cc_n }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la17_cc_n
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la17_cc_p }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la17_cc_p
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la18_cc_n }]; #IO_L12N_T1_MRCC_16 Sch=fmc_la18_cc_n
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la18_cc_p }]; #IO_L12P_T1_MRCC_16 Sch=fmc_la18_cc_p
+#set_property -dict { PACKAGE_PIN A19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2_16 Sch=fmc_la_n[19]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2_16 Sch=fmc_la_p[19]
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L18N_T2_16 Sch=fmc_la_n[20]
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L18P_T2_16 Sch=fmc_la_p[20]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L14N_T2_SRCC_16 Sch=fmc_la_n[21]
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L14P_T2_SRCC_16 Sch=fmc_la_p[21]
+#set_property -dict { PACKAGE_PIN D21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L23N_T3_16 Sch=fmc_la_n[22]
+#set_property -dict { PACKAGE_PIN E21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L23P_T3_16 Sch=fmc_la_p[22]
+#set_property -dict { PACKAGE_PIN A21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L21N_T3_DQS_16 Sch=fmc_la_n[23]
+#set_property -dict { PACKAGE_PIN B21   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L21P_T3_DQS_16 Sch=fmc_la_p[23]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L7N_T1_16 Sch=fmc_la_n[24]
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L7P_T1_16 Sch=fmc_la_p[24]
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L2N_T0_16 Sch=fmc_la_n[25]
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L2P_T0_16 Sch=fmc_la_p[25]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[26]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[26]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L16N_T2_16 Sch=fmc_la_n[27]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L16P_T2_16 Sch=fmc_la_p[27]
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L8N_T1_16 Sch=fmc_la_n[28]
+#set_property -dict { PACKAGE_PIN C13   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L8P_T1_16 Sch=fmc_la_p[28]
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[29]
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[29]
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L10N_T1_16 Sch=fmc_la_n[30]
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L10P_T1_16 Sch=fmc_la_p[30]
+#set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L4N_T0_16 Sch=fmc_la_n[31]
+#set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L4P_T0_16 Sch=fmc_la_p[31]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[32]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[32]
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L1N_T0_16 Sch=fmc_la_n[33]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L1P_T0_16 Sch=fmc_la_p[33]
+
+
+## Configuration options, can be used for all designs
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
diff --git a/Bibliotheken/digilent-xdc-master/README.md b/Bibliotheken/digilent-xdc-master/README.md
new file mode 100644
index 0000000..d9ab1ae
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/README.md
@@ -0,0 +1,4 @@
+# digilent-xdc
+A collection of Master XDC files for Digilent FPGA and Zynq boards. 
+
+Documentation for these boards, including schematics and reference manuals, can be found through the [Programmable Logic](https://digilent.com/reference/programmable-logic/start) landing page on the  Digilent Reference site.
\ No newline at end of file
diff --git a/Bibliotheken/digilent-xdc-master/Sword-Master.xdc b/Bibliotheken/digilent-xdc-master/Sword-Master.xdc
new file mode 100644
index 0000000..056d4b0
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Sword-Master.xdc
@@ -0,0 +1,521 @@
+## This file is a general .xdc for the Sword Rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## 200MHz Differential Clock Signal
+#set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { clk_p }]; #IO_L12P_T1_MRCC_33 Sch=fpga_sysclk_p
+#set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { clk_n }]; #IO_L12N_T1_MRCC_33 Sch=fpga_sysclk_n
+#create_clock -add -name sys_clk_pin -period 5.00 -waveform {0 2.5} [get_ports clk_p]
+
+## User Reset Button
+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS15 } [get_ports { rst }]; #IO_0_VRN_33 Sch=user_rst
+
+## Switches
+#set_property -dict { PACKAGE_PIN AG19  IOSTANDARD LVCMOS18 } [get_ports { sw[0] }];  #IO_L8P_T1_32      Sch=sw[0]
+#set_property -dict { PACKAGE_PIN AH19  IOSTANDARD LVCMOS18 } [get_ports { sw[1] }];  #IO_L8N_T1_32      Sch=sw[1]
+#set_property -dict { PACKAGE_PIN AH17  IOSTANDARD LVCMOS18 } [get_ports { sw[2] }];  #IO_L5P_T0_32      Sch=sw[2]
+#set_property -dict { PACKAGE_PIN AF16  IOSTANDARD LVCMOS18 } [get_ports { sw[3] }];  #IO_L6N_T0_VREF_32 Sch=sw[3]
+#set_property -dict { PACKAGE_PIN AH16  IOSTANDARD LVCMOS18 } [get_ports { sw[4] }];  #IO_L3P_T0_DQS_32  Sch=sw[4]
+#set_property -dict { PACKAGE_PIN AE16  IOSTANDARD LVCMOS18 } [get_ports { sw[5] }];  #IO_L6P_T0_32      Sch=sw[5]
+#set_property -dict { PACKAGE_PIN AJ19  IOSTANDARD LVCMOS18 } [get_ports { sw[6] }];  #IO_L7P_T1_32      Sch=sw[6]
+#set_property -dict { PACKAGE_PIN AK19  IOSTANDARD LVCMOS18 } [get_ports { sw[7] }];  #IO_L7N_T1_32      Sch=sw[7]
+#set_property -dict { PACKAGE_PIN AJ17  IOSTANDARD LVCMOS18 } [get_ports { sw[8] }];  #IO_L5N_T0_32      Sch=sw[8]
+#set_property -dict { PACKAGE_PIN AJ16  IOSTANDARD LVCMOS18 } [get_ports { sw[9] }];  #IO_L3N_T0_DQS_32  Sch=sw[9]
+#set_property -dict { PACKAGE_PIN AK16  IOSTANDARD LVCMOS18 } [get_ports { sw[10] }]; #IO_L1P_T0_32      Sch=sw[10]
+#set_property -dict { PACKAGE_PIN AK15  IOSTANDARD LVCMOS18 } [get_ports { sw[11] }]; #IO_L1N_T0_32      Sch=sw[11]
+#set_property -dict { PACKAGE_PIN AG15  IOSTANDARD LVCMOS18 } [get_ports { sw[12] }]; #IO_L2P_T0_32      Sch=sw[12]
+#set_property -dict { PACKAGE_PIN AH15  IOSTANDARD LVCMOS18 } [get_ports { sw[13] }]; #IO_L2N_T0_32      Sch=sw[13]
+#set_property -dict { PACKAGE_PIN AG14  IOSTANDARD LVCMOS18 } [get_ports { sw[14] }]; #IO_L4N_T0_32      Sch=sw[14]
+#set_property -dict { PACKAGE_PIN AF15  IOSTANDARD LVCMOS18 } [get_ports { sw[15] }]; #IO_L4P_T0_32      Sch=sw[15]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L19P_T3_18 Sch=led16_b
+#set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L20P_T3_18 Sch=led16_g
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L19N_T3_VREF_18 Sch=led16_r
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L20N_T3_18 Sch=led17_b
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_L21N_T3_DQS_18 Sch=led17_g
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L21P_T3_DQS_18 Sch=led17_r
+
+## LEDs
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L9P_T1_DQS_18 Sch=ld[0]
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L9N_T1_DQS_18 Sch=ld[1]
+#set_property -dict { PACKAGE_PIN H11   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L10P_T1_18 Sch=ld[2]
+#set_property -dict { PACKAGE_PIN H12   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L10N_T1_18 Sch=ld[3]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L11P_T1_SRCC_18 Sch=ld[4]
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L11N_T1_SRCC_18 Sch=ld[5]
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L12P_T1_MRCC_18 Sch=ld[6]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L12N_T1_MRCC_18 Sch=ld[7]
+#set_property -dict { PACKAGE_PIN F12   IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L14P_T2_SRCC_18 Sch=ld[8]
+#set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_18 Sch=ld[9]
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L15P_T2_DQS_18 Sch=ld[10]
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_18 Sch=ld[11]
+#set_property -dict { PACKAGE_PIN F11   IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_18 Sch=ld[12]
+#set_property -dict { PACKAGE_PIN AB27  IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L12P_T1_MRCC_13 Sch=ld[13]
+#set_property -dict { PACKAGE_PIN AC27  IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L12N_T1_MRCC_13 Sch=ld[14]
+#set_property -dict { PACKAGE_PIN G30   IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L24N_T3_16 Sch=ld[15]
+
+## Twenty-Five Button Keypad
+#set_property -dict { PACKAGE_PIN AE13  IOSTANDARD LVCMOS15 } [get_ports { btn_c[0] }]; #IO_L19P_T3_33 Sch=btn_c[0]
+#set_property -dict { PACKAGE_PIN AJ14  IOSTANDARD LVCMOS15 } [get_ports { btn_c[1] }]; #IO_L21N_T3_DQS_33 Sch=btn_c[1]
+#set_property -dict { PACKAGE_PIN AJ13  IOSTANDARD LVCMOS15 } [get_ports { btn_c[2] }]; #IO_L22P_T3_33 Sch=btn_c[2]
+#set_property -dict { PACKAGE_PIN AH14  IOSTANDARD LVCMOS15 } [get_ports { btn_c[3] }]; #IO_L21P_T3_DQS_33 Sch=btn_c[3]
+#set_property -dict { PACKAGE_PIN AG12  IOSTANDARD LVCMOS15 } [get_ports { btn_c[4] }]; #IO_L23N_T3_33 Sch=btn_c[4]
+#set_property -dict { PACKAGE_PIN AK14  IOSTANDARD LVCMOS15 } [get_ports { btn_r[0] }]; #IO_L20P_T3_33 Sch=btn_r[0]
+#set_property -dict { PACKAGE_PIN AK13  IOSTANDARD LVCMOS15 } [get_ports { btn_r[1] }]; #IO_L20N_T3_33 Sch=btn_r[1]
+#set_property -dict { PACKAGE_PIN AJ12  IOSTANDARD LVCMOS15 } [get_ports { btn_r[2] }]; #IO_L22N_T3_33 Sch=btn_r[2]
+#set_property -dict { PACKAGE_PIN AF12  IOSTANDARD LVCMOS15 } [get_ports { btn_r[3] }]; #IO_L23P_T3_33 Sch=btn_r[3]
+#set_property -dict { PACKAGE_PIN AH10  IOSTANDARD LVCMOS15 } [get_ports { btn_r[4] }]; #IO_L13N_T2_MRCC_33 Sch=btn_r[4]
+
+## Seven Segment Display
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { sseg_clk }]; #IO_L17P_T2_18 Sch=7seg_clk
+#set_property -dict { PACKAGE_PIN A12   IOSTANDARD LVCMOS33 } [get_ports { sseg_en }]; #IO_L17N_T2_18 Sch=7seg_en
+#set_property -dict { PACKAGE_PIN E11   IOSTANDARD LVCMOS33 } [get_ports { sseg_sdo }]; #IO_L16N_T2_18 Sch=7seg_sdo
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN E24   IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L4P_T0_16 Sch=ja_p[1]
+#set_property -dict { PACKAGE_PIN D24   IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L4N_T0_16 Sch=ja_n[1]
+#set_property -dict { PACKAGE_PIN G23   IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L6P_T0_16 Sch=ja_p[2]
+#set_property -dict { PACKAGE_PIN G24   IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L6N_T0_VREF_16 Sch=ja_n[2]
+#set_property -dict { PACKAGE_PIN F26   IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L5P_T0_16 Sch=ja_p[3]
+#set_property -dict { PACKAGE_PIN E26   IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L5N_T0_16 Sch=ja_n[3]
+#set_property -dict { PACKAGE_PIN B27   IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L7P_T1_16 Sch=ja_p[4]
+#set_property -dict { PACKAGE_PIN A27   IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L7N_T1_16 Sch=ja_n[4]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN B28   IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L9P_T1_DQS_16 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN A28   IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L9N_T1_DQS_16 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN A25   IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L10P_T1_16 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN A26   IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L10N_T1_16 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN D26   IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L11P_T1_SRCC_16 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN C26   IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L11N_T1_SRCC_16 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN C25   IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L12P_T1_MRCC_16 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN B25   IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L12N_T1_MRCC_16 Sch=jb_n[4]
+
+## Pmod Header JC
+#set_property -dict { PACKAGE_PIN E28   IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L14P_T2_SRCC_16 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN D28   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L14N_T2_SRCC_16 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN C29   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_16 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN B29   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_16 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN D29   IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_16 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN C30   IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L16N_T2_16 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN B30   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L17P_T2_16 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN A30   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L17N_T2_16 Sch=jc[10]
+
+## Pmod Header JD
+#set_property -dict { PACKAGE_PIN E29   IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L18P_T2_16 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN E30   IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L18N_T2_16 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN H24   IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L19P_T3_16 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN H25   IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L19N_T3_VREF_16 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN G28   IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L20P_T3_16 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN F28   IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20N_T3_16 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN G27   IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_16 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN F27   IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_16 Sch=jd[10]
+
+## USB-UART Interface
+## NOTE: 
+#set_property -dict { PACKAGE_PIN F30   IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L22N_T3_16 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN G29   IOSTANDARD LVCMOS33 } [get_ports { uart_rx }]; #IO_L22P_T3_16 Sch=uart_txd_in
+
+## USB-HID PS/2 Interface for Keyboard
+#set_property -dict { PACKAGE_PIN AF23  IOSTANDARD LVCMOS33 } [get_ports { ps2_keyboard_clk }]; #IO_L11N_T1_SRCC_12 Sch=ps2_clk[0]
+#set_property -dict { PACKAGE_PIN AD23  IOSTANDARD LVCMOS33 } [get_ports { ps2_keyboard_data }]; #IO_L12P_T1_MRCC_12 Sch=ps2_data[0]
+
+## USB-HID PS/2 Interface for Mouse
+#set_property -dict { PACKAGE_PIN AE24  IOSTANDARD LVCMOS33 } [get_ports { ps2_mouse_clk }]; #IO_L12N_T1_MRCC_12 Sch=ps2_clk[1]
+#set_property -dict { PACKAGE_PIN AF22  IOSTANDARD LVCMOS33 } [get_ports { ps2_mouse_data }]; #IO_L13P_T2_MRCC_12 Sch=ps2_data[1]
+
+## Audio Codec
+#set_property -dict { PACKAGE_PIN AJ18  IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L9P_T1_DQS_32 Sch=aud_adc_sdata
+#set_property -dict { PACKAGE_PIN AF18  IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L11P_T1_SRCC_32 Sch=aud_adr[0]
+#set_property -dict { PACKAGE_PIN AG18  IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L11N_T1_SRCC_32 Sch=aud_adr[1]
+#set_property -dict { PACKAGE_PIN AD19  IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L10P_T1_32 Sch=aud_bclk
+#set_property -dict { PACKAGE_PIN AK18  IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L9N_T1_DQS_32 Sch=aud_dac_sdata
+#set_property -dict { PACKAGE_PIN AE19  IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_T1_32 Sch=aud_lrclk
+#set_property -dict { PACKAGE_PIN AF17  IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L12P_T1_MRCC_32 Sch=aud_mclk
+#set_property -dict { PACKAGE_PIN AB14  IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_25_VRP_32 Sch=aud_scl
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_0_VRN_32 Sch=aud_sda
+
+## Dedicated Analog Inputs
+#set_property -dict { PACKAGE_PIN R15   } [get_ports { v_p }]; #VP_0 Sch=v_p
+#set_property -dict { PACKAGE_PIN T14   } [get_ports { v_n }]; #VN_0 Sch=v_n
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN N22   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L20N_T3_A19_15 Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN N25   IOSTANDARD LVCMOS33 } [get_ports { ck_io1  }]; #IO_L18P_T2_A24_15 Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN P22   IOSTANDARD LVCMOS33 } [get_ports { ck_io2  }]; #IO_L22N_T3_A16_15 Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN G25   IOSTANDARD LVCMOS33 } [get_ports { ck_io3  }]; #IO_25_16 Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN L25   IOSTANDARD LVCMOS33 } [get_ports { ck_io4  }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN M25   IOSTANDARD LVCMOS33 } [get_ports { ck_io5  }]; #IO_L23N_T3_FWE_B_15 Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN L26   IOSTANDARD LVCMOS33 } [get_ports { ck_io6  }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN K29   IOSTANDARD LVCMOS33 } [get_ports { ck_io7  }]; #IO_L13N_T2_MRCC_15 Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN M29   IOSTANDARD LVCMOS33 } [get_ports { ck_io8  }]; #IO_L15P_T2_DQS_15 Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN M30   IOSTANDARD LVCMOS33 } [get_ports { ck_io9  }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=ck_io[9]
+
+## ChipKit SPI Header
+## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13
+#set_property -dict { PACKAGE_PIN L28   IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss   }]; #IO_L14N_T2_SRCC_15 Sch=ck_io10_ss
+#set_property -dict { PACKAGE_PIN M27   IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L16N_T2_A27_15 Sch=ck_io11_mosi
+#set_property -dict { PACKAGE_PIN N29   IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L17P_T2_A26_15 Sch=ck_io12_miso
+#set_property -dict { PACKAGE_PIN N30   IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck  }]; #IO_L17N_T2_A25_15 Sch=ck_io13_sck
+
+## ChipKit Inner Digital Header
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L6P_T0_15 Sch=ck_io[26]
+#set_property -dict { PACKAGE_PIN N24   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L21N_T3_DQS_A18_15 Sch=ck_io[27]
+#set_property -dict { PACKAGE_PIN P23   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L21P_T3_DQS_15 Sch=ck_io[28]
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_0_15 Sch=ck_io[29]
+#set_property -dict { PACKAGE_PIN P21   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A17_15 Sch=ck_io[30]
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L19N_T3_A21_VREF_15 Sch=ck_io[31]
+#set_property -dict { PACKAGE_PIN F23   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_0_16 Sch=ck_io[32]
+#set_property -dict { PACKAGE_PIN K28   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_15 	  	Sch=ck_io[33]
+#set_property -dict { PACKAGE_PIN L27   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L11N_T1_SRCC_AD12N_15 	Sch=ck_io[34]
+#set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19P_T3_A22_15 			Sch=ck_io[35]
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_25_15 Sch=ck_io[36]
+#set_property -dict { PACKAGE_PIN M28   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L14P_T2_SRCC_15 Sch=ck_io[37]
+#set_property -dict { PACKAGE_PIN M22   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L24P_T3_RS1_15 Sch=ck_io[38]
+#set_property -dict { PACKAGE_PIN M23   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L24N_T3_RS0_15 Sch=ck_io[39]
+#set_property -dict { PACKAGE_PIN N27   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16P_T2_A28_15 Sch=ck_io[40]
+#set_property -dict { PACKAGE_PIN N26   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18N_T2_A23_15 Sch=ck_io[41]
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN J29   IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L7P_T1_AD10P_15 Sch=ck_an_p[0] ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN H29   IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L7N_T1_AD10N_15 Sch=ck_an_n[0] ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN L22   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15 Sch=ck_an_p[1] ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN L23   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15 Sch=ck_an_n[1] ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN J23   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[2] ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN J24   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[2] ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN K23   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[3] ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN K24   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[3] ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN L21   IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L4P_T0_AD9P_15 Sch=ck_an_p[4] ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN K21   IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L4N_T0_AD9N_15 Sch=ck_an_n[4] ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN J21   IOSTANDARD LVCMOS33 } [get_ports { vaux2_p }]; #IO_L5P_T0_AD2P_15 Sch=ck_an_p[5] ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN J22   IOSTANDARD LVCMOS33 } [get_ports { vaux2_n }]; #IO_L5N_T0_AD2N_15 Sch=ck_an_n[5] ChipKit pin=A5
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN B23   IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L1P_T0_16 Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN A23   IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L1N_T0_16 Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN E23   IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L2P_T0_16 Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN D23   IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L2N_T0_16 Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN F25   IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L3P_T0_DQS_16 Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN E25   IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L3N_T0_DQS_16 Sch=ck_a[5]
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
+#set_property -dict { PACKAGE_PIN J27   IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L8P_T1_AD3P_15 Sch=fpga_ad_p[3] 		  ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN J28   IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L8N_T1_AD3N_15 Sch=fpga_ad_n[3] 		  ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN L30   IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fpga_ad_p[11] ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN K30   IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fpga_ad_n[11] ChipKit pin=A9
+#set_property -dict { PACKAGE_PIN K26   IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L10P_T1_AD4P_15 Sch=fpga_ad_p[4] 	  ChipKit pin=A10
+#set_property -dict { PACKAGE_PIN J26   IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L10N_T1_AD4N_15 Sch=fpga_ad_n[4] 	  ChipKit pin=A11
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN J28   IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L8N_T1_AD3N_15 Sch=fpga_ad_n[3]
+#set_property -dict { PACKAGE_PIN J27   IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L8P_T1_AD3P_15 Sch=fpga_ad_p[3]
+#set_property -dict { PACKAGE_PIN K30   IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fpga_ad_n[11]
+#set_property -dict { PACKAGE_PIN L30   IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fpga_ad_p[11]
+#set_property -dict { PACKAGE_PIN J26   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L10N_T1_AD4N_15 Sch=fpga_ad_n[4]
+#set_property -dict { PACKAGE_PIN K26   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L10P_T1_AD4P_15 Sch=fpga_ad_p[4]
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN K25   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN N21   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L20P_T3_A20_15 Sch=ck_sda
+
+## Misc. ChipKit signals
+#set_property -dict { PACKAGE_PIN M24   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L23P_T3_FOE_B_15 Sch=ck_ioa
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L6N_T0_VREF_15 Sch=ck_rst
+
+## Fan Control
+#set_property -dict { PACKAGE_PIN H27   IOSTANDARD LVCMOS33 } [get_ports { fan_pwm }]; #IO_L23N_T3_16 Sch=fan_pwm
+#set_property -dict { PACKAGE_PIN H26   IOSTANDARD LVCMOS33 } [get_ports { fan_tach }]; #IO_L23P_T3_16 Sch=fan_tach
+
+## USB Host Port
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { usbh_gpx }]; #IO_L22P_T3_18 Sch=usbh_gpx
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { usbh_int }]; #IO_L22N_T3_18 Sch=usbh_int
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { usbh_miso }]; #IO_L24P_T3_18 Sch=usbh_miso
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { usbh_mosi }]; #IO_L24N_T3_18 Sch=usbh_mosi
+#set_property -dict { PACKAGE_PIN AD13  IOSTANDARD LVCMOS15 } [get_ports { usbh_rst }]; #IO_25_VRP_33 Sch=usbh_rst
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { usbh_sclk }]; #IO_L23P_T3_18 Sch=usbh_sclk
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { usbh_ss }]; #IO_L23N_T3_18 Sch=usbh_ss
+
+## RS232 Connector
+#set_property -dict { PACKAGE_PIN D11   IOSTANDARD LVCMOS33 } [get_ports { rs232_rxd }]; #IO_L18P_T2_18 Sch=uart1_rxd
+#set_property -dict { PACKAGE_PIN G12   IOSTANDARD LVCMOS33 } [get_ports { rs232_txd }]; #IO_0_18 Sch=uart1_txd
+
+# 3-Pin UART Connector (TTL-Compliant)
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { ttl_rxd }]; #IO_L18N_T2_18 Sch=uart2_rxd
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { ttl_txd }]; #IO_25_18 Sch=uart2_txd
+
+## VGA Connector
+#set_property -dict { PACKAGE_PIN AA23  IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L4N_T0_12 Sch=vga_b[3]
+#set_property -dict { PACKAGE_PIN AC24  IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L9P_T1_DQS_12 Sch=vga_b[4]
+#set_property -dict { PACKAGE_PIN AD24  IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L9N_T1_DQS_12 Sch=vga_b[5]
+#set_property -dict { PACKAGE_PIN AB23  IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L3N_T0_DQS_12 Sch=vga_b[6]
+#set_property -dict { PACKAGE_PIN AB22  IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L3P_T0_DQS_12 Sch=vga_b[7]
+#set_property -dict { PACKAGE_PIN AA22  IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L4P_T0_12 Sch=vga_g[2]
+#set_property -dict { PACKAGE_PIN AC21  IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L5N_T0_12 Sch=vga_g[3]
+#set_property -dict { PACKAGE_PIN Y21   IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2P_T0_12 Sch=vga_g[4]
+#set_property -dict { PACKAGE_PIN AC20  IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L5P_T0_12 Sch=vga_g[5]
+#set_property -dict { PACKAGE_PIN AB20  IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L6N_T0_VREF_12 Sch=vga_g[6]
+#set_property -dict { PACKAGE_PIN AA20  IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L6P_T0_12 Sch=vga_g[7]
+#set_property -dict { PACKAGE_PIN AC25  IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7N_T1_12 Sch=vga_r[3]
+#set_property -dict { PACKAGE_PIN AB24  IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7P_T1_12 Sch=vga_r[4]
+#set_property -dict { PACKAGE_PIN Y24   IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_12 Sch=vga_r[5]
+#set_property -dict { PACKAGE_PIN Y23   IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L1P_T0_12 Sch=vga_r[6]
+#set_property -dict { PACKAGE_PIN AD22  IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L8N_T1_12 Sch=vga_r[7]
+#set_property -dict { PACKAGE_PIN AD21  IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L10P_T1_12 Sch=vga_hs
+#set_property -dict { PACKAGE_PIN AE23  IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L11P_T1_SRCC_12 Sch=vga_vs
+#set_property -dict { PACKAGE_PIN AC22  IOSTANDARD LVCMOS33 } [get_ports { vga_scl }]; #IO_L8P_T1_12 Sch=vga_scl
+#set_property -dict { PACKAGE_PIN AA21  IOSTANDARD LVCMOS33 } [get_ports { vga_sda }]; #IO_L2N_T0_12 Sch=vga_sda
+
+## HDMI Input
+#set_property -dict { PACKAGE_PIN AF21  IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L19N_T3_VREF_12 Sch=hdmi_rx_cec
+#set_property -dict { PACKAGE_PIN AH29  IOSTANDARD LVDS     } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN AG29  IOSTANDARD LVDS     } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN AF20  IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L19P_T3_12 Sch=hdmi_rx_hpa
+#set_property -dict { PACKAGE_PIN AK26  IOSTANDARD LVDS     } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN AJ26  IOSTANDARD LVDS     } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN AH27  IOSTANDARD LVDS     } [get_ports { hdmi_rx_n[1] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN AH26  IOSTANDARD LVDS     } [get_ports { hdmi_rx_p[1] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN AF27  IOSTANDARD LVDS     } [get_ports { hdmi_rx_n[2] }]; #IO_L23N_T3_13 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN AF26  IOSTANDARD LVDS     } [get_ports { hdmi_rx_p[2] }]; #IO_L23P_T3_13 Sch=hdmi_rx_p[2]
+#set_property -dict { PACKAGE_PIN AK24  IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17N_T2_12 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN AK23  IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17P_T2_12 Sch=hdmi_rx_sda
+
+## HDMI Output
+#set_property -dict { PACKAGE_PIN AH25  IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L18N_T2_12 Sch=hdmi_tx_cec
+#set_property -dict { PACKAGE_PIN AH20  IOSTANDARD LVDS     } [get_ports { hdmi_tx_clk_n }]; #IO_L22N_T3_12 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN AG20  IOSTANDARD LVDS     } [get_ports { hdmi_tx_clk_p }]; #IO_L22P_T3_12 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN AG25  IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L18P_T2_12 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN AJ21  IOSTANDARD LVDS     } [get_ports { hdmi_tx_n[0] }]; #IO_L23N_T3_12 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN AH21  IOSTANDARD LVDS     } [get_ports { hdmi_tx_p[0] }]; #IO_L23P_T3_12 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN AJ23  IOSTANDARD LVDS     } [get_ports { hdmi_tx_n[1] }]; #IO_L21N_T3_DQS_12 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN AJ22  IOSTANDARD LVDS     } [get_ports { hdmi_tx_p[1] }]; #IO_L21P_T3_DQS_12 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN AH22  IOSTANDARD LVDS     } [get_ports { hdmi_tx_n[2] }]; #IO_L20N_T3_12 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN AG22  IOSTANDARD LVDS     } [get_ports { hdmi_tx_p[2] }]; #IO_L20P_T3_12 Sch=hdmi_tx_p[2]
+#set_property -dict { PACKAGE_PIN AK20  IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L24P_T3_12 Sch=hdmi_tx_scl
+#set_property -dict { PACKAGE_PIN AK21  IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L24N_T3_12 Sch=hdmi_tx_sda
+
+## Ethernet
+#set_property -dict { PACKAGE_PIN AB18  IOSTANDARD LVCMOS18 } [get_ports { eth_intb }]; #IO_L16N_T2_32 Sch=eth_intb
+#set_property -dict { PACKAGE_PIN AA18  IOSTANDARD LVCMOS18 } [get_ports { eth_mdc }]; #IO_L16P_T2_32 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS18 } [get_ports { eth_mdio }]; #IO_L15N_T2_DQS_32 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS18 } [get_ports { eth_phyrst }]; #IO_L15P_T2_DQS_32 Sch=eth_phyrst
+#set_property -dict { PACKAGE_PIN AB19  IOSTANDARD LVCMOS18 } [get_ports { eth_pmeb }]; #IO_L17P_T2_32 Sch=eth_pmeb
+#set_property -dict { PACKAGE_PIN AD18  IOSTANDARD LVCMOS18 } [get_ports { eth_rx_clk }]; #IO_L13P_T2_MRCC_32 Sch=eth_rx_clk
+#set_property -dict { PACKAGE_PIN AE14  IOSTANDARD LVCMOS18 } [get_ports { eth_rx_ctl }]; #IO_L19N_T3_VREF_32 Sch=eth_rx_ctl
+#set_property -dict { PACKAGE_PIN AE15  IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[0] }]; #IO_L19P_T3_32 Sch=eth_rx_d[0]
+#set_property -dict { PACKAGE_PIN AE18  IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[1] }]; #IO_L13N_T2_MRCC_32 Sch=eth_rx_d[1]
+#set_property -dict { PACKAGE_PIN AD16  IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[2] }]; #IO_L14N_T2_SRCC_32 Sch=eth_rx_d[2]
+#set_property -dict { PACKAGE_PIN AC19  IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[3] }]; #IO_L17N_T2_32 Sch=eth_rx_d[3]
+#set_property -dict { PACKAGE_PIN AB15  IOSTANDARD LVCMOS18 } [get_ports { eth_tx_clk }]; #IO_L20N_T3_32 Sch=eth_tx_clk
+#set_property -dict { PACKAGE_PIN AA15  IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[0] }]; #IO_L20P_T3_32 Sch=eth_tx_d[0]
+#set_property -dict { PACKAGE_PIN AD17  IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[1] }]; #IO_L14P_T2_SRCC_32 Sch=eth_tx_d[1]
+#set_property -dict { PACKAGE_PIN AG17  IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[2] }]; #IO_L12N_T1_MRCC_32 Sch=eth_tx_d[2]
+#set_property -dict { PACKAGE_PIN AC17  IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[3] }]; #IO_L18N_T2_32 Sch=eth_tx_d[3]
+#set_property -dict { PACKAGE_PIN AB17  IOSTANDARD LVCMOS18 } [get_ports { eth_tx_en }]; #IO_L18P_T2_32 Sch=eth_tx_en
+
+## SFP+ Clock Multiplier / FPGA GTX Transceiver Clock Source
+#set_property -dict { PACKAGE_PIN AC16  IOSTANDARD LVCMOS18 } [get_ports { sfp_clk_alarm_b }]; #IO_L21P_T3_DQS_32 Sch=sfp_clk_alarm_b
+#set_property -dict { PACKAGE_PIN AC15  IOSTANDARD LVCMOS18 } [get_ports { sfp_clk_rst }]; #IO_L21N_T3_DQS_32 Sch=sfp_clk_rst
+#set_property -dict { PACKAGE_PIN AE20  IOSTANDARD LVCMOS33 } [get_ports { sfp_clk_scl }]; #IO_25_12 Sch=sfp_clk_scl
+#set_property -dict { PACKAGE_PIN Y20   IOSTANDARD LVCMOS33 } [get_ports { sfp_clk_sda }]; #IO_0_12 Sch=sfp_clk_sda
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVDS     } [get_ports { sfp_rec_clk_n }]; #IO_L13N_T2_MRCC_18 Sch=sfp_rec_clk_n
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVDS     } [get_ports { sfp_rec_clk_p }]; #IO_L13P_T2_MRCC_18 Sch=sfp_rec_clk_p
+
+## SFP+ Connector 1
+#set_property -dict { PACKAGE_PIN AA17  IOSTANDARD LVCMOS18 } [get_ports { sfp1_mod_detect }]; #IO_L23P_T3_32 Sch=sfp1_mod_detect
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS18 } [get_ports { sfp1_rs[0] }]; #IO_L24P_T3_32 Sch=sfp1_rs[0]
+#set_property -dict { PACKAGE_PIN Y15   IOSTANDARD LVCMOS18 } [get_ports { sfp1_rs[1] }]; #IO_L24N_T3_32 Sch=sfp1_rs[1]
+#set_property -dict { PACKAGE_PIN AA16  IOSTANDARD LVCMOS18 } [get_ports { sfp1_rx_los }]; #IO_L23N_T3_32 Sch=sfp1_rx_los
+#set_property -dict { PACKAGE_PIN AD14  IOSTANDARD LVCMOS18 } [get_ports { sfp1_tx_disable }]; #IO_L22N_T3_32 Sch=sfp1_tx_disable
+#set_property -dict { PACKAGE_PIN AC14  IOSTANDARD LVCMOS18 } [get_ports { sfp1_tx_fault }]; #IO_L22P_T3_32 Sch=sfp1_tx_fault
+#set_property -dict { PACKAGE_PIN C27   IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp1_scl }]; #IO_L13N_T2_MRCC_16 Sch=i2c_sfp1_scl
+#set_property -dict { PACKAGE_PIN D27   IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp1_sda }]; #IO_L13P_T2_MRCC_16 Sch=i2c_sfp1_sda
+
+## SFP+ Connector 2
+#set_property -dict { PACKAGE_PIN AH11  IOSTANDARD LVCMOS15 } [get_ports { sfp2_mod_detect }]; #IO_L18P_T2_33 Sch=sfp2_mod_detect
+#set_property -dict { PACKAGE_PIN AE10  IOSTANDARD LVCMOS15 } [get_ports { sfp2_rs[0] }]; #IO_L14P_T2_SRCC_33 Sch=sfp2_rs[0]
+#set_property -dict { PACKAGE_PIN AF10  IOSTANDARD LVCMOS15 } [get_ports { sfp2_rs[1] }]; #IO_L14N_T2_SRCC_33 Sch=sfp2_rs[1]
+#set_property -dict { PACKAGE_PIN AJ11  IOSTANDARD LVCMOS15 } [get_ports { sfp2_rx_los }]; #IO_L18N_T2_33 Sch=sfp2_rx_los
+#set_property -dict { PACKAGE_PIN AK10  IOSTANDARD LVCMOS15 } [get_ports { sfp2_tx_disable }]; #IO_L17N_T2_33 Sch=sfp2_tx_disable
+#set_property -dict { PACKAGE_PIN AK11  IOSTANDARD LVCMOS15 } [get_ports { sfp2_tx_fault }]; #IO_L17P_T2_33 Sch=sfp2_tx_fault
+#set_property -dict { PACKAGE_PIN B24   IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp2_scl }]; #IO_L8N_T1_16 Sch=i2c_sfp2_scl
+#set_property -dict { PACKAGE_PIN C24   IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp2_sda }]; #IO_L8P_T1_16 Sch=i2c_sfp2_sda
+
+## Quad-SPI Flash
+## NOTE: the SCK clock signal can be driven using the STARTUPE2 primitive
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
+#set_property -dict { PACKAGE_PIN P24   IOSTANDARD LVCMOS33 } [get_ports { qspi_d[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0]
+#set_property -dict { PACKAGE_PIN R25   IOSTANDARD LVCMOS33 } [get_ports { qspi_d[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1]
+#set_property -dict { PACKAGE_PIN R20   IOSTANDARD LVCMOS33 } [get_ports { qspi_d[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2]
+#set_property -dict { PACKAGE_PIN R21   IOSTANDARD LVCMOS33 } [get_ports { qspi_d[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3]
+
+## SD Card Slot
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_25_14 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN AJ24  IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L15P_T2_DQS_12 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN AE25  IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_12 Sch=sd_dat[0]
+#set_property -dict { PACKAGE_PIN AF25  IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L16N_T2_12 Sch=sd_dat[1]
+#set_property -dict { PACKAGE_PIN AG24  IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L14P_T2_SRCC_12 Sch=sd_dat[2]
+#set_property -dict { PACKAGE_PIN AH24  IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_12 Sch=sd_dat[3]
+#set_property -dict { PACKAGE_PIN AE21  IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L10N_T1_12 Sch=sd_reset
+#set_property -dict { PACKAGE_PIN AK25  IOSTANDARD LVCMOS33 } [get_ports { sd_sclk }]; #IO_L15N_T2_DQS_12 Sch=sd_sclk
+
+## Parallel Flash Memory
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { flash_byte }]; #IO_L19P_T3_17 Sch=flash_byte
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { flash_ce[0] }]; #IO_L18P_T2_17 Sch=flash_ce[1]
+#set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS33 } [get_ports { flash_ce[1] }]; #IO_L15P_T2_DQS_17 Sch=flash_ce[2]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { flash_oe }]; #IO_L15N_T2_DQS_17 Sch=flash_oe
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { flash_rst }]; #IO_L16N_T2_17 Sch=flash_rst
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { flash_ryby[0] }]; #IO_L16P_T2_17 Sch=flash_ryby[1]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { flash_ryby[1] }]; #IO_L24N_T3_17 Sch=flash_ryby[2]
+#set_property -dict { PACKAGE_PIN G22   IOSTANDARD LVCMOS33 } [get_ports { flash_we }]; #IO_L9P_T1_DQS_17 Sch=flash_we
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { flash_a[0] }]; #IO_L13P_T2_MRCC_17 Sch=flash_a[0]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { flash_a[1] }]; #IO_L22N_T3_17 Sch=flash_a[1]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { flash_a[2] }]; #IO_L17N_T2_17 Sch=flash_a[2]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { flash_a[3] }]; #IO_L20P_T3_17 Sch=flash_a[3]
+#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { flash_a[4] }]; #IO_L20N_T3_17 Sch=flash_a[4]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { flash_a[5] }]; #IO_L22P_T3_17 Sch=flash_a[5]
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { flash_a[6] }]; #IO_L17P_T2_17 Sch=flash_a[6]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { flash_a[7] }]; #IO_L14N_T2_SRCC_17 Sch=flash_a[7]
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { flash_a[8] }]; #IO_L12P_T1_MRCC_17 Sch=flash_a[8]
+#set_property -dict { PACKAGE_PIN F22   IOSTANDARD LVCMOS33 } [get_ports { flash_a[9] }]; #IO_L9N_T1_DQS_17 Sch=flash_a[9]
+#set_property -dict { PACKAGE_PIN C19   IOSTANDARD LVCMOS33 } [get_ports { flash_a[10] }]; #IO_L24P_T3_17 Sch=flash_a[10]
+#set_property -dict { PACKAGE_PIN E20   IOSTANDARD LVCMOS33 } [get_ports { flash_a[11] }]; #IO_L12N_T1_MRCC_17 Sch=flash_a[11]
+#set_property -dict { PACKAGE_PIN D22   IOSTANDARD LVCMOS33 } [get_ports { flash_a[12] }]; #IO_L10P_T1_17 Sch=flash_a[12]
+#set_property -dict { PACKAGE_PIN F21   IOSTANDARD LVCMOS33 } [get_ports { flash_a[13] }]; #IO_L11P_T1_SRCC_17 Sch=flash_a[13]
+#set_property -dict { PACKAGE_PIN C22   IOSTANDARD LVCMOS33 } [get_ports { flash_a[14] }]; #IO_L10N_T1_17 Sch=flash_a[14]
+#set_property -dict { PACKAGE_PIN E21   IOSTANDARD LVCMOS33 } [get_ports { flash_a[15] }]; #IO_L11N_T1_SRCC_17 Sch=flash_a[15]
+#set_property -dict { PACKAGE_PIN A21   IOSTANDARD LVCMOS33 } [get_ports { flash_a[16] }]; #IO_L21N_T3_DQS_17 Sch=flash_a[16]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { flash_a[17] }]; #IO_L13N_T2_MRCC_17 Sch=flash_a[17]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { flash_a[18] }]; #IO_25_17 Sch=flash_a[18]
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { flash_a[19] }]; #IO_L14P_T2_SRCC_17 Sch=flash_a[19]
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { flash_a[20] }]; #IO_L18N_T2_17 Sch=flash_a[20]
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { flash_a[21] }]; #IO_0_17 Sch=flash_a[21]
+#set_property -dict { PACKAGE_PIN B22   IOSTANDARD LVCMOS33 } [get_ports { flash_a[22] }]; #IO_L23P_T3_17 Sch=flash_a[22]
+#set_property -dict { PACKAGE_PIN A22   IOSTANDARD LVCMOS33 } [get_ports { flash_a[23] }]; #IO_L23N_T3_17 Sch=flash_a[23]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { flash_a[24] }]; #IO_L19N_T3_VREF_17 Sch=flash_a[24]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { flash_a[25] }]; #IO_L21P_T3_DQS_17 Sch=flash_a[25]
+#set_property -dict { PACKAGE_PIN L11   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[0] }]; #IO_L6P_T0_18 Sch=flash_dq[0]
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[1] }]; #IO_L4P_T0_18 Sch=flash_dq[1]
+#set_property -dict { PACKAGE_PIN L12   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[2] }]; #IO_L3P_T0_DQS_18 Sch=flash_dq[2]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[3] }]; #IO_L5N_T0_18 Sch=flash_dq[3]
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[4] }]; #IO_L2P_T0_18 Sch=flash_dq[4]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[5] }]; #IO_L2N_T0_18 Sch=flash_dq[5]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[6] }]; #IO_L1P_T0_18 Sch=flash_dq[6]
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[7] }]; #IO_L7N_T1_18 Sch=flash_dq[7]
+#set_property -dict { PACKAGE_PIN K11   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[8] }]; #IO_L6N_T0_VREF_18 Sch=flash_dq[8]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[9] }]; #IO_L3N_T0_DQS_18 Sch=flash_dq[9]
+#set_property -dict { PACKAGE_PIN J11   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[10] }]; #IO_L8P_T1_18 Sch=flash_dq[10]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[11] }]; #IO_L5P_T0_18 Sch=flash_dq[11]
+#set_property -dict { PACKAGE_PIN J12   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[12] }]; #IO_L8N_T1_18 Sch=flash_dq[12]
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[13] }]; #IO_L7P_T1_18 Sch=flash_dq[13]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[14] }]; #IO_L4N_T0_18 Sch=flash_dq[14]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[15] }]; #IO_L1N_T0_18 Sch=flash_dq[15]
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[16] }]; #IO_L3P_T0_DQS_17 Sch=flash_dq[16]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[17] }]; #IO_L3N_T0_DQS_17 Sch=flash_dq[17]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[18] }]; #IO_L6P_T0_17 Sch=flash_dq[18]
+#set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[19] }]; #IO_L4N_T0_17 Sch=flash_dq[19]
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[20] }]; #IO_L2N_T0_17 Sch=flash_dq[20]
+#set_property -dict { PACKAGE_PIN K20   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[21] }]; #IO_L6N_T0_VREF_17 Sch=flash_dq[21]
+#set_property -dict { PACKAGE_PIN D21   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[22] }]; #IO_L8P_T1_17 Sch=flash_dq[22]
+#set_property -dict { PACKAGE_PIN C21   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[23] }]; #IO_L8N_T1_17 Sch=flash_dq[23]
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[24] }]; #IO_L5P_T0_17 Sch=flash_dq[24]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[25] }]; #IO_L1N_T0_17 Sch=flash_dq[25]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[26] }]; #IO_L1P_T0_17 Sch=flash_dq[26]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[27] }]; #IO_L4P_T0_17 Sch=flash_dq[27]
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[28] }]; #IO_L2P_T0_17 Sch=flash_dq[28]
+#set_property -dict { PACKAGE_PIN H22   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[29] }]; #IO_L7N_T1_17 Sch=flash_dq[29]
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[30] }]; #IO_L5N_T0_17 Sch=flash_dq[30]
+#set_property -dict { PACKAGE_PIN H21   IOSTANDARD LVCMOS33 } [get_ports { flash_dq[31] }]; #IO_L7P_T1_17 Sch=flash_dq[31]
+
+## SRAM Memories
+#set_property -dict { PACKAGE_PIN U24   IOSTANDARD LVCMOS33 } [get_ports { sram1_bhe }]; #IO_L23P_T3_A03_D19_14 Sch=sram1-bhe
+#set_property -dict { PACKAGE_PIN AG30  IOSTANDARD LVCMOS33 } [get_ports { sram1_ble }]; #IO_L18P_T2_13 Sch=sram1-ble
+#set_property -dict { PACKAGE_PIN T25   IOSTANDARD LVCMOS33 } [get_ports { sram1_ce }]; #IO_L14P_T2_SRCC_14 Sch=sram1-ce
+#set_property -dict { PACKAGE_PIN AF30  IOSTANDARD LVCMOS33 } [get_ports { sram1_oe }]; #IO_L16N_T2_13 Sch=sram1-oe
+#set_property -dict { PACKAGE_PIN AE28  IOSTANDARD LVCMOS33 } [get_ports { sram1_we }]; #IO_L14P_T2_SRCC_13 Sch=sram1-we
+#set_property -dict { PACKAGE_PIN AC29  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[0] }]; #IO_L7P_T1_13 Sch=sram1-io[0]
+#set_property -dict { PACKAGE_PIN T23   IOSTANDARD LVCMOS33 } [get_ports { sram1_io[1] }]; #IO_L5N_T0_D07_14 Sch=sram1-io[1]
+#set_property -dict { PACKAGE_PIN AC30  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[2] }]; #IO_L7N_T1_13 Sch=sram1-io[2]
+#set_property -dict { PACKAGE_PIN T22   IOSTANDARD LVCMOS33 } [get_ports { sram1_io[3] }]; #IO_L5P_T0_D06_14 Sch=sram1-io[3]
+#set_property -dict { PACKAGE_PIN AD26  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[4] }]; #IO_L19N_T3_VREF_13 Sch=sram1-io[4]
+#set_property -dict { PACKAGE_PIN AF28  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[5] }]; #IO_L14N_T2_SRCC_13 Sch=sram1-io[5]
+#set_property -dict { PACKAGE_PIN AB29  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[6] }]; #IO_L10P_T1_13 Sch=sram1-io[6]
+#set_property -dict { PACKAGE_PIN AB30  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[7] }]; #IO_L10N_T1_13 Sch=sram1-io[7]
+#set_property -dict { PACKAGE_PIN AH30  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[8] }]; #IO_L18N_T2_13 Sch=sram1-io[8]
+#set_property -dict { PACKAGE_PIN AJ29  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[9] }]; #IO_L17N_T2_13 Sch=sram1-io[9]
+#set_property -dict { PACKAGE_PIN V25   IOSTANDARD LVCMOS33 } [get_ports { sram1_io[10] }]; #IO_L18P_T2_A12_D28_14 Sch=sram1-io[10]
+#set_property -dict { PACKAGE_PIN V24   IOSTANDARD LVCMOS33 } [get_ports { sram1_io[11] }]; #IO_L23N_T3_A02_D18_14 Sch=sram1-io[11]
+#set_property -dict { PACKAGE_PIN U23   IOSTANDARD LVCMOS33 } [get_ports { sram1_io[12] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram1-io[12]
+#set_property -dict { PACKAGE_PIN V22   IOSTANDARD LVCMOS33 } [get_ports { sram1_io[13] }]; #IO_L22N_T3_A04_D20_14 Sch=sram1-io[13]
+#set_property -dict { PACKAGE_PIN AK30  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[14] }]; #IO_L15N_T2_DQS_13 Sch=sram1-io[14]
+#set_property -dict { PACKAGE_PIN AK29  IOSTANDARD LVCMOS33 } [get_ports { sram1_io[15] }]; #IO_L15P_T2_DQS_13 Sch=sram1-io[15]
+
+#set_property -dict { PACKAGE_PIN AB28  IOSTANDARD LVCMOS33 } [get_ports { sram2_bhe[0] }]; #IO_L5N_T0_13 Sch=sram2-bhe[1]
+#set_property -dict { PACKAGE_PIN V26   IOSTANDARD LVCMOS33 } [get_ports { sram2_bhe[1] }]; #IO_L16P_T2_CSI_B_14 Sch=sram2-bhe[2]
+#set_property -dict { PACKAGE_PIN AC26  IOSTANDARD LVCMOS33 } [get_ports { sram2_ble[0] }]; #IO_L19P_T3_13 Sch=sram2-ble[1]
+#set_property -dict { PACKAGE_PIN W27   IOSTANDARD LVCMOS33 } [get_ports { sram2_ble[1] }]; #IO_L2P_T0_13 Sch=sram2-ble[2]
+#set_property -dict { PACKAGE_PIN Y28   IOSTANDARD LVCMOS33 } [get_ports { sram2_ce[0] }]; #IO_L3P_T0_DQS_13 Sch=sram2-ce[1]
+#set_property -dict { PACKAGE_PIN P28   IOSTANDARD LVCMOS33 } [get_ports { sram2_ce[1] }]; #IO_L8N_T1_D12_14 Sch=sram2-ce[2]
+#set_property -dict { PACKAGE_PIN AB25  IOSTANDARD LVCMOS33 } [get_ports { sram2_oe[0] }]; #IO_L6N_T0_VREF_13 Sch=sram2-oe[1]
+#set_property -dict { PACKAGE_PIN U30   IOSTANDARD LVCMOS33 } [get_ports { sram2_oe[1] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram2-oe[2]
+#set_property -dict { PACKAGE_PIN W23   IOSTANDARD LVCMOS33 } [get_ports { sram2_we[0] }]; #IO_L20P_T3_A08_D24_14 Sch=sram2-we[1]
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { sram2_we[1] }]; #IO_L4P_T0_D04_14 Sch=sram2-we[2]
+#set_property -dict { PACKAGE_PIN Y26   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[0] }]; #IO_L1P_T0_13 Sch=sram2-io[0]
+#set_property -dict { PACKAGE_PIN AA26  IOSTANDARD LVCMOS33 } [get_ports { sram2_io[1] }]; #IO_L1N_T0_13 Sch=sram2-io[1]
+#set_property -dict { PACKAGE_PIN U27   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[2] }]; #IO_L13P_T2_MRCC_14 Sch=sram2-io[2]
+#set_property -dict { PACKAGE_PIN AA28  IOSTANDARD LVCMOS33 } [get_ports { sram2_io[3] }]; #IO_L3N_T0_DQS_13 Sch=sram2-io[3]
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sram2-io[4]
+#set_property -dict { PACKAGE_PIN W26   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[5] }]; #IO_L18N_T2_A11_D27_14 Sch=sram2-io[5]
+#set_property -dict { PACKAGE_PIN U22   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[6] }]; #IO_L21P_T3_DQS_14 Sch=sram2-io[6]
+#set_property -dict { PACKAGE_PIN P26   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[7] }]; #IO_L10P_T1_D14_14 Sch=sram2-io[7]
+#set_property -dict { PACKAGE_PIN Y25   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[8] }]; #IO_0_13 Sch=sram2-io[8]
+#set_property -dict { PACKAGE_PIN AA25  IOSTANDARD LVCMOS33 } [get_ports { sram2_io[9] }]; #IO_L6P_T0_13 Sch=sram2-io[9]
+#set_property -dict { PACKAGE_PIN AA27  IOSTANDARD LVCMOS33 } [get_ports { sram2_io[10] }]; #IO_L5P_T0_13 Sch=sram2-io[10]
+#set_property -dict { PACKAGE_PIN W24   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[11] }]; #IO_L20N_T3_A07_D23_14 Sch=sram2-io[11]
+#set_property -dict { PACKAGE_PIN W22   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[12] }]; #IO_L24N_T3_A00_D16_14 Sch=sram2-io[12]
+#set_property -dict { PACKAGE_PIN W21   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[13] }]; #IO_L24P_T3_A01_D17_14 Sch=sram2-io[13]
+#set_property -dict { PACKAGE_PIN AD28  IOSTANDARD LVCMOS33 } [get_ports { sram2_io[14] }]; #IO_L11N_T1_SRCC_13 Sch=sram2-io[14]
+#set_property -dict { PACKAGE_PIN AD27  IOSTANDARD LVCMOS33 } [get_ports { sram2_io[15] }]; #IO_L11P_T1_SRCC_13 Sch=sram2-io[15]
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[16] }]; #IO_0_14 Sch=sram2-io[16]
+#set_property -dict { PACKAGE_PIN R26   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[17] }]; #IO_L10N_T1_D15_14 Sch=sram2-io[17]
+#set_property -dict { PACKAGE_PIN R30   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[18] }]; #IO_L9P_T1_DQS_14 Sch=sram2-io[18]
+#set_property -dict { PACKAGE_PIN T30   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[19] }]; #IO_L9N_T1_DQS_D13_14 Sch=sram2-io[19]
+#set_property -dict { PACKAGE_PIN R29   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[20] }]; #IO_L7N_T1_D10_14 Sch=sram2-io[20]
+#set_property -dict { PACKAGE_PIN R28   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[21] }]; #IO_L11P_T1_SRCC_14 Sch=sram2-io[21]
+#set_property -dict { PACKAGE_PIN P29   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[22] }]; #IO_L7P_T1_D09_14 Sch=sram2-io[22]
+#set_property -dict { PACKAGE_PIN P27   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[23] }]; #IO_L8P_T1_D11_14 Sch=sram2-io[23]
+#set_property -dict { PACKAGE_PIN U29   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[24] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram2-io[24]
+#set_property -dict { PACKAGE_PIN V30   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[25] }]; #IO_L17N_T2_A13_D29_14 Sch=sram2-io[25]
+#set_property -dict { PACKAGE_PIN U28   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[26] }]; #IO_L13N_T2_MRCC_14 Sch=sram2-io[26]
+#set_property -dict { PACKAGE_PIN W28   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[27] }]; #IO_L2N_T0_13 Sch=sram2-io[27]
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=sram2-io[28]
+#set_property -dict { PACKAGE_PIN T21   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[29] }]; #IO_L4N_T0_D05_14 Sch=sram2-io[29]
+#set_property -dict { PACKAGE_PIN V29   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[30] }]; #IO_L17P_T2_A14_D30_14 Sch=sram2-io[30]
+#set_property -dict { PACKAGE_PIN W29   IOSTANDARD LVCMOS33 } [get_ports { sram2_io[31] }]; #IO_L4P_T0_13 Sch=sram2-io[31]
+
+#set_property -dict { PACKAGE_PIN AE29  IOSTANDARD LVCMOS33 } [get_ports { sram_a[0] }]; #IO_L9N_T1_DQS_13 Sch=sram-a[0]
+#set_property -dict { PACKAGE_PIN AE30  IOSTANDARD LVCMOS33 } [get_ports { sram_a[1] }]; #IO_L16P_T2_13 Sch=sram-a[1]
+#set_property -dict { PACKAGE_PIN AD29  IOSTANDARD LVCMOS33 } [get_ports { sram_a[2] }]; #IO_L9P_T1_DQS_13 Sch=sram-a[2]
+#set_property -dict { PACKAGE_PIN V27   IOSTANDARD LVCMOS33 } [get_ports { sram_a[3] }]; #IO_L16N_T2_A15_D31_14 Sch=sram-a[3]
+#set_property -dict { PACKAGE_PIN T26   IOSTANDARD LVCMOS33 } [get_ports { sram_a[4] }]; #IO_L12P_T1_MRCC_14 Sch=sram-a[4]
+#set_property -dict { PACKAGE_PIN U25   IOSTANDARD LVCMOS33 } [get_ports { sram_a[5] }]; #IO_L14N_T2_SRCC_14 Sch=sram-a[5]
+#set_property -dict { PACKAGE_PIN T28   IOSTANDARD LVCMOS33 } [get_ports { sram_a[6] }]; #IO_L11N_T1_SRCC_14 Sch=sram-a[6]
+#set_property -dict { PACKAGE_PIN R24   IOSTANDARD LVCMOS33 } [get_ports { sram_a[7] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sram-a[7]
+#set_property -dict { PACKAGE_PIN AK28  IOSTANDARD LVCMOS33 } [get_ports { sram_a[8] }]; #IO_L20N_T3_13 Sch=sram-a[8]
+#set_property -dict { PACKAGE_PIN AJ27  IOSTANDARD LVCMOS33 } [get_ports { sram_a[9] }]; #IO_L20P_T3_13 Sch=sram-a[9]
+#set_property -dict { PACKAGE_PIN Y30   IOSTANDARD LVCMOS33 } [get_ports { sram_a[10] }]; #IO_L8P_T1_13 Sch=sram-a[10]
+#set_property -dict { PACKAGE_PIN Y29   IOSTANDARD LVCMOS33 } [get_ports { sram_a[11] }]; #IO_L4N_T0_13 Sch=sram-a[11]
+#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { sram_a[12] }]; #IO_L19P_T3_A10_D26_14 Sch=sram-a[12]
+#set_property -dict { PACKAGE_PIN AG27  IOSTANDARD LVCMOS33 } [get_ports { sram_a[13] }]; #IO_L21P_T3_DQS_13 Sch=sram-a[13]
+#set_property -dict { PACKAGE_PIN V21   IOSTANDARD LVCMOS33 } [get_ports { sram_a[14] }]; #IO_L22P_T3_A05_D21_14 Sch=sram-a[14]
+#set_property -dict { PACKAGE_PIN AG28  IOSTANDARD LVCMOS33 } [get_ports { sram_a[15] }]; #IO_L21N_T3_DQS_13 Sch=sram-a[15]
+#set_property -dict { PACKAGE_PIN AE26  IOSTANDARD LVCMOS33 } [get_ports { sram_a[16] }]; #IO_25_13 Sch=sram-a[16]
+#set_property -dict { PACKAGE_PIN T27   IOSTANDARD LVCMOS33 } [get_ports { sram_a[17] }]; #IO_L12N_T1_MRCC_14 Sch=sram-a[17]
+#set_property -dict { PACKAGE_PIN AJ28  IOSTANDARD LVCMOS33 } [get_ports { sram_a[18] }]; #IO_L17P_T2_13 Sch=sram-a[18]
+#set_property -dict { PACKAGE_PIN AA30  IOSTANDARD LVCMOS33 } [get_ports { sram_a[19] }]; #IO_L8N_T1_13 Sch=sram-a[19]
diff --git a/Bibliotheken/digilent-xdc-master/USB104-A7-100T-Master.xdc b/Bibliotheken/digilent-xdc-master/USB104-A7-100T-Master.xdc
new file mode 100644
index 0000000..c0f66d7
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/USB104-A7-100T-Master.xdc
@@ -0,0 +1,186 @@
+## This file is a general .xdc for the USB104 A7-100T Rev. B.2
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## 100MHz Clock
+#set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]; #IO_L12P_T1_MRCC Sch=GCLK100
+#create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
+
+## Buttons
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L16N_T2_A15_D31_14 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L17P_T2_A14_D30_14 Sch=btn[1]
+
+## LEDs
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_14 Sch=led[0]
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_14 Sch=led[1]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L13N_T2_MRCC_14 Sch=led[2]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L14P_T2_SRCC_14 Sch=led[3]
+
+## USB UART
+## Note: Port names are from the perspective of the FPGA.
+#set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports { uart_rx }]; #IO_L20P_T3_A08_D24_14 Sch=uart_txd_in
+#set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports { uart_tx }]; #IO_L20N_T3_A07_D23_14 Sch=uart_rxd_out
+
+## DPTI/DSPI
+#set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports { prog_spien }]; #IO_L4P_T0_D04_14     Sch=prog_spien
+#set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports { prog_d[0] }];  #IO_L4N_T0_D05_14     Sch=prog_d[0]/sck
+#set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports { prog_d[1] }];  #IO_L5P_T0_D06_14     Sch=prog_d[1]/mosi
+#set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports { prog_d[2] }];  #IO_L5N_T0_D07_14     Sch=prog_d[2]/miso
+#set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports { prog_d[3] }];  #IO_L6N_T0_D08_14     Sch=prog_d[3]/ss
+#set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports { prog_d[4] }];  #IO_L7P_T1_D09_14     Sch=prog_d[4]
+#set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports { prog_d[5] }];  #IO_L7N_T1_D10_14     Sch=prog_d[5]
+#set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports { prog_d[6] }];  #IO_L8P_T1_D11_14     Sch=prog_d[6]
+#set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports { prog_d[7] }];  #IO_L8N_T1_D12_14     Sch=prog_d[7]
+#set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports { prog_oen }];   #IO_L9P_T1_DQS_14     Sch=prog_oen
+#set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports { prog_siwun }]; #IO_L9N_T1_DQS_D13_14 Sch=prog_siwun
+#set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports { prog_rxen }];  #IO_L10P_T1_D14_14    Sch=prog_rxen
+#set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports { prog_txen }];  #IO_L10N_T1_D15_14    Sch=prog_txen
+#set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports { prog_rdn }];   #IO_L11P_T1_SRCC_14   Sch=prog_rdn
+#set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports { prog_wrn }];   #IO_L11N_T1_SRCC_14   Sch=prog_wrn
+#set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports { prog_clko }];  #IO_L12P_T1_MRCC_14   Sch=prog_clko
+
+## Quad SPI Flash
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }}];   #IO_L6P_T0_FCS_B_14      Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { qspi_sck }];   #IO_L3N_T0_DQS_EMCCLK_14 Sch=qspi_sck
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14   Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14    Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14        Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14        Sch=qspi_dq[3]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_35 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_35 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L14P_T2_SRCC_35 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L14N_T2_SRCC_35 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L15P_T2_DQS_35  Sch=ja[7]
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L15N_T2_DQS_35  Sch=ja[8]
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L16P_T2_35      Sch=ja[9]
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L16N_T2_35      Sch=ja[10]
+
+### Pmod Header JB
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L7P_T1_AD6P_35     Sch=jb[1]
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L10N_T1_AD15N_35   Sch=jb[2]
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_AD15P_35   Sch=jb[3]
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L7N_T1_AD6N_35     Sch=jb[4]
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L8N_T1_AD14N_35    Sch=jb[9]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L8P_T1_AD14P_35    Sch=jb[10]
+
+### Pmod Header JC
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L1N_T0_AD4N_35     Sch=jc[1]
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L1P_T0_AD4P_35     Sch=jc[2]
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L2N_T0_AD12N_35    Sch=jc[3]
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L4N_T0_35          Sch=jc[4]
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_AD12P_35    Sch=jc[9]
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L4P_T0_35          Sch=jc[10]
+
+## SYZYGY Port
+#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=syzygy_d_p[0]
+#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=syzygy_d_n[0]
+#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[1] }]; #IO_L7P_T1_AD2P_15     Sch=syzygy_d_p[1]
+#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[1] }]; #IO_L7N_T1_AD2N_15     Sch=syzygy_d_n[1]
+#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[2] }]; #IO_L8P_T1_AD10P_15    Sch=syzygy_d_p[2]
+#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[2] }]; #IO_L8N_T1_AD10N_15    Sch=syzygy_d_n[2]
+#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[3] }]; #IO_L10P_T1_AD11P_15   Sch=syzygy_d_p[3]
+#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[3] }]; #IO_L10N_T1_AD11N_15   Sch=syzygy_d_n[3]
+#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[4] }]; #IO_L11P_T1_SRCC_15    Sch=syzygy_d_p[4]
+#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[4] }]; #IO_L11N_T1_SRCC_15    Sch=syzygy_d_n[4]
+#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[5] }]; #IO_L12P_T1_MRCC_15    Sch=syzygy_d_p[5]
+#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[5] }]; #IO_L12N_T1_MRCC_15    Sch=syzygy_d_n[5]
+#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[6] }]; #IO_L20P_T3_A20_15     Sch=syzygy_d_p[6]
+#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[6] }]; #IO_L20N_T3_A19_15     Sch=syzygy_d_n[6]
+#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[7] }]; #IO_L21P_T3_DQS_15     Sch=syzygy_d_p[7]
+#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[7] }]; #IO_L21N_T3_DQS_A18_15 Sch=syzygy_d_n[7]
+
+#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }];  #IO_L19P_T3_A22_15       Sch=syzygy_s[16]
+#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }];  #IO_L19N_T3_A21_VREF_15  Sch=syzygy_s[17]
+#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }];  #IO_L22P_T3_A17_15       Sch=syzygy_s[18]
+#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }];  #IO_L22N_T3_A16_15       Sch=syzygy_s[19]
+#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }];  #IO_L23P_T3_FOE_B_15     Sch=syzygy_s[20]
+#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }];  #IO_L23N_T3_FWE_B_15     Sch=syzygy_s[21]
+#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }];  #IO_L24P_T3_RS1_15       Sch=syzygy_s[22]
+#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }];  #IO_L24N_T3_RS0_15       Sch=syzygy_s[23]
+#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }];  #IO_L15P_T2_DQS_15       Sch=syzygy_s[24]
+#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }];  #IO_L15N_T2_DQS_ADV_B_15 Sch=syzygy_s[25]
+#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }];  #IO_L16P_T2_A28_15       Sch=syzygy_s[26]
+#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }];  #IO_L16N_T2_A27_15       Sch=syzygy_s[27]
+
+#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_p }]; #IO_L13P_T2_MRCC_15 Sch=syzygy_p2c_clk_p
+#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_n }]; #IO_L13N_T2_MRCC_15 Sch=syzygy_p2c_clk_n
+#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_c2p_clk_p }]; #IO_L14P_T2_SRCC_15 Sch=syzygy_c2p_clk_p
+#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_c2p_clk_n }]; #IO_L14N_T2_SRCC_15 Sch=syzygy_c2p_clk_n
+
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { syzygy_scl }]; #IO_L18P_T2_A12_D28_14 Sch=syzygy_scl
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { syzygy_sda }]; #IO_L18N_T2_A11_D27_14 Sch=syzygy_sda
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 }             [get_ports { syzygy_det }]; #IO_L19P_T3_A10_D26_14 Sch=syzygy_det
+
+## Encryption Chip
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L18P_T2_35 Sch=crypto_sda
+
+# Platform MCU Firmware Reprogramming
+#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { mcu_rstn }]; #IO_25_14              Sch=mcu_nrst_fpga
+#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { mcu_cs }];   #IO_L22N_T3_A04_D20_14 Sch=mcu_cs
+#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { mcu_mosi }]; #IO_L23P_T3_A03_D19_14 Sch=mcu_mosi
+#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { mcu_miso }]; #IO_L23N_T3_A02_D18_14 Sch=mcu_miso
+#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 }  [get_ports { mcu_sck }];  #IO_L24P_T3_A01_D17_14 Sch=mcu_sck
+
+## Miscellaneous
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[1] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=mcu_rsvd[1]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[2] }]; #IO_L22P_T3_A05_D21_14     Sch=mcu_rsvd[2]
+
+## DDR3
+#set_property -dict { PACKAGE_PIN R6 } [get_ports { ddr3_a[0] }];  #IO_L19P_T3_34      Sch=ddr3_a[0]
+#set_property -dict { PACKAGE_PIN R7 } [get_ports { ddr3_a[1] }];  #IO_L23P_T3_34      Sch=ddr3_a[1]
+#set_property -dict { PACKAGE_PIN P2 } [get_ports { ddr3_a[10] }]; #IO_L15P_T2_DQS_34  Sch=ddr3_a[10]
+#set_property -dict { PACKAGE_PIN P5 } [get_ports { ddr3_a[11] }]; #IO_L13N_T2_MRCC_34 Sch=ddr3_a[11]
+#set_property -dict { PACKAGE_PIN R1 } [get_ports { ddr3_a[12] }]; #IO_L17P_T2_34      Sch=ddr3_a[12]
+#set_property -dict { PACKAGE_PIN U8 } [get_ports { ddr3_a[13] }]; #IO_25_34           Sch=ddr3_a[13]
+#set_property -dict { PACKAGE_PIN N6 } [get_ports { ddr3_a[14] }]; #IO_L18N_T2_34      Sch=ddr3_a[14]
+#set_property -dict { PACKAGE_PIN T6 } [get_ports { ddr3_a[2] }];  #IO_L23N_T3_34      Sch=ddr3_a[2]
+#set_property -dict { PACKAGE_PIN U7 } [get_ports { ddr3_a[3] }];  #IO_L22P_T3_34      Sch=ddr3_a[3]
+#set_property -dict { PACKAGE_PIN T1 } [get_ports { ddr3_a[4] }];  #IO_L17N_T2_34      Sch=ddr3_a[4]
+#set_property -dict { PACKAGE_PIN V7 } [get_ports { ddr3_a[5] }];  #IO_L20P_T3_34      Sch=ddr3_a[5]
+#set_property -dict { PACKAGE_PIN P3 } [get_ports { ddr3_a[6] }];  #IO_L14N_T2_SRCC_34 Sch=ddr3_a[6]
+#set_property -dict { PACKAGE_PIN T8 } [get_ports { ddr3_a[7] }];  #IO_L24N_T3_34      Sch=ddr3_a[7]
+#set_property -dict { PACKAGE_PIN M6 } [get_ports { ddr3_a[8] }];  #IO_L18P_T2_34      Sch=ddr3_a[8]
+#set_property -dict { PACKAGE_PIN R8 } [get_ports { ddr3_a[9] }];  #IO_L24P_T3_34      Sch=ddr3_a[9]
+#set_property -dict { PACKAGE_PIN V6 } [get_ports { ddr3_ba[0] }]; #IO_L20N_T3_34      Sch=ddr3_ba[0]
+#set_property -dict { PACKAGE_PIN R2 } [get_ports { ddr3_ba[1] }]; #IO_L15N_T2_DQS_34  Sch=ddr3_ba[1]
+#set_property -dict { PACKAGE_PIN R5 } [get_ports { ddr3_ba[2] }]; #IO_L19N_T3_VREF_34 Sch=ddr3_ba[2]
+#set_property -dict { PACKAGE_PIN N4 } [get_ports { ddr3_cas }];   #IO_L16N_T2_34      Sch=ddr3_cas
+#set_property -dict { PACKAGE_PIN V9    IOSTANDARD LVDS } [get_ports { ddr3_ck_n }]; #IO_L21N_T3_DQS_34 Sch=ddr3_ck_n
+#set_property -dict { PACKAGE_PIN U9    IOSTANDARD LVDS } [get_ports { ddr3_ck_p }]; #IO_L21P_T3_DQS_34 Sch=ddr3_ck_p
+#set_property -dict { PACKAGE_PIN N5 } [get_ports { ddr3_cke[0] }]; #IO_L13P_T2_MRCC_34 Sch=ddr3_cke[0]
+#set_property -dict { PACKAGE_PIN R3 } [get_ports { ddr3_d[0] }];   #IO_L11P_T1_SRCC_34 Sch=ddr3_d[0]
+#set_property -dict { PACKAGE_PIN V1 } [get_ports { ddr3_d[1] }];   #IO_L7N_T1_34       Sch=ddr3_d[1]
+#set_property -dict { PACKAGE_PIN M2 } [get_ports { ddr3_d[10] }];  #IO_L4N_T0_34       Sch=ddr3_d[10]
+#set_property -dict { PACKAGE_PIN L4 } [get_ports { ddr3_d[11] }];  #IO_L5N_T0_34       Sch=ddr3_d[11]
+#set_property -dict { PACKAGE_PIN L6 } [get_ports { ddr3_d[12] }];  #IO_L6P_T0_34       Sch=ddr3_d[12]
+#set_property -dict { PACKAGE_PIN K3 } [get_ports { ddr3_d[13] }];  #IO_L2P_T0_34       Sch=ddr3_d[13]
+#set_property -dict { PACKAGE_PIN M1 } [get_ports { ddr3_d[14] }];  #IO_L1N_T0_34       Sch=ddr3_d[14]
+#set_property -dict { PACKAGE_PIN K5 } [get_ports { ddr3_d[15] }];  #IO_L5P_T0_34       Sch=ddr3_d[15]
+#set_property -dict { PACKAGE_PIN T3 } [get_ports { ddr3_d[2] }];   #IO_L11N_T1_SRCC_34 Sch=ddr3_d[2]
+#set_property -dict { PACKAGE_PIN U4 } [get_ports { ddr3_d[3] }];   #IO_L8P_T1_34       Sch=ddr3_d[3]
+#set_property -dict { PACKAGE_PIN U3 } [get_ports { ddr3_d[4] }];   #IO_L8N_T1_34       Sch=ddr3_d[4]
+#set_property -dict { PACKAGE_PIN V5 } [get_ports { ddr3_d[5] }];   #IO_L10P_T1_34      Sch=ddr3_d[5]
+#set_property -dict { PACKAGE_PIN T5 } [get_ports { ddr3_d[6] }];   #IO_L12P_T1_MRCC_34 Sch=ddr3_d[6]
+#set_property -dict { PACKAGE_PIN V4 } [get_ports { ddr3_d[7] }];   #IO_L10N_T1_34      Sch=ddr3_d[7]
+#set_property -dict { PACKAGE_PIN M3 } [get_ports { ddr3_d[8] }];   #IO_L4P_T0_34       Sch=ddr3_d[8]
+#set_property -dict { PACKAGE_PIN L3 } [get_ports { ddr3_d[9] }];   #IO_L2N_T0_34       Sch=ddr3_d[9]
+#set_property -dict { PACKAGE_PIN U1 } [get_ports { ddr3_dm[0] }];  #IO_L7P_T1_34       Sch=ddr3_dm[0]
+#set_property -dict { PACKAGE_PIN L1 } [get_ports { ddr3_dm[1] }];  #IO_L1P_T0_34       Sch=ddr3_dm[1]
+#set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVDS } [get_ports { ddr3_dqs_n[0] }]; #IO_L9N_T1_DQS_34 Sch=ddr3_dqs_n[0]
+#set_property -dict { PACKAGE_PIN U2    IOSTANDARD LVDS } [get_ports { ddr3_dqs_p[0] }]; #IO_L9P_T1_DQS_34 Sch=ddr3_dqs_p[0]
+#set_property -dict { PACKAGE_PIN N1    IOSTANDARD LVDS } [get_ports { ddr3_dqs_n[1] }]; #IO_L3N_T0_DQS_34 Sch=ddr3_dqs_n[1]
+#set_property -dict { PACKAGE_PIN N2    IOSTANDARD LVDS } [get_ports { ddr3_dqs_p[1] }]; #IO_L3P_T0_DQS_34 Sch=ddr3_dqs_p[1]
+#set_property -dict { PACKAGE_PIN P4 } [get_ports { ddr3_odt }];   #IO_L14P_T2_SRCC_34 Sch=ddr3_odt
+#set_property -dict { PACKAGE_PIN M4 } [get_ports { ddr3_ras }];   #IO_L16P_T2_34      Sch=ddr3_ras
+#set_property -dict { PACKAGE_PIN K6 } [get_ports { ddr3_reset }]; #IO_0_34            Sch=ddr3_reset
+#set_property -dict { PACKAGE_PIN U6 } [get_ports { ddr3_we }];    #IO_L22N_T3_34      Sch=ddr3_we
+
+## Bitstream Settings
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
\ No newline at end of file
diff --git a/Bibliotheken/digilent-xdc-master/Zedboard-Master.xdc b/Bibliotheken/digilent-xdc-master/Zedboard-Master.xdc
new file mode 100644
index 0000000..806c74c
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Zedboard-Master.xdc
@@ -0,0 +1,375 @@
+# ----------------------------------------------------------------------------
+#     _____
+#    /     \
+#   /____   \____
+#  / \===\   \==/
+# /___\===\___\/  AVNET Design Resource Center
+#      \======/         www.em.avnet.com/drc
+#       \====/    
+# ----------------------------------------------------------------------------
+# 
+#  Created With Avnet UCF Generator V0.4.0 
+#     Date: Saturday, June 30, 2012 
+#     Time: 12:18:55 AM 
+# 
+#  This design is the property of Avnet.  Publication of this
+#  design is not authorized without written consent from Avnet.
+#  
+#  Please direct any questions to:
+#     ZedBoard.org Community Forums
+#     http://www.zedboard.org
+# 
+#  Disclaimer:
+#     Avnet, Inc. makes no warranty for the use of this code or design.
+#     This code is provided  "As Is". Avnet, Inc assumes no responsibility for
+#     any errors, which may appear in this code, nor does it make a commitment
+#     to update the information contained herein. Avnet, Inc specifically
+#     disclaims any implied warranties of fitness for a particular purpose.
+#                      Copyright(c) 2012 Avnet, Inc.
+#                              All rights reserved.
+# 
+# ----------------------------------------------------------------------------
+# 
+#  Notes:
+# 
+#  10 August 2012
+#     IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V, 
+#     2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.  
+#     By default, Vadj is expected to be set to 1.8V but if a different 
+#     voltage is used for a particular design, then the corresponding IO 
+#     standard within this UCF should also be updated to reflect the actual 
+#     Vadj jumper selection.
+# 
+#  09 September 2012
+#     Net names are not allowed to contain hyphen characters '-' since this
+#     is not a legal VHDL87 or Verilog character within an identifier.  
+#     HDL net names are adjusted to contain no hyphen characters '-' but 
+#     rather use underscore '_' characters.  Comment net name with the hyphen 
+#     characters will remain in place since these are intended to match the 
+#     schematic net names in order to better enable schematic search.
+#
+#  17 April 2014
+#     Pin constraint for toggle switch SW7 was corrected to M15 location.
+#
+#  16 April 2015
+#     Corrected the way that entire banks are assigned to a particular IO
+#     standard so that it works with more recent versions of Vivado Design
+#     Suite and moved the IO standard constraints to the end of the file 
+#     along with some better organization and notes like we do with our SOMs.
+#
+#   6 June 2016
+#     Corrected error in signal name for package pin N19 (FMC Expansion Connector)
+#	
+#
+# ----------------------------------------------------------------------------
+
+# ----------------------------------------------------------------------------
+# Audio Codec - Bank 13
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}];  # "AC-ADR0"
+#set_property PACKAGE_PIN Y5  [get_ports {AC_ADR1}];  # "AC-ADR1"
+#set_property PACKAGE_PIN Y8  [get_ports {SDATA_O}];  # "AC-GPIO0"
+#set_property PACKAGE_PIN AA7 [get_ports {SDATA_I}];  # "AC-GPIO1"
+#set_property PACKAGE_PIN AA6 [get_ports {BCLK_O}];  # "AC-GPIO2"
+#set_property PACKAGE_PIN Y6  [get_ports {LRCLK_O}];  # "AC-GPIO3"
+#set_property PACKAGE_PIN AB2 [get_ports {MCLK_O}];  # "AC-MCLK"
+#set_property PACKAGE_PIN AB4 [get_ports {iic_rtl_scl_io}];  # "AC-SCK"
+#set_property PACKAGE_PIN AB5 [get_ports {iic_rtl_sda_io}];  # "AC-SDA"
+
+# ----------------------------------------------------------------------------
+# Clock Source - Bank 13
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN Y9 [get_ports {GCLK}];  # "GCLK"
+
+# ----------------------------------------------------------------------------
+# JA Pmod - Bank 13 
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN Y11  [get_ports {JA1}];  # "JA1"
+#set_property PACKAGE_PIN AA8  [get_ports {JA10}];  # "JA10"
+#set_property PACKAGE_PIN AA11 [get_ports {JA2}];  # "JA2"
+#set_property PACKAGE_PIN Y10  [get_ports {JA3}];  # "JA3"
+#set_property PACKAGE_PIN AA9  [get_ports {JA4}];  # "JA4"
+#set_property PACKAGE_PIN AB11 [get_ports {JA7}];  # "JA7"
+#set_property PACKAGE_PIN AB10 [get_ports {JA8}];  # "JA8"
+#set_property PACKAGE_PIN AB9  [get_ports {JA9}];  # "JA9"
+
+
+# ----------------------------------------------------------------------------
+# JB Pmod - Bank 13
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN W12 [get_ports {JB1}];  # "JB1"
+#set_property PACKAGE_PIN W11 [get_ports {JB2}];  # "JB2"
+#set_property PACKAGE_PIN V10 [get_ports {JB3}];  # "JB3"
+#set_property PACKAGE_PIN W8 [get_ports {JB4}];  # "JB4"
+#set_property PACKAGE_PIN V12 [get_ports {JB7}];  # "JB7"
+#set_property PACKAGE_PIN W10 [get_ports {JB8}];  # "JB8"
+#set_property PACKAGE_PIN V9 [get_ports {JB9}];  # "JB9"
+#set_property PACKAGE_PIN V8 [get_ports {JB10}];  # "JB10"
+
+# ----------------------------------------------------------------------------
+# JC Pmod - Bank 13
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN AB6 [get_ports {JC1_N}];  # "JC1_N"
+#set_property PACKAGE_PIN AB7 [get_ports {JC1_P}];  # "JC1_P"
+#set_property PACKAGE_PIN AA4 [get_ports {JC2_N}];  # "JC2_N"
+#set_property PACKAGE_PIN Y4  [get_ports {JC2_P}];  # "JC2_P"
+#set_property PACKAGE_PIN T6  [get_ports {JC3_N}];  # "JC3_N"
+#set_property PACKAGE_PIN R6  [get_ports {JC3_P}];  # "JC3_P"
+#set_property PACKAGE_PIN U4  [get_ports {JC4_N}];  # "JC4_N"
+#set_property PACKAGE_PIN T4  [get_ports {JC4_P}];  # "JC4_P"
+
+# ----------------------------------------------------------------------------
+# JD Pmod - Bank 13
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN W7 [get_ports {JD1_N}];  # "JD1_N"
+#set_property PACKAGE_PIN V7 [get_ports {JD1_P}];  # "JD1_P"
+#set_property PACKAGE_PIN V4 [get_ports {JD2_N}];  # "JD2_N"
+#set_property PACKAGE_PIN V5 [get_ports {JD2_P}];  # "JD2_P"
+#set_property PACKAGE_PIN W5 [get_ports {JD3_N}];  # "JD3_N"
+#set_property PACKAGE_PIN W6 [get_ports {JD3_P}];  # "JD3_P"
+#set_property PACKAGE_PIN U5 [get_ports {JD4_N}];  # "JD4_N"
+#set_property PACKAGE_PIN U6 [get_ports {JD4_P}];  # "JD4_P"
+
+# ----------------------------------------------------------------------------
+# OLED Display - Bank 13
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN U10  [get_ports {OLED_DC}];  # "OLED-DC"
+#set_property PACKAGE_PIN U9   [get_ports {OLED_RES}];  # "OLED-RES"
+#set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}];  # "OLED-SCLK"
+#set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}];  # "OLED-SDIN"
+#set_property PACKAGE_PIN U11  [get_ports {OLED_VBAT}];  # "OLED-VBAT"
+#set_property PACKAGE_PIN U12  [get_ports {OLED_VDD}];  # "OLED-VDD"
+
+# ----------------------------------------------------------------------------
+# HDMI Output - Bank 33
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN W18  [get_ports {HD_CLK}];  # "HD-CLK"
+#set_property PACKAGE_PIN Y13  [get_ports {HD_D0}];  # "HD-D0"
+#set_property PACKAGE_PIN AA13 [get_ports {HD_D1}];  # "HD-D1"
+#set_property PACKAGE_PIN W13  [get_ports {HD_D10}];  # "HD-D10"
+#set_property PACKAGE_PIN W15  [get_ports {HD_D11}];  # "HD-D11"
+#set_property PACKAGE_PIN V15  [get_ports {HD_D12}];  # "HD-D12"
+#set_property PACKAGE_PIN U17  [get_ports {HD_D13}];  # "HD-D13"
+#set_property PACKAGE_PIN V14  [get_ports {HD_D14}];  # "HD-D14"
+#set_property PACKAGE_PIN V13  [get_ports {HS_D15}];  # "HD-D15"
+#set_property PACKAGE_PIN AA14 [get_ports {HD_D2}];  # "HD-D2"
+#set_property PACKAGE_PIN Y14  [get_ports {HD_D3}];  # "HD-D3"
+#set_property PACKAGE_PIN AB15 [get_ports {HD_D4}];  # "HD-D4"
+#set_property PACKAGE_PIN AB16 [get_ports {HD_D5}];  # "HD-D5"
+#set_property PACKAGE_PIN AA16 [get_ports {HD_D6}];  # "HD-D6"
+#set_property PACKAGE_PIN AB17 [get_ports {HD_D7}];  # "HD-D7"
+#set_property PACKAGE_PIN AA17 [get_ports {HD_D8}];  # "HD-D8"
+#set_property PACKAGE_PIN Y15  [get_ports {HD_D9}];  # "HD-D9"
+#set_property PACKAGE_PIN U16  [get_ports {HD_DE}];  # "HD-DE"
+#set_property PACKAGE_PIN V17  [get_ports {HD_HSYNC}];  # "HD-HSYNC"
+#set_property PACKAGE_PIN W16  [get_ports {HD_INT}];  # "HD-INT"
+#set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}];  # "HD-SCL"
+#set_property PACKAGE_PIN Y16  [get_ports {HD_SDA}];  # "HD-SDA"
+#set_property PACKAGE_PIN U15  [get_ports {HD_SPDIF}];  # "HD-SPDIF"
+#set_property PACKAGE_PIN Y18  [get_ports {HD_SPDIFO}];  # "HD-SPDIFO"
+#set_property PACKAGE_PIN W17  [get_ports {HD_VSYNC}];  # "HD-VSYNC"
+
+# ----------------------------------------------------------------------------
+# User LEDs - Bank 33
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN T22 [get_ports {LD0}];  # "LD0"
+#set_property PACKAGE_PIN T21 [get_ports {LD1}];  # "LD1"
+#set_property PACKAGE_PIN U22 [get_ports {LD2}];  # "LD2"
+#set_property PACKAGE_PIN U21 [get_ports {LD3}];  # "LD3"
+#set_property PACKAGE_PIN V22 [get_ports {LD4}];  # "LD4"
+#set_property PACKAGE_PIN W22 [get_ports {LD5}];  # "LD5"
+#set_property PACKAGE_PIN U19 [get_ports {LD6}];  # "LD6"
+#set_property PACKAGE_PIN U14 [get_ports {LD7}];  # "LD7"
+
+# ----------------------------------------------------------------------------
+# VGA Output - Bank 33
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN Y21  [get_ports {VGA_B1}];  # "VGA-B1"
+#set_property PACKAGE_PIN Y20  [get_ports {VGA_B2}];  # "VGA-B2"
+#set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}];  # "VGA-B3"
+#set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}];  # "VGA-B4"
+#set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}];  # "VGA-G1"
+#set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}];  # "VGA-G2"
+#set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}];  # "VGA-G3"
+#set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}];  # "VGA-G4"
+#set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}];  # "VGA-HS"
+#set_property PACKAGE_PIN V20  [get_ports {VGA_R1}];  # "VGA-R1"
+#set_property PACKAGE_PIN U20  [get_ports {VGA_R2}];  # "VGA-R2"
+#set_property PACKAGE_PIN V19  [get_ports {VGA_R3}];  # "VGA-R3"
+#set_property PACKAGE_PIN V18  [get_ports {VGA_R4}];  # "VGA-R4"
+#set_property PACKAGE_PIN Y19  [get_ports {VGA_VS}];  # "VGA-VS"
+
+# ----------------------------------------------------------------------------
+# User Push Buttons - Bank 34
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN P16 [get_ports {BTNC}];  # "BTNC"
+#set_property PACKAGE_PIN R16 [get_ports {BTND}];  # "BTND"
+#set_property PACKAGE_PIN N15 [get_ports {BTNL}];  # "BTNL"
+#set_property PACKAGE_PIN R18 [get_ports {BTNR}];  # "BTNR"
+#set_property PACKAGE_PIN T18 [get_ports {BTNU}];  # "BTNU"
+
+# ----------------------------------------------------------------------------
+# USB OTG Reset - Bank 34
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}];  # "OTG-VBUSOC"
+
+# ----------------------------------------------------------------------------
+# XADC GIO - Bank 34
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}];  # "XADC-GIO0"
+#set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}];  # "XADC-GIO1"
+#set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}];  # "XADC-GIO2"
+#set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}];  # "XADC-GIO3"
+
+# ----------------------------------------------------------------------------
+# Miscellaneous - Bank 34
+# ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN K16 [get_ports {PUDC_B}];  # "PUDC_B"
+
+## ----------------------------------------------------------------------------
+## USB OTG Reset - Bank 35
+## ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}];  # "OTG-RESETN"
+
+## ----------------------------------------------------------------------------
+## User DIP Switches - Bank 35
+## ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN F22 [get_ports {SW0}];  # "SW0"
+#set_property PACKAGE_PIN G22 [get_ports {SW1}];  # "SW1"
+#set_property PACKAGE_PIN H22 [get_ports {SW2}];  # "SW2"
+#set_property PACKAGE_PIN F21 [get_ports {SW3}];  # "SW3"
+#set_property PACKAGE_PIN H19 [get_ports {SW4}];  # "SW4"
+#set_property PACKAGE_PIN H18 [get_ports {SW5}];  # "SW5"
+#set_property PACKAGE_PIN H17 [get_ports {SW6}];  # "SW6"
+#set_property PACKAGE_PIN M15 [get_ports {SW7}];  # "SW7"
+
+## ----------------------------------------------------------------------------
+## XADC AD Channels - Bank 35
+## ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN E16 [get_ports {AD0N_R}];  # "XADC-AD0N-R"
+#set_property PACKAGE_PIN F16 [get_ports {AD0P_R}];  # "XADC-AD0P-R"
+#set_property PACKAGE_PIN D17 [get_ports {AD8N_N}];  # "XADC-AD8N-R"
+#set_property PACKAGE_PIN D16 [get_ports {AD8P_R}];  # "XADC-AD8P-R"
+
+## ----------------------------------------------------------------------------
+## FMC Expansion Connector - Bank 13
+## ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}];  # "FMC-SCL"
+#set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}];  # "FMC-SDA"
+
+## ----------------------------------------------------------------------------
+## FMC Expansion Connector - Bank 33
+## ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}];  # "FMC-PRSNT"
+
+## ----------------------------------------------------------------------------
+## FMC Expansion Connector - Bank 34
+## ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}];  # "FMC-CLK0_N"
+#set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}];  # "FMC-CLK0_P"
+#set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}];  # "FMC-LA00_CC_N"
+#set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}];  # "FMC-LA00_CC_P"
+#set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}];  # "FMC-LA01_CC_N"
+#set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}];  # "FMC-LA01_CC_P" - corrected 6/6/16 GE
+#set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}];  # "FMC-LA02_N"
+#set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}];  # "FMC-LA02_P"
+#set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}];  # "FMC-LA03_N"
+#set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}];  # "FMC-LA03_P"
+#set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}];  # "FMC-LA04_N"
+#set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}];  # "FMC-LA04_P"
+#set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}];  # "FMC-LA05_N"
+#set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}];  # "FMC-LA05_P"
+#set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}];  # "FMC-LA06_N"
+#set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}];  # "FMC-LA06_P"
+#set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}];  # "FMC-LA07_N"
+#set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}];  # "FMC-LA07_P"
+#set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}];  # "FMC-LA08_N"
+#set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}];  # "FMC-LA08_P"
+#set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}];  # "FMC-LA09_N"
+#set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}];  # "FMC-LA09_P"
+#set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}];  # "FMC-LA10_N"
+#set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}];  # "FMC-LA10_P"
+#set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}];  # "FMC-LA11_N"
+#set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}];  # "FMC-LA11_P"
+#set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}];  # "FMC-LA12_N"
+#set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}];  # "FMC-LA12_P"
+#set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}];  # "FMC-LA13_N"
+#set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}];  # "FMC-LA13_P"
+#set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}];  # "FMC-LA14_N"
+#set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}];  # "FMC-LA14_P"
+#set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}];  # "FMC-LA15_N"
+#set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}];  # "FMC-LA15_P"
+#set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}];  # "FMC-LA16_N"
+#set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}];  # "FMC-LA16_P"
+
+## ----------------------------------------------------------------------------
+## FMC Expansion Connector - Bank 35
+## ---------------------------------------------------------------------------- 
+#set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}];  # "FMC-CLK1_N"
+#set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}];  # "FMC-CLK1_P"
+#set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}];  # "FMC-LA17_CC_N"
+#set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}];  # "FMC-LA17_CC_P"
+#set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}];  # "FMC-LA18_CC_N"
+#set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}];  # "FMC-LA18_CC_P"
+#set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}];  # "FMC-LA19_N"
+#set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}];  # "FMC-LA19_P"
+#set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}];  # "FMC-LA20_N"
+#set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}];  # "FMC-LA20_P"
+#set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}];  # "FMC-LA21_N"
+#set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}];  # "FMC-LA21_P"
+#set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}];  # "FMC-LA22_N"
+#set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}];  # "FMC-LA22_P"
+#set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}];  # "FMC-LA23_N"
+#set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}];  # "FMC-LA23_P"
+#set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}];  # "FMC-LA24_N"
+#set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}];  # "FMC-LA24_P"
+#set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}];  # "FMC-LA25_N"
+#set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}];  # "FMC-LA25_P"
+#set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}];  # "FMC-LA26_N"
+#set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}];  # "FMC-LA26_P"
+#set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}];  # "FMC-LA27_N"
+#set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}];  # "FMC-LA27_P"
+#set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}];  # "FMC-LA28_N"
+#set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}];  # "FMC-LA28_P"
+#set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}];  # "FMC-LA29_N"
+#set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}];  # "FMC-LA29_P"
+#set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}];  # "FMC-LA30_N"
+#set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}];  # "FMC-LA30_P"
+#set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}];  # "FMC-LA31_N"
+#set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}];  # "FMC-LA31_P"
+#set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}];  # "FMC-LA32_N"
+#set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}];  # "FMC-LA32_P"
+#set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}];  # "FMC-LA33_N"
+#set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}];  # "FMC-LA33_P"
+
+
+# ----------------------------------------------------------------------------
+# IOSTANDARD Constraints
+#
+# Note that these IOSTANDARD constraints are applied to all IOs currently
+# assigned within an I/O bank.  If these IOSTANDARD constraints are 
+# evaluated prior to other PACKAGE_PIN constraints being applied, then 
+# the IOSTANDARD specified will likely not be applied properly to those 
+# pins.  Therefore, bank wide IOSTANDARD constraints should be placed 
+# within the XDC file in a location that is evaluated AFTER all 
+# PACKAGE_PIN constraints within the target bank have been evaluated.
+#
+# Un-comment one or more of the following IOSTANDARD constraints according to
+# the bank pin assignments that are required within a design.
+# ---------------------------------------------------------------------------- 
+
+# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. 
+set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
+
+# Set the bank voltage for IO Bank 34 to 1.8V by default.
+# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
+# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
+set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
+
+# Set the bank voltage for IO Bank 35 to 1.8V by default.
+# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
+# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
+set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
+
+# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. 
+set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
diff --git a/Bibliotheken/digilent-xdc-master/Zybo-Master.xdc b/Bibliotheken/digilent-xdc-master/Zybo-Master.xdc
new file mode 100644
index 0000000..3c77c23
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Zybo-Master.xdc
@@ -0,0 +1,146 @@
+## This file is a general .xdc for the ZYBO Rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used signals according to the project
+
+
+##Clock signal
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
+
+
+##Switches
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }];  #IO_L24P_T3_34 Sch=SW1
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3
+
+
+##Buttons
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3
+
+
+##LEDs
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
+
+
+##I2S Audio Codec
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC
+
+
+##Audio Codec/external EEPROM IIC bus
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA
+
+
+##Additional Ethernet signals
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B
+
+
+##HDMI Signals
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P
+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA
+
+
+##Pmod Header JA (XADC)
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
+
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N
+
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N
+
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N
+
+
+##Pmod Header JE
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10
+
+
+##USB-OTG overcurrent detect pin
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC
+
+
+##VGA Connector
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS
diff --git a/Bibliotheken/digilent-xdc-master/Zybo-Z7-Master.xdc b/Bibliotheken/digilent-xdc-master/Zybo-Z7-Master.xdc
new file mode 100644
index 0000000..9e6546e
--- /dev/null
+++ b/Bibliotheken/digilent-xdc-master/Zybo-Z7-Master.xdc
@@ -0,0 +1,198 @@
+## This file is a general .xdc for the Zybo Z7 Rev. B
+## It is compatible with the Zybo Z7-20 and Zybo Z7-10
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+##Clock signal
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
+
+
+##Switches
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
+
+
+##Buttons
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
+
+
+##LEDs
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
+
+
+##RGB LED 5 (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y11   IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
+#set_property -dict { PACKAGE_PIN T5    IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
+#set_property -dict { PACKAGE_PIN Y12   IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
+
+##RGB LED 6
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
+
+
+##Audio Codec
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
+ 
+ 
+##Additional Ethernet signals
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33  PULLUP true    } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
+
+
+##USB-OTG over-current detect pin
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
+
+
+##Fan (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS33  PULLUP true    } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
+
+
+##HDMI RX
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
+
+##HDMI RX CEC (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
+
+
+##HDMI TX
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
+
+##HDMI TX CEC 
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
+ 
+
+##Pmod Header JA (XADC)
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p		   
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P             
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P            
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P             
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N        
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N             
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N            
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N             
+ 
+
+##Pmod Header JB (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33     } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]		 
+#set_property -dict { PACKAGE_PIN W8    IOSTANDARD LVCMOS33     } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]         
+#set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33     } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]        
+#set_property -dict { PACKAGE_PIN V7    IOSTANDARD LVCMOS33     } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]        
+#set_property -dict { PACKAGE_PIN Y7    IOSTANDARD LVCMOS33     } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]        
+#set_property -dict { PACKAGE_PIN Y6    IOSTANDARD LVCMOS33     } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]        
+#set_property -dict { PACKAGE_PIN V6    IOSTANDARD LVCMOS33     } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]             
+#set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33     } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]             
+                                                                                                                                 
+                                                                                                                                 
+##Pmod Header JC                                                                                                                  
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33     } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]   			 
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33     } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]		     
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33     } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]              
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33     } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]              
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33     } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]              
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33     } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]              
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33     } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]              
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33     } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]              
+                                                                                                                                 
+                                                                                                                                 
+##Pmod Header JD                                                                                                                  
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33     } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]                  
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33     } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]				 
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33     } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]                  
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33     } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]             
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33     } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]            
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33     } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]            
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33     } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]             
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33     } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]             
+                                                                                                                                 
+                                                                                                                                 
+##Pmod Header JE                                                                                                                  
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]						 
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]                     
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]                          
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]                     
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]                  
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]                  
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]                     
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]                    
+
+
+##Pcam MIPI CSI-2 Connector
+## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
+#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
+#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 	PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
+ 
+ 
+##Unloaded Crypto Chip SWI (for future use)
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
+ 
+ 
+##Unconnected Pins (Zybo Z7-20 only)
+#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
+#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
+#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
+#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
+#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
+#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
+#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
+#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
+#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
+#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
+#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
+#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
+
+
diff --git a/Bibliotheken/vivado-boards-master.zip b/Bibliotheken/vivado-boards-master.zip
new file mode 100644
index 0000000..6f2939d
Binary files /dev/null and b/Bibliotheken/vivado-boards-master.zip differ
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/License.txt b/Bibliotheken/vivado-boards-master/vivado-boards-master/License.txt
new file mode 100644
index 0000000..b76cf0c
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/License.txt
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/README.md b/Bibliotheken/vivado-boards-master/vivado-boards-master/README.md
new file mode 100644
index 0000000..ac00883
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/README.md
@@ -0,0 +1,13 @@
+# Vivado Board Files for Digilent FPGA Boards
+
+This repository contains the files used by Vivado IP Integrator to support Digilent system boards. They include board interfaces, preset configurations for the IP that can connect to those interfaces, and the constraints required to connect the pins of those interfaces to physical FPGA pins. Memory Interface Generator (MIG) project files are also included for non-Zynq boards which can be used to configure the Xilinx MIG IP for use with Microblaze systems.
+
+The `old` folder is for use with Vivado versions 2014.4 and below. The `new` folder covers Vivado 2015.x and above.
+
+Installation instructions for the `new` files can be found in [Section 3](https://reference.digilentinc.com/vivado/installing-vivado/start#installing_digilent_board_files) of the *Installing Vivado, Xilinx SDK, and Digilent Board Files* guide on the Digilent Wiki.
+
+Installation instructions for the `old` files can be found in the [Installing Vivado Board Files for Digilent Boards (Legacy)](https://reference.digilentinc.com/vivado:boardfiles) guide on the Digilent Wiki.
+
+## Notes
+
+* Boards with ChipKit/Arduino headers have the pin locations of CK_IO10 and CK_SS swapped in order to support connection to the [Multi-Touch Display Shield](https://reference.digilentinc.com/reference/add-ons/mtdshield/start). This is not an ideal solution, and may be revised in future. See [Issue 5](https://github.com/Digilent/vivado-boards/issues/5) for more information.
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/board.xml
new file mode 100644
index 0000000..50f4535
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/board.xml
@@ -0,0 +1,1247 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-100" display_name="Arty A7-100" url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">E.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Arty A7-100</description>
+<components>
+  <component name="part0" display_name="Arty A7-100" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+		<description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+        <description>4-position user DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+	  <description>Secondary interface to communicate with ethernet phy. </description>
+        <port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">
+        <description>Primary interface to communicate with ethernet phy in MII mode. </description>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_txd_1"/> 
+              <pin_map port_index="2" component_pin="eth_txd_2"/> 
+              <pin_map port_index="3" component_pin="eth_txd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rxd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rxd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rxd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_dv"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS" physical_port="eth_crs" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_crs"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="COL" physical_port="eth_col" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_col"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rstn"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">
+        <description>I2C Pullups to enable shield I2C</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_pullup_0"/> 
+              <pin_map port_index="1" component_pin="i2c_pullup_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+        <description>4 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<parameters>
+            <parameter name="rst_polarity" value="0"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">
+        <description>4 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="clk" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>256 MB DDR3L memory SODIMM </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	 <component_modes>
+        <component_mode name="mii" display_name="MII mode">
+		  <interfaces>
+            <interface name="eth_mii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1" optional="true"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">
+  <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+  	<description>Push buttons 3 to 0</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+  <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+  	<description>CPU Reset Push Button, active low</description>
+  </component>
+  <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB leds 12 to 0 (3 per LED)</description>
+  </component>
+  <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 0 through 19</description>
+  </component>
+  <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 26 through 41</description>
+  </component>
+  <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+  	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+    <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+    <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>
+	<connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+  <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">
+    <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+    <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">
+    <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>
+  </connection>
+  <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+    <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml
new file mode 100644
index 0000000..dc32e54
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1L">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
+  <pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
+  <pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
+  <pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
+  <pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
+  <pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
+  <pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
+  <pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
+  <pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
+  <pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
+  <pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="96" name ="JA1" iostandard="LVCMOS33"   loc="G13"/>
+  <pin index="97" name ="JA2" iostandard="LVCMOS33"   loc="B11"/>
+  <pin index="98" name ="JA3" iostandard="LVCMOS33"   loc="A11"/>
+  <pin index="99" name ="JA4" iostandard="LVCMOS33"   loc="D12"/>
+  <pin index="100" name ="JA7" iostandard="LVCMOS33"  loc="D13"/>
+  <pin index="101" name ="JA8" iostandard="LVCMOS33"  loc="B18"/>
+  <pin index="102" name ="JA9" iostandard="LVCMOS33"  loc="A18"/>
+  <pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="104" name ="JB1" iostandard="LVCMOS33"  loc="E15"/>
+  <pin index="105" name ="JB2" iostandard="LVCMOS33"  loc="E16"/>
+  <pin index="106" name ="JB3" iostandard="LVCMOS33"  loc="D15"/>
+  <pin index="107" name ="JB4" iostandard="LVCMOS33"  loc="C15"/>
+  <pin index="108" name ="JB7" iostandard="LVCMOS33"  loc="J17"/>
+  <pin index="109" name ="JB8" iostandard="LVCMOS33"  loc="J18"/>
+  <pin index="110" name ="JB9" iostandard="LVCMOS33"  loc="K15"/>
+  <pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="112" name ="JC1"  iostandard="LVCMOS33" loc="U12"/>
+  <pin index="113" name ="JC2" iostandard="LVCMOS33"  loc="V12"/>
+  <pin index="114" name ="JC3" iostandard="LVCMOS33"  loc="V10"/>
+  <pin index="115" name ="JC4" iostandard="LVCMOS33"  loc="V11"/>
+  <pin index="116" name ="JC7" iostandard="LVCMOS33"  loc="U14"/>
+  <pin index="117" name ="JC8" iostandard="LVCMOS33"  loc="V14"/>
+  <pin index="118" name ="JC9" iostandard="LVCMOS33"  loc="T13"/>
+  <pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="120" name ="JD1" iostandard="LVCMOS33"  loc="D4"/>
+  <pin index="121" name ="JD2" iostandard="LVCMOS33"  loc="D3"/>
+  <pin index="122" name ="JD3" iostandard="LVCMOS33"  loc="F4"/>
+  <pin index="123" name ="JD4" iostandard="LVCMOS33"  loc="F3"/>
+  <pin index="124" name ="JD7" iostandard="LVCMOS33"  loc="E2"/>
+  <pin index="125" name ="JD8" iostandard="LVCMOS33"  loc="D2"/>
+  <pin index="126" name ="JD9" iostandard="LVCMOS33"  loc="H2"/>
+  <pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/preset.xml
new file mode 100644
index 0000000..ec20fb4
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/preset.xml
@@ -0,0 +1,418 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_12bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="mii_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.PHY_TYPE" value="MII"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.Physical_Interface" value="MII"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="shield_dp0_dp19_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="uart_preset">
+   <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/board.xml
new file mode 100644
index 0000000..1bffd15
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/board.xml
@@ -0,0 +1,1247 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-100" display_name="Arty A7-100" url="https://digilent.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">E.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Arty A7-100</description>
+<components>
+  <component name="part0" display_name="Arty A7-100" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/arty-a7/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+		<description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+        <description>4-position user DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+	  <description>Secondary interface to communicate with ethernet phy. </description>
+        <port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">
+        <description>Primary interface to communicate with ethernet phy in MII mode. </description>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_txd_1"/> 
+              <pin_map port_index="2" component_pin="eth_txd_2"/> 
+              <pin_map port_index="3" component_pin="eth_txd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rxd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rxd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rxd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_dv"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS" physical_port="eth_crs" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_crs"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="COL" physical_port="eth_col" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_col"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rstn"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">
+        <description>I2C Pullups to enable shield I2C</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_pullup_0"/> 
+              <pin_map port_index="1" component_pin="i2c_pullup_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+        <description>4 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<parameters>
+            <parameter name="rst_polarity" value="0"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">
+        <description>4 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>256 MB DDR3L memory SODIMM </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	 <component_modes>
+        <component_mode name="mii" display_name="MII mode">
+		  <interfaces>
+            <interface name="eth_mii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1" optional="true"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">
+  <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+  	<description>Push buttons 3 to 0</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+  <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+  	<description>CPU Reset Push Button, active low</description>
+  </component>
+  <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB leds 12 to 0 (3 per LED)</description>
+  </component>
+  <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 0 through 19</description>
+  </component>
+  <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 26 through 41</description>
+  </component>
+  <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+  	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+    <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+    <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>
+	<connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+  <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">
+    <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+    <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">
+    <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>
+  </connection>
+  <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+    <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/part0_pins.xml
new file mode 100644
index 0000000..dc32e54
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/part0_pins.xml
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1L">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
+  <pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
+  <pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
+  <pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
+  <pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
+  <pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
+  <pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
+  <pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
+  <pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
+  <pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
+  <pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="96" name ="JA1" iostandard="LVCMOS33"   loc="G13"/>
+  <pin index="97" name ="JA2" iostandard="LVCMOS33"   loc="B11"/>
+  <pin index="98" name ="JA3" iostandard="LVCMOS33"   loc="A11"/>
+  <pin index="99" name ="JA4" iostandard="LVCMOS33"   loc="D12"/>
+  <pin index="100" name ="JA7" iostandard="LVCMOS33"  loc="D13"/>
+  <pin index="101" name ="JA8" iostandard="LVCMOS33"  loc="B18"/>
+  <pin index="102" name ="JA9" iostandard="LVCMOS33"  loc="A18"/>
+  <pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="104" name ="JB1" iostandard="LVCMOS33"  loc="E15"/>
+  <pin index="105" name ="JB2" iostandard="LVCMOS33"  loc="E16"/>
+  <pin index="106" name ="JB3" iostandard="LVCMOS33"  loc="D15"/>
+  <pin index="107" name ="JB4" iostandard="LVCMOS33"  loc="C15"/>
+  <pin index="108" name ="JB7" iostandard="LVCMOS33"  loc="J17"/>
+  <pin index="109" name ="JB8" iostandard="LVCMOS33"  loc="J18"/>
+  <pin index="110" name ="JB9" iostandard="LVCMOS33"  loc="K15"/>
+  <pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="112" name ="JC1"  iostandard="LVCMOS33" loc="U12"/>
+  <pin index="113" name ="JC2" iostandard="LVCMOS33"  loc="V12"/>
+  <pin index="114" name ="JC3" iostandard="LVCMOS33"  loc="V10"/>
+  <pin index="115" name ="JC4" iostandard="LVCMOS33"  loc="V11"/>
+  <pin index="116" name ="JC7" iostandard="LVCMOS33"  loc="U14"/>
+  <pin index="117" name ="JC8" iostandard="LVCMOS33"  loc="V14"/>
+  <pin index="118" name ="JC9" iostandard="LVCMOS33"  loc="T13"/>
+  <pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="120" name ="JD1" iostandard="LVCMOS33"  loc="D4"/>
+  <pin index="121" name ="JD2" iostandard="LVCMOS33"  loc="D3"/>
+  <pin index="122" name ="JD3" iostandard="LVCMOS33"  loc="F4"/>
+  <pin index="123" name ="JD4" iostandard="LVCMOS33"  loc="F3"/>
+  <pin index="124" name ="JD7" iostandard="LVCMOS33"  loc="E2"/>
+  <pin index="125" name ="JD8" iostandard="LVCMOS33"  loc="D2"/>
+  <pin index="126" name ="JD9" iostandard="LVCMOS33"  loc="H2"/>
+  <pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/preset.xml
new file mode 100644
index 0000000..ec20fb4
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.1/preset.xml
@@ -0,0 +1,418 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_12bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="mii_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.PHY_TYPE" value="MII"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.Physical_Interface" value="MII"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="shield_dp0_dp19_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="uart_preset">
+   <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/board.xml
new file mode 100644
index 0000000..4074b84
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/board.xml
@@ -0,0 +1,1247 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-35" display_name="Arty A7-35" url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">E.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Arty A7-35</description>
+<components>
+  <component name="part0" display_name="Arty A7-35" type="fpga" part_name="xc7a35ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start"> <!--CONFIRM URL-->
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+		<description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+        <description>4-position user DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+	  <description>Secondary interface to communicate with ethernet phy. </description>
+        <port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">
+        <description>Primary interface to communicate with ethernet phy in MII mode. </description>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_txd_1"/> 
+              <pin_map port_index="2" component_pin="eth_txd_2"/> 
+              <pin_map port_index="3" component_pin="eth_txd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rxd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rxd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rxd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_dv"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS" physical_port="eth_crs" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_crs"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="COL" physical_port="eth_col" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_col"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rstn"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">
+        <description>I2C Pullups to enable shield I2C</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_pullup_0"/> 
+              <pin_map port_index="1" component_pin="i2c_pullup_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+        <description>4 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<parameters>
+            <parameter name="rst_polarity" value="0"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">
+        <description>4 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="clk" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>256 MB DDR3L memory SODIMM </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	 <component_modes>
+        <component_mode name="mii" display_name="MII mode">
+		  <interfaces>
+            <interface name="eth_mii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1" optional="true"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">
+  <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+  	<description>Push buttons 3 to 0</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+  <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+  	<description>CPU Reset Push Button, active low</description>
+  </component>
+  <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB leds 12 to 0 (3 per LED)</description>
+  </component>
+  <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 0 through 19</description>
+  </component>
+  <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 26 through 41</description>
+  </component>
+  <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+  	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+    <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+    <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>
+	<connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+  <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">
+    <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+    <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">
+    <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>
+  </connection>
+  <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+    <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/part0_pins.xml
new file mode 100644
index 0000000..3f6de55
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/part0_pins.xml
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a35tcsg324-1L">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
+  <pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
+  <pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
+  <pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
+  <pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
+  <pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
+  <pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
+  <pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
+  <pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
+  <pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
+  <pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="96" name ="JA1" iostandard="LVCMOS33"   loc="G13"/>
+  <pin index="97" name ="JA2" iostandard="LVCMOS33"   loc="B11"/>
+  <pin index="98" name ="JA3" iostandard="LVCMOS33"   loc="A11"/>
+  <pin index="99" name ="JA4" iostandard="LVCMOS33"   loc="D12"/>
+  <pin index="100" name ="JA7" iostandard="LVCMOS33"  loc="D13"/>
+  <pin index="101" name ="JA8" iostandard="LVCMOS33"  loc="B18"/>
+  <pin index="102" name ="JA9" iostandard="LVCMOS33"  loc="A18"/>
+  <pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="104" name ="JB1" iostandard="LVCMOS33"  loc="E15"/>
+  <pin index="105" name ="JB2" iostandard="LVCMOS33"  loc="E16"/>
+  <pin index="106" name ="JB3" iostandard="LVCMOS33"  loc="D15"/>
+  <pin index="107" name ="JB4" iostandard="LVCMOS33"  loc="C15"/>
+  <pin index="108" name ="JB7" iostandard="LVCMOS33"  loc="J17"/>
+  <pin index="109" name ="JB8" iostandard="LVCMOS33"  loc="J18"/>
+  <pin index="110" name ="JB9" iostandard="LVCMOS33"  loc="K15"/>
+  <pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="112" name ="JC1"  iostandard="LVCMOS33" loc="U12"/>
+  <pin index="113" name ="JC2" iostandard="LVCMOS33"  loc="V12"/>
+  <pin index="114" name ="JC3" iostandard="LVCMOS33"  loc="V10"/>
+  <pin index="115" name ="JC4" iostandard="LVCMOS33"  loc="V11"/>
+  <pin index="116" name ="JC7" iostandard="LVCMOS33"  loc="U14"/>
+  <pin index="117" name ="JC8" iostandard="LVCMOS33"  loc="V14"/>
+  <pin index="118" name ="JC9" iostandard="LVCMOS33"  loc="T13"/>
+  <pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="120" name ="JD1" iostandard="LVCMOS33"  loc="D4"/>
+  <pin index="121" name ="JD2" iostandard="LVCMOS33"  loc="D3"/>
+  <pin index="122" name ="JD3" iostandard="LVCMOS33"  loc="F4"/>
+  <pin index="123" name ="JD4" iostandard="LVCMOS33"  loc="F3"/>
+  <pin index="124" name ="JD7" iostandard="LVCMOS33"  loc="E2"/>
+  <pin index="125" name ="JD8" iostandard="LVCMOS33"  loc="D2"/>
+  <pin index="126" name ="JD9" iostandard="LVCMOS33"  loc="H2"/>
+  <pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/preset.xml
new file mode 100644
index 0000000..8f0b6c3
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.0/preset.xml
@@ -0,0 +1,418 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_12bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="mii_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.PHY_TYPE" value="MII"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.Physical_Interface" value="MII"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="shield_dp0_dp19_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="uart_preset">
+   <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/board.xml
new file mode 100644
index 0000000..f0ebb73
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/board.xml
@@ -0,0 +1,1247 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-35" display_name="Arty A7-35" url="https://digilent.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">E.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Arty A7-35</description>
+<components>
+  <component name="part0" display_name="Arty A7-35" type="fpga" part_name="xc7a35ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/arty-a7/start"> <!--CONFIRM URL-->
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+		<description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+        <description>4-position user DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+	  <description>Secondary interface to communicate with ethernet phy. </description>
+        <port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">
+        <description>Primary interface to communicate with ethernet phy in MII mode. </description>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_txd_1"/> 
+              <pin_map port_index="2" component_pin="eth_txd_2"/> 
+              <pin_map port_index="3" component_pin="eth_txd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rxd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rxd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rxd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_dv"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS" physical_port="eth_crs" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_crs"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="COL" physical_port="eth_col" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_col"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rstn"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">
+        <description>I2C Pullups to enable shield I2C</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_pullup_0"/> 
+              <pin_map port_index="1" component_pin="i2c_pullup_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+        <description>4 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<parameters>
+            <parameter name="rst_polarity" value="0"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">
+        <description>4 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>256 MB DDR3L memory SODIMM </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	 <component_modes>
+        <component_mode name="mii" display_name="MII mode">
+		  <interfaces>
+            <interface name="eth_mii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1" optional="true"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">
+  <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+  	<description>Push buttons 3 to 0</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+  <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+  	<description>CPU Reset Push Button, active low</description>
+  </component>
+  <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB leds 12 to 0 (3 per LED)</description>
+  </component>
+  <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 0 through 19</description>
+  </component>
+  <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 26 through 41</description>
+  </component>
+  <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+  	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+    <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+    <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>
+	<connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+  <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">
+    <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+    <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">
+    <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>
+  </connection>
+  <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+    <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/part0_pins.xml
new file mode 100644
index 0000000..3f6de55
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/part0_pins.xml
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a35tcsg324-1L">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
+  <pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
+  <pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
+  <pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
+  <pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
+  <pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
+  <pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
+  <pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
+  <pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
+  <pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
+  <pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="96" name ="JA1" iostandard="LVCMOS33"   loc="G13"/>
+  <pin index="97" name ="JA2" iostandard="LVCMOS33"   loc="B11"/>
+  <pin index="98" name ="JA3" iostandard="LVCMOS33"   loc="A11"/>
+  <pin index="99" name ="JA4" iostandard="LVCMOS33"   loc="D12"/>
+  <pin index="100" name ="JA7" iostandard="LVCMOS33"  loc="D13"/>
+  <pin index="101" name ="JA8" iostandard="LVCMOS33"  loc="B18"/>
+  <pin index="102" name ="JA9" iostandard="LVCMOS33"  loc="A18"/>
+  <pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="104" name ="JB1" iostandard="LVCMOS33"  loc="E15"/>
+  <pin index="105" name ="JB2" iostandard="LVCMOS33"  loc="E16"/>
+  <pin index="106" name ="JB3" iostandard="LVCMOS33"  loc="D15"/>
+  <pin index="107" name ="JB4" iostandard="LVCMOS33"  loc="C15"/>
+  <pin index="108" name ="JB7" iostandard="LVCMOS33"  loc="J17"/>
+  <pin index="109" name ="JB8" iostandard="LVCMOS33"  loc="J18"/>
+  <pin index="110" name ="JB9" iostandard="LVCMOS33"  loc="K15"/>
+  <pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="112" name ="JC1"  iostandard="LVCMOS33" loc="U12"/>
+  <pin index="113" name ="JC2" iostandard="LVCMOS33"  loc="V12"/>
+  <pin index="114" name ="JC3" iostandard="LVCMOS33"  loc="V10"/>
+  <pin index="115" name ="JC4" iostandard="LVCMOS33"  loc="V11"/>
+  <pin index="116" name ="JC7" iostandard="LVCMOS33"  loc="U14"/>
+  <pin index="117" name ="JC8" iostandard="LVCMOS33"  loc="V14"/>
+  <pin index="118" name ="JC9" iostandard="LVCMOS33"  loc="T13"/>
+  <pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="120" name ="JD1" iostandard="LVCMOS33"  loc="D4"/>
+  <pin index="121" name ="JD2" iostandard="LVCMOS33"  loc="D3"/>
+  <pin index="122" name ="JD3" iostandard="LVCMOS33"  loc="F4"/>
+  <pin index="123" name ="JD4" iostandard="LVCMOS33"  loc="F3"/>
+  <pin index="124" name ="JD7" iostandard="LVCMOS33"  loc="E2"/>
+  <pin index="125" name ="JD8" iostandard="LVCMOS33"  loc="D2"/>
+  <pin index="126" name ="JD9" iostandard="LVCMOS33"  loc="H2"/>
+  <pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/preset.xml
new file mode 100644
index 0000000..8f0b6c3
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-35/E.0/1.1/preset.xml
@@ -0,0 +1,418 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_12bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="mii_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.PHY_TYPE" value="MII"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.Physical_Interface" value="MII"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="shield_dp0_dp19_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="uart_preset">
+   <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/board.xml
new file mode 100644
index 0000000..af685e3
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/board.xml
@@ -0,0 +1,1097 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-s7-25" display_name="Arty S7-25" url="https://digilent.com/reference/programmable-logic/arty-s7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">E.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Arty S7-25</description>
+<components>
+  <component name="part0" display_name="Arty S7-25" type="fpga" part_name="xc7s25csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/arty-s7/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+		<description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+        <description>4-position user DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+        <description>4 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<parameters>
+            <parameter name="rst_polarity" value="0"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp9" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp9" preset_proc="shield_dp0_dp9_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp9_tri_i" dir="in" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp9_tri_o" dir="out" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp9_tri_t" dir="out" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_a0_a5" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_a0_a5" preset_proc="shield_a0_a5_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_a0_a5_tri_i" dir="in" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_a0_a5_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_a0_a5_tri_t" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_a10_a11" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_a10_a11" preset_proc="shield_a10_a11_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_a10_a11_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_a10_a11_tri_o" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_a10_a11_tri_t" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="ddr_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="ddr_clock" preset_proc="ddr_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="ddr_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="ddr_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="12000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sys_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="12000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>256 MB DDR3L memory SODIMM </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+  	<description>Push buttons 3 to 0</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+  <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+  	<description>CPU Reset Push Button, active low</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB LEDs 1 through 0 (3 per LED)</description>
+  </component>
+  <component name="shield_dp0_dp9" display_name="Shield Pins 0 through 9" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 0 through 9</description>
+  </component>
+  <component name="shield_a0_a5" display_name="Shield Pins A0 through A5 (digital)" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins A0 through A5 for digital use</description>
+  </component>
+  <component name="shield_a10_a11" display_name="Shield Pins A10 through A11 (digital)" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins A10 through A11 for digital use</description>
+  </component>
+  <component name="spi" display_name="SPI connector J7" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+  <component name="ddr_clock" display_name="DDR Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>1.35V Single-Ended 100MHz oscillator used as DDR clock on the board</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>3.3V Single-Ended 12MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+  	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+    <connection_map name="part0_dip_switches_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+    <connection_map name="part0_push_buttons_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="12" c1_end_index="17" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="18" c1_end_index="19" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="20" c1_end_index="24" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="25" c1_end_index="25" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_ddr_clock" component1="part0" component2="ddr_clock">
+    <connection_map name="part0_ddr_clock_1" c1_st_index="26" c1_end_index="26" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_ddr_clock_1" c1_st_index="27" c1_end_index="27" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp9" component1="part0" component2="shield_dp0_dp9">
+    <connection_map name="part0_shield_dp0_dp9_1" c1_st_index="28" c1_end_index="37" c2_st_index="0" c2_end_index="9"/>
+  </connection>
+  <connection name="part0_shield_a0_a5" component1="part0" component2="shield_a0_a5">
+    <connection_map name="part0_shield_a0_a5_1" c1_st_index="38" c1_end_index="43" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_shield_a10_a11" component1="part0" component2="shield_a10_a11">
+    <connection_map name="part0_shield_a10_a11_1" c1_st_index="44" c1_end_index="45" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="46" c1_end_index="49" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="50" c1_end_index="51" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="52" c1_end_index="59" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="60" c1_end_index="67" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="68" c1_end_index="75" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="76" c1_end_index="83" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/part0_pins.xml
new file mode 100644
index 0000000..ba2a256
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/part0_pins.xml
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7s25csga324-1">
+<pins>
+  <pin index="0" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="1" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="H18"/>
+  <pin index="2" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="3" name ="dip_switches_4bits_tri_i_3" iostandard="SSTL135" loc="M5"/>
+  <pin index="4" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+  <pin index="5" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="6" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="J16"/>
+  <pin index="7" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="H13"/>
+  <pin index="8" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="9" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="10" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="E13"/>
+  <pin index="11" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="12" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="13" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="14" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="15" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/>
+  <pin index="16" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="17" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="E14"/>
+  <pin index="18" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="19" name ="usb_uart_txd" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="20" name ="qspi_csn_i" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="21" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="22" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="23" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="24" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M15"/>
+  <pin index="25" name ="reset" iostandard="LVCMOS33" loc="C18"/>
+  <pin index="26" name ="ddr_clk" iostandard="SSTL135" loc="R2"/>
+  <pin index="27" name ="sys_clk" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="28" name ="shield_dp0_dp9_tri_i_0" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="29" name ="shield_dp0_dp9_tri_i_1" iostandard="LVCMOS33" loc="N13"/>
+  <pin index="30" name ="shield_dp0_dp9_tri_i_2" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="31" name ="shield_dp0_dp9_tri_i_3" iostandard="LVCMOS33" loc="R14"/>
+  <pin index="32" name ="shield_dp0_dp9_tri_i_4" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="33" name ="shield_dp0_dp9_tri_i_5" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="34" name ="shield_dp0_dp9_tri_i_6" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="35" name ="shield_dp0_dp9_tri_i_7" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="36" name ="shield_dp0_dp9_tri_i_8" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="37" name ="shield_dp0_dp9_tri_i_9" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="38" name ="shield_a0_a5_tri_i_0" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="39" name ="shield_a0_a5_tri_i_1" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="40" name ="shield_a0_a5_tri_i_2" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="41" name ="shield_a0_a5_tri_i_3" iostandard="LVCMOS33" loc="C13"/>
+  <pin index="42" name ="shield_a0_a5_tri_i_4" iostandard="LVCMOS33" loc="C14"/>
+  <pin index="43" name ="shield_a0_a5_tri_i_5" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="44" name ="shield_a10_a11_tri_i_0" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="45" name ="shield_a10_a11_tri_i_1" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="46" name ="spi_miso_i" iostandard="LVCMOS33" loc="K14"/>
+  <pin index="47" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="48" name ="spi_sclk_i" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="49" name ="spi_ss_i" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="50" name ="i2c_scl_i" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="51" name ="i2c_sda_i" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="52" name ="JA1" iostandard="LVCMOS33"  loc="L17"/>
+  <pin index="53" name ="JA2" iostandard="LVCMOS33"  loc="L18"/>
+  <pin index="54" name ="JA3" iostandard="LVCMOS33"  loc="M14"/>
+  <pin index="55" name ="JA4" iostandard="LVCMOS33"  loc="N14"/>
+  <pin index="56" name ="JA7" iostandard="LVCMOS33"  loc="M16"/>
+  <pin index="57" name ="JA8" iostandard="LVCMOS33"  loc="M17"/>
+  <pin index="58" name ="JA9" iostandard="LVCMOS33"  loc="M18"/>
+  <pin index="59" name ="JA10" iostandard="LVCMOS33" loc="N18"/>
+  <pin index="60" name ="JB1" iostandard="LVCMOS33"  loc="P17"/>
+  <pin index="61" name ="JB2" iostandard="LVCMOS33"  loc="P18"/>
+  <pin index="62" name ="JB3" iostandard="LVCMOS33"  loc="R18"/>
+  <pin index="63" name ="JB4" iostandard="LVCMOS33"  loc="T18"/>
+  <pin index="64" name ="JB7" iostandard="LVCMOS33"  loc="P14"/>
+  <pin index="65" name ="JB8" iostandard="LVCMOS33"  loc="P15"/>
+  <pin index="66" name ="JB9" iostandard="LVCMOS33"  loc="N15"/>
+  <pin index="67" name ="JB10" iostandard="LVCMOS33" loc="P16"/>
+  <pin index="68" name ="JC1"  iostandard="LVCMOS33" loc="U15"/>
+  <pin index="69" name ="JC2" iostandard="LVCMOS33"  loc="V16"/>
+  <pin index="70" name ="JC3" iostandard="LVCMOS33"  loc="U17"/>
+  <pin index="71" name ="JC4" iostandard="LVCMOS33"  loc="U18"/>
+  <pin index="72" name ="JC7" iostandard="LVCMOS33"  loc="U16"/>
+  <pin index="73" name ="JC8" iostandard="LVCMOS33"  loc="P13"/>
+  <pin index="74" name ="JC9" iostandard="LVCMOS33"  loc="R13"/>
+  <pin index="75" name ="JC10" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="76" name ="JD1" iostandard="LVCMOS33"  loc="V15"/>
+  <pin index="77" name ="JD2" iostandard="LVCMOS33"  loc="U12"/>
+  <pin index="78" name ="JD3" iostandard="LVCMOS33"  loc="V13"/>
+  <pin index="79" name ="JD4" iostandard="LVCMOS33"  loc="T12"/>
+  <pin index="80" name ="JD7" iostandard="LVCMOS33"  loc="T13"/>
+  <pin index="81" name ="JD8" iostandard="LVCMOS33"  loc="R11"/>
+  <pin index="82" name ="JD9" iostandard="LVCMOS33"  loc="T11"/>
+  <pin index="83" name ="JD10" iostandard="LVCMOS33" loc="U11"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/preset.xml
new file mode 100644
index 0000000..be425ed
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-25/E.0/preset.xml
@@ -0,0 +1,425 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="shield_dp0_dp9_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_a0_a5_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_a10_a11_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+
+   <ip_preset preset_proc_name="uart_preset">
+   <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="ddr_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/board.xml
new file mode 100644
index 0000000..feeac73
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/board.xml
@@ -0,0 +1,1097 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-s7-50" display_name="Arty S7-50" url="https://digilent.com/reference/programmable-logic/arty-s7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Arty S7-50</description>
+<components>
+  <component name="part0" display_name="Arty S7-50" type="fpga" part_name="xc7s50csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/arty-s7/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+		<description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+        <description>4-position user DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+        <description>4 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<parameters>
+            <parameter name="rst_polarity" value="0"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp9" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp9" preset_proc="shield_dp0_dp9_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp9_tri_i" dir="in" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp9_tri_o" dir="out" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp9_tri_t" dir="out" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_a0_a5" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_a0_a5" preset_proc="shield_a0_a5_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_a0_a5_tri_i" dir="in" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_a0_a5_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_a0_a5_tri_t" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_a10_a11" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_a10_a11" preset_proc="shield_a10_a11_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_a10_a11_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_a10_a11_tri_o" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_a10_a11_tri_t" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="ddr_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="ddr_clock" preset_proc="ddr_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		    <port_maps>
+          <port_map logical_port="CLK" physical_port="ddr_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="ddr_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="12000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sys_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="12000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>256 MB DDR3L memory SODIMM </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+  	<description>Push buttons 3 to 0</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+  <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+  	<description>CPU Reset Push Button, active low</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB LEDs 1 through 0 (3 per LED)</description>
+  </component>
+  <component name="shield_dp0_dp9" display_name="Shield Pins 0 through 9" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 0 through 9</description>
+  </component>
+  <component name="shield_a0_a5" display_name="Shield Pins A0 through A5 (digital)" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins A0 through A5 for digital use</description>
+  </component>
+  <component name="shield_a10_a11" display_name="Shield Pins A10 through A11 (digital)" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins A10 through A11 for digital use</description>
+  </component>
+  <component name="spi" display_name="SPI connector J7" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+  <component name="ddr_clock" display_name="DDR Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>1.35V Single-Ended 100MHz oscillator used as DDR clock on the board</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>3.3V Single-Ended 12MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+  	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+    <connection_map name="part0_dip_switches_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+    <connection_map name="part0_push_buttons_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="12" c1_end_index="17" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="18" c1_end_index="19" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="20" c1_end_index="24" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="25" c1_end_index="25" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_ddr_clock" component1="part0" component2="ddr_clock">
+    <connection_map name="part0_ddr_clock_1" c1_st_index="26" c1_end_index="26" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_ddr_clock_1" c1_st_index="27" c1_end_index="27" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp9" component1="part0" component2="shield_dp0_dp9">
+    <connection_map name="part0_shield_dp0_dp9_1" c1_st_index="28" c1_end_index="37" c2_st_index="0" c2_end_index="9"/>
+  </connection>
+  <connection name="part0_shield_a0_a5" component1="part0" component2="shield_a0_a5">
+    <connection_map name="part0_shield_a0_a5_1" c1_st_index="38" c1_end_index="43" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_shield_a10_a11" component1="part0" component2="shield_a10_a11">
+    <connection_map name="part0_shield_a10_a11_1" c1_st_index="44" c1_end_index="45" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="46" c1_end_index="49" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="50" c1_end_index="51" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="52" c1_end_index="59" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="60" c1_end_index="67" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="68" c1_end_index="75" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="76" c1_end_index="83" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/part0_pins.xml
new file mode 100644
index 0000000..e801960
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/part0_pins.xml
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7s50csga324-1">
+<pins>
+  <pin index="0" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="1" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="H18"/>
+  <pin index="2" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="3" name ="dip_switches_4bits_tri_i_3" iostandard="SSTL135" loc="M5"/>
+  <pin index="4" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+  <pin index="5" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="6" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="J16"/>
+  <pin index="7" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="H13"/>
+  <pin index="8" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="9" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="10" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="E13"/>
+  <pin index="11" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="12" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="13" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="14" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="15" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/>
+  <pin index="16" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="17" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="E14"/>
+  <pin index="18" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="19" name ="usb_uart_txd" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="20" name ="qspi_csn_i" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="21" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="22" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="23" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="24" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M15"/>
+  <pin index="25" name ="reset" iostandard="LVCMOS33" loc="C18"/>
+  <pin index="26" name ="ddr_clk" iostandard="SSTL135" loc="R2"/>
+  <pin index="27" name ="sys_clk" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="28" name ="shield_dp0_dp9_tri_i_0" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="29" name ="shield_dp0_dp9_tri_i_1" iostandard="LVCMOS33" loc="N13"/>
+  <pin index="30" name ="shield_dp0_dp9_tri_i_2" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="31" name ="shield_dp0_dp9_tri_i_3" iostandard="LVCMOS33" loc="R14"/>
+  <pin index="32" name ="shield_dp0_dp9_tri_i_4" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="33" name ="shield_dp0_dp9_tri_i_5" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="34" name ="shield_dp0_dp9_tri_i_6" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="35" name ="shield_dp0_dp9_tri_i_7" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="36" name ="shield_dp0_dp9_tri_i_8" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="37" name ="shield_dp0_dp9_tri_i_9" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="38" name ="shield_a0_a5_tri_i_0" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="39" name ="shield_a0_a5_tri_i_1" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="40" name ="shield_a0_a5_tri_i_2" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="41" name ="shield_a0_a5_tri_i_3" iostandard="LVCMOS33" loc="C13"/>
+  <pin index="42" name ="shield_a0_a5_tri_i_4" iostandard="LVCMOS33" loc="C14"/>
+  <pin index="43" name ="shield_a0_a5_tri_i_5" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="44" name ="shield_a10_a11_tri_i_0" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="45" name ="shield_a10_a11_tri_i_1" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="46" name ="spi_miso_i" iostandard="LVCMOS33" loc="K14"/>
+  <pin index="47" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="48" name ="spi_sclk_i" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="49" name ="spi_ss_i" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="50" name ="i2c_scl_i" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="51" name ="i2c_sda_i" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="52" name ="JA1" iostandard="LVCMOS33"  loc="L17"/>
+  <pin index="53" name ="JA2" iostandard="LVCMOS33"  loc="L18"/>
+  <pin index="54" name ="JA3" iostandard="LVCMOS33"  loc="M14"/>
+  <pin index="55" name ="JA4" iostandard="LVCMOS33"  loc="N14"/>
+  <pin index="56" name ="JA7" iostandard="LVCMOS33"  loc="M16"/>
+  <pin index="57" name ="JA8" iostandard="LVCMOS33"  loc="M17"/>
+  <pin index="58" name ="JA9" iostandard="LVCMOS33"  loc="M18"/>
+  <pin index="59" name ="JA10" iostandard="LVCMOS33" loc="N18"/>
+  <pin index="60" name ="JB1" iostandard="LVCMOS33"  loc="P17"/>
+  <pin index="61" name ="JB2" iostandard="LVCMOS33"  loc="P18"/>
+  <pin index="62" name ="JB3" iostandard="LVCMOS33"  loc="R18"/>
+  <pin index="63" name ="JB4" iostandard="LVCMOS33"  loc="T18"/>
+  <pin index="64" name ="JB7" iostandard="LVCMOS33"  loc="P14"/>
+  <pin index="65" name ="JB8" iostandard="LVCMOS33"  loc="P15"/>
+  <pin index="66" name ="JB9" iostandard="LVCMOS33"  loc="N15"/>
+  <pin index="67" name ="JB10" iostandard="LVCMOS33" loc="P16"/>
+  <pin index="68" name ="JC1"  iostandard="LVCMOS33" loc="U15"/>
+  <pin index="69" name ="JC2" iostandard="LVCMOS33"  loc="V16"/>
+  <pin index="70" name ="JC3" iostandard="LVCMOS33"  loc="U17"/>
+  <pin index="71" name ="JC4" iostandard="LVCMOS33"  loc="U18"/>
+  <pin index="72" name ="JC7" iostandard="LVCMOS33"  loc="U16"/>
+  <pin index="73" name ="JC8" iostandard="LVCMOS33"  loc="P13"/>
+  <pin index="74" name ="JC9" iostandard="LVCMOS33"  loc="R13"/>
+  <pin index="75" name ="JC10" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="76" name ="JD1" iostandard="LVCMOS33"  loc="V15"/>
+  <pin index="77" name ="JD2" iostandard="LVCMOS33"  loc="U12"/>
+  <pin index="78" name ="JD3" iostandard="LVCMOS33"  loc="V13"/>
+  <pin index="79" name ="JD4" iostandard="LVCMOS33"  loc="T12"/>
+  <pin index="80" name ="JD7" iostandard="LVCMOS33"  loc="T13"/>
+  <pin index="81" name ="JD8" iostandard="LVCMOS33"  loc="R11"/>
+  <pin index="82" name ="JD9" iostandard="LVCMOS33"  loc="T11"/>
+  <pin index="83" name ="JD10" iostandard="LVCMOS33" loc="U11"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/preset.xml
new file mode 100644
index 0000000..be425ed
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-s7-50/B.0/preset.xml
@@ -0,0 +1,425 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="shield_dp0_dp9_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_a0_a5_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_a10_a11_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+
+   <ip_preset preset_proc_name="uart_preset">
+   <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="ddr_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/board.xml
new file mode 100644
index 0000000..ae4d777
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/board.xml
@@ -0,0 +1,588 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-10" display_name="Arty Z7-10" url="https://digilent.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Arty Z7-10 </description>
+<components>
+  <component name="part0" display_name="Arty Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/arty-z7/start">
+    <interfaces>
+      <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+      </interface>
+      <interface mode="master" name="sws_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_2bits" preset_proc="dip_switches_2bits_preset">
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="sws_2bits_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sws_2bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="sws_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sys_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="125000000" />
+       </parameters>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>	  
+    </interfaces>
+  </component>
+  
+  <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Buttons 3 to 0</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+  <component name="sws_2bits" display_name="2 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 1 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  <description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
+  </component>
+
+  <component name="i2c" display_name="I2C on J2" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+  </component>
+  <component name="shield_dp0_dp13" display_name="Shield Pins 0 through 13" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Digital Shield pins DP0 through DP13</description>
+  </component>
+  <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+    <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+    <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sws_2bits" component1="part0" component2="sws_2bits">
+    <connection_map name="part0_sws_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="10" c1_end_index="10" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="11" c1_end_index="18" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="19" c1_end_index="26" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="27" c1_end_index="28" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="29" c1_end_index="34" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
+    <connection_map name="part0_shield_dp0_dp13_1" c1_st_index="35" c1_end_index="48" c2_st_index="0" c2_end_index="13"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="65" c1_end_index="68" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/part0_pins.xml
new file mode 100644
index 0000000..98bb741
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/part0_pins.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z010clg400-1">
+<pins>
+  <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="D19"/>
+  <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="D20"/>
+  <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="L20"/>
+  <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="L19"/>
+  <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="R14"/>
+  <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="8" name ="sws_2bits_tri_i_0" iostandard="LVCMOS33" loc="M20"/>
+  <pin index="9" name ="sws_2bits_tri_i_1" iostandard="LVCMOS33" loc="M19"/>
+  <pin index="10" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="11" name ="JA1" iostandard="LVCMOS33" loc="Y18"/>
+  <pin index="12" name ="JA2" iostandard="LVCMOS33" loc="Y19"/>
+  <pin index="13" name ="JA3" iostandard="LVCMOS33" loc="Y16"/>
+  <pin index="14" name ="JA4" iostandard="LVCMOS33" loc="Y17"/>
+  <pin index="15" name ="JA7" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="16" name ="JA8" iostandard="LVCMOS33" loc="U19"/>
+  <pin index="17" name ="JA9" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="18" name ="JA10" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="19" name ="JB1" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="20" name ="JB2" iostandard="LVCMOS33" loc="Y14"/>
+  <pin index="21" name ="JB3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="22" name ="JB4" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="23" name ="JB7" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="24" name ="JB8" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="25" name ="JB9" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="26" name ="JB10" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="27" name ="i2c_scl_i" iostandard="LVCMOS33" loc="P16"/>
+  <pin index="28" name ="i2c_sda_i" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="29" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="L15"/>
+  <pin index="30" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="31" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="32" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="33" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="34" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="M15"/>
+  <pin index="35" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="36" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="37" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="38" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="39" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="40" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="41" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="42" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="43" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="44" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="V18"/>
+  <pin index="45" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="46" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="47" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="48" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="65" name ="spi_miso_i" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="66" name ="spi_mosi_i" iostandard="LVCMOS33" loc="T12"/>
+  <pin index="67" name ="spi_sclk_i" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="68" name ="spi_ss_i" iostandard="LVCMOS33" loc="T16"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/preset.xml
new file mode 100644
index 0000000..6408405
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-10/A.0/preset.xml
@@ -0,0 +1,1111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ps7_preset">
+    <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+      <user_parameters>
+        <user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/> 
+        <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/> 
+        <user_parameter name="CONFIG.PCW_UART0_BASEADDR" value="0xE0000000"/> 
+        <user_parameter name="CONFIG.PCW_UART0_HIGHADDR" value="0xE0000FFF"/> 
+        <user_parameter name="CONFIG.PCW_UART1_BASEADDR" value="0xE0001000"/> 
+        <user_parameter name="CONFIG.PCW_UART1_HIGHADDR" value="0xE0001FFF"/> 
+        <user_parameter name="CONFIG.PCW_I2C0_BASEADDR" value="0xE0004000"/> 
+        <user_parameter name="CONFIG.PCW_I2C0_HIGHADDR" value="0xE0004FFF"/> 
+        <user_parameter name="CONFIG.PCW_I2C1_BASEADDR" value="0xE0005000"/> 
+        <user_parameter name="CONFIG.PCW_I2C1_HIGHADDR" value="0xE0005FFF"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_BASEADDR" value="0xE0006000"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_HIGHADDR" value="0xE0006FFF"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_BASEADDR" value="0xE0007000"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_HIGHADDR" value="0xE0007FFF"/> 
+        <user_parameter name="CONFIG.PCW_CAN0_BASEADDR" value="0xE0008000"/> 
+        <user_parameter name="CONFIG.PCW_CAN0_HIGHADDR" value="0xE0008FFF"/> 
+        <user_parameter name="CONFIG.PCW_CAN1_BASEADDR" value="0xE0009000"/> 
+        <user_parameter name="CONFIG.PCW_CAN1_HIGHADDR" value="0xE0009FFF"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_BASEADDR" value="0xE000A000"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_HIGHADDR" value="0xE000AFFF"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_BASEADDR" value="0xE000B000"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_HIGHADDR" value="0xE000BFFF"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_BASEADDR" value="0xE000C000"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_HIGHADDR" value="0xE000CFFF"/> 
+        <user_parameter name="CONFIG.PCW_SDIO0_BASEADDR" value="0xE0100000"/> 
+        <user_parameter name="CONFIG.PCW_SDIO0_HIGHADDR" value="0xE0100FFF"/> 
+        <user_parameter name="CONFIG.PCW_SDIO1_BASEADDR" value="0xE0101000"/> 
+        <user_parameter name="CONFIG.PCW_SDIO1_HIGHADDR" value="0xE0101FFF"/> 
+        <user_parameter name="CONFIG.PCW_USB0_BASEADDR" value="0xE0102000"/> 
+        <user_parameter name="CONFIG.PCW_USB0_HIGHADDR" value="0xE0102fff"/> 
+        <user_parameter name="CONFIG.PCW_USB1_BASEADDR" value="0xE0103000"/> 
+        <user_parameter name="CONFIG.PCW_USB1_HIGHADDR" value="0xE0103fff"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_BASEADDR" value="0xE0104000"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_HIGHADDR" value="0xE0104fff"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_BASEADDR" value="0xE0105000"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_HIGHADDR" value="0xE0105fff"/> 
+        <user_parameter name="CONFIG.PCW_FCLK_CLK0_BUF" value="true"/> 
+        <user_parameter name="CONFIG.PCW_FCLK_CLK1_BUF" value="false"/> 
+        <user_parameter name="CONFIG.PCW_FCLK_CLK2_BUF" value="false"/> 
+        <user_parameter name="CONFIG.PCW_FCLK_CLK3_BUF" value="false"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.91"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="25.8"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="25.8"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" value="0.223"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" value="0.212"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" value="0.085"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" value="0.092"/> 
+        <user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/> 
+        <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/> 
+        <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/> 
+        <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/> 
+        <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ" value="60"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ" value="166.666666"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ" value="-1"/> 
+        <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ" value="-1"/> 
+        <user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ" value="25"/> 
+        <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/> 
+        <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/> 
+        <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" value="650.000000"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" value="525.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" value="10.096154"/> 
+        <user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" value="200.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ" value="10.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" value="125.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" value="10.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ" value="60"/> 
+        <user_parameter name="CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ" value="60"/> 
+        <user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ" value="100.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ" value="10.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" value="10.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" value="23.8095"/> 
+        <user_parameter name="CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" value="23.8095"/> 
+        <user_parameter name="CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" value="200.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" value="200.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" value="100.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_CLK0_FREQ" value="100000000"/> 
+        <user_parameter name="CONFIG.PCW_CLK1_FREQ" value="50000000"/> 
+        <user_parameter name="CONFIG.PCW_CLK2_FREQ" value="50000000"/> 
+        <user_parameter name="CONFIG.PCW_CLK3_FREQ" value="50000000"/> 
+        <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/> 
+        <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/> 
+        <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/> 
+        <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" value="10"/> 
+        <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" value="20"/> 
+        <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" value="20"/> 
+        <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" value="20"/> 
+        <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/> 
+        <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/> 
+        <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/> 
+        <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/> 
+        <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/> 
+        <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/> 
+        <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/> 
+        <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/> 
+        <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_VALID" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_VALID" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_VALID" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_CAN0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_CAN1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_ENET0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_ENET1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_PTP_ENET0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_PTP_ENET1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_GPIO" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_I2C0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_I2C1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_PJTAG" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SPI0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SPI1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_UART0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_UART1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_TTC0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_TTC1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_WDT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_TRACE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USE_M_AXI_GP1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_GP0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_GP1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_ACP" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_HP0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_HP1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_HP2" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_HP3" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_GP0_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_GP1_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_ACP_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP0_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP1_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP2_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP3_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_USE_DMA0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DMA1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DMA2" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DMA3" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_TRACE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_TRACE_PIPELINE_WIDTH" value="8"/> 
+        <user_parameter name="CONFIG.PCW_INCLUDE_TRACE_BUFFER" value="0"/> 
+        <user_parameter name="CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE" value="128"/> 
+        <user_parameter name="CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY" value="12"/> 
+        <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DEBUG" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_CR_FABRIC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USE_AXI_FABRIC_IDLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DDR_BYPASS" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_FABRIC_INTERRUPT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_PROC_EVENT_BUS" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_EXPANDED_IOP" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_HIGH_OCM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_PS_SLCR_REGISTERS" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_CORESIGHT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SRAM_INT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/> 
+        <user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/> 
+        <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_ID_WIDTH" value="12"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH" value="12"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_ID_WIDTH" value="12"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH" value="12"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_GP0_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_GP1_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_ACP_ID_WIDTH" value="3"/> 
+        <user_parameter name="CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL" value="0"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_ACP_ARUSER_VAL" value="31"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_ACP_AWUSER_VAL" value="31"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP0_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP0_DATA_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP1_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP1_DATA_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP2_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP2_DATA_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP3_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP3_DATA_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_EN_DDR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_SMC" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_QSPI" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_CAN0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CAN1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_ENET0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_ENET1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_GPIO" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_I2C0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_I2C1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_PJTAG" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_SDIO0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_SDIO1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_SPI0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_SPI1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_UART0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_UART1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_MODEM_UART0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_MODEM_UART1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_TTC0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_TTC1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_WDT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_TRACE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_USB0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_USB1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DQ_WIDTH" value="32"/> 
+        <user_parameter name="CONFIG.PCW_DQS_WIDTH" value="4"/> 
+        <user_parameter name="CONFIG.PCW_DM_WIDTH" value="4"/> 
+        <user_parameter name="CONFIG.PCW_MIO_PRIMITIVE" value="54"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLK0_PORT" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLK1_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLK2_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLK3_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_RST0_PORT" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_RST1_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_RST2_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_RST3_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLKTRIG0_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLKTRIG1_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLKTRIG2_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLKTRIG3_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC_ABORT_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC2_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC3_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC4_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC5_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC6_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC7_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SMC_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_QSPI_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_CTI_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_GPIO_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_USB0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_ENET0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SDIO0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_I2C0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SPI0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_UART0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_CAN0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_USB1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_ENET1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SDIO1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_I2C1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SPI1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_UART1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_CAN1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_IRQ_F2P_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/> 
+        <user_parameter name="CONFIG.PCW_CORE0_FIQ_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CORE0_IRQ_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CORE1_FIQ_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CORE1_IRQ_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_VALUE_SILVERSION" value="3"/> 
+        <user_parameter name="CONFIG.PCW_IMPORT_BOARD_PRESET" value="None"/> 
+        <user_parameter name="CONFIG.PCW_PERIPHERAL_BOARD_PRESET" value="None"/> 
+        <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41J256M16 RE-125"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PORT0_HPR_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PORT1_HPR_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PORT2_HPR_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PORT3_HPR_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/> 
+        <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/> 
+        <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/> 
+        <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/> 
+        <user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE" value="0"/>  
+        <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/> 
+        <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_GRP_MDIO_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD1_GRP_CD_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD1_GRP_WP_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD1_GRP_POW_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/> 
+        <user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_GRP_SS0_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_GRP_SS1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_GRP_SS2_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_GRP_SS0_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_GRP_SS1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/> 
+        <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/> 
+        <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/> 
+        <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/> 
+        <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/> 
+        <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC" value="External"/> 
+        <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC" value="External"/> 
+        <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/> 
+        <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/> 
+        <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/> 
+        <user_parameter name="CONFIG.PCW_I2C_RESET_POLARITY" value="Active Low"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_GENERATE_SUMMARY" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/> 
+        <user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/> 
+        <user_parameter name="CONFIG.PCW_PS7_SI_REV" value="PRODUCTION"/> 
+        <user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_TR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_PC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_CEOE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_WE_TIME" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_TR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_PC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_CEOE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_WE_TIME" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_TR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_PC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_CEOE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_WE_TIME" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_TR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_PC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_CEOE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_WE_TIME" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_AR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_CLR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_REA" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T0" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T1" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T2" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T3" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T4" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T5" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T6" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_NAME" value="clg400"/> 
+        <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="dip_switches_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_dp0_dp13_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/board.xml
new file mode 100644
index 0000000..66e26d5
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/board.xml
@@ -0,0 +1,661 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-20" display_name="Arty Z7-20" url="https://digilent.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Arty Z7-20 </description>
+<components>
+  <component name="part0" display_name="Arty Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/arty-z7/start">
+    <interfaces>
+      <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+      </interface>
+      <interface mode="master" name="sws_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_2bits" preset_proc="dip_switches_2bits_preset">
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="sws_2bits_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sws_2bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="sws_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sys_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="125000000" />
+       </parameters>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>	  
+    </interfaces>
+  </component>
+  
+  <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Buttons 3 to 0</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+  <component name="sws_2bits" display_name="2 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 1 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  <description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
+  </component>
+
+  <component name="i2c" display_name="I2C on J2" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+  </component>
+  <component name="shield_dp0_dp13" display_name="Shield Pins 0 through 13" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Digital Shield pins DP0 through DP13</description>
+  </component>
+  <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Digital Shield pins DP26 through DP41</description>
+  </component>
+  <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+    <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+    <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sws_2bits" component1="part0" component2="sws_2bits">
+    <connection_map name="part0_sws_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="10" c1_end_index="10" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="11" c1_end_index="18" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="19" c1_end_index="26" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="27" c1_end_index="28" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="29" c1_end_index="34" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
+    <connection_map name="part0_shield_dp0_dp13_1" c1_st_index="35" c1_end_index="48" c2_st_index="0" c2_end_index="13"/>
+  </connection>
+  <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+    <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="49" c1_end_index="64" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="65" c1_end_index="68" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/part0_pins.xml
new file mode 100644
index 0000000..1f58f63
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/part0_pins.xml
@@ -0,0 +1,97 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z020clg400-1">
+<pins>
+  <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="D19"/>
+  <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="D20"/>
+  <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="L20"/>
+  <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="L19"/>
+  <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="R14"/>
+  <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="8" name ="sws_2bits_tri_i_0" iostandard="LVCMOS33" loc="M20"/>
+  <pin index="9" name ="sws_2bits_tri_i_1" iostandard="LVCMOS33" loc="M19"/>
+  <pin index="10" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="11" name ="JA1" iostandard="LVCMOS33" loc="Y18"/>
+  <pin index="12" name ="JA2" iostandard="LVCMOS33" loc="Y19"/>
+  <pin index="13" name ="JA3" iostandard="LVCMOS33" loc="Y16"/>
+  <pin index="14" name ="JA4" iostandard="LVCMOS33" loc="Y17"/>
+  <pin index="15" name ="JA7" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="16" name ="JA8" iostandard="LVCMOS33" loc="U19"/>
+  <pin index="17" name ="JA9" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="18" name ="JA10" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="19" name ="JB1" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="20" name ="JB2" iostandard="LVCMOS33" loc="Y14"/>
+  <pin index="21" name ="JB3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="22" name ="JB4" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="23" name ="JB7" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="24" name ="JB8" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="25" name ="JB9" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="26" name ="JB10" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="27" name ="i2c_scl_i" iostandard="LVCMOS33" loc="P16"/>
+  <pin index="28" name ="i2c_sda_i" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="29" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="L15"/>
+  <pin index="30" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="31" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="32" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="33" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="34" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="M15"/>
+  <pin index="35" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="36" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="37" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="38" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="39" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="40" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="41" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="42" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="43" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="44" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="V18"/>
+  <pin index="45" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="46" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="47" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="48" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="49" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U5"/>
+  <pin index="50" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V5"/>
+  <pin index="51" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="V6"/>
+  <pin index="52" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="U7"/>
+  <pin index="53" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="V7"/>
+  <pin index="54" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="U8"/>
+  <pin index="55" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="V8"/>
+  <pin index="56" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="57" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="W10"/>
+  <pin index="58" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="W6"/>
+  <pin index="59" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="Y6"/>
+  <pin index="60" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="Y7"/>
+  <pin index="61" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="W8"/>
+  <pin index="62" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="Y8"/>
+  <pin index="63" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="W9"/>
+  <pin index="64" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="Y9"/>
+  <pin index="65" name ="spi_miso_i" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="66" name ="spi_mosi_i" iostandard="LVCMOS33" loc="T12"/>
+  <pin index="67" name ="spi_sclk_i" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="68" name ="spi_ss_i" iostandard="LVCMOS33" loc="T16"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/preset.xml
new file mode 100644
index 0000000..99e012e
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/preset.xml
@@ -0,0 +1,1129 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ps7_preset">
+    <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+      <user_parameters>
+        <user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/> 
+        <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/> 
+        <user_parameter name="CONFIG.PCW_UART0_BASEADDR" value="0xE0000000"/> 
+        <user_parameter name="CONFIG.PCW_UART0_HIGHADDR" value="0xE0000FFF"/> 
+        <user_parameter name="CONFIG.PCW_UART1_BASEADDR" value="0xE0001000"/> 
+        <user_parameter name="CONFIG.PCW_UART1_HIGHADDR" value="0xE0001FFF"/> 
+        <user_parameter name="CONFIG.PCW_I2C0_BASEADDR" value="0xE0004000"/> 
+        <user_parameter name="CONFIG.PCW_I2C0_HIGHADDR" value="0xE0004FFF"/> 
+        <user_parameter name="CONFIG.PCW_I2C1_BASEADDR" value="0xE0005000"/> 
+        <user_parameter name="CONFIG.PCW_I2C1_HIGHADDR" value="0xE0005FFF"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_BASEADDR" value="0xE0006000"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_HIGHADDR" value="0xE0006FFF"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_BASEADDR" value="0xE0007000"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_HIGHADDR" value="0xE0007FFF"/> 
+        <user_parameter name="CONFIG.PCW_CAN0_BASEADDR" value="0xE0008000"/> 
+        <user_parameter name="CONFIG.PCW_CAN0_HIGHADDR" value="0xE0008FFF"/> 
+        <user_parameter name="CONFIG.PCW_CAN1_BASEADDR" value="0xE0009000"/> 
+        <user_parameter name="CONFIG.PCW_CAN1_HIGHADDR" value="0xE0009FFF"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_BASEADDR" value="0xE000A000"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_HIGHADDR" value="0xE000AFFF"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_BASEADDR" value="0xE000B000"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_HIGHADDR" value="0xE000BFFF"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_BASEADDR" value="0xE000C000"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_HIGHADDR" value="0xE000CFFF"/> 
+        <user_parameter name="CONFIG.PCW_SDIO0_BASEADDR" value="0xE0100000"/> 
+        <user_parameter name="CONFIG.PCW_SDIO0_HIGHADDR" value="0xE0100FFF"/> 
+        <user_parameter name="CONFIG.PCW_SDIO1_BASEADDR" value="0xE0101000"/> 
+        <user_parameter name="CONFIG.PCW_SDIO1_HIGHADDR" value="0xE0101FFF"/> 
+        <user_parameter name="CONFIG.PCW_USB0_BASEADDR" value="0xE0102000"/> 
+        <user_parameter name="CONFIG.PCW_USB0_HIGHADDR" value="0xE0102fff"/> 
+        <user_parameter name="CONFIG.PCW_USB1_BASEADDR" value="0xE0103000"/> 
+        <user_parameter name="CONFIG.PCW_USB1_HIGHADDR" value="0xE0103fff"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_BASEADDR" value="0xE0104000"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_HIGHADDR" value="0xE0104fff"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_BASEADDR" value="0xE0105000"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_HIGHADDR" value="0xE0105fff"/> 
+        <user_parameter name="CONFIG.PCW_FCLK_CLK0_BUF" value="true"/> 
+        <user_parameter name="CONFIG.PCW_FCLK_CLK1_BUF" value="false"/> 
+        <user_parameter name="CONFIG.PCW_FCLK_CLK2_BUF" value="false"/> 
+        <user_parameter name="CONFIG.PCW_FCLK_CLK3_BUF" value="false"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.91"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="25.8"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="25.8"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" value="0.223"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" value="0.212"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" value="0.085"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" value="0.092"/> 
+        <user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/> 
+        <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/> 
+        <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/> 
+        <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/> 
+        <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ" value="60"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ" value="166.666666"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ" value="-1"/> 
+        <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ" value="-1"/> 
+        <user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ" value="25"/> 
+        <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="133.333333"/> 
+        <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/> 
+        <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/> 
+        <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" value="650.000000"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" value="525.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" value="10.096154"/> 
+        <user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" value="200.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ" value="10.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" value="125.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" value="10.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ" value="60"/> 
+        <user_parameter name="CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ" value="60"/> 
+        <user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ" value="100.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ" value="10.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" value="10.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" value="23.8095"/> 
+        <user_parameter name="CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" value="23.8095"/> 
+        <user_parameter name="CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" value="200.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" value="200.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" value="100.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/> 
+        <user_parameter name="CONFIG.PCW_CLK0_FREQ" value="100000000"/> 
+        <user_parameter name="CONFIG.PCW_CLK1_FREQ" value="50000000"/> 
+        <user_parameter name="CONFIG.PCW_CLK2_FREQ" value="50000000"/> 
+        <user_parameter name="CONFIG.PCW_CLK3_FREQ" value="50000000"/> 
+        <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/> 
+        <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/> 
+        <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/> 
+        <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" value="10"/> 
+        <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" value="20"/> 
+        <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" value="20"/> 
+        <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" value="20"/> 
+        <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/> 
+        <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/> 
+        <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/> 
+        <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/> 
+        <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/> 
+        <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/> 
+        <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/> 
+        <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/> 
+        <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_VALID" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_VALID" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_VALID" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_CAN0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_CAN1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_ENET0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_ENET1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_PTP_ENET0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_PTP_ENET1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_GPIO" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_I2C0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_I2C1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_PJTAG" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SPI0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SPI1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_UART0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_UART1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_TTC0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_TTC1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_WDT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_TRACE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USE_M_AXI_GP1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_GP0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_GP1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_ACP" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_HP0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_HP1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_HP2" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_S_AXI_HP3" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_GP0_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_GP1_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_ACP_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP0_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP1_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP2_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP3_FREQMHZ" value="10"/> 
+        <user_parameter name="CONFIG.PCW_USE_DMA0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DMA1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DMA2" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DMA3" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_TRACE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_TRACE_PIPELINE_WIDTH" value="8"/> 
+        <user_parameter name="CONFIG.PCW_INCLUDE_TRACE_BUFFER" value="0"/> 
+        <user_parameter name="CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE" value="128"/> 
+        <user_parameter name="CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY" value="12"/> 
+        <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DEBUG" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_CR_FABRIC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USE_AXI_FABRIC_IDLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DDR_BYPASS" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_FABRIC_INTERRUPT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_PROC_EVENT_BUS" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_EXPANDED_IOP" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_HIGH_OCM" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_PS_SLCR_REGISTERS" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_CORESIGHT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_EMIO_SRAM_INT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/> 
+        <user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/> 
+        <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_ID_WIDTH" value="12"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH" value="12"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_ID_WIDTH" value="12"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" value="0"/> 
+        <user_parameter name="CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH" value="12"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_GP0_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_GP1_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_ACP_ID_WIDTH" value="3"/> 
+        <user_parameter name="CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL" value="0"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_ACP_ARUSER_VAL" value="31"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_ACP_AWUSER_VAL" value="31"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP0_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP0_DATA_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP1_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP1_DATA_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP2_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP2_DATA_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP3_ID_WIDTH" value="6"/> 
+        <user_parameter name="CONFIG.PCW_S_AXI_HP3_DATA_WIDTH" value="64"/> 
+        <user_parameter name="CONFIG.PCW_EN_DDR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_SMC" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_QSPI" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_CAN0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CAN1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_ENET0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_ENET1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_GPIO" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_I2C0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_I2C1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_PJTAG" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_SDIO0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_SDIO1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_SPI0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_SPI1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_UART0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_UART1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_MODEM_UART0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_MODEM_UART1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_TTC0" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_TTC1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_WDT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_TRACE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_USB0" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_USB1" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DQ_WIDTH" value="32"/> 
+        <user_parameter name="CONFIG.PCW_DQS_WIDTH" value="4"/> 
+        <user_parameter name="CONFIG.PCW_DM_WIDTH" value="4"/> 
+        <user_parameter name="CONFIG.PCW_MIO_PRIMITIVE" value="54"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLK0_PORT" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLK1_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLK2_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLK3_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_RST0_PORT" value="1"/> 
+        <user_parameter name="CONFIG.PCW_EN_RST1_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_RST2_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_RST3_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLKTRIG0_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLKTRIG1_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLKTRIG2_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_EN_CLKTRIG3_PORT" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC_ABORT_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC2_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC3_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC4_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC5_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC6_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_DMAC7_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SMC_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_QSPI_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_CTI_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_GPIO_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_USB0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_ENET0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SDIO0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_I2C0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SPI0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_UART0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_CAN0_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_USB1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_ENET1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SDIO1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_I2C1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_SPI1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_UART1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_P2F_CAN1_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_IRQ_F2P_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/> 
+        <user_parameter name="CONFIG.PCW_CORE0_FIQ_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CORE0_IRQ_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CORE1_FIQ_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_CORE1_IRQ_INTR" value="0"/> 
+        <user_parameter name="CONFIG.PCW_VALUE_SILVERSION" value="3"/> 
+        <user_parameter name="CONFIG.PCW_IMPORT_BOARD_PRESET" value="None"/> 
+        <user_parameter name="CONFIG.PCW_PERIPHERAL_BOARD_PRESET" value="None"/> 
+        <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41J256M16 RE-125"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PORT0_HPR_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PORT1_HPR_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PORT2_HPR_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PORT3_HPR_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/> 
+        <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/> 
+        <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/> 
+        <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/> 
+        <user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE" value="0"/>  
+        <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/> 
+        <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_GRP_MDIO_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD1_GRP_CD_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD1_GRP_WP_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SD1_GRP_POW_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/> 
+        <user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_GRP_SS0_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_GRP_SS1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI0_GRP_SS2_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_GRP_SS0_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_SPI1_GRP_SS1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/> 
+        <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/> 
+        <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/> 
+        <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/> 
+        <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/> 
+        <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/> 
+        <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC" value="External"/> 
+        <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC" value="External"/> 
+        <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_CLKSRC" value="CPU_1X"/> 
+        <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/> 
+        <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/> 
+        <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/> 
+        <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/> 
+        <user_parameter name="CONFIG.PCW_I2C_RESET_POLARITY" value="Active Low"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_GENERATE_SUMMARY" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/> 
+        <user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/> 
+        <user_parameter name="CONFIG.PCW_PS7_SI_REV" value="PRODUCTION"/> 
+        <user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_TR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_PC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_CEOE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_WE_TIME" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_TR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_PC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_CEOE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_WE_TIME" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_TR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_PC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_CEOE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS0_WE_TIME" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_TR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_PC" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_CEOE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NOR_CS1_WE_TIME" value="0"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_AR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_CLR" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WP" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_REA" value="1"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RC" value="11"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T0" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T1" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T2" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T3" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T4" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T5" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_SMC_CYCLE_T6" value="NA"/> 
+        <user_parameter name="CONFIG.PCW_PACKAGE_NAME" value="clg400"/> 
+        <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="dip_switches_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_dp0_dp13_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+
+
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/board.xml
new file mode 100644
index 0000000..8fedc5f
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/board.xml
@@ -0,0 +1,1259 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="arty" display_name="Arty" url="https://reference.digilentinc.com/reference/programmable-logic/arty/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">C.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Arty</description>
+<components>
+  <component name="part0" display_name="Arty" type="fpga" part_name="xc7a35ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+		<description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+        <description>4-position user DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+	  <description>Secondary interface to communicate with ethernet phy. </description>
+        <port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">
+        <description>Primary interface to communicate with ethernet phy in MII mode. </description>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_txd_1"/> 
+              <pin_map port_index="2" component_pin="eth_txd_2"/> 
+              <pin_map port_index="3" component_pin="eth_txd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rxd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rxd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rxd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_dv"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS" physical_port="eth_crs" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_crs"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="COL" physical_port="eth_col" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_col"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rstn"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+        <description>Shield I2C</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">
+        <description>I2C Pullups to enable shield I2C</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_pullup_0"/> 
+              <pin_map port_index="1" component_pin="i2c_pullup_1"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="i2c_pullup" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_pullup_0"/> 
+              <pin_map port_index="1" component_pin="i2c_pullup_1"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="i2c_pullup" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="i2c_pullup_0"/> 
+              <pin_map port_index="1" component_pin="i2c_pullup_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+        <description>4 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<parameters>
+            <parameter name="rst_polarity" value="0"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">
+        <description>4 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 
+              <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 
+              <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 
+              <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 
+              <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+        <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>256 MB DDR3L memory SODIMM </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	 <component_modes>
+        <component_mode name="mii" display_name="MII mode">
+		  <interfaces>
+            <interface name="eth_mii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1" optional="true"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+  <description>Shield i2c</description>
+  </component>
+  <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">
+  <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+  	<description>Push buttons 3 to 0</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+  <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+  	<description>CPU Reset Push Button, active low</description>
+  </component>
+  <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+  	<description>RGB leds 12 to 0 (3 per LED)</description>
+  </component>
+  <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 0 through 19</description>
+  </component>
+  <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+  	<description>Shield pins 26 through 41</description>
+  </component>
+  <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+  	<description>Shield SPI</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  	<description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+  	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+    <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+    <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>
+	<connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_i2c" component1="part0" component2="i2c">
+    <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+  <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">
+    <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+    <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>
+  </connection>
+  <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">
+    <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>
+  </connection>
+  <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+    <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_spi" component1="part0" component2="spi">
+    <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/part0_pins.xml
new file mode 100644
index 0000000..3f6de55
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/part0_pins.xml
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a35tcsg324-1L">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
+  <pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
+  <pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
+  <pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
+  <pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
+  <pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
+  <pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
+  <pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
+  <pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
+  <pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
+  <pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="96" name ="JA1" iostandard="LVCMOS33"   loc="G13"/>
+  <pin index="97" name ="JA2" iostandard="LVCMOS33"   loc="B11"/>
+  <pin index="98" name ="JA3" iostandard="LVCMOS33"   loc="A11"/>
+  <pin index="99" name ="JA4" iostandard="LVCMOS33"   loc="D12"/>
+  <pin index="100" name ="JA7" iostandard="LVCMOS33"  loc="D13"/>
+  <pin index="101" name ="JA8" iostandard="LVCMOS33"  loc="B18"/>
+  <pin index="102" name ="JA9" iostandard="LVCMOS33"  loc="A18"/>
+  <pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="104" name ="JB1" iostandard="LVCMOS33"  loc="E15"/>
+  <pin index="105" name ="JB2" iostandard="LVCMOS33"  loc="E16"/>
+  <pin index="106" name ="JB3" iostandard="LVCMOS33"  loc="D15"/>
+  <pin index="107" name ="JB4" iostandard="LVCMOS33"  loc="C15"/>
+  <pin index="108" name ="JB7" iostandard="LVCMOS33"  loc="J17"/>
+  <pin index="109" name ="JB8" iostandard="LVCMOS33"  loc="J18"/>
+  <pin index="110" name ="JB9" iostandard="LVCMOS33"  loc="K15"/>
+  <pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="112" name ="JC1"  iostandard="LVCMOS33" loc="U12"/>
+  <pin index="113" name ="JC2" iostandard="LVCMOS33"  loc="V12"/>
+  <pin index="114" name ="JC3" iostandard="LVCMOS33"  loc="V10"/>
+  <pin index="115" name ="JC4" iostandard="LVCMOS33"  loc="V11"/>
+  <pin index="116" name ="JC7" iostandard="LVCMOS33"  loc="U14"/>
+  <pin index="117" name ="JC8" iostandard="LVCMOS33"  loc="V14"/>
+  <pin index="118" name ="JC9" iostandard="LVCMOS33"  loc="T13"/>
+  <pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="120" name ="JD1" iostandard="LVCMOS33"  loc="D4"/>
+  <pin index="121" name ="JD2" iostandard="LVCMOS33"  loc="D3"/>
+  <pin index="122" name ="JD3" iostandard="LVCMOS33"  loc="F4"/>
+  <pin index="123" name ="JD4" iostandard="LVCMOS33"  loc="F3"/>
+  <pin index="124" name ="JD7" iostandard="LVCMOS33"  loc="E2"/>
+  <pin index="125" name ="JD8" iostandard="LVCMOS33"  loc="D2"/>
+  <pin index="126" name ="JD9" iostandard="LVCMOS33"  loc="H2"/>
+  <pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/preset.xml
new file mode 100644
index 0000000..c53ad75
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty/C.0/preset.xml
@@ -0,0 +1,414 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_12bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="12"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="mii_preset">
+	  <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.PHY_TYPE" value="MII"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.Physical_Interface" value="MII"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="shield_dp0_dp19_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="uart_preset">
+   <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 		  
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/board.xml
new file mode 100644
index 0000000..f37c4b9
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/board.xml
@@ -0,0 +1,827 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="basys3" display_name="Basys3" url="https://digilent.com/reference/programmable-logic/basys-3/start" preset_file="preset.xml">
+<compatible_board_revisions>
+  <revision id="0">C.0</revision>
+</compatible_board_revisions>
+<file_version>1.2</file_version>
+<description>Basys3</description>
+<components>
+  <component name="part0" display_name="Basys3" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/basys-3/start">
+    <interfaces>
+      <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="led_16bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="1" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="seven_seg_led_an_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_disp" preset_proc="seven_seg_led_seg_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_disp_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_disp_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_disp_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_disp_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="seven_seg_led_disp_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="seven_seg_led_disp_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="seven_seg_led_disp_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="seven_seg_led_disp_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>Switches 15 to 0</description>
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 15 to 0</description>
+  </component>
+  <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push buttons 3 to 0 [Down Right Left Up]</description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset Signal (BTNC)" type="chip" sub_type="reset" major_group="Reset">
+	<description>Reset button (BTNC)</description>
+  </component>
+  <component name="seven_seg_led_an" display_name="7 Segment Display - Anodes" type="chip" sub_type="led" major_group="GPIO">
+	<description>Seven Segment Anodes</description>
+  </component>
+  <component name="seven_seg_led_disp" display_name="7 Segment Display - Segments" type="chip" sub_type="led" major_group="GPIO">
+	<description>Seven Segment display segments</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+	<description>100 MHz System Clock</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB UART</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="1" c1_end_index="16" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="17" c1_end_index="32" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="33" c1_end_index="36" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="37" c1_end_index="41" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="42" c1_end_index="42" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+    <connection_map name="part0_seven_seg_led_an_1" c1_st_index="43" c1_end_index="46" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_seven_seg_led_disp" component1="part0" component2="seven_seg_led_disp">
+    <connection_map name="part0_seven_seg_led_disp_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="55" c1_end_index="56" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="57" c1_end_index="64" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="65" c1_end_index="72" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="73" c1_end_index="80" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="81" c1_end_index="88" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/part0_pins.xml
new file mode 100644
index 0000000..bbf7cb0
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/part0_pins.xml
@@ -0,0 +1,117 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a35tcpg236-1">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="W5"/>
+  <pin index="1" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="2" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="3" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="4" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="W17"/>
+  <pin index="5" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="6" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="7" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="8" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="9" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS33" loc="V2"/>
+  <pin index="10" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS33" loc="T3"/>
+  <pin index="11" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="T2"/>
+  <pin index="12" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="R3"/>
+  <pin index="13" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="W2"/>
+  <pin index="14" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U1"/>
+  <pin index="15" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="T1"/>
+  <pin index="16" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="R2"/>
+  <pin index="17" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="18" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="E19"/>
+  <pin index="19" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="U19"/>
+  <pin index="20" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="V19"/>
+  <pin index="21" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="22" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="U15"/>
+  <pin index="23" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="24" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="25" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="26" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="V3"/>
+  <pin index="27" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="W3"/>
+  <pin index="28" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="U3"/>
+  <pin index="29" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="P3"/>
+  <pin index="30" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="N3"/>
+  <pin index="31" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="P1"/>
+  <pin index="32" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="L1"/>
+  <pin index="33" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="34" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="35" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="T17"/>
+  <pin index="36" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="37" name ="qspi_csn_i" iostandard="LVCMOS33" loc="K19"/>
+  <pin index="38" name ="qspi_db0_i" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="39" name ="qspi_db1_i" iostandard="LVCMOS33" loc="D19"/>
+  <pin index="40" name ="qspi_db2_i" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="41" name ="qspi_db3_i" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="42" name ="reset" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="43" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="U2"/>
+  <pin index="44" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="U4"/>
+  <pin index="45" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="V4"/>
+  <pin index="46" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="W4"/>
+  <pin index="47" name ="seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="W7"/>
+  <pin index="48" name ="seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="W6"/>
+  <pin index="49" name ="seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="U8"/>
+  <pin index="50" name ="seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="V8"/>
+  <pin index="51" name ="seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="U5"/>
+  <pin index="52" name ="seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="V5"/>
+  <pin index="53" name ="seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="U7"/>
+  <pin index="54" name ="seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="V7"/>
+  <pin index="55" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="56" name ="usb_uart_txd" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="57" name ="JA1" iostandard="LVCMOS33"  loc="J1"/>
+  <pin index="58" name ="JA2" iostandard="LVCMOS33"  loc="L2"/>
+  <pin index="59" name ="JA3" iostandard="LVCMOS33"  loc="J2"/>
+  <pin index="60" name ="JA4" iostandard="LVCMOS33"  loc="G2"/>
+  <pin index="61" name ="JA7" iostandard="LVCMOS33"  loc="H1"/>
+  <pin index="62" name ="JA8" iostandard="LVCMOS33"  loc="K2"/>
+  <pin index="63" name ="JA9" iostandard="LVCMOS33"  loc="H2"/>
+  <pin index="64" name ="JA10" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="65" name ="JB1" iostandard="LVCMOS33"  loc="A14"/>
+  <pin index="66" name ="JB2" iostandard="LVCMOS33"  loc="A16"/>
+  <pin index="67" name ="JB3" iostandard="LVCMOS33"  loc="B15"/>
+  <pin index="68" name ="JB4" iostandard="LVCMOS33"  loc="B16"/>
+  <pin index="69" name ="JB7" iostandard="LVCMOS33"  loc="A15"/>
+  <pin index="70" name ="JB8" iostandard="LVCMOS33"  loc="A17"/>
+  <pin index="71" name ="JB9" iostandard="LVCMOS33"  loc="C15"/>
+  <pin index="72" name ="JB10" iostandard="LVCMOS33" loc="C16"/>
+  <pin index="73" name ="JC1"  iostandard="LVCMOS33" loc="K17"/>
+  <pin index="74" name ="JC2" iostandard="LVCMOS33"  loc="M18"/>
+  <pin index="75" name ="JC3" iostandard="LVCMOS33"  loc="N17"/>
+  <pin index="76" name ="JC4" iostandard="LVCMOS33"  loc="P18"/>
+  <pin index="77" name ="JC7" iostandard="LVCMOS33"  loc="L17"/>
+  <pin index="78" name ="JC8" iostandard="LVCMOS33"  loc="M19"/>
+  <pin index="79" name ="JC9" iostandard="LVCMOS33"  loc="P17"/>
+  <pin index="80" name ="JC10" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="81" name ="JXADC1" iostandard="LVCMOS33"  loc="J3"/>
+  <pin index="82" name ="JXADC2" iostandard="LVCMOS33"  loc="L3"/>
+  <pin index="83" name ="JXADC3" iostandard="LVCMOS33"  loc="M2"/>
+  <pin index="84" name ="JXADC4" iostandard="LVCMOS33"  loc="N2"/>
+  <pin index="85" name ="JXADC7" iostandard="LVCMOS33"  loc="K3"/>
+  <pin index="86" name ="JXADC8" iostandard="LVCMOS33"  loc="M3"/>
+  <pin index="87" name ="JXADC9" iostandard="LVCMOS33"  loc="M1"/>
+  <pin index="88" name ="JXADC10" iostandard="LVCMOS33" loc="N1"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/preset.xml
new file mode 100644
index 0000000..5e2b014
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/basys3/C.0/preset.xml
@@ -0,0 +1,338 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="mii_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.PHY_TYPE" value="MII"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.Physical_Interface" value="MII"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="seven_seg_led_an_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="seven_seg_led_seg_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+        <user_parameters>		  
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+		  <user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+      <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+		<user_parameter name="CONFIG.RESET_PORT" value="resetn"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/board.xml
new file mode 100644
index 0000000..369bdc7
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/board.xml
@@ -0,0 +1,416 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="cmod-s7-25" display_name="Cmod S7-25" url="https://digilent.com/reference/programmable-logic/cmod-s7/start" preset_file="preset.xml">
+    <compatible_board_revisions>
+      <revision id="0">B.0</revision>
+    </compatible_board_revisions>
+    <file_version>1.0</file_version>
+    <description>Cmod S7-25</description>
+    <components>
+        <component name="part0" display_name="Cmod S7-25" type="fpga" part_name="xc7s25csga225-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-s7/start">
+            <interfaces>
+                <interface mode="slave"  name="sys_clock"          type="xilinx.com:signal:clock_rtl:1.0"        of_component="sys_clock"          preset_proc="sys_clock_preset">
+                    <description>12 MHz Single-Ended System Clock</description>
+                    <port_maps>
+                        <port_map logical_port="CLK" physical_port="clk" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="clk"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                    <parameters>
+                        <parameter name="frequency" value="12000000"/>
+                    </parameters>
+                </interface>
+                <interface mode="slave"  name="reset"              type="xilinx.com:signal:reset_rtl:1.0"        of_component="reset">
+                    <description>BTN0 used as Active High System Reset</description>
+                    <port_maps>
+                        <port_map logical_port="RST" physical_port="reset_btn0" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                    <parameters>
+                        <parameter name="rst_polarity" value="1"/>
+                    </parameters>
+                </interface>
+                <interface mode="master" name="led_4bits"          type="xilinx.com:interface:gpio_rtl:1.0"      of_component="led_4bits"          preset_proc="output_4bits_preset">
+                    <description>4 LEDs</description>
+                    <port_maps>
+                        <port_map logical_port="TRI_O" physical_port="led_4bits_tri_io" dir="out" left="3" right="0">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="led_4bits_tri_io_0"/>
+                                <pin_map port_index="1" component_pin="led_4bits_tri_io_1"/>
+                                <pin_map port_index="2" component_pin="led_4bits_tri_io_2"/>
+                                <pin_map port_index="3" component_pin="led_4bits_tri_io_3"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                </interface>
+                <interface mode="master" name="rgb_led_3bits"      type="xilinx.com:interface:gpio_rtl:1.0"      of_component="rgb_led_3bits"      preset_proc="rgb_led_3bits_preset">
+                    <description>RGB LED</description>
+                    <port_maps>
+                        <port_map logical_port="TRI_O" physical_port="rgb_led_3bits_tri_io" dir="out" left="2" right="0">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="rgb_led_3bits_tri_io_0"/>
+                                <pin_map port_index="1" component_pin="rgb_led_3bits_tri_io_1"/>
+                                <pin_map port_index="2" component_pin="rgb_led_3bits_tri_io_2"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                </interface>
+                <interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0"      of_component="push_buttons_2bits" preset_proc="input_2bits_preset">
+                    <description>2 Push Buttons</description>
+                    <port_maps>
+                        <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
+                                <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                </interface>
+                <interface mode="master" name="push_buttons_1bit"  type="xilinx.com:interface:gpio_rtl:1.0"      of_component="push_buttons_2bits" preset_proc="input_1bit_preset">
+                    <description>Only BTN1</description>
+                    <port_maps>
+                        <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                </interface>
+                <!-- Add "pio_32bits" ? -->
+                <interface mode="master" name="usb_uart"           type="xilinx.com:interface:uart_rtl:1.0"      of_component="usb_uart"           preset_proc="usb_uart_preset">
+                    <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+                    <port_maps>
+                        <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="usb_uart_txd"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                </interface>
+                <interface mode="master" name="qspi_flash"         type="xilinx.com:interface:spi_rtl:1.0"       of_component="qspi_flash"         preset_proc="qspi_flash_preset">
+                    <description>Quad SPI Flash</description>
+                    <preferred_ips>
+                        <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+                    </preferred_ips>
+                    <port_maps>
+                        <port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db0"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db0"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db0"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db1"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db1"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db1"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db2"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db2"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db2"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db3"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db3"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_db3"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="SS_I"  physical_port="qspi_csn" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_csn"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="SS_O"  physical_port="qspi_csn" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_csn"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="SS_T"  physical_port="qspi_csn" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_csn"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="SCK_I"  physical_port="qspi_sck" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_sck"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="SCK_O"  physical_port="qspi_sck" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_sck"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="SCK_T"  physical_port="qspi_sck" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="qspi_sck"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                </interface>
+                <interface mode="master" name="ja"                 type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+                    <description>Pmod Connector JA</description>
+                    <port_maps>
+                        <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA1"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA1"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA1"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA2"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA2"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA2"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA3"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA3"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA3"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA4"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA4"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA4"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA7"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA7"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA7"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA8"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA8"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA8"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA9"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA9"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA9"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA10"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA10"/>
+                            </pin_maps>
+                        </port_map>
+                        <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+                            <pin_maps>
+                                <pin_map port_index="0" component_pin="JA10"/>
+                            </pin_maps>
+                        </port_map>
+                    </port_maps>
+                </interface>
+            </interfaces>
+        </component>
+        <component name="sys_clock"          display_name="System Clock" type="chip" sub_type="system_clock"      major_group="Clocks">
+            <description>12 MHz System Clock</description>
+        </component>
+        <component name="reset"              display_name="Reset (BTN0)" type="chip" sub_type="reset"             major_group="Reset">
+            <description>Configure BTN0 as System Reset button, active high</description>
+        </component>
+        <component name="led_4bits"          display_name="4 LEDs"       type="chip" sub_type="led"               major_group="GPIO">
+            <description>LEDs 3 to 0</description>
+        </component>
+        <component name="rgb_led_3bits"      display_name="RGB LED"      type="chip" sub_type="led"               major_group="GPIO">
+            <description>RGB LED 2 downto 0 (ordered RGB)</description>
+        </component>
+				
+        <component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button"       major_group="GPIO">
+            <description>Push Buttons 1 to 0</description>
+            <component_modes>
+                <component_mode name="2_btns" display_name="2 Buttons (No Reset)">
+                    <interfaces>
+                        <interface name="push_buttons_2bits" order="0"/>
+                    </interfaces>
+                </component_mode>
+                <component_mode name="1_btn" display_name="Only BTN1">
+                    <interfaces>
+                        <interface name="push_buttons_1bit" order="0"/>
+                    </interfaces>
+                </component_mode>
+            </component_modes>
+        </component>
+        <component name="usb_uart"           display_name="USB UART"     type="chip" sub_type="uart"              major_group="UART">
+            <description>USB UART</description>
+        </component>
+        <component name="qspi_flash"         display_name="QSPI Flash"   type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+            <description>QSPI Flash</description>
+        </component>
+        <component name="ja"                 display_name="Connector JA" type="chip" sub_type="chip"              major_group="Pmod">
+            <description>Pmod Connector JA</description>
+        </component>
+    </components>
+    <jtag_chains>
+        <jtag_chain name="chain1">
+            <position name="0" component="part0"/>
+        </jtag_chain>
+    </jtag_chains>
+    <connections>
+        <connection name="part0_sys_clock"                    component1="part0" component2="sys_clock">
+            <connection_map name="part0_sys_clock_1"          c1_st_index="0"    c1_end_index="0"       c2_st_index="0" c2_end_index="0"/>
+        </connection>
+        <connection name="part0_reset"                        component1="part0" component2="reset">
+            <connection_map name="part0_reset_1"              c1_st_index="8"    c1_end_index="8"       c2_st_index="0" c2_end_index="0"/>
+        </connection>
+        <connection name="part0_led_4bits"                    component1="part0" component2="led_4bits">
+            <connection_map name="part0_led_4bits_1"          c1_st_index="1"    c1_end_index="4"       c2_st_index="0" c2_end_index="3"/>
+        </connection>
+        <connection name="part0_rgb_led_3bits"                component1="part0" component2="rgb_led_3bits">
+            <connection_map name="part0_rgb_led_3bits_1"      c1_st_index="5"    c1_end_index="7"       c2_st_index="0" c2_end_index="2"/>
+        </connection>
+        <connection name="part0_push_buttons_2bits"           component1="part0" component2="push_buttons_2bits">
+            <connection_map name="part0_push_buttons_2bits_1" c1_st_index="8"    c1_end_index="9"       c2_st_index="0" c2_end_index="1"/>
+        </connection>
+        <connection name="part0_usb_uart"                     component1="part0" component2="usb_uart">
+            <connection_map name="part0_usb_uart_1"           c1_st_index="10"   c1_end_index="11"      c2_st_index="0" c2_end_index="1"/>
+        </connection>
+        <connection name="part0_qspi_flash"                   component1="part0" component2="qspi_flash">
+            <connection_map name="part0_qspi_flash_1"         c1_st_index="12"   c1_end_index="17"      c2_st_index="0" c2_end_index="5"/>
+        </connection>
+        <connection name="part0_ja"                           component1="part0" component2="ja">
+            <connection_map name="part0_ja_1"                 c1_st_index="18"   c1_end_index="25"      c2_st_index="0" c2_end_index="7"/>
+        </connection>
+        </connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/part0_pins.xml
new file mode 100644
index 0000000..168ea6f
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/part0_pins.xml
@@ -0,0 +1,60 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7s25csga225-1">
+    <pins>
+        <pin index="0"  name="clk"                        iostandard="LVCMOS33" loc="M9"/> <!-- Schematic Name: GCLK -->
+
+        <pin index="1"  name="led_4bits_tri_io_0"         iostandard="LVCMOS33" loc="E2"/> <!-- Schematic Name: LED1 -->
+        <pin index="2"  name="led_4bits_tri_io_1"         iostandard="LVCMOS33" loc="K1"/> <!-- Schematic Name: LED2 -->
+        <pin index="3"  name="led_4bits_tri_io_2"         iostandard="LVCMOS33" loc="J1"/> <!-- Schematic Name: LED3 -->
+        <pin index="4"  name="led_4bits_tri_io_3"         iostandard="LVCMOS33" loc="E1"/> <!-- Schematic Name: LED4 -->
+
+        <pin index="5"  name="rgb_led_3bits_tri_io_0"     iostandard="LVCMOS33" loc="F1"/> <!-- Schematic Name: LED0_B -->
+        <pin index="6"  name="rgb_led_3bits_tri_io_1"     iostandard="LVCMOS33" loc="D3"/> <!-- Schematic Name: LED0_G -->
+        <pin index="7"  name="rgb_led_3bits_tri_io_2"     iostandard="LVCMOS33" loc="F2"/> <!-- Schematic Name: LED0_R -->
+
+        <pin index="8"  name="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="D2"/> <!-- Schematic Name: BTN0 -->
+        <pin index="9"  name="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="D1"/> <!-- Schematic Name: BTN1 -->
+
+        <pin index="10" name="usb_uart_txd"               iostandard="LVCMOS33" loc="L12"/> <!-- Schematic Name: UART_RXD_OUT -->
+        <pin index="11" name="usb_uart_rxd"               iostandard="LVCMOS33" loc="K15"/> <!-- Schematic Name: UART_TXD_IN -->
+
+        <pin index="12" name="qspi_db0"                   iostandard="LVCMOS33" loc="H14"/> <!-- Schematic Name: QSPI_DQ0 -->
+        <pin index="13" name="qspi_db1"                   iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: QSPI_DQ1 -->
+        <pin index="14" name="qspi_db2"                   iostandard="LVCMOS33" loc="J12"/> <!-- Schematic Name: QSPI_DQ2 -->
+        <pin index="15" name="qspi_db3"                   iostandard="LVCMOS33" loc="K13"/> <!-- Schematic Name: QSPI_DQ3 -->
+        <pin index="16" name="qspi_csn"                   iostandard="LVCMOS33" loc="L11"/> <!-- Schematic Name: QSPI_CS -->
+        <pin index="17" name="qspi_sck"                   iostandard="LVCMOS33" loc="K12"/> <!-- Schematic Name: QSPI_CS -->
+                            
+        <pin index="18" name="JA1"                        iostandard="LVCMOS33" loc="J2"/> <!-- Schematic Name: JA1 -->
+        <pin index="19" name="JA2"                        iostandard="LVCMOS33" loc="H2"/> <!-- Schematic Name: JA2 -->
+        <pin index="20" name="JA3"                        iostandard="LVCMOS33" loc="H4"/> <!-- Schematic Name: JA3 -->
+        <pin index="21" name="JA4"                        iostandard="LVCMOS33" loc="F3"/> <!-- Schematic Name: JA4 -->
+        <pin index="22" name="JA7"                        iostandard="LVCMOS33" loc="H3"/> <!-- Schematic Name: JA7 -->
+        <pin index="23" name="JA8"                        iostandard="LVCMOS33" loc="H1"/> <!-- Schematic Name: JA8 -->
+        <pin index="24" name="JA9"                        iostandard="LVCMOS33" loc="G1"/> <!-- Schematic Name: JA9 -->
+        <pin index="25" name="JA10"                       iostandard="LVCMOS33" loc="F4"/> <!-- Schematic Name: JA10 -->
+    </pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/preset.xml
new file mode 100644
index 0000000..a0b6b52
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod-s7-25/B.0/preset.xml
@@ -0,0 +1,326 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+    <ip_preset preset_proc_name="sys_clock_preset">
+        <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+            <user_parameters>
+                <user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/> 
+                <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+                <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
+                <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+            </user_parameters>
+        </ip>
+    </ip_preset>
+    <ip_preset preset_proc_name="output_4bits_preset">
+        <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+                <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+                <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+                <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+                <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+                <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+            </user_parameters>
+        </ip>
+    </ip_preset>
+    <ip_preset preset_proc_name="rgb_led_3bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+                <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI1_SIZE" value="3"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI2_SIZE" value="3"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI3_SIZE" value="3"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI4_SIZE" value="3"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+                <user_parameter name="CONFIG.GPI1_SIZE" value="3"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+                <user_parameter name="CONFIG.GPI2_SIZE" value="3"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+                <user_parameter name="CONFIG.GPI1_SIZE" value="3"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+                <user_parameter name="CONFIG.GPI2_SIZE" value="3"/> 
+            </user_parameters>
+        </ip>
+    </ip_preset>
+    <ip_preset preset_proc_name="input_1bit_preset">
+        <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+                <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+                <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+                <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+                <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+                <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+                <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+                <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+                <user_parameter name="CONFIG.GPI3_SIZE" value="1"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+                <user_parameter name="CONFIG.GPI4_SIZE" value="1"/> 
+            </user_parameters>
+        </ip>
+    </ip_preset>
+    <ip_preset preset_proc_name="input_2bits_preset">
+        <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+                <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+                <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+                <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+                <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+                <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+                <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+                <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+                <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+                <user_parameter name="CONFIG.GPI3_SIZE" value="2"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+                <user_parameter name="CONFIG.GPI4_SIZE" value="2"/> 
+            </user_parameters>
+        </ip>
+    </ip_preset>
+    <ip_preset preset_proc_name="usb_uart_preset">
+        <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+                <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+            </user_parameters>
+        </ip>
+        <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+            <user_parameters>
+                <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+                <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+            </user_parameters>
+        </ip>
+    </ip_preset>
+    <ip_preset preset_proc_name="qspi_flash_preset">
+        <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+            <user_parameters>
+                <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+                <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+                <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+                <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+                <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+            </user_parameters>
+        </ip>
+    </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/board.xml
new file mode 100644
index 0000000..4243293
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/board.xml
@@ -0,0 +1,478 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-15t" display_name="Cmod A7-15t" url="https://digilent.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">
+<compatible_board_revisions>
+  <revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.2</file_version>
+<description>Cmod A7-15t</description>
+<components>
+  <component name="part0" display_name="Cmod A7-15t" type="fpga" part_name="xc7a15tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-a7/start">
+    <interfaces>
+	<interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">
+        <description>512KB SRAM</description>
+		<port_maps>
+          <port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="18" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_addr_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_addr_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_addr_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_addr_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_addr_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_addr_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_addr_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_addr_7"/> 
+              <pin_map port_index="8" component_pin="cellular_ram_addr_8"/> 
+              <pin_map port_index="9" component_pin="cellular_ram_addr_9"/> 
+              <pin_map port_index="10" component_pin="cellular_ram_addr_10"/> 
+              <pin_map port_index="11" component_pin="cellular_ram_addr_11"/> 
+              <pin_map port_index="12" component_pin="cellular_ram_addr_12"/> 
+              <pin_map port_index="13" component_pin="cellular_ram_addr_13"/> 
+              <pin_map port_index="14" component_pin="cellular_ram_addr_14"/> 
+              <pin_map port_index="15" component_pin="cellular_ram_addr_15"/> 
+              <pin_map port_index="16" component_pin="cellular_ram_addr_16"/> 
+              <pin_map port_index="17" component_pin="cellular_ram_addr_17"/> 
+              <pin_map port_index="18" component_pin="cellular_ram_addr_18"/>
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_oen"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_wen"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_ce_n"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_2bits" preset_proc="led_2bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_2bits_tri_o" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_3bits_preset">
+        <description>RGB LED</description>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+			  <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_2bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Use BTN0 as System Reset, active high</description>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset_btn0" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="1" />
+       </parameters>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <description>12 MHz Single-Ended System Clock</description>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="12000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	</interfaces>
+  </component>
+  <component name="cellular_ram" display_name="Cell RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">
+	<description>512KB SRAM</description>
+  </component>
+  <component name="led_2bits" display_name="2 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 1 to 0</description>
+  </component>
+  <component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
+	<description>RGB led 2 downto 0 [R G B]</description>
+  </component>
+  <component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push buttons 1 to 0</description>
+	<component_modes>
+        <component_mode name="2_btns" display_name="2 Buttons (No Reset)">
+		  <interfaces>
+            <interface name="push_buttons_2bits" order="0"/>
+          </interfaces>
+		</component_mode>
+		<component_mode name="1_btn" display_name="Just use BTN1">
+		  <interfaces>
+            <interface name="push_buttons_1bit" order="0"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
+	<description>Configure BTN0 as System Reset button, active high</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+	<description>12 MHz System Clock</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB UART</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">
+    <connection_map name="part0_cellular_ram_1" c1_st_index="1" c1_end_index="30" c2_st_index="0" c2_end_index="29"/>
+  </connection>
+  <connection name="part0_led_2bits" component1="part0" component2="led_2bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="35" c2_st_index="0" c2_end_index="2"/>
+  </connection>
+  <connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
+    <connection_map name="part0_push_buttons_2bits_1" c1_st_index="41" c1_end_index="42" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="36" c1_end_index="40" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="45" c1_end_index="52" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/part0_pins.xml
new file mode 100644
index 0000000..4c19b85
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/part0_pins.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a15tcpg236-1">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="L17"/>
+  <pin index="1" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="2" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="M19"/>
+  <pin index="3" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="4" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="5" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="6" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="7" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="8" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="9" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="U19"/>
+  <pin index="10" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="V19"/>
+  <pin index="11" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="12" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="T17"/>
+  <pin index="13" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="14" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="15" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="16" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="17" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="18" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="W17"/>
+  <pin index="19" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="20" name ="cellular_ram_dq_0" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="21" name ="cellular_ram_dq_1" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="22" name ="cellular_ram_dq_2" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="23" name ="cellular_ram_dq_3" iostandard="LVCMOS33" loc="U15"/>
+  <pin index="24" name ="cellular_ram_dq_4" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="25" name ="cellular_ram_dq_5" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="26" name ="cellular_ram_dq_6" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="27" name ="cellular_ram_dq_7" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="28" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="P19"/>
+  <pin index="29" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R19"/>
+  <pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="N19"/>
+  <pin index="31" name ="led_2bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/>
+  <pin index="32" name ="led_2bits_tri_o_1" iostandard="LVCMOS33" loc="C16"/>
+  <pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="36" name ="qspi_csn" iostandard="LVCMOS33" loc="K19"/>
+  <pin index="37" name ="qspi_db0" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="38" name ="qspi_db1" iostandard="LVCMOS33" loc="D19"/>
+  <pin index="39" name ="qspi_db2" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="40" name ="qspi_db3" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="41" name ="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="42" name ="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="43" name ="usb_uart_txd" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="44" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="45" name ="JA1" iostandard="LVCMOS33"  loc="G17"/>
+  <pin index="46" name ="JA2" iostandard="LVCMOS33"  loc="G19"/>
+  <pin index="47" name ="JA3" iostandard="LVCMOS33"  loc="N18"/>
+  <pin index="48" name ="JA4" iostandard="LVCMOS33"  loc="L18"/>
+  <pin index="49" name ="JA7" iostandard="LVCMOS33"  loc="H17"/>
+  <pin index="50" name ="JA8" iostandard="LVCMOS33"  loc="H19"/>
+  <pin index="51" name ="JA9" iostandard="LVCMOS33"  loc="J19"/>
+  <pin index="52" name ="JA10" iostandard="LVCMOS33" loc="K18"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/preset.xml
new file mode 100644
index 0000000..6c63460
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/preset.xml
@@ -0,0 +1,301 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="sram_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_emc">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_MAX_MEM_WIDTH" value="8"/>
+			<user_parameter name="CONFIG.C_MEM0_TYPE" value="1"/>
+			<user_parameter name="CONFIG.C_MEM0_WIDTH" value="8"/>
+			<user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_TLZWE_PS_MEM_0" value="3000"/>
+			<user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="8000"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+	<ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_3bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="push_buttons_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+      <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/board.xml
new file mode 100644
index 0000000..942f1b7
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/board.xml
@@ -0,0 +1,478 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-35t" display_name="Cmod A7-35t" url="https://digilent.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">
+<compatible_board_revisions>
+  <revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.2</file_version>
+<description>Cmod A7-35t</description>
+<components>
+  <component name="part0" display_name="Cmod A7-35t" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-a7/start">
+    <interfaces>
+	<interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">
+        <description>512KB SRAM</description>
+		<port_maps>
+          <port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="18" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_addr_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_addr_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_addr_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_addr_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_addr_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_addr_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_addr_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_addr_7"/> 
+              <pin_map port_index="8" component_pin="cellular_ram_addr_8"/> 
+              <pin_map port_index="9" component_pin="cellular_ram_addr_9"/> 
+              <pin_map port_index="10" component_pin="cellular_ram_addr_10"/> 
+              <pin_map port_index="11" component_pin="cellular_ram_addr_11"/> 
+              <pin_map port_index="12" component_pin="cellular_ram_addr_12"/> 
+              <pin_map port_index="13" component_pin="cellular_ram_addr_13"/> 
+              <pin_map port_index="14" component_pin="cellular_ram_addr_14"/> 
+              <pin_map port_index="15" component_pin="cellular_ram_addr_15"/> 
+              <pin_map port_index="16" component_pin="cellular_ram_addr_16"/> 
+              <pin_map port_index="17" component_pin="cellular_ram_addr_17"/> 
+              <pin_map port_index="18" component_pin="cellular_ram_addr_18"/>
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_oen"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_wen"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_ce_n"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_2bits" preset_proc="led_2bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_2bits_tri_o" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_3bits_preset">
+        <description>RGB LED</description>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+			  <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_2bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Use BTN0 as System Reset, active high</description>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset_btn0" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="1" />
+       </parameters>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <description>12 MHz Single-Ended System Clock</description>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="12000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	</interfaces>
+  </component>
+  <component name="cellular_ram" display_name="Cell RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">
+	<description>512KB SRAM</description>
+  </component>
+  <component name="led_2bits" display_name="2 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 1 to 0</description>
+  </component>
+  <component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
+	<description>RGB led 2 downto 0 [R G B]</description>
+  </component>
+  <component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push buttons 1 to 0</description>
+	<component_modes>
+        <component_mode name="2_btns" display_name="2 Buttons (No Reset)">
+		  <interfaces>
+            <interface name="push_buttons_2bits" order="0"/>
+          </interfaces>
+		</component_mode>
+		<component_mode name="1_btn" display_name="Just use BTN1">
+		  <interfaces>
+            <interface name="push_buttons_1bit" order="0"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
+	<description>Configure BTN0 as System Reset button, active high</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+	<description>12 MHz System Clock</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB UART</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">
+    <connection_map name="part0_cellular_ram_1" c1_st_index="1" c1_end_index="30" c2_st_index="0" c2_end_index="29"/>
+  </connection>
+  <connection name="part0_led_2bits" component1="part0" component2="led_2bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="35" c2_st_index="0" c2_end_index="2"/>
+  </connection>
+  <connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
+    <connection_map name="part0_push_buttons_2bits_1" c1_st_index="41" c1_end_index="42" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="36" c1_end_index="40" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="45" c1_end_index="52" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/part0_pins.xml
new file mode 100644
index 0000000..ee7bbe0
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/part0_pins.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a35tcpg236-1">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="L17"/>
+  <pin index="1" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="2" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="M19"/>
+  <pin index="3" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="4" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="5" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="6" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="7" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="8" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="9" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="U19"/>
+  <pin index="10" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="V19"/>
+  <pin index="11" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="12" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="T17"/>
+  <pin index="13" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="14" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="15" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="16" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="17" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="18" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="W17"/>
+  <pin index="19" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="20" name ="cellular_ram_dq_0" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="21" name ="cellular_ram_dq_1" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="22" name ="cellular_ram_dq_2" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="23" name ="cellular_ram_dq_3" iostandard="LVCMOS33" loc="U15"/>
+  <pin index="24" name ="cellular_ram_dq_4" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="25" name ="cellular_ram_dq_5" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="26" name ="cellular_ram_dq_6" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="27" name ="cellular_ram_dq_7" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="28" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="P19"/>
+  <pin index="29" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R19"/>
+  <pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="N19"/>
+  <pin index="31" name ="led_2bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/>
+  <pin index="32" name ="led_2bits_tri_o_1" iostandard="LVCMOS33" loc="C16"/>
+  <pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="36" name ="qspi_csn" iostandard="LVCMOS33" loc="K19"/>
+  <pin index="37" name ="qspi_db0" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="38" name ="qspi_db1" iostandard="LVCMOS33" loc="D19"/>
+  <pin index="39" name ="qspi_db2" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="40" name ="qspi_db3" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="41" name ="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="42" name ="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="43" name ="usb_uart_txd" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="44" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="45" name ="JA1" iostandard="LVCMOS33"  loc="G17"/>
+  <pin index="46" name ="JA2" iostandard="LVCMOS33"  loc="G19"/>
+  <pin index="47" name ="JA3" iostandard="LVCMOS33"  loc="N18"/>
+  <pin index="48" name ="JA4" iostandard="LVCMOS33"  loc="L18"/>
+  <pin index="49" name ="JA7" iostandard="LVCMOS33"  loc="H17"/>
+  <pin index="50" name ="JA8" iostandard="LVCMOS33"  loc="H19"/>
+  <pin index="51" name ="JA9" iostandard="LVCMOS33"  loc="J19"/>
+  <pin index="52" name ="JA10" iostandard="LVCMOS33" loc="K18"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/preset.xml
new file mode 100644
index 0000000..947361c
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/preset.xml
@@ -0,0 +1,301 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="sram_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_emc">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_MAX_MEM_WIDTH" value="8"/>
+			<user_parameter name="CONFIG.C_MEM0_TYPE" value="1"/>
+			<user_parameter name="CONFIG.C_MEM0_WIDTH" value="8"/>
+			<user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_TLZWE_PS_MEM_0" value="3000"/>
+			<user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="8000"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+	<ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_3bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="push_buttons_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	      <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+      <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/board.xml
new file mode 100644
index 0000000..cb7a551
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/board.xml
@@ -0,0 +1,691 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-07s" display_name="Cora Z7-07S" url="https://digilent.com/reference/programmable-logic/cora-z7/start" preset_file="preset.xml" >
+	<compatible_board_revisions>
+		<revision id="0">B.0</revision>
+	</compatible_board_revisions>
+	<file_version>1.1</file_version>
+	<description>Cora Z7-07S</description>
+	<components>
+		<component name="part0" display_name="Cora Z7-07S" type="fpga" part_name="xc7z007sclg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/cora-z7/start">
+			<interfaces>
+				<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+				</interface>
+				<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+					<port_maps>
+						<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="sys_clk"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+					<parameters>
+						<parameter name="frequency" value="125000000" />
+					</parameters>
+				</interface>
+				<interface mode="master" name="btns_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_2bits" preset_proc="input_2bits_preset">
+					<description>2 Push Buttons</description>
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_I" physical_port="btns_2bits_tri_i" dir="in" left="1" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="btns_2bits_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="btns_2bits_tri_i_1"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="rgb_leds" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_leds" preset_proc="output_6bits_preset">
+					<description>2 RGB LEDs</description>
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_O" physical_port="rgb_leds_tri_o" dir="out" left="5" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/> 
+								<pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
+								<pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
+								<pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
+								<pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
+								<pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+					<port_maps>
+						<port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+							<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA10"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA10"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA10"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+					<port_maps>
+						<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+							<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB10"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB10"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB10"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="shield_i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="shield_i2c">
+					<description>Shield I2C</description>
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="SDA_I" physical_port="shield_i2c_sda_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_sda_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SDA_O" physical_port="shield_i2c_sda_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_sda_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SDA_T" physical_port="shield_i2c_sda_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_sda_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCL_I" physical_port="shield_i2c_scl_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_scl_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCL_O" physical_port="shield_i2c_scl_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_scl_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCL_T" physical_port="shield_i2c_scl_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_scl_i"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="shield_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="shield_spi" preset_proc="shield_spi_preset">
+					<description>Shield SPI</description>
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="IO0_I" physical_port="shield_spi_mosi_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_mosi_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO0_O" physical_port="shield_spi_mosi_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_mosi_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO0_T" physical_port="shield_spi_mosi_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_mosi_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO1_I" physical_port="shield_spi_miso_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_miso_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO1_O" physical_port="shield_spi_miso_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_miso_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO1_T" physical_port="shield_spi_miso_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_miso_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCK_I" physical_port="shield_spi_sck_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_sck_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCK_O" physical_port="shield_spi_sck_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_sck_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCK_T" physical_port="shield_spi_sck_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_sck_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SS_I" physical_port="shield_spi_ss_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_ss_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SS_O" physical_port="shield_spi_ss_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_ss_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SS_T" physical_port="shield_spi_ss_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_ss_i"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+								<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+								<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+								<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+								<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+								<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+								<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="user_dio" type="xilinx.com:interface:gpio_rtl:1.0" of_component="user_dio" preset_proc="user_dio_preset">
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_I" physical_port="user_dio_tri_i" dir="in" left="11" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0"  component_pin="user_dio_tri_i_0"/> 
+								<pin_map port_index="1"  component_pin="user_dio_tri_i_1"/> 
+								<pin_map port_index="2"  component_pin="user_dio_tri_i_2"/> 
+								<pin_map port_index="3"  component_pin="user_dio_tri_i_3"/> 
+								<pin_map port_index="4"  component_pin="user_dio_tri_i_4"/> 
+								<pin_map port_index="5"  component_pin="user_dio_tri_i_5"/> 
+								<pin_map port_index="6"  component_pin="user_dio_tri_i_6"/> 
+								<pin_map port_index="7"  component_pin="user_dio_tri_i_7"/> 
+								<pin_map port_index="8"  component_pin="user_dio_tri_i_8"/> 
+								<pin_map port_index="9"  component_pin="user_dio_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="user_dio_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="user_dio_tri_i_11"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_O" physical_port="user_dio_tri_o" dir="out" left="11" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0"  component_pin="user_dio_tri_i_0"/> 
+								<pin_map port_index="1"  component_pin="user_dio_tri_i_1"/> 
+								<pin_map port_index="2"  component_pin="user_dio_tri_i_2"/> 
+								<pin_map port_index="3"  component_pin="user_dio_tri_i_3"/> 
+								<pin_map port_index="4"  component_pin="user_dio_tri_i_4"/> 
+								<pin_map port_index="5"  component_pin="user_dio_tri_i_5"/> 
+								<pin_map port_index="6"  component_pin="user_dio_tri_i_6"/> 
+								<pin_map port_index="7"  component_pin="user_dio_tri_i_7"/> 
+								<pin_map port_index="8"  component_pin="user_dio_tri_i_8"/> 
+								<pin_map port_index="9"  component_pin="user_dio_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="user_dio_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="user_dio_tri_i_11"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_T" physical_port="user_dio_tri_t" dir="out" left="11" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0"  component_pin="user_dio_tri_i_0"/> 
+								<pin_map port_index="1"  component_pin="user_dio_tri_i_1"/> 
+								<pin_map port_index="2"  component_pin="user_dio_tri_i_2"/> 
+								<pin_map port_index="3"  component_pin="user_dio_tri_i_3"/> 
+								<pin_map port_index="4"  component_pin="user_dio_tri_i_4"/> 
+								<pin_map port_index="5"  component_pin="user_dio_tri_i_5"/> 
+								<pin_map port_index="6"  component_pin="user_dio_tri_i_6"/> 
+								<pin_map port_index="7"  component_pin="user_dio_tri_i_7"/> 
+								<pin_map port_index="8"  component_pin="user_dio_tri_i_8"/> 
+								<pin_map port_index="9"  component_pin="user_dio_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="user_dio_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="user_dio_tri_i_11"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+			</interfaces>
+		</component>
+		<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+		<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+			<description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
+		</component>
+		<component name="btns_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+			<description>Buttons 1 to 0</description>
+		</component>
+		<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+			<description>Pmod Connector JA</description>
+		</component>
+		<component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+			<description>Pmod Connector JB</description>
+		</component>
+		<component name="rgb_leds" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+			<description>RGB LEDs 5 to 0 (3 bits per LED, ordered "RGBRGB")</description>
+		</component>
+		<component name="shield_i2c" display_name="Shield I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+			<description>Shield I2C</description>
+		</component>
+		<component name="shield_spi" display_name="Shield SPI on J7" type="chip" sub_type="mux" major_group="SPI">
+			<description>Shield SPI</description>
+		</component>
+		<component name="shield_dp0_dp13" display_name="Shield Pins 0 to 13" type="chip" sub_type="led" major_group="GPIO">
+			<description>Digital Shield pins DP0 through DP13</description>
+		</component>
+		<component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+			<description>Digital Shield pins DP26 through DP41</description>
+		</component>
+		<component name="user_dio" display_name="User Digital I/O on J1" type="chip" sub_type="led" major_group="GPIO">
+			<description>User Digital I/O pins 1 through 12</description>
+		</component>
+	
+	</components>
+
+	<jtag_chains>
+		<jtag_chain name="chain1">
+			<position name="0" component="part0"/>
+		</jtag_chain>
+	</jtag_chains>
+
+	<connections>
+		<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+			<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+		</connection>
+		<connection name="part0_btns_2bits" component1="part0" component2="btns_2bits">
+			<connection_map name="part0_btns_2bits_1" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
+		</connection>
+		<connection name="part0_rgb_leds" component1="part0" component2="rgb_leds">
+			<connection_map name="part0_rgb_leds_1" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
+		</connection>
+		<connection name="part0_ja" component1="part0" component2="ja">
+			<connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+		</connection>
+		<connection name="part0_jb" component1="part0" component2="jb">
+			<connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+		</connection>
+		<connection name="part0_shield_i2c" component1="part0" component2="shield_i2c">
+			<connection_map name="part0_shield_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+		</connection>
+		<connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
+			<connection_map name="part0_shield_dp0_dp13_1" c1_st_index="27" c1_end_index="40" c2_st_index="0" c2_end_index="13"/>
+		</connection>
+		<connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+			<connection_map name="part0_shield_dp26_dp41_1" c1_st_index="41" c1_end_index="56" c2_st_index="0" c2_end_index="15"/>
+		</connection>
+		<connection name="part0_shield_spi" component1="part0" component2="shield_spi">
+			<connection_map name="part0_shield_spi_1" c1_st_index="57" c1_end_index="60" c2_st_index="0" c2_end_index="3"/>
+		</connection>
+		<connection name="part0_user_dio" component1="part0" component2="user_dio">
+			<connection_map name="part0_user_dio_1" c1_st_index="61" c1_end_index="72" c2_st_index="0" c2_end_index="11"/>
+		</connection>
+	</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/part0_pins.xml
new file mode 100644
index 0000000..2d8d5fd
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/part0_pins.xml
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z007sclg400-1">
+	<pins>
+		<pin index="0" name ="sys_clk" 			          iostandard="LVCMOS33" loc="H16"/> <!-- Schematic Name: SYSCLK -->
+
+		<pin index="1" name ="btns_2bits_tri_i_0"         iostandard="LVCMOS33" loc="D20"/> <!-- Schematic Name: BTN0 -->
+		<pin index="2" name ="btns_2bits_tri_i_1"         iostandard="LVCMOS33" loc="D19"/> <!-- Schematic Name: BTN1 -->
+
+		<pin index="3" name ="rgb_leds_tri_o_0"           iostandard="LVCMOS33" loc="N15"/> <!-- Schematic Name: LED0_R -->
+		<pin index="4" name ="rgb_leds_tri_o_1"           iostandard="LVCMOS33" loc="G17"/> <!-- Schematic Name: LED0_G -->
+		<pin index="5" name ="rgb_leds_tri_o_2"           iostandard="LVCMOS33" loc="L15"/> <!-- Schematic Name: LED0_B -->
+		<pin index="6" name ="rgb_leds_tri_o_3"           iostandard="LVCMOS33" loc="M15"/> <!-- Schematic Name: LED1_R -->
+		<pin index="7" name ="rgb_leds_tri_o_4"           iostandard="LVCMOS33" loc="L14"/> <!-- Schematic Name: LED1_G -->
+		<pin index="8" name ="rgb_leds_tri_o_5"           iostandard="LVCMOS33" loc="G14"/> <!-- Schematic Name: LED1_B -->
+
+		<pin index="9"  name ="JA1" 			          iostandard="LVCMOS33" loc="Y18"/> <!-- Schematic Name: JA1_P -->
+		<pin index="10" name ="JA2" 			          iostandard="LVCMOS33" loc="Y19"/> <!-- Schematic Name: JA1_N -->
+		<pin index="11" name ="JA3" 			          iostandard="LVCMOS33" loc="Y16"/> <!-- Schematic Name: JA2_P -->
+		<pin index="12" name ="JA4" 			          iostandard="LVCMOS33" loc="Y17"/> <!-- Schematic Name: JA2_N -->
+		<pin index="13" name ="JA7" 			          iostandard="LVCMOS33" loc="U18"/> <!-- Schematic Name: JA3_P -->
+		<pin index="14" name ="JA8" 			          iostandard="LVCMOS33" loc="U19"/> <!-- Schematic Name: JA3_N -->
+		<pin index="15" name ="JA9" 			          iostandard="LVCMOS33" loc="W18"/> <!-- Schematic Name: JA4_P -->
+		<pin index="16" name ="JA10"			          iostandard="LVCMOS33" loc="W19"/> <!-- Schematic Name: JA4_N -->
+
+		<pin index="17" name ="JB1" 			          iostandard="LVCMOS33" loc="W14"/> <!-- Schematic Name: JB1_P -->
+		<pin index="18" name ="JB2" 			          iostandard="LVCMOS33" loc="Y14"/> <!-- Schematic Name: JB1_N -->
+		<pin index="19" name ="JB3" 			          iostandard="LVCMOS33" loc="T11"/> <!-- Schematic Name: JB2_P -->
+		<pin index="20" name ="JB4" 			          iostandard="LVCMOS33" loc="T10"/> <!-- Schematic Name: JB2_N -->
+		<pin index="21" name ="JB7" 			          iostandard="LVCMOS33" loc="V16"/> <!-- Schematic Name: JB3_P -->
+		<pin index="22" name ="JB8" 			          iostandard="LVCMOS33" loc="W16"/> <!-- Schematic Name: JB3_N -->
+		<pin index="23" name ="JB9" 			          iostandard="LVCMOS33" loc="V12"/> <!-- Schematic Name: JB4_P -->
+		<pin index="24" name ="JB10"			          iostandard="LVCMOS33" loc="W13"/> <!-- Schematic Name: JB4_N -->
+
+		<pin index="25" name ="shield_i2c_sda_i"          iostandard="LVCMOS33" loc="P15"/> <!-- Schematic Name: CK_SDA -->
+		<pin index="26" name ="shield_i2c_scl_i"          iostandard="LVCMOS33" loc="P16"/> <!-- Schematic Name: CK_SCL -->
+
+		<pin index="27" name ="shield_dp0_dp13_tri_i_0"   iostandard="LVCMOS33" loc="U14"/> <!-- Schematic Name: CK_IO0 -->
+		<pin index="28" name ="shield_dp0_dp13_tri_i_1"   iostandard="LVCMOS33" loc="V13"/> <!-- Schematic Name: CK_IO1 -->
+		<pin index="29" name ="shield_dp0_dp13_tri_i_2"   iostandard="LVCMOS33" loc="T14"/> <!-- Schematic Name: CK_IO2 -->
+		<pin index="30" name ="shield_dp0_dp13_tri_i_3"   iostandard="LVCMOS33" loc="T15"/> <!-- Schematic Name: CK_IO3 -->
+		<pin index="31" name ="shield_dp0_dp13_tri_i_4"   iostandard="LVCMOS33" loc="V17"/> <!-- Schematic Name: CK_IO4 -->
+		<pin index="33" name ="shield_dp0_dp13_tri_i_5"   iostandard="LVCMOS33" loc="V18"/> <!-- Schematic Name: CK_IO5 -->
+		<pin index="33" name ="shield_dp0_dp13_tri_i_6"   iostandard="LVCMOS33" loc="R17"/> <!-- Schematic Name: CK_IO6 -->
+		<pin index="34" name ="shield_dp0_dp13_tri_i_7"   iostandard="LVCMOS33" loc="R14"/> <!-- Schematic Name: CK_IO7 -->
+		<pin index="35" name ="shield_dp0_dp13_tri_i_8"   iostandard="LVCMOS33" loc="N18"/> <!-- Schematic Name: CK_IO8 -->
+		<pin index="36" name ="shield_dp0_dp13_tri_i_9"   iostandard="LVCMOS33" loc="M18"/> <!-- Schematic Name: CK_IO9 -->
+		<pin index="37" name ="shield_dp0_dp13_tri_i_10"  iostandard="LVCMOS33" loc="U15"/> <!-- Schematic Name: CK_IO10 -->
+		<pin index="38" name ="shield_dp0_dp13_tri_i_11"  iostandard="LVCMOS33" loc="K18"/> <!-- Schematic Name: CK_IO11 -->
+		<pin index="39" name ="shield_dp0_dp13_tri_i_12"  iostandard="LVCMOS33" loc="J18"/> <!-- Schematic Name: CK_IO12 -->
+		<pin index="40" name ="shield_dp0_dp13_tri_i_13"  iostandard="LVCMOS33" loc="G15"/> <!-- Schematic Name: CK_IO13 -->
+
+		<pin index="41" name ="shield_dp26_dp41_tri_i_0"  iostandard="LVCMOS33" loc="R16"/> <!-- Schematic Name: CK_IO26 -->
+		<pin index="42" name ="shield_dp26_dp41_tri_i_1"  iostandard="LVCMOS33" loc="U12"/> <!-- Schematic Name: CK_IO27 -->
+		<pin index="43" name ="shield_dp26_dp41_tri_i_2"  iostandard="LVCMOS33" loc="U13"/> <!-- Schematic Name: CK_IO28 -->
+		<pin index="44" name ="shield_dp26_dp41_tri_i_3"  iostandard="LVCMOS33" loc="V15"/> <!-- Schematic Name: CK_IO29 -->
+		<pin index="45" name ="shield_dp26_dp41_tri_i_4"  iostandard="LVCMOS33" loc="T16"/> <!-- Schematic Name: CK_IO30 -->
+		<pin index="46" name ="shield_dp26_dp41_tri_i_5"  iostandard="LVCMOS33" loc="U17"/> <!-- Schematic Name: CK_IO31 -->
+		<pin index="47" name ="shield_dp26_dp41_tri_i_6"  iostandard="LVCMOS33" loc="T17"/> <!-- Schematic Name: CK_IO32 -->
+		<pin index="48" name ="shield_dp26_dp41_tri_i_7"  iostandard="LVCMOS33" loc="R18"/> <!-- Schematic Name: CK_IO33 -->
+		<pin index="49" name ="shield_dp26_dp41_tri_i_8"  iostandard="LVCMOS33" loc="P18"/> <!-- Schematic Name: CK_IO34 -->
+		<pin index="50" name ="shield_dp26_dp41_tri_i_9"  iostandard="LVCMOS33" loc="N17"/> <!-- Schematic Name: CK_IO35 -->
+		<pin index="51" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="M17"/> <!-- Schematic Name: CK_IO36 -->
+		<pin index="52" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="L17"/> <!-- Schematic Name: CK_IO37 -->
+		<pin index="53" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="H17"/> <!-- Schematic Name: CK_IO38 -->
+		<pin index="54" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="H18"/> <!-- Schematic Name: CK_IO39 -->
+		<pin index="55" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="G18"/> <!-- Schematic Name: CK_IO40 -->
+		<pin index="56" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="L20"/> <!-- Schematic Name: CK_IO41 -->
+		
+		<pin index="57" name ="shield_spi_miso_i"         iostandard="LVCMOS33" loc="W15"/> <!-- Schematic Name: CK_MISO -->
+		<pin index="58" name ="shield_spi_mosi_i"         iostandard="LVCMOS33" loc="T12"/> <!-- Schematic Name: CK_MOSI -->
+		<pin index="59" name ="shield_spi_sck_i"          iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: CK_SCK -->
+		<pin index="60" name ="shield_spi_ss_i"           iostandard="LVCMOS33" loc="F16"/> <!-- Schematic Name: CK_SS -->
+		
+		<pin index="61" name ="user_dio_tri_i_0"          iostandard="LVCMOS33" loc="L19"/> <!-- Schematic Name: USER_DIO1 -->
+		<pin index="62" name ="user_dio_tri_i_1"          iostandard="LVCMOS33" loc="M19"/> <!-- Schematic Name: USER_DIO2 -->
+		<pin index="63" name ="user_dio_tri_i_2"          iostandard="LVCMOS33" loc="N20"/> <!-- Schematic Name: USER_DIO3 -->
+		<pin index="64" name ="user_dio_tri_i_3"          iostandard="LVCMOS33" loc="P20"/> <!-- Schematic Name: USER_DIO4 -->
+		<pin index="65" name ="user_dio_tri_i_4"          iostandard="LVCMOS33" loc="P19"/> <!-- Schematic Name: USER_DIO5 -->
+		<pin index="66" name ="user_dio_tri_i_5"          iostandard="LVCMOS33" loc="R19"/> <!-- Schematic Name: USER_DIO6 -->
+		<pin index="67" name ="user_dio_tri_i_6"          iostandard="LVCMOS33" loc="T20"/> <!-- Schematic Name: USER_DIO7 -->
+		<pin index="68" name ="user_dio_tri_i_7"          iostandard="LVCMOS33" loc="T19"/> <!-- Schematic Name: USER_DIO8 -->
+		<pin index="69" name ="user_dio_tri_i_8"          iostandard="LVCMOS33" loc="U20"/> <!-- Schematic Name: USER_DIO9 -->
+		<pin index="70" name ="user_dio_tri_i_9"          iostandard="LVCMOS33" loc="V20"/> <!-- Schematic Name: USER_DIO10 -->
+		<pin index="71" name ="user_dio_tri_i_10"         iostandard="LVCMOS33" loc="W20"/> <!-- Schematic Name: USER_DIO11 -->
+		<pin index="72" name ="user_dio_tri_i_11"         iostandard="LVCMOS33" loc="K19"/> <!-- Schematic Name: USER_DIO12 -->
+
+		
+		
+	</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/preset.xml
new file mode 100644
index 0000000..9599c53
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-07s/B.0/preset.xml
@@ -0,0 +1,617 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="ps7_preset">
+		<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+			<user_parameters>
+				<user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+				<user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+				<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/>
+				<user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
+				<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+				<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+				<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+				<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/>
+				<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/>
+				<user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+				<user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+				<user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+				<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+				<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/> 
+				<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
+				<user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+				<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+				<user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+				<user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/>
+				<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+				<user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+				<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+				<user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="10"/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+				<user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/>
+				<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="15.8"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="15.8"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+				<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+				<user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+				<user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+				<user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="sys_clock_preset">
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+			<user_parameters>
+				<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/> 
+				<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+				<user_parameter name="CONFIG.USE_RESET" value="false"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+				<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+				<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+				<user_parameter name="CONFIG.USE_RESET" value="false"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="input_2bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI3_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI4_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="output_6bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPO1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPO1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPO2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPO2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPO3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPO3_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPO4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPO4_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPO1" value="1"/> 
+				<user_parameter name="CONFIG.GPO1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPO2" value="1"/> 
+				<user_parameter name="CONFIG.GPO2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPO3" value="1"/> 
+				<user_parameter name="CONFIG.GPO3_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPO4" value="1"/> 
+				<user_parameter name="CONFIG.GPO4_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="shield_spi_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+				<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+				<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+				<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="shield_dp0_dp13_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>		  
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="shield_dp26_dp41_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>		  
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="user_dio_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>		  
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/board.xml
new file mode 100644
index 0000000..53d6c9c
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/board.xml
@@ -0,0 +1,691 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-10" display_name="Cora Z7-10" url="https://digilent.com/reference/programmable-logic/cora-z7/start" preset_file="preset.xml" >
+	<compatible_board_revisions>
+		<revision id="0">B.0</revision>
+	</compatible_board_revisions>
+	<file_version>1.1</file_version>
+	<description>Cora Z7-10</description>
+	<components>
+		<component name="part0" display_name="Cora Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/cora-z7/start">
+			<interfaces>
+				<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+				</interface>
+				<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+					<port_maps>
+						<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="sys_clk"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+					<parameters>
+						<parameter name="frequency" value="125000000" />
+					</parameters>
+				</interface>
+				<interface mode="master" name="btns_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_2bits" preset_proc="input_2bits_preset">
+					<description>2 Push Buttons</description>
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_I" physical_port="btns_2bits_tri_i" dir="in" left="1" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="btns_2bits_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="btns_2bits_tri_i_1"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="rgb_leds" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_leds" preset_proc="output_6bits_preset">
+					<description>2 RGB LEDs</description>
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_O" physical_port="rgb_leds_tri_o" dir="out" left="5" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/> 
+								<pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
+								<pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
+								<pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
+								<pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
+								<pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+					<port_maps>
+						<port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+							<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA10"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA10"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JA10"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+					<port_maps>
+						<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+							<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB1"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB2"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB3"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB4"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB7"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB8"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB9"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB10"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB10"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="JB10"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="shield_i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="shield_i2c">
+					<description>Shield I2C</description>
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="SDA_I" physical_port="shield_i2c_sda_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_sda_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SDA_O" physical_port="shield_i2c_sda_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_sda_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SDA_T" physical_port="shield_i2c_sda_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_sda_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCL_I" physical_port="shield_i2c_scl_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_scl_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCL_O" physical_port="shield_i2c_scl_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_scl_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCL_T" physical_port="shield_i2c_scl_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_i2c_scl_i"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="shield_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="shield_spi" preset_proc="shield_spi_preset">
+					<description>Shield SPI</description>
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="IO0_I" physical_port="shield_spi_mosi_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_mosi_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO0_O" physical_port="shield_spi_mosi_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_mosi_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO0_T" physical_port="shield_spi_mosi_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_mosi_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO1_I" physical_port="shield_spi_miso_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_miso_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO1_O" physical_port="shield_spi_miso_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_miso_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="IO1_T" physical_port="shield_spi_miso_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_miso_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCK_I" physical_port="shield_spi_sck_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_sck_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCK_O" physical_port="shield_spi_sck_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_sck_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SCK_T" physical_port="shield_spi_sck_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_sck_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SS_I" physical_port="shield_spi_ss_i" dir="in">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_ss_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SS_O" physical_port="shield_spi_ss_o" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_ss_i"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="SS_T" physical_port="shield_spi_ss_t" dir="out">
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_spi_ss_i"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+								<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+								<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+								<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+								<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 
+								<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 
+								<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 
+								<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 
+								<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 
+								<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 
+								<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 
+								<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 
+								<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 
+								<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 
+								<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 
+								<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 
+								<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 
+								<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+				<interface mode="master" name="user_dio" type="xilinx.com:interface:gpio_rtl:1.0" of_component="user_dio" preset_proc="user_dio_preset">
+					<preferred_ips>
+						<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+					</preferred_ips>
+					<port_maps>
+						<port_map logical_port="TRI_I" physical_port="user_dio_tri_i" dir="in" left="11" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0"  component_pin="user_dio_tri_i_0"/> 
+								<pin_map port_index="1"  component_pin="user_dio_tri_i_1"/> 
+								<pin_map port_index="2"  component_pin="user_dio_tri_i_2"/> 
+								<pin_map port_index="3"  component_pin="user_dio_tri_i_3"/> 
+								<pin_map port_index="4"  component_pin="user_dio_tri_i_4"/> 
+								<pin_map port_index="5"  component_pin="user_dio_tri_i_5"/> 
+								<pin_map port_index="6"  component_pin="user_dio_tri_i_6"/> 
+								<pin_map port_index="7"  component_pin="user_dio_tri_i_7"/> 
+								<pin_map port_index="8"  component_pin="user_dio_tri_i_8"/> 
+								<pin_map port_index="9"  component_pin="user_dio_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="user_dio_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="user_dio_tri_i_11"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_O" physical_port="user_dio_tri_o" dir="out" left="11" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0"  component_pin="user_dio_tri_i_0"/> 
+								<pin_map port_index="1"  component_pin="user_dio_tri_i_1"/> 
+								<pin_map port_index="2"  component_pin="user_dio_tri_i_2"/> 
+								<pin_map port_index="3"  component_pin="user_dio_tri_i_3"/> 
+								<pin_map port_index="4"  component_pin="user_dio_tri_i_4"/> 
+								<pin_map port_index="5"  component_pin="user_dio_tri_i_5"/> 
+								<pin_map port_index="6"  component_pin="user_dio_tri_i_6"/> 
+								<pin_map port_index="7"  component_pin="user_dio_tri_i_7"/> 
+								<pin_map port_index="8"  component_pin="user_dio_tri_i_8"/> 
+								<pin_map port_index="9"  component_pin="user_dio_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="user_dio_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="user_dio_tri_i_11"/> 
+							</pin_maps>
+						</port_map>
+						<port_map logical_port="TRI_T" physical_port="user_dio_tri_t" dir="out" left="11" right="0"> 
+							<pin_maps>
+								<pin_map port_index="0"  component_pin="user_dio_tri_i_0"/> 
+								<pin_map port_index="1"  component_pin="user_dio_tri_i_1"/> 
+								<pin_map port_index="2"  component_pin="user_dio_tri_i_2"/> 
+								<pin_map port_index="3"  component_pin="user_dio_tri_i_3"/> 
+								<pin_map port_index="4"  component_pin="user_dio_tri_i_4"/> 
+								<pin_map port_index="5"  component_pin="user_dio_tri_i_5"/> 
+								<pin_map port_index="6"  component_pin="user_dio_tri_i_6"/> 
+								<pin_map port_index="7"  component_pin="user_dio_tri_i_7"/> 
+								<pin_map port_index="8"  component_pin="user_dio_tri_i_8"/> 
+								<pin_map port_index="9"  component_pin="user_dio_tri_i_9"/> 
+								<pin_map port_index="10" component_pin="user_dio_tri_i_10"/> 
+								<pin_map port_index="11" component_pin="user_dio_tri_i_11"/> 
+							</pin_maps>
+						</port_map>
+					</port_maps>
+				</interface>
+			</interfaces>
+		</component>
+		<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+		<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+			<description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
+		</component>
+		<component name="btns_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+			<description>Buttons 1 to 0</description>
+		</component>
+		<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+			<description>Pmod Connector JA</description>
+		</component>
+		<component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+			<description>Pmod Connector JB</description>
+		</component>
+		<component name="rgb_leds" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+			<description>RGB LEDs 5 to 0 (3 bits per LED, ordered "RGBRGB")</description>
+		</component>
+		<component name="shield_i2c" display_name="Shield I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+			<description>Shield I2C</description>
+		</component>
+		<component name="shield_spi" display_name="Shield SPI on J7" type="chip" sub_type="mux" major_group="SPI">
+			<description>Shield SPI</description>
+		</component>
+		<component name="shield_dp0_dp13" display_name="Shield Pins 0 to 13" type="chip" sub_type="led" major_group="GPIO">
+			<description>Digital Shield pins DP0 through DP13</description>
+		</component>
+		<component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+			<description>Digital Shield pins DP26 through DP41</description>
+		</component>
+		<component name="user_dio" display_name="User Digital I/O on J1" type="chip" sub_type="led" major_group="GPIO">
+			<description>User Digital I/O pins 1 through 12</description>
+		</component>
+	
+	</components>
+
+	<jtag_chains>
+		<jtag_chain name="chain1">
+			<position name="0" component="part0"/>
+		</jtag_chain>
+	</jtag_chains>
+
+	<connections>
+		<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+			<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+		</connection>
+		<connection name="part0_btns_2bits" component1="part0" component2="btns_2bits">
+			<connection_map name="part0_btns_2bits_1" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
+		</connection>
+		<connection name="part0_rgb_leds" component1="part0" component2="rgb_leds">
+			<connection_map name="part0_rgb_leds_1" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
+		</connection>
+		<connection name="part0_ja" component1="part0" component2="ja">
+			<connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+		</connection>
+		<connection name="part0_jb" component1="part0" component2="jb">
+			<connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+		</connection>
+		<connection name="part0_shield_i2c" component1="part0" component2="shield_i2c">
+			<connection_map name="part0_shield_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+		</connection>
+		<connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
+			<connection_map name="part0_shield_dp0_dp13_1" c1_st_index="27" c1_end_index="40" c2_st_index="0" c2_end_index="13"/>
+		</connection>
+		<connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+			<connection_map name="part0_shield_dp26_dp41_1" c1_st_index="41" c1_end_index="56" c2_st_index="0" c2_end_index="15"/>
+		</connection>
+		<connection name="part0_shield_spi" component1="part0" component2="shield_spi">
+			<connection_map name="part0_shield_spi_1" c1_st_index="57" c1_end_index="60" c2_st_index="0" c2_end_index="3"/>
+		</connection>
+		<connection name="part0_user_dio" component1="part0" component2="user_dio">
+			<connection_map name="part0_user_dio_1" c1_st_index="61" c1_end_index="72" c2_st_index="0" c2_end_index="11"/>
+		</connection>
+	</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/part0_pins.xml
new file mode 100644
index 0000000..3a548d8
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/part0_pins.xml
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z010clg400-1">
+	<pins>
+		<pin index="0" name ="sys_clk" 			          iostandard="LVCMOS33" loc="H16"/> <!-- Schematic Name: SYSCLK -->
+
+		<pin index="1" name ="btns_2bits_tri_i_0"         iostandard="LVCMOS33" loc="D20"/> <!-- Schematic Name: BTN0 -->
+		<pin index="2" name ="btns_2bits_tri_i_1"         iostandard="LVCMOS33" loc="D19"/> <!-- Schematic Name: BTN1 -->
+
+		<pin index="3" name ="rgb_leds_tri_o_0"           iostandard="LVCMOS33" loc="N15"/> <!-- Schematic Name: LED0_R -->
+		<pin index="4" name ="rgb_leds_tri_o_1"           iostandard="LVCMOS33" loc="G17"/> <!-- Schematic Name: LED0_G -->
+		<pin index="5" name ="rgb_leds_tri_o_2"           iostandard="LVCMOS33" loc="L15"/> <!-- Schematic Name: LED0_B -->
+		<pin index="6" name ="rgb_leds_tri_o_3"           iostandard="LVCMOS33" loc="M15"/> <!-- Schematic Name: LED1_R -->
+		<pin index="7" name ="rgb_leds_tri_o_4"           iostandard="LVCMOS33" loc="L14"/> <!-- Schematic Name: LED1_G -->
+		<pin index="8" name ="rgb_leds_tri_o_5"           iostandard="LVCMOS33" loc="G14"/> <!-- Schematic Name: LED1_B -->
+
+		<pin index="9"  name ="JA1" 			          iostandard="LVCMOS33" loc="Y18"/> <!-- Schematic Name: JA1_P -->
+		<pin index="10" name ="JA2" 			          iostandard="LVCMOS33" loc="Y19"/> <!-- Schematic Name: JA1_N -->
+		<pin index="11" name ="JA3" 			          iostandard="LVCMOS33" loc="Y16"/> <!-- Schematic Name: JA2_P -->
+		<pin index="12" name ="JA4" 			          iostandard="LVCMOS33" loc="Y17"/> <!-- Schematic Name: JA2_N -->
+		<pin index="13" name ="JA7" 			          iostandard="LVCMOS33" loc="U18"/> <!-- Schematic Name: JA3_P -->
+		<pin index="14" name ="JA8" 			          iostandard="LVCMOS33" loc="U19"/> <!-- Schematic Name: JA3_N -->
+		<pin index="15" name ="JA9" 			          iostandard="LVCMOS33" loc="W18"/> <!-- Schematic Name: JA4_P -->
+		<pin index="16" name ="JA10"			          iostandard="LVCMOS33" loc="W19"/> <!-- Schematic Name: JA4_N -->
+
+		<pin index="17" name ="JB1" 			          iostandard="LVCMOS33" loc="W14"/> <!-- Schematic Name: JB1_P -->
+		<pin index="18" name ="JB2" 			          iostandard="LVCMOS33" loc="Y14"/> <!-- Schematic Name: JB1_N -->
+		<pin index="19" name ="JB3" 			          iostandard="LVCMOS33" loc="T11"/> <!-- Schematic Name: JB2_P -->
+		<pin index="20" name ="JB4" 			          iostandard="LVCMOS33" loc="T10"/> <!-- Schematic Name: JB2_N -->
+		<pin index="21" name ="JB7" 			          iostandard="LVCMOS33" loc="V16"/> <!-- Schematic Name: JB3_P -->
+		<pin index="22" name ="JB8" 			          iostandard="LVCMOS33" loc="W16"/> <!-- Schematic Name: JB3_N -->
+		<pin index="23" name ="JB9" 			          iostandard="LVCMOS33" loc="V12"/> <!-- Schematic Name: JB4_P -->
+		<pin index="24" name ="JB10"			          iostandard="LVCMOS33" loc="W13"/> <!-- Schematic Name: JB4_N -->
+
+		<pin index="25" name ="shield_i2c_sda_i"          iostandard="LVCMOS33" loc="P15"/> <!-- Schematic Name: CK_SDA -->
+		<pin index="26" name ="shield_i2c_scl_i"          iostandard="LVCMOS33" loc="P16"/> <!-- Schematic Name: CK_SCL -->
+
+		<pin index="27" name ="shield_dp0_dp13_tri_i_0"   iostandard="LVCMOS33" loc="U14"/> <!-- Schematic Name: CK_IO0 -->
+		<pin index="28" name ="shield_dp0_dp13_tri_i_1"   iostandard="LVCMOS33" loc="V13"/> <!-- Schematic Name: CK_IO1 -->
+		<pin index="29" name ="shield_dp0_dp13_tri_i_2"   iostandard="LVCMOS33" loc="T14"/> <!-- Schematic Name: CK_IO2 -->
+		<pin index="30" name ="shield_dp0_dp13_tri_i_3"   iostandard="LVCMOS33" loc="T15"/> <!-- Schematic Name: CK_IO3 -->
+		<pin index="31" name ="shield_dp0_dp13_tri_i_4"   iostandard="LVCMOS33" loc="V17"/> <!-- Schematic Name: CK_IO4 -->
+		<pin index="33" name ="shield_dp0_dp13_tri_i_5"   iostandard="LVCMOS33" loc="V18"/> <!-- Schematic Name: CK_IO5 -->
+		<pin index="33" name ="shield_dp0_dp13_tri_i_6"   iostandard="LVCMOS33" loc="R17"/> <!-- Schematic Name: CK_IO6 -->
+		<pin index="34" name ="shield_dp0_dp13_tri_i_7"   iostandard="LVCMOS33" loc="R14"/> <!-- Schematic Name: CK_IO7 -->
+		<pin index="35" name ="shield_dp0_dp13_tri_i_8"   iostandard="LVCMOS33" loc="N18"/> <!-- Schematic Name: CK_IO8 -->
+		<pin index="36" name ="shield_dp0_dp13_tri_i_9"   iostandard="LVCMOS33" loc="M18"/> <!-- Schematic Name: CK_IO9 -->
+		<pin index="37" name ="shield_dp0_dp13_tri_i_10"  iostandard="LVCMOS33" loc="U15"/> <!-- Schematic Name: CK_IO10 -->
+		<pin index="38" name ="shield_dp0_dp13_tri_i_11"  iostandard="LVCMOS33" loc="K18"/> <!-- Schematic Name: CK_IO11 -->
+		<pin index="39" name ="shield_dp0_dp13_tri_i_12"  iostandard="LVCMOS33" loc="J18"/> <!-- Schematic Name: CK_IO12 -->
+		<pin index="40" name ="shield_dp0_dp13_tri_i_13"  iostandard="LVCMOS33" loc="G15"/> <!-- Schematic Name: CK_IO13 -->
+
+		<pin index="41" name ="shield_dp26_dp41_tri_i_0"  iostandard="LVCMOS33" loc="R16"/> <!-- Schematic Name: CK_IO26 -->
+		<pin index="42" name ="shield_dp26_dp41_tri_i_1"  iostandard="LVCMOS33" loc="U12"/> <!-- Schematic Name: CK_IO27 -->
+		<pin index="43" name ="shield_dp26_dp41_tri_i_2"  iostandard="LVCMOS33" loc="U13"/> <!-- Schematic Name: CK_IO28 -->
+		<pin index="44" name ="shield_dp26_dp41_tri_i_3"  iostandard="LVCMOS33" loc="V15"/> <!-- Schematic Name: CK_IO29 -->
+		<pin index="45" name ="shield_dp26_dp41_tri_i_4"  iostandard="LVCMOS33" loc="T16"/> <!-- Schematic Name: CK_IO30 -->
+		<pin index="46" name ="shield_dp26_dp41_tri_i_5"  iostandard="LVCMOS33" loc="U17"/> <!-- Schematic Name: CK_IO31 -->
+		<pin index="47" name ="shield_dp26_dp41_tri_i_6"  iostandard="LVCMOS33" loc="T17"/> <!-- Schematic Name: CK_IO32 -->
+		<pin index="48" name ="shield_dp26_dp41_tri_i_7"  iostandard="LVCMOS33" loc="R18"/> <!-- Schematic Name: CK_IO33 -->
+		<pin index="49" name ="shield_dp26_dp41_tri_i_8"  iostandard="LVCMOS33" loc="P18"/> <!-- Schematic Name: CK_IO34 -->
+		<pin index="50" name ="shield_dp26_dp41_tri_i_9"  iostandard="LVCMOS33" loc="N17"/> <!-- Schematic Name: CK_IO35 -->
+		<pin index="51" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="M17"/> <!-- Schematic Name: CK_IO36 -->
+		<pin index="52" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="L17"/> <!-- Schematic Name: CK_IO37 -->
+		<pin index="53" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="H17"/> <!-- Schematic Name: CK_IO38 -->
+		<pin index="54" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="H18"/> <!-- Schematic Name: CK_IO39 -->
+		<pin index="55" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="G18"/> <!-- Schematic Name: CK_IO40 -->
+		<pin index="56" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="L20"/> <!-- Schematic Name: CK_IO41 -->
+		
+		<pin index="57" name ="shield_spi_miso_i"         iostandard="LVCMOS33" loc="W15"/> <!-- Schematic Name: CK_MISO -->
+		<pin index="58" name ="shield_spi_mosi_i"         iostandard="LVCMOS33" loc="T12"/> <!-- Schematic Name: CK_MOSI -->
+		<pin index="59" name ="shield_spi_sck_i"          iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: CK_SCK -->
+		<pin index="60" name ="shield_spi_ss_i"           iostandard="LVCMOS33" loc="F16"/> <!-- Schematic Name: CK_SS -->
+		
+		<pin index="61" name ="user_dio_tri_i_0"          iostandard="LVCMOS33" loc="L19"/> <!-- Schematic Name: USER_DIO1 -->
+		<pin index="62" name ="user_dio_tri_i_1"          iostandard="LVCMOS33" loc="M19"/> <!-- Schematic Name: USER_DIO2 -->
+		<pin index="63" name ="user_dio_tri_i_2"          iostandard="LVCMOS33" loc="N20"/> <!-- Schematic Name: USER_DIO3 -->
+		<pin index="64" name ="user_dio_tri_i_3"          iostandard="LVCMOS33" loc="P20"/> <!-- Schematic Name: USER_DIO4 -->
+		<pin index="65" name ="user_dio_tri_i_4"          iostandard="LVCMOS33" loc="P19"/> <!-- Schematic Name: USER_DIO5 -->
+		<pin index="66" name ="user_dio_tri_i_5"          iostandard="LVCMOS33" loc="R19"/> <!-- Schematic Name: USER_DIO6 -->
+		<pin index="67" name ="user_dio_tri_i_6"          iostandard="LVCMOS33" loc="T20"/> <!-- Schematic Name: USER_DIO7 -->
+		<pin index="68" name ="user_dio_tri_i_7"          iostandard="LVCMOS33" loc="T19"/> <!-- Schematic Name: USER_DIO8 -->
+		<pin index="69" name ="user_dio_tri_i_8"          iostandard="LVCMOS33" loc="U20"/> <!-- Schematic Name: USER_DIO9 -->
+		<pin index="70" name ="user_dio_tri_i_9"          iostandard="LVCMOS33" loc="V20"/> <!-- Schematic Name: USER_DIO10 -->
+		<pin index="71" name ="user_dio_tri_i_10"         iostandard="LVCMOS33" loc="W20"/> <!-- Schematic Name: USER_DIO11 -->
+		<pin index="72" name ="user_dio_tri_i_11"         iostandard="LVCMOS33" loc="K19"/> <!-- Schematic Name: USER_DIO12 -->
+
+		
+		
+	</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/preset.xml
new file mode 100644
index 0000000..d90c60d
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cora-z7-10/B.0/preset.xml
@@ -0,0 +1,617 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="ps7_preset">
+		<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+			<user_parameters>
+				<user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+				<user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+				<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/>
+				<user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
+				<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+				<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+				<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+				<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/>
+				<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/>
+				<user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+				<user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+				<user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+				<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+				<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/> 
+				<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
+				<user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+				<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+				<user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+				<user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/>
+				<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+				<user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+				<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+				<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+				<user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+				<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="10"/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+				<user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/>
+				<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="15.8"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="15.8"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/> 
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+				<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+				<user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+				<user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+				<user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="sys_clock_preset">
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+			<user_parameters>
+				<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/> 
+				<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+				<user_parameter name="CONFIG.USE_RESET" value="false"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+				<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+				<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+				<user_parameter name="CONFIG.USE_RESET" value="false"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="input_2bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI3_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI4_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="output_6bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPO1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPO1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPO2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPO2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPO3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPO3_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPO4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPO4_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPO1" value="1"/> 
+				<user_parameter name="CONFIG.GPO1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPO2" value="1"/> 
+				<user_parameter name="CONFIG.GPO2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPO3" value="1"/> 
+				<user_parameter name="CONFIG.GPO3_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPO4" value="1"/> 
+				<user_parameter name="CONFIG.GPO4_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="shield_spi_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+				<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+				<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+				<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="shield_dp0_dp13_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>		  
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="shield_dp26_dp41_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>		  
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="user_dio_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>		  
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/> 
+				<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/board.xml
new file mode 100644
index 0000000..f514803
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/board.xml
@@ -0,0 +1,376 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://www.digilentinc.com" preset_file="preset.xml">
+<compatible_board_revisions>
+	<revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Eclypse Z7</description>
+
+<components>
+	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
+	<component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com">
+		<interfaces> 
+			<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+				<port_maps>
+					<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+						<pin_maps>
+							<pin_map port_index="0" component_pin="sys_clk"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+				<parameters>
+					<parameter name="frequency" value="125000000"/>
+				</parameters>
+			</interface>
+			<interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
+				<description>Buttons</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="1" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="rgbled_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_6bits" preset_proc="rgbled_6bits_preset">
+				<description>8 LEDs</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="rgbled_6bits_tri_o" dir="out" left="5" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="rgbled_6bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="rgbled_6bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="rgbled_6bits_tri_o_2"/> 
+							<pin_map port_index="3" component_pin="rgbled_6bits_tri_o_3"/> 
+							<pin_map port_index="4" component_pin="rgbled_6bits_tri_o_4"/> 
+							<pin_map port_index="5" component_pin="rgbled_6bits_tri_o_5"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_ja">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+			</interface>
+		</interfaces>
+	</component>
+	
+	<!-- Descriptions of components that will appear in the IPI Board tab -->
+	<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+		<description>3.3V Single-Ended 125 MHz clock from Ethernet PHY</description>
+	</component>
+	<component name="btn_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+		<description>Buttons 1 to 0</description>
+	</component>
+	<component name="rgbled_6bits" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+		<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+	</component>
+	<component name="pmod_ja" display_name="Pmod Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JA</description>
+	</component>
+	<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JB</description>
+	</component>
+	<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+</components>
+
+<jtag_chains>
+	<jtag_chain name="chain1">
+		<position name="0" component="part0"/>
+	</jtag_chain>
+</jtag_chains>
+
+<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
+	<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+		<connection_map name="part0_sys_clock_map" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+	</connection>
+	<connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
+		<connection_map name="part0_btn_2bits_map"    c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+	<connection name="part0_rgbled_6bits" component1="part0" component2="rgbled_6bits">
+		<connection_map name="part0_rgbled_6bits_map" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
+	</connection>
+	<connection name="part0_pmod_ja" component1="part0" component2="pmod_ja">
+		<connection_map name="part0_pmod_ja_map" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
+		<connection_map name="part0_pmod_jb_map" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+</connections>
+
+</board>
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/part0_pins.xml
new file mode 100644
index 0000000..b2155f3
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/part0_pins.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z020clg484-1">
+<pins>
+    <pin index="0"  name="sys_clk"              iostandard="LVCMOS33" loc="D18"/> <!-- Sch=sysclk    -->
+    
+	<pin index="1"  name="btn_2bits_tri_i_0"    iostandard="LVCMOS33" loc="C17"/> <!-- Sch=btn[0]    -->
+    <pin index="2"  name="btn_2bits_tri_i_1"    iostandard="LVCMOS33" loc="C18"/> <!-- Sch=btn[1]    -->
+    
+	<pin index="3"  name="rgbled_6bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/> <!-- Sch=led0_b    -->
+    <pin index="4"  name="rgbled_6bits_tri_o_1" iostandard="LVCMOS33" loc="B16"/> <!-- Sch=led0_g    -->
+    <pin index="5"  name="rgbled_6bits_tri_o_2" iostandard="LVCMOS33" loc="B17"/> <!-- Sch=led0_r    -->
+    <pin index="6"  name="rgbled_6bits_tri_o_3" iostandard="LVCMOS33" loc="A16"/> <!-- Sch=led1_b    -->
+    <pin index="7"  name="rgbled_6bits_tri_o_4" iostandard="LVCMOS33" loc="A18"/> <!-- Sch=led1_g    -->
+    <pin index="8"  name="rgbled_6bits_tri_o_5" iostandard="LVCMOS33" loc="A19"/> <!-- Sch=led1_r    -->
+	
+    <pin index="9"  name="JA1"                  iostandard="LVCMOS33" loc="H17"/> <!-- Sch=ja1_fpga  -->
+    <pin index="10" name="JA2"                  iostandard="LVCMOS33" loc="H18"/> <!-- Sch=ja2_fpga  -->
+    <pin index="11" name="JA3"                  iostandard="LVCMOS33" loc="E16"/> <!-- Sch=ja3_fpga  -->
+    <pin index="12" name="JA4"                  iostandard="LVCMOS33" loc="F16"/> <!-- Sch=ja4_fpga  -->
+    <pin index="13" name="JA7"                  iostandard="LVCMOS33" loc="D17"/> <!-- Sch=ja7_fpga  -->
+    <pin index="14" name="JA8"                  iostandard="LVCMOS33" loc="D16"/> <!-- Sch=ja8_fpga  -->
+    <pin index="15" name="JA9"                  iostandard="LVCMOS33" loc="D15"/> <!-- Sch=ja9_fpga  -->
+    <pin index="16" name="JA10"                 iostandard="LVCMOS33" loc="E15"/> <!-- Sch=ja10_fpga -->
+    
+	<pin index="17" name="JB1"                  iostandard="LVCMOS33" loc="G16"/> <!-- Sch=jb1_fpga  -->
+    <pin index="18" name="JB2"                  iostandard="LVCMOS33" loc="G15"/> <!-- Sch=jb2_fpga  -->
+    <pin index="19" name="JB3"                  iostandard="LVCMOS33" loc="E18"/> <!-- Sch=jb3_fpga  -->
+    <pin index="20" name="JB4"                  iostandard="LVCMOS33" loc="F18"/> <!-- Sch=jb4_fpga  -->
+    <pin index="21" name="JB7"                  iostandard="LVCMOS33" loc="F17"/> <!-- Sch=jb7_fpga  -->
+    <pin index="22" name="JB8"                  iostandard="LVCMOS33" loc="G17"/> <!-- Sch=jb8_fpga  -->
+    <pin index="23" name="JB9"                  iostandard="LVCMOS33" loc="B15"/> <!-- Sch=jb9_fpga  -->
+    <pin index="24" name="JB10"                 iostandard="LVCMOS33" loc="C15"/> <!-- Sch=jb10_fpga -->
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/preset.xml
new file mode 100644
index 0000000..352e459
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/A.0/preset.xml
@@ -0,0 +1,608 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<!-- Contains IP configurations for Block/Connection Automation flows -->
+<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
+<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
+<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="ps7_preset">
+		<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+			<user_parameters>
+				<user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" 			value="666.666687"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" 			value="10.158730"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" 			value="125.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" 			value="100.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ"  			value="50.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ"  			value="100.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ"   			value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" 					value="40"					/>
+				<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1"   			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" 					value="1333.333"  			/>
+				<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0"  				value="2"  					/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0"   			value="15"  				/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1"   			value="7"  					/>
+				<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" 					value="32"					/>
+				<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" 					value="1066.667"  			/>
+				<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0"  				value="2"  					/>
+				<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" 						value="0x3FFFFFFF"			/>
+				<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" 						value="MIO 16 .. 27"  		/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO"						value="MIO 52 .. 53"  		/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" 				value="IO PLL"  			/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" 			value="8"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" 				value="1000 Mbps"  			/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" 						value="MIO 9"				/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE"					value="0" 					/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT"						value="Share reset pin"  	/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" 						value="0"		  			/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_ENET0"    						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_I2C1"     						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_UART0"    						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_ENET0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_GPIO"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_I2C1"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_QSPI"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_SDIO0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_UART0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_USB0"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" 				value="100"  				/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" 						value="MIO"  				/>
+				<user_parameter name="CONFIG.PCW_I2C0_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_GRP_INT_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_I2C1_IO" 							value="MIO 12 .. 13"  		/>
+				<user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ"   				value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_I2C_RESET_ENABLE" 						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_I2C_RESET_SELECT" 						value="Share reset pin"  	/>
+				<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV"  					value="30"					/>
+				<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ"   					value="1000.000"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_0_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE"							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_10_PULLUP"							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_10_SLEW"							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" 						value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_11_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_12_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_13_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_14_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_15_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_16_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_17_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_18_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_19_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_1_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_20_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_21_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_22_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_23_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_24_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_25_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_26_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_27_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_28_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_29_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_2_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_30_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_31_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_32_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_33_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_34_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_35_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_36_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_37_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_38_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_39_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_3_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_40_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_41_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_42_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_43_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_44_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_45_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_46_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_47_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_48_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_49_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_4_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_50_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_51_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE"							value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_52_SLEW"							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_53_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_5_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_6_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_7_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_8_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_9_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" 					value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#I2C 1#I2C 1#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
+				<user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" 						value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#scl#sda#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
+				<user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE"				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE"				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" 		value="0.202" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" 		value="0.202" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" 		value="0.029" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" 		value="0.031" 				/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0"  			value="5"  					/>
+				<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" 					value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO"						value="MIO 8"  				/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO"					value="MIO 1 .. 6"  		/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" 				value="5"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ"  				value="200"  				/>
+				<user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" 							value="MIO 1 .. 6"  		/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO"							value="MIO 47"  			/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE"					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" 				value="1"					/>
+				<user_parameter name="CONFIG.PCW_SD0_SD0_IO"							value="MIO 40 .. 45"  		/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" 				value="20"  				/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ"  				value="50"  				/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" 				value="1"			  		/>
+				<user_parameter name="CONFIG.PCW_SINGLE_QSPI_DATA_MODE" 				value="x4"  				/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0"  			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE"				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_UART0_IO" 						value="MIO 14 .. 15"  		/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" 				value="10"  				/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ"  				value="100"  				/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" 				value="1"			  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ"   			value="533.333374"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" 			value="3"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" 						value="8"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" 						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" 		value="63.2909"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" 		value="63.2909"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" 		value="49.1639"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" 		value="49.1639"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" 			value="10"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" 						value="6"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" 			value="4096 MBits"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" 			value="32.2611"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" 			value="32.2666"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" 			value="44.6376"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" 			value="44.3743"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0"		value="0.202"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1"		value="0.202"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2"		value="0.029"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3"		value="0.031"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" 			value="32.5236"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" 			value="32.3526"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" 			value="44.4929"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" 			value="44.4683"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" 				value="16 Bits"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" 				value="DDR 3 (Low Voltage)" />
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" 					value="MT41K256M16 RE-125"  />
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" 			value="15"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" 				value="DDR3_1066F"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW"						value="40.0"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN"					value="35.0"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" 						value="48.75"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD"						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" 						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE"				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ"  				value="60"  				/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_IO" 						value="MIO 46"  			/>
+				<user_parameter name="CONFIG.PCW_USB0_USB0_IO" 							value="MIO 28 .. 39"  		/>
+				<user_parameter name="CONFIG.PCW_USB1_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" 						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" 						value="Share reset pin"  	/>
+				<!--
+				<user_parameter name="CONFIG.PCW_USE_DMA0" 								value="0" 					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" 			value="5"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" 			value="2"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CLK0_FREQ"								value="100000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK1_FREQ"								value="10000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK2_FREQ"								value="10000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK3_FREQ"								value="10000000"  			/>
+				-->
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="sys_clock_preset">
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+			<user_parameters>
+				<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"                            /> 
+				<user_parameter name="CONFIG.PRIM_SOURCE"  value="Single_ended_clock_capable_pin" />
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"                           />
+				<user_parameter name="CONFIG.SECONDARY_IN_FREQ"    value="125"                            />
+				<user_parameter name="CONFIG.SECONDARY_SOURCE"     value="Single_ended_clock_capable_pin" />
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="btn_2bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="rgbled_6bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/board.xml
new file mode 100644
index 0000000..20768cd
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/board.xml
@@ -0,0 +1,376 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://digilent.com/reference/programmable-logic/eclypse-z7/start" preset_file="preset.xml">
+<compatible_board_revisions>
+	<revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Eclypse Z7</description>
+
+<components>
+	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
+	<component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/eclypse-z7/start">
+		<interfaces> 
+			<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+				<port_maps>
+					<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+						<pin_maps>
+							<pin_map port_index="0" component_pin="sys_clk"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+				<parameters>
+					<parameter name="frequency" value="125000000"/>
+				</parameters>
+			</interface>
+			<interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
+				<description>Buttons</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="1" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="rgbled_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_6bits" preset_proc="rgbled_6bits_preset">
+				<description>8 LEDs</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="rgbled_6bits_tri_o" dir="out" left="5" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="rgbled_6bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="rgbled_6bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="rgbled_6bits_tri_o_2"/> 
+							<pin_map port_index="3" component_pin="rgbled_6bits_tri_o_3"/> 
+							<pin_map port_index="4" component_pin="rgbled_6bits_tri_o_4"/> 
+							<pin_map port_index="5" component_pin="rgbled_6bits_tri_o_5"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_ja">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+			</interface>
+		</interfaces>
+	</component>
+	
+	<!-- Descriptions of components that will appear in the IPI Board tab -->
+	<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+		<description>3.3V Single-Ended 125 MHz clock from Ethernet PHY</description>
+	</component>
+	<component name="btn_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+		<description>Buttons 1 to 0</description>
+	</component>
+	<component name="rgbled_6bits" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+		<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+	</component>
+	<component name="pmod_ja" display_name="Pmod Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JA</description>
+	</component>
+	<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JB</description>
+	</component>
+	<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+</components>
+
+<jtag_chains>
+	<jtag_chain name="chain1">
+		<position name="0" component="part0"/>
+	</jtag_chain>
+</jtag_chains>
+
+<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
+	<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+		<connection_map name="part0_sys_clock_map" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+	</connection>
+	<connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
+		<connection_map name="part0_btn_2bits_map"    c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+	<connection name="part0_rgbled_6bits" component1="part0" component2="rgbled_6bits">
+		<connection_map name="part0_rgbled_6bits_map" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
+	</connection>
+	<connection name="part0_pmod_ja" component1="part0" component2="pmod_ja">
+		<connection_map name="part0_pmod_ja_map" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
+		<connection_map name="part0_pmod_jb_map" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+</connections>
+
+</board>
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/part0_pins.xml
new file mode 100644
index 0000000..71a442f
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/part0_pins.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z020clg484-1">
+<pins>
+    <pin index="0"  name="sys_clk"              iostandard="LVCMOS33" loc="D18"/> <!-- Sch=sysclk    -->
+    
+	<pin index="1"  name="btn_2bits_tri_i_0"    iostandard="LVCMOS33" loc="C17"/> <!-- Sch=btn[0]    -->
+    <pin index="2"  name="btn_2bits_tri_i_1"    iostandard="LVCMOS33" loc="C18"/> <!-- Sch=btn[1]    -->
+    
+	<pin index="3"  name="rgbled_6bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/> <!-- Sch=led0_b    -->
+    <pin index="4"  name="rgbled_6bits_tri_o_1" iostandard="LVCMOS33" loc="B16"/> <!-- Sch=led0_g    -->
+    <pin index="5"  name="rgbled_6bits_tri_o_2" iostandard="LVCMOS33" loc="B17"/> <!-- Sch=led0_r    -->
+    <pin index="6"  name="rgbled_6bits_tri_o_3" iostandard="LVCMOS33" loc="A16"/> <!-- Sch=led1_b    -->
+    <pin index="7"  name="rgbled_6bits_tri_o_4" iostandard="LVCMOS33" loc="A18"/> <!-- Sch=led1_g    -->
+    <pin index="8"  name="rgbled_6bits_tri_o_5" iostandard="LVCMOS33" loc="A19"/> <!-- Sch=led1_r    -->
+	
+    <pin index="9"  name="JA1"                  iostandard="LVCMOS33" loc="B15"/> <!-- Sch=ja1_fpga  -->
+    <pin index="10" name="JA2"                  iostandard="LVCMOS33" loc="C15"/> <!-- Sch=ja2_fpga  -->
+    <pin index="11" name="JA3"                  iostandard="LVCMOS33" loc="D15"/> <!-- Sch=ja3_fpga  -->
+    <pin index="12" name="JA4"                  iostandard="LVCMOS33" loc="E16"/> <!-- Sch=ja4_fpga  -->
+    <pin index="13" name="JA7"                  iostandard="LVCMOS33" loc="E15"/> <!-- Sch=ja7_fpga  -->
+    <pin index="14" name="JA8"                  iostandard="LVCMOS33" loc="F17"/> <!-- Sch=ja8_fpga  -->
+    <pin index="15" name="JA9"                  iostandard="LVCMOS33" loc="F16"/> <!-- Sch=ja9_fpga  -->
+    <pin index="16" name="JA10"                 iostandard="LVCMOS33" loc="G16"/> <!-- Sch=ja10_fpga -->
+    
+	<pin index="17" name="JB1"                  iostandard="LVCMOS33" loc="G15"/> <!-- Sch=jb1_fpga  -->
+    <pin index="18" name="JB2"                  iostandard="LVCMOS33" loc="D16"/> <!-- Sch=jb2_fpga  -->
+    <pin index="19" name="JB3"                  iostandard="LVCMOS33" loc="D17"/> <!-- Sch=jb3_fpga  -->
+    <pin index="20" name="JB4"                  iostandard="LVCMOS33" loc="E18"/> <!-- Sch=jb4_fpga  -->
+    <pin index="21" name="JB7"                  iostandard="LVCMOS33" loc="F18"/> <!-- Sch=jb7_fpga  -->
+    <pin index="22" name="JB8"                  iostandard="LVCMOS33" loc="G17"/> <!-- Sch=jb8_fpga  -->
+    <pin index="23" name="JB9"                  iostandard="LVCMOS33" loc="H18"/> <!-- Sch=jb9_fpga  -->
+    <pin index="24" name="JB10"                 iostandard="LVCMOS33" loc="H17"/> <!-- Sch=jb10_fpga -->
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/preset.xml
new file mode 100644
index 0000000..c32c99d
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/eclypse-z7/B.0/preset.xml
@@ -0,0 +1,608 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<!-- Contains IP configurations for Block/Connection Automation flows -->
+<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
+<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
+<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="ps7_preset">
+		<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+			<user_parameters>
+				<user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" 			value="666.666687"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" 			value="10.158730"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" 			value="125.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" 			value="100.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ"  			value="50.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ"  			value="100.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ"   			value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" 					value="40"					/>
+				<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1"   			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" 					value="1333.333"  			/>
+				<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0"  				value="2"  					/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0"   			value="15"  				/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1"   			value="7"  					/>
+				<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" 					value="32"					/>
+				<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" 					value="1066.667"  			/>
+				<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0"  				value="2"  					/>
+				<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" 						value="0x3FFFFFFF"			/>
+				<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" 						value="MIO 16 .. 27"  		/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO"						value="MIO 52 .. 53"  		/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" 				value="IO PLL"  			/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" 			value="8"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" 				value="1000 Mbps"  			/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" 						value="MIO 9"				/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE"					value="0" 					/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT"						value="Share reset pin"  	/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" 						value="0"		  			/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_ENET0"    						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_I2C1"     						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_UART0"    						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_ENET0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_GPIO"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_I2C1"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_QSPI"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_SDIO0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_UART0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_USB0"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" 				value="100"  				/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" 						value="MIO"  				/>
+				<user_parameter name="CONFIG.PCW_I2C0_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_GRP_INT_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_I2C1_IO" 							value="MIO 12 .. 13"  		/>
+				<user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ"   				value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_I2C_RESET_ENABLE" 						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_I2C_RESET_SELECT" 						value="Share reset pin"  	/>
+				<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV"  					value="30"					/>
+				<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ"   					value="1000.000"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_0_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE"							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_10_PULLUP"							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_10_SLEW"							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" 						value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_11_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_12_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_13_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_14_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_15_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_16_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_17_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_18_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_19_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_1_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_20_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_21_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_22_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_23_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_24_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_25_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_26_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_27_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_28_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_29_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_2_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_30_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_31_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_32_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_33_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_34_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_35_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_36_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_37_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_38_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_39_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_3_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_40_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_41_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_42_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_43_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_44_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_45_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_46_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_47_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_48_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_49_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_4_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_50_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_51_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE"							value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_52_SLEW"							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_53_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_5_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_6_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_7_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_8_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_9_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" 					value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#I2C 1#I2C 1#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
+				<user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" 						value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#scl#sda#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
+				<user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE"				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE"				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" 		value="0.202" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" 		value="0.202" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" 		value="0.029" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" 		value="0.031" 				/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0"  			value="5"  					/>
+				<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" 					value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO"						value="MIO 8"  				/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO"					value="MIO 1 .. 6"  		/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" 				value="5"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ"  				value="200"  				/>
+				<user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" 							value="MIO 1 .. 6"  		/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO"							value="MIO 47"  			/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE"					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" 				value="1"					/>
+				<user_parameter name="CONFIG.PCW_SD0_SD0_IO"							value="MIO 40 .. 45"  		/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" 				value="20"  				/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ"  				value="50"  				/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" 				value="1"			  		/>
+				<user_parameter name="CONFIG.PCW_SINGLE_QSPI_DATA_MODE" 				value="x4"  				/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0"  			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE"				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_UART0_IO" 						value="MIO 14 .. 15"  		/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" 				value="10"  				/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ"  				value="100"  				/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" 				value="1"			  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ"   			value="533.333374"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" 			value="3"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" 						value="8"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" 						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" 		value="63.2909"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" 		value="63.2909"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" 		value="49.1639"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" 		value="49.1639"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" 			value="10"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" 						value="6"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" 			value="4096 MBits"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" 			value="32.2611"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" 			value="32.2666"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" 			value="44.6376"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" 			value="44.3743"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0"		value="0.202"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1"		value="0.202"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2"		value="0.029"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3"		value="0.031"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" 			value="32.5236"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" 			value="32.3526"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" 			value="44.4929"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" 			value="44.4683"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" 				value="16 Bits"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" 				value="DDR 3 (Low Voltage)" />
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" 					value="MT41K256M16 RE-125"  />
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" 			value="15"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" 				value="DDR3_1066F"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW"						value="40.0"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN"					value="35.0"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" 						value="48.75"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD"						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" 						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE"				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ"  				value="60"  				/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_IO" 						value="MIO 46"  			/>
+				<user_parameter name="CONFIG.PCW_USB0_USB0_IO" 							value="MIO 28 .. 39"  		/>
+				<user_parameter name="CONFIG.PCW_USB1_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" 						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" 						value="Share reset pin"  	/>
+				<!--
+				<user_parameter name="CONFIG.PCW_USE_DMA0" 								value="0" 					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" 			value="5"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" 			value="2"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CLK0_FREQ"								value="100000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK1_FREQ"								value="10000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK2_FREQ"								value="10000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK3_FREQ"								value="10000000"  			/>
+				-->
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="sys_clock_preset">
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+			<user_parameters>
+				<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"                            /> 
+				<user_parameter name="CONFIG.PRIM_SOURCE"  value="Single_ended_clock_capable_pin" />
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"                           />
+				<user_parameter name="CONFIG.SECONDARY_IN_FREQ"    value="125"                            />
+				<user_parameter name="CONFIG.SECONDARY_SOURCE"     value="Single_ended_clock_capable_pin" />
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="btn_2bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="rgbled_6bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/board.xml
new file mode 100644
index 0000000..94f9e82
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/board.xml
@@ -0,0 +1,535 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.1" vendor="digilentinc.com" name="gzu_3eg" display_name="Genesys ZU-3EG" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">
+<compatible_board_revisions>
+	<revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Genesys ZU-3EG</description>
+
+<components>
+	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
+	<component name="part0" display_name="Genesys ZU-3EG" type="fpga" part_name="xczu3eg-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">
+		<interfaces>
+			<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset"> 
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
+				</preferred_ips>
+			</interface>
+			<interface mode="master" name="btn_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_5bits" preset_proc="btn_5bits_preset">
+				<description>5 PL Buttons (Ordered "UCDLR")</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="btn_5bits_tri_i" dir="in" left="4" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="btn_5bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="btn_5bits_tri_i_1"/> 
+							<pin_map port_index="2" component_pin="btn_5bits_tri_i_2"/> 
+							<pin_map port_index="3" component_pin="btn_5bits_tri_i_3"/> 
+							<pin_map port_index="4" component_pin="btn_5bits_tri_i_4"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="switch_4bits" preset_proc="switch_4bits_preset">
+				<description>4 PL Switches</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="switch_4bits_tri_i" dir="in" left="3" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="switch_4bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="switch_4bits_tri_i_1"/> 
+							<pin_map port_index="2" component_pin="switch_4bits_tri_i_2"/> 
+							<pin_map port_index="3" component_pin="switch_4bits_tri_i_3"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="rgbled_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_3bits" preset_proc="rgbled_3bits_preset">
+				<description>PL RGB LED (ordered RGB)</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="rgbled_3bits_tri_o" dir="out" left="2" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="rgbled_3bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="rgbled_3bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="rgbled_3bits_tri_o_2"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+				<description>4 LEDs</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+							<pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jc">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jd">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+		</interfaces>
+	</component>
+	
+	<!-- Descriptions of components that will appear in the IPI Board tab -->
+	<component name="ps8_fixedio" display_name="PS8 Fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
+	<component name="btn_5bits" display_name="5 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+		<description>5 Buttons (Ordered "UCDLR")</description>
+	</component>
+	<component name="switch_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+		<description>4 Switches</description>
+	</component>
+	<component name="rgbled_3bits" display_name="1 RGB LED" type="chip" sub_type="led" major_group="GPIO">
+		<description>1 RGB LED (Ordered "RGB")</description>
+	</component>
+	<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+		<description>4 LEDs</description>
+	</component>
+	<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JB</description>
+	</component>
+	<component name="pmod_jc" display_name="Pmod Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JC</description>
+	</component>
+	<component name="pmod_jd" display_name="Pmod Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JD</description>
+	</component>
+</components>
+
+<jtag_chains>
+	<jtag_chain name="chain1">
+		<position name="0" component="part0"/>
+	</jtag_chain>
+</jtag_chains>
+
+<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
+	<connection name="part0_btn_5bits" component1="part0" component2="btn_5bits">
+		<connection_map name="part0_btn_5bits_map"    c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
+	</connection>
+	<connection name="part0_switch_4bits" component1="part0" component2="switch_4bits">
+		<connection_map name="part0_switch_4bits_map" c1_st_index="5" c1_end_index="8" c2_st_index="0" c2_end_index="3"/>
+	</connection>
+	<connection name="rgbled_3bits" component1="part0" component2="rgbled_3bits">
+		<connection_map name="part0_rgbled_3bits_map"    c1_st_index="9" c1_end_index="11" c2_st_index="0" c2_end_index="2"/>
+	</connection>
+	<connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+		<connection_map name="part0_led_4bits_map" c1_st_index="12" c1_end_index="15" c2_st_index="0" c2_end_index="3"/>
+	</connection>
+	<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
+		<connection_map name="part0_pmod_jb_map" c1_st_index="16" c1_end_index="23" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jc" component1="part0" component2="pmod_jc">
+		<connection_map name="part0_pmod_jc_map" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jd" component1="part0" component2="pmod_jd">
+		<connection_map name="part0_pmod_jd_map" c1_st_index="32" c1_end_index="39" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+</connections>
+
+</board>
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/part0_pins.xml
new file mode 100644
index 0000000..e6c135c
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/part0_pins.xml
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xczu3eg-sfvc784-1-e">
+<pins>
+	<pin index="0" name="btn_5bits_tri_i_0" iostandard="LVCMOS18" loc="A12"/> <!-- Sch=BTNR -->
+    <pin index="1" name="btn_5bits_tri_i_1" iostandard="LVCMOS18" loc="F12"/> <!-- Sch=BTNL -->
+	<pin index="2" name="btn_5bits_tri_i_2" iostandard="LVCMOS18" loc="J12"/> <!-- Sch=BTND -->
+    <pin index="3" name="btn_5bits_tri_i_3" iostandard="LVCMOS18" loc="H12"/> <!-- Sch=BTNC -->
+    <pin index="4" name="btn_5bits_tri_i_4" iostandard="LVCMOS18" loc="B10"/> <!-- Sch=BTNU -->
+
+    <pin index="5" name="switch_4bits_tri_i_0" iostandard="LVCMOS33" loc="AB15"/> <!-- Sch=SW0 -->
+    <pin index="6" name="switch_4bits_tri_i_1" iostandard="LVCMOS33" loc="W12"/>  <!-- Sch=SW1 -->
+    <pin index="7" name="switch_4bits_tri_i_2" iostandard="LVCMOS33" loc="Y13"/>  <!-- Sch=SW2 -->
+    <pin index="8" name="switch_4bits_tri_i_3" iostandard="LVCMOS33" loc="AB14"/> <!-- Sch=SW3 -->
+    
+	<pin index="9"  name="rgbled_3bits_tri_o_0" iostandard="LVCMOS12" loc="A8"/> <!-- Sch=LD5_B -->
+    <pin index="10" name="rgbled_3bits_tri_o_1" iostandard="LVCMOS12" loc="B9"/> <!-- Sch=LD5_G -->
+    <pin index="11" name="rgbled_3bits_tri_o_2" iostandard="LVCMOS12" loc="C9"/> <!-- Sch=LD5_R -->
+
+    <pin index="12" name="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="J14"/> <!-- Sch=LD1 -->
+    <pin index="13" name="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="K14"/> <!-- Sch=LD2 -->
+    <pin index="14" name="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="L13"/> <!-- Sch=LD3 -->
+    <pin index="15" name="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="L14"/> <!-- Sch=LD4 -->
+
+    <pin index="16" name="JB1"  iostandard="LVCMOS33" loc="AE13"/> <!-- Sch=JB1  -->
+    <pin index="17" name="JB2"  iostandard="LVCMOS33" loc="AG14"/> <!-- Sch=JB2  -->
+    <pin index="18" name="JB3"  iostandard="LVCMOS33" loc="AH14"/> <!-- Sch=JB3  -->
+    <pin index="19" name="JB4"  iostandard="LVCMOS33" loc="AG13"/> <!-- Sch=JB4  -->
+    <pin index="20" name="JB7"  iostandard="LVCMOS33" loc="AE14"/> <!-- Sch=JB7  -->
+    <pin index="21" name="JB8"  iostandard="LVCMOS33" loc="AF13"/> <!-- Sch=JB8  -->
+    <pin index="22" name="JB9"  iostandard="LVCMOS33" loc="AE15"/> <!-- Sch=JB9  -->
+    <pin index="23" name="JB10" iostandard="LVCMOS33" loc="AH13"/> <!-- Sch=JB10 -->
+    
+	<pin index="24" name="JC1"  iostandard="LVCMOS33" loc="E13"/> <!-- Sch=JC1  -->
+    <pin index="25" name="JC2"  iostandard="LVCMOS33" loc="G13"/> <!-- Sch=JC2  -->
+    <pin index="26" name="JC3"  iostandard="LVCMOS33" loc="B13"/> <!-- Sch=JC3  -->
+    <pin index="27" name="JC4"  iostandard="LVCMOS33" loc="D14"/> <!-- Sch=JC4  -->
+    <pin index="28" name="JC7"  iostandard="LVCMOS33" loc="F13"/> <!-- Sch=JC7  -->
+    <pin index="29" name="JC8"  iostandard="LVCMOS33" loc="C13"/> <!-- Sch=JC8  -->
+    <pin index="30" name="JC9"  iostandard="LVCMOS33" loc="C14"/> <!-- Sch=JC9  -->
+    <pin index="31" name="JC10" iostandard="LVCMOS33" loc="A13"/> <!-- Sch=JC10 -->
+    
+	<pin index="32" name="JD1"  iostandard="LVCMOS33" loc="E15"/> <!-- Sch=JD1  -->
+    <pin index="33" name="JD2"  iostandard="LVCMOS33" loc="A14"/> <!-- Sch=JD2  -->
+    <pin index="34" name="JD3"  iostandard="LVCMOS33" loc="B15"/> <!-- Sch=JD3  -->
+    <pin index="35" name="JD4"  iostandard="LVCMOS33" loc="F15"/> <!-- Sch=JD4  -->
+    <pin index="36" name="JD7"  iostandard="LVCMOS33" loc="E14"/> <!-- Sch=JD7  -->
+    <pin index="37" name="JD8"  iostandard="LVCMOS33" loc="B14"/> <!-- Sch=JD8  -->
+    <pin index="38" name="JD9"  iostandard="LVCMOS33" loc="D15"/> <!-- Sch=JD9  -->
+    <pin index="39" name="JD10" iostandard="LVCMOS33" loc="A15"/> <!-- Sch=JD10 -->
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/preset.xml
new file mode 100644
index 0000000..0277e7f
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/B.0/preset.xml
@@ -0,0 +1,1008 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<!-- Contains IP configurations for Block/Connection Automation flows -->
+<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
+<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
+<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="zynq_ultra_ps_e_preset">
+		<ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" version="*">
+			<user_parameters>
+				<user_parameter name="CONFIG.PSU__PRESET_APPLIED" value="1"/>
+				<user_parameter name="CONFIG.PSU_BANK_0_IO_STANDARD" value="LVCMOS33"/>
+				<user_parameter name="CONFIG.PSU_BANK_1_IO_STANDARD" value="LVCMOS18"/>
+				<user_parameter name="CONFIG.PSU_BANK_2_IO_STANDARD" value="LVCMOS18"/>
+				<user_parameter name="CONFIG.PSU_BANK_3_IO_STANDARD" value="LVCMOS33"/>
+				<user_parameter name="CONFIG.PSU_DDR_RAM_HIGHADDR" value="0xFFFFFFFF"/>
+				<user_parameter name="CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET" value="0x800000000"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__ACT_DDR_FREQ_MHZ" value="930"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL" value="APLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED" value="0"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ" value="1200.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ" value="1200"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV" value="80"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED" value="0"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ" value="1200"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0" value="5"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ" value="250.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ" value="250.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL" value="DPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ" value="465.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ" value="933"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL" value="APLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ" value="600.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ" value="600"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV" value="93"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ" value="27.138"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0" value="16"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" value="RPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ" value="24.843750"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ" value="25"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0" value="15"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" value="RPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ" value="26.500000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ" value="27"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0" value="5"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" value="VPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ" value="300.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ" value="300"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" value="APLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ" value="600.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ" value="600"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ" value="500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" value="600"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0" value="5"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ" value="100.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL" value="DPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ" value="465.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ" value="533.333"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ" value="27.138"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ" value="500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" value="500"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0" value="30"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ" value="50.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ" value="50"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ" value="500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" value="500"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0" value="6"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ" value="250.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ" value="1500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ" value="1500"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ" value="27.138"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED" value="0"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL" value="RPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ" value="265.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" value="267"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0" value="15"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ" value="100.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ" value="500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" value="500"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0" value="8"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ" value="187.500000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ" value="200"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0" value="15"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0" value="4"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL" value="RPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV" value="53"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED" value="0"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ" value="25"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0" value="8"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ" value="187.500000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" value="200"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ" value="30.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0" value="25"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ" value="20.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ" value="20"/>
+				<user_parameter name="CONFIG.PSU__DDRC__AL" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__BANK_ADDR_COUNT" value="2"/>
+				<user_parameter name="CONFIG.PSU__DDRC__BUS_WIDTH" value="64 Bit"/>
+				<user_parameter name="CONFIG.PSU__DDRC__CL" value="12"/>
+				<user_parameter name="CONFIG.PSU__DDRC__CLOCK_STOP_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__COL_ADDR_COUNT" value="10"/>
+				<user_parameter name="CONFIG.PSU__DDRC__RANK_ADDR_COUNT" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__CWL" value="10"/>
+				<user_parameter name="CONFIG.PSU__DDRC__BG_ADDR_COUNT" value="2"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DEVICE_CAPACITY" value="4096 MBits"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DRAM_WIDTH" value="8 Bits"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ECC" value="Disabled"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ECC_SCRUB" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__FREQ_MHZ" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__MEMORY_TYPE" value="DDR 4"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ROW_ADDR_COUNT" value="15"/>
+				<user_parameter name="CONFIG.PSU__DDRC__SPEED_BIN" value="DDR4_1866L"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_FAW" value="30.0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_RAS_MIN" value="34"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_RC" value="47.06"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_RCD" value="12"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_RP" value="12"/>
+				<user_parameter name="CONFIG.PSU__DDRC__TRAIN_DATA_EYE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__TRAIN_READ_GATE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__VREF" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__BRC_MAPPING" value="ROW_BANK_COL"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__STATIC_RD_MODE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PWR_DOWN_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PLL_BYPASS" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_T_REF_MODE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_T_REF_RANGE" value="Normal (0-85)"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR3_T_REF_RANGE" value="NA"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE" value="NA"/>
+				<user_parameter name="CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE" value="NA"/>
+				<user_parameter name="CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE" value="NA"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PHY_DBI_MODE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DM_DBI" value="DM_NO_DBI"/>
+				<user_parameter name="CONFIG.PSU__DDRC__COMPONENTS" value="UDIMM"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PARITY_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_CRC_CONTROL" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__FGRM" value="1X"/>
+				<user_parameter name="CONFIG.PSU__DDRC__VENDOR_PART" value="OTHERS"/>
+				<user_parameter name="CONFIG.PSU__DDRC__SB_TARGET" value="12-12-12"/>
+				<user_parameter name="CONFIG.PSU__DDRC__LP_ASR" value="manual normal"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__SELF_REF_ABORT" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ADDR_MIRROR" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__EN_2ND_CLK" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PER_BANK_REFRESH" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE_DP_SWITCH" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE_2T_TIMING" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__RD_DQS_CENTER" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_0_3" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_4_7" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_8_11" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_12_15" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_16_19" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_20_23" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_24_27" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_28_31" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_32_35" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_36_39" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_40_43" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_44_47" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_48_51" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_52_55" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_56_59" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_60_63" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_64_67" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_68_71" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDR__INTERFACE__FREQMHZ" value="466.5"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__IO" value="GT Lane3"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__IO" value="GT Lane2"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DLL__ISUSED" value="1"/>
+				<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__IO" value="EMIO"/>
+				<user_parameter name="CONFIG.PSU__DP__LANE_SEL" value="Dual Higher"/>
+				<user_parameter name="CONFIG.PSU__DP__REF_CLK_FREQ" value="108"/>
+				<user_parameter name="CONFIG.PSU__DP__REF_CLK_SEL" value="Ref Clk2"/>
+				<user_parameter name="CONFIG.PSU__ENET0__GRP_MDIO__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__ENET0__GRP_MDIO__IO" value="MIO 76 .. 77"/>
+				<user_parameter name="CONFIG.PSU__ENET0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__ENET0__FIFO__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET0__PTP__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET0__PERIPHERAL__IO" value="MIO 26 .. 37"/>
+				<user_parameter name="CONFIG.PSU__ENET0__TSU__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__FIFO__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__PTP__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__GRP_MDIO__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__TSU__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__GPIO0_MIO__IO" value="MIO 0 .. 25"/>
+				<user_parameter name="CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__GPIO1_MIO__IO" value="MIO 26 .. 51"/>
+				<user_parameter name="CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO" value="3"/>
+				<user_parameter name="CONFIG.PSU__GPIO_EMIO_WIDTH" value="3"/>
+				<user_parameter name="CONFIG.PSU__GPIO_EMIO__WIDTH" value="[94:0]"/>
+				<user_parameter name="CONFIG.PSU__GT_REF_CLK__FREQMHZ" value="33.333"/>
+				<user_parameter name="CONFIG.PSU__GT__LINK_SPEED" value="HBR"/>
+				<user_parameter name="CONFIG.PSU__GT__VLT_SWNG_LVL_4" value="0"/>
+				<user_parameter name="CONFIG.PSU__GT__PRE_EMPH_LVL_4" value="0"/>
+				<user_parameter name="CONFIG.PSU__HIGH_ADDRESS__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__IO" value="MIO 22 .. 23"/>
+				<user_parameter name="CONFIG.PSU__I2C0__GRP_INT__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__IO" value="MIO 8 .. 9"/>
+				<user_parameter name="CONFIG.PSU__I2C1__GRP_INT__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO" value="MIO 7"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE0__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE0__IO" value="GT Lane0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE2__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE3__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__RESET__POLARITY" value="Active Low"/>
+				<user_parameter name="CONFIG.PSU__PCIE__REF_CLK_SEL" value="Ref Clk0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__REF_CLK_FREQ" value="100"/>
+				<user_parameter name="CONFIG.PSU__PCIE__DEVICE_PORT_TYPE" value="Root Port"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH" value="x1"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LINK_SPEED" value="5.0 Gb/s"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR0_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR0_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR0_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR0_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR1_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR1_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR1_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR1_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR2_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR2_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR2_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR2_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR3_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR3_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR3_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR3_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR4_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR4_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR4_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR4_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR5_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR5_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR5_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR5_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__EROM_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__EROM_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE" value="256 bytes"/>
+				<user_parameter name="CONFIG.PSU__PCIE__VENDOR_ID" value="0x10EE"/>
+				<user_parameter name="CONFIG.PSU__PCIE__DEVICE_ID" value="0xD011"/>
+				<user_parameter name="CONFIG.PSU__PCIE__REVISION_ID" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID" value="0x10EE"/>
+				<user_parameter name="CONFIG.PSU__PCIE__SUBSYSTEM_ID" value="0x7"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_BASE" value="0x06"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_SUB" value="0x04"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_VALUE" value="0x60400"/>
+				<user_parameter name="CONFIG.PSU__PCIE__AER_CAPABILITY" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__RECEIVER_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__SURPRISE_DOWN" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__FLOW_CONTROL_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__COMPLTION_TIMEOUT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__COMPLETER_ABORT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__RECEIVER_OVERFLOW" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ECRC_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ACS_VIOLAION" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MC_BLOCKED_TLP" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ACS_VIOLATION" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MULTIHEADER" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ECRC_CHECK" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ECRC_GEN" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CRS_SW_VISIBILITY" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__INTX_GENERATION" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSI_CAPABILITY" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_CAPABILITY" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_TABLE_SIZE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR" value=""/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_PBA_OFFSET" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR" value=""/>
+				<user_parameter name="CONFIG.PSU__PSS_REF_CLK__FREQMHZ" value="30"/>
+				<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__IO" value="MIO 0 .. 5"/>
+				<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__MODE" value="Single"/>
+				<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE" value="x4"/>
+				<user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__IO" value="MIO 6"/>
+				<user_parameter name="CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD" value="0"/>
+				<user_parameter name="CONFIG.PSU__QSPI_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__GRP_CD__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__GRP_POW__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__GRP_WP__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__RESET__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0_ROUTE_THROUGH_FPD" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD1__DATA_TRANSFER_MODE" value="8Bit"/>
+				<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__IO" value="MIO 39 .. 51"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_CD__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_CD__IO" value="MIO 45"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_POW__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_POW__IO" value="MIO 43"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_WP__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD1__SLOT_TYPE" value="SD 3.0"/>
+				<user_parameter name="CONFIG.PSU__SD1__RESET__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD1_ROUTE_THROUGH_FPD" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD1_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SPI0__PERIPHERAL__IO" value="MIO 12 .. 17"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS0__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS0__IO" value="MIO 15"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS1__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS1__IO" value="MIO 14"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS2__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI1__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI1__GRP_SS0__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI1__GRP_SS1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI1__GRP_SS2__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__TTC0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__TTC0__CLOCK__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__TTC0__WAVEOUT__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__TTC0__PERIPHERAL__IO" value="NA"/>
+				<user_parameter name="CONFIG.PSU__UART0__BAUD_RATE" value="115200"/>
+				<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__IO" value="MIO 18 .. 19"/>
+				<user_parameter name="CONFIG.PSU__UART0__MODEM__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__UART0_LOOP_UART1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__UART1__BAUD_RATE" value="115200"/>
+				<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__IO" value="EMIO"/>
+				<user_parameter name="CONFIG.PSU__UART1__MODEM__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB0__REF_CLK_SEL" value="Ref Clk0"/>
+				<user_parameter name="CONFIG.PSU__USB0__REF_CLK_FREQ" value="100"/>
+				<user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__IO" value="MIO 52 .. 63"/>
+				<user_parameter name="CONFIG.PSU__USB0__RESET__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB0_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB1__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__USB1__PERIPHERAL__IO" value="MIO 64 .. 75"/>
+				<user_parameter name="CONFIG.PSU__USB1__RESET__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB1_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__IO" value="GT Lane1"/>
+				<user_parameter name="CONFIG.PSU__USB3_0__EMIO__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB__RESET__MODE" value="Disable"/>
+				<user_parameter name="CONFIG.PSU__USE__IRQ0" value="1"/>
+				<user_parameter name="CONFIG.PSU__USE__S_AXI_GP0" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	
+	<ip_preset preset_proc_name="btn_5bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="switch_4bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="rgbled_3bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="led_4bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/board.xml
new file mode 100644
index 0000000..a369eb7
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/board.xml
@@ -0,0 +1,535 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.1" vendor="digilentinc.com" name="gzu_3eg" display_name="Genesys ZU-3EG" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">
+<compatible_board_revisions>
+	<revision id="0">D.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Genesys ZU-3EG</description>
+
+<components>
+	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
+	<component name="part0" display_name="Genesys ZU-3EG" type="fpga" part_name="xczu3eg-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">
+		<interfaces>
+			<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset"> 
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
+				</preferred_ips>
+			</interface>
+			<interface mode="master" name="btn_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_5bits" preset_proc="btn_5bits_preset">
+				<description>5 PL Buttons (Ordered "UCDLR")</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="btn_5bits_tri_i" dir="in" left="4" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="btn_5bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="btn_5bits_tri_i_1"/> 
+							<pin_map port_index="2" component_pin="btn_5bits_tri_i_2"/> 
+							<pin_map port_index="3" component_pin="btn_5bits_tri_i_3"/> 
+							<pin_map port_index="4" component_pin="btn_5bits_tri_i_4"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="switch_4bits" preset_proc="switch_4bits_preset">
+				<description>4 PL Switches</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="switch_4bits_tri_i" dir="in" left="3" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="switch_4bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="switch_4bits_tri_i_1"/> 
+							<pin_map port_index="2" component_pin="switch_4bits_tri_i_2"/> 
+							<pin_map port_index="3" component_pin="switch_4bits_tri_i_3"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="rgbled_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_3bits" preset_proc="rgbled_3bits_preset">
+				<description>PL RGB LED (ordered RGB)</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="rgbled_3bits_tri_o" dir="out" left="2" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="rgbled_3bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="rgbled_3bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="rgbled_3bits_tri_o_2"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+				<description>4 LEDs</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+							<pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jc">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jd">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+		</interfaces>
+	</component>
+	
+	<!-- Descriptions of components that will appear in the IPI Board tab -->
+	<component name="ps8_fixedio" display_name="PS8 Fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
+	<component name="btn_5bits" display_name="5 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+		<description>5 Buttons (Ordered "UCDLR")</description>
+	</component>
+	<component name="switch_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+		<description>4 Switches</description>
+	</component>
+	<component name="rgbled_3bits" display_name="1 RGB LED" type="chip" sub_type="led" major_group="GPIO">
+		<description>1 RGB LED (Ordered "RGB")</description>
+	</component>
+	<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+		<description>4 LEDs</description>
+	</component>
+	<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JB</description>
+	</component>
+	<component name="pmod_jc" display_name="Pmod Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JC</description>
+	</component>
+	<component name="pmod_jd" display_name="Pmod Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JD</description>
+	</component>
+</components>
+
+<jtag_chains>
+	<jtag_chain name="chain1">
+		<position name="0" component="part0"/>
+	</jtag_chain>
+</jtag_chains>
+
+<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
+	<connection name="part0_btn_5bits" component1="part0" component2="btn_5bits">
+		<connection_map name="part0_btn_5bits_map"    c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
+	</connection>
+	<connection name="part0_switch_4bits" component1="part0" component2="switch_4bits">
+		<connection_map name="part0_switch_4bits_map" c1_st_index="5" c1_end_index="8" c2_st_index="0" c2_end_index="3"/>
+	</connection>
+	<connection name="rgbled_3bits" component1="part0" component2="rgbled_3bits">
+		<connection_map name="part0_rgbled_3bits_map"    c1_st_index="9" c1_end_index="11" c2_st_index="0" c2_end_index="2"/>
+	</connection>
+	<connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+		<connection_map name="part0_led_4bits_map" c1_st_index="12" c1_end_index="15" c2_st_index="0" c2_end_index="3"/>
+	</connection>
+	<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
+		<connection_map name="part0_pmod_jb_map" c1_st_index="16" c1_end_index="23" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jc" component1="part0" component2="pmod_jc">
+		<connection_map name="part0_pmod_jc_map" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jd" component1="part0" component2="pmod_jd">
+		<connection_map name="part0_pmod_jd_map" c1_st_index="32" c1_end_index="39" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+</connections>
+
+</board>
\ No newline at end of file
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/part0_pins.xml
new file mode 100644
index 0000000..d9573ec
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/part0_pins.xml
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xczu3eg-sfvc784-1-e">
+<pins>
+	<pin index="0" name="btn_5bits_tri_i_0" iostandard="LVCMOS18" loc="A12"/> <!-- Sch=BTNR -->
+    <pin index="1" name="btn_5bits_tri_i_1" iostandard="LVCMOS18" loc="F12"/> <!-- Sch=BTNL -->
+	<pin index="2" name="btn_5bits_tri_i_2" iostandard="LVCMOS18" loc="J12"/> <!-- Sch=BTND -->
+    <pin index="3" name="btn_5bits_tri_i_3" iostandard="LVCMOS18" loc="H12"/> <!-- Sch=BTNC -->
+    <pin index="4" name="btn_5bits_tri_i_4" iostandard="LVCMOS18" loc="B10"/> <!-- Sch=BTNU -->
+
+    <pin index="5" name="switch_4bits_tri_i_0" iostandard="LVCMOS33" loc="AB15"/> <!-- Sch=SW0 -->
+    <pin index="6" name="switch_4bits_tri_i_1" iostandard="LVCMOS33" loc="W12"/>  <!-- Sch=SW1 -->
+    <pin index="7" name="switch_4bits_tri_i_2" iostandard="LVCMOS33" loc="Y13"/>  <!-- Sch=SW2 -->
+    <pin index="8" name="switch_4bits_tri_i_3" iostandard="LVCMOS33" loc="AB14"/> <!-- Sch=SW3 -->
+    
+	<pin index="9"  name="rgbled_3bits_tri_o_0" iostandard="LVCMOS12" loc="A8"/> <!-- Sch=LD5_B -->
+    <pin index="10" name="rgbled_3bits_tri_o_1" iostandard="LVCMOS12" loc="B9"/> <!-- Sch=LD5_G -->
+    <pin index="11" name="rgbled_3bits_tri_o_2" iostandard="LVCMOS12" loc="C9"/> <!-- Sch=LD5_R -->
+
+    <pin index="12" name="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="J14"/> <!-- Sch=LD1 -->
+    <pin index="13" name="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="K14"/> <!-- Sch=LD2 -->
+    <pin index="14" name="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="L13"/> <!-- Sch=LD3 -->
+    <pin index="15" name="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="L14"/> <!-- Sch=LD4 -->
+
+    <pin index="16" name="JB1"  iostandard="LVCMOS33" loc="AE13"/> <!-- Sch=JB1  -->
+    <pin index="17" name="JB2"  iostandard="LVCMOS33" loc="AG14"/> <!-- Sch=JB2  -->
+    <pin index="18" name="JB3"  iostandard="LVCMOS33" loc="AH14"/> <!-- Sch=JB3  -->
+    <pin index="19" name="JB4"  iostandard="LVCMOS33" loc="AG13"/> <!-- Sch=JB4  -->
+    <pin index="20" name="JB7"  iostandard="LVCMOS33" loc="AE14"/> <!-- Sch=JB7  -->
+    <pin index="21" name="JB8"  iostandard="LVCMOS33" loc="AF13"/> <!-- Sch=JB8  -->
+    <pin index="22" name="JB9"  iostandard="LVCMOS33" loc="AE15"/> <!-- Sch=JB9  -->
+    <pin index="23" name="JB10" iostandard="LVCMOS33" loc="AH13"/> <!-- Sch=JB10 -->
+    
+	<pin index="24" name="JC1"  iostandard="LVCMOS33" loc="E13"/> <!-- Sch=JC1  -->
+    <pin index="25" name="JC2"  iostandard="LVCMOS33" loc="G13"/> <!-- Sch=JC2  -->
+    <pin index="26" name="JC3"  iostandard="LVCMOS33" loc="B13"/> <!-- Sch=JC3  -->
+    <pin index="27" name="JC4"  iostandard="LVCMOS33" loc="D14"/> <!-- Sch=JC4  -->
+    <pin index="28" name="JC7"  iostandard="LVCMOS33" loc="F13"/> <!-- Sch=JC7  -->
+    <pin index="29" name="JC8"  iostandard="LVCMOS33" loc="C13"/> <!-- Sch=JC8  -->
+    <pin index="30" name="JC9"  iostandard="LVCMOS33" loc="C14"/> <!-- Sch=JC9  -->
+    <pin index="31" name="JC10" iostandard="LVCMOS33" loc="A13"/> <!-- Sch=JC10 -->
+    
+	<pin index="32" name="JD1"  iostandard="LVCMOS33" loc="E15"/> <!-- Sch=JD1  -->
+    <pin index="33" name="JD2"  iostandard="LVCMOS33" loc="A14"/> <!-- Sch=JD2  -->
+    <pin index="34" name="JD3"  iostandard="LVCMOS33" loc="B15"/> <!-- Sch=JD3  -->
+    <pin index="35" name="JD4"  iostandard="LVCMOS33" loc="F15"/> <!-- Sch=JD4  -->
+    <pin index="36" name="JD7"  iostandard="LVCMOS33" loc="E14"/> <!-- Sch=JD7  -->
+    <pin index="37" name="JD8"  iostandard="LVCMOS33" loc="B14"/> <!-- Sch=JD8  -->
+    <pin index="38" name="JD9"  iostandard="LVCMOS33" loc="D15"/> <!-- Sch=JD9  -->
+    <pin index="39" name="JD10" iostandard="LVCMOS33" loc="A15"/> <!-- Sch=JD10 -->
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/preset.xml
new file mode 100644
index 0000000..74e3cb1
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-3eg/D.0/preset.xml
@@ -0,0 +1,1008 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<!-- Contains IP configurations for Block/Connection Automation flows -->
+<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
+<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
+<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="zynq_ultra_ps_e_preset">
+		<ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" version="*">
+			<user_parameters>
+				<user_parameter name="CONFIG.PSU__PRESET_APPLIED" value="1"/>
+				<user_parameter name="CONFIG.PSU_BANK_0_IO_STANDARD" value="LVCMOS33"/>
+				<user_parameter name="CONFIG.PSU_BANK_1_IO_STANDARD" value="LVCMOS18"/>
+				<user_parameter name="CONFIG.PSU_BANK_2_IO_STANDARD" value="LVCMOS18"/>
+				<user_parameter name="CONFIG.PSU_BANK_3_IO_STANDARD" value="LVCMOS33"/>
+				<user_parameter name="CONFIG.PSU_DDR_RAM_HIGHADDR" value="0xFFFFFFFF"/>
+				<user_parameter name="CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET" value="0x800000000"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_0_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_1_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_2_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_3_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_4_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_5_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_6_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_7_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_8_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_9_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_10_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_11_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_12_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_13_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_14_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_15_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_16_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_17_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_18_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_19_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_20_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_21_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_22_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_23_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_24_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_25_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_26_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_27_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_28_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_29_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_30_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_DRIVE_STRENGTH" value="8"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_31_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_32_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_33_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_34_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_35_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_36_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_37_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_38_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_39_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_40_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_41_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_42_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_43_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_44_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_45_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_46_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_47_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_48_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_49_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_50_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_51_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_52_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_53_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_54_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_55_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_56_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_57_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_58_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_59_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_60_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_61_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_62_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_63_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_64_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_65_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_66_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_PULLUPDOWN" value="pulldown"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_67_DIRECTION" value="in"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_68_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_69_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_70_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_71_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_72_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_73_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_74_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_DRIVE_STRENGTH" value="12"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_INPUT_TYPE" value="schmitt"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_SLEW" value="fast"/>
+				<user_parameter name="CONFIG.PSU_MIO_75_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_PULLUPDOWN" value="pullup"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_76_DIRECTION" value="out"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_PULLUPDOWN" value="disable"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_DRIVE_STRENGTH" value="4"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_POLARITY" value="Default"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_INPUT_TYPE" value="cmos"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_SLEW" value="slow"/>
+				<user_parameter name="CONFIG.PSU_MIO_77_DIRECTION" value="inout"/>
+				<user_parameter name="CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__ACT_DDR_FREQ_MHZ" value="930"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL" value="APLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED" value="0"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ" value="1200.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ" value="1200"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV" value="80"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED" value="0"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ" value="1200"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0" value="5"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ" value="250.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ" value="250.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL" value="DPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ" value="465.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ" value="933"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL" value="APLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ" value="600.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ" value="600"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV" value="93"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ" value="27.138"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0" value="16"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" value="RPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ" value="24.843750"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ" value="25"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0" value="15"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" value="RPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ" value="26.500000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ" value="27"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0" value="5"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" value="VPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ" value="300.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ" value="300"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" value="APLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ" value="600.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ" value="600"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ" value="500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" value="600"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0" value="5"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ" value="100.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL" value="DPLL"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ" value="465.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ" value="533.333"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ" value="27.138"/>
+				<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ" value="500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" value="500"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0" value="30"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ" value="50.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ" value="50"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ" value="500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" value="500"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0" value="6"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ" value="250.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ" value="250"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ" value="1500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ" value="1500"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ" value="27.138"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED" value="0"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL" value="RPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ" value="265.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" value="267"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0" value="15"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ" value="100.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ" value="500.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" value="500"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0" value="8"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ" value="187.500000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ" value="200"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0" value="15"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0" value="4"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL" value="RPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA" value="0.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV" value="53"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0" value="2"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED" value="0"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ" value="25"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0" value="8"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ" value="187.500000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" value="200"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ" value="30.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" value="100"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0" value="25"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1" value="3"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" value="IOPLL"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ" value="20.000000"/>
+				<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ" value="20"/>
+				<user_parameter name="CONFIG.PSU__DDRC__AL" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__BANK_ADDR_COUNT" value="2"/>
+				<user_parameter name="CONFIG.PSU__DDRC__BUS_WIDTH" value="64 Bit"/>
+				<user_parameter name="CONFIG.PSU__DDRC__CL" value="12"/>
+				<user_parameter name="CONFIG.PSU__DDRC__CLOCK_STOP_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__COL_ADDR_COUNT" value="10"/>
+				<user_parameter name="CONFIG.PSU__DDRC__RANK_ADDR_COUNT" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__CWL" value="10"/>
+				<user_parameter name="CONFIG.PSU__DDRC__BG_ADDR_COUNT" value="2"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DEVICE_CAPACITY" value="4096 MBits"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DRAM_WIDTH" value="8 Bits"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ECC" value="Disabled"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ECC_SCRUB" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__FREQ_MHZ" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__MEMORY_TYPE" value="DDR 4"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ROW_ADDR_COUNT" value="15"/>
+				<user_parameter name="CONFIG.PSU__DDRC__SPEED_BIN" value="DDR4_1866L"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_FAW" value="30.0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_RAS_MIN" value="34"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_RC" value="47.06"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_RCD" value="12"/>
+				<user_parameter name="CONFIG.PSU__DDRC__T_RP" value="12"/>
+				<user_parameter name="CONFIG.PSU__DDRC__TRAIN_DATA_EYE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__TRAIN_READ_GATE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__VREF" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__BRC_MAPPING" value="ROW_BANK_COL"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__STATIC_RD_MODE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PWR_DOWN_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PLL_BYPASS" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_T_REF_MODE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_T_REF_RANGE" value="Normal (0-85)"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR3_T_REF_RANGE" value="NA"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE" value="NA"/>
+				<user_parameter name="CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE" value="NA"/>
+				<user_parameter name="CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE" value="NA"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PHY_DBI_MODE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DM_DBI" value="DM_NO_DBI"/>
+				<user_parameter name="CONFIG.PSU__DDRC__COMPONENTS" value="UDIMM"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PARITY_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_CRC_CONTROL" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__FGRM" value="1X"/>
+				<user_parameter name="CONFIG.PSU__DDRC__VENDOR_PART" value="OTHERS"/>
+				<user_parameter name="CONFIG.PSU__DDRC__SB_TARGET" value="12-12-12"/>
+				<user_parameter name="CONFIG.PSU__DDRC__LP_ASR" value="manual normal"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__SELF_REF_ABORT" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ADDR_MIRROR" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__EN_2ND_CLK" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__PER_BANK_REFRESH" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE_DP_SWITCH" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__ENABLE_2T_TIMING" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__RD_DQS_CENTER" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_0_3" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_4_7" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_8_11" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_12_15" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_16_19" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_20_23" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_24_27" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_28_31" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_32_35" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_36_39" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_40_43" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_44_47" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_48_51" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_52_55" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_56_59" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_60_63" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_64_67" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDRC__DQMAP_68_71" value="0"/>
+				<user_parameter name="CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DDR__INTERFACE__FREQMHZ" value="466.5"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__IO" value="GT Lane3"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__IO" value="GT Lane2"/>
+				<user_parameter name="CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DLL__ISUSED" value="1"/>
+				<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__IO" value="EMIO"/>
+				<user_parameter name="CONFIG.PSU__DP__LANE_SEL" value="Dual Higher"/>
+				<user_parameter name="CONFIG.PSU__DP__REF_CLK_FREQ" value="108"/>
+				<user_parameter name="CONFIG.PSU__DP__REF_CLK_SEL" value="Ref Clk2"/>
+				<user_parameter name="CONFIG.PSU__ENET0__GRP_MDIO__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__ENET0__GRP_MDIO__IO" value="MIO 76 .. 77"/>
+				<user_parameter name="CONFIG.PSU__ENET0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__ENET0__FIFO__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET0__PTP__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET0__PERIPHERAL__IO" value="MIO 26 .. 37"/>
+				<user_parameter name="CONFIG.PSU__ENET0__TSU__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__FIFO__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__PTP__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__GRP_MDIO__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__ENET1__TSU__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__GPIO0_MIO__IO" value="MIO 0 .. 25"/>
+				<user_parameter name="CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__GPIO1_MIO__IO" value="MIO 26 .. 51"/>
+				<user_parameter name="CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO" value="3"/>
+				<user_parameter name="CONFIG.PSU__GPIO_EMIO_WIDTH" value="3"/>
+				<user_parameter name="CONFIG.PSU__GPIO_EMIO__WIDTH" value="[94:0]"/>
+				<user_parameter name="CONFIG.PSU__GT_REF_CLK__FREQMHZ" value="33.333"/>
+				<user_parameter name="CONFIG.PSU__GT__LINK_SPEED" value="HBR"/>
+				<user_parameter name="CONFIG.PSU__GT__VLT_SWNG_LVL_4" value="0"/>
+				<user_parameter name="CONFIG.PSU__GT__PRE_EMPH_LVL_4" value="0"/>
+				<user_parameter name="CONFIG.PSU__HIGH_ADDRESS__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__IO" value="MIO 22 .. 23"/>
+				<user_parameter name="CONFIG.PSU__I2C0__GRP_INT__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__IO" value="MIO 8 .. 9"/>
+				<user_parameter name="CONFIG.PSU__I2C1__GRP_INT__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO" value="MIO 7"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE0__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE0__IO" value="GT Lane0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE2__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LANE3__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__RESET__POLARITY" value="Active Low"/>
+				<user_parameter name="CONFIG.PSU__PCIE__REF_CLK_SEL" value="Ref Clk0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__REF_CLK_FREQ" value="100"/>
+				<user_parameter name="CONFIG.PSU__PCIE__DEVICE_PORT_TYPE" value="Root Port"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH" value="x1"/>
+				<user_parameter name="CONFIG.PSU__PCIE__LINK_SPEED" value="5.0 Gb/s"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR0_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR0_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR0_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR0_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR1_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR1_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR1_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR1_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR2_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR2_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR2_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR2_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR3_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR3_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR3_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR3_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR4_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR4_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR4_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR4_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR5_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR5_64BIT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR5_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__BAR5_PREFETCHABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__EROM_ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__EROM_VAL" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE" value="256 bytes"/>
+				<user_parameter name="CONFIG.PSU__PCIE__VENDOR_ID" value="0x10EE"/>
+				<user_parameter name="CONFIG.PSU__PCIE__DEVICE_ID" value="0xD011"/>
+				<user_parameter name="CONFIG.PSU__PCIE__REVISION_ID" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID" value="0x10EE"/>
+				<user_parameter name="CONFIG.PSU__PCIE__SUBSYSTEM_ID" value="0x7"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_BASE" value="0x06"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_SUB" value="0x04"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE" value="0x0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_VALUE" value="0x60400"/>
+				<user_parameter name="CONFIG.PSU__PCIE__AER_CAPABILITY" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__RECEIVER_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__SURPRISE_DOWN" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__FLOW_CONTROL_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__COMPLTION_TIMEOUT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__COMPLETER_ABORT" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__RECEIVER_OVERFLOW" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ECRC_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ACS_VIOLAION" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MC_BLOCKED_TLP" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ACS_VIOLATION" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MULTIHEADER" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ECRC_CHECK" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__ECRC_GEN" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__CRS_SW_VISIBILITY" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__INTX_GENERATION" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSI_CAPABILITY" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_CAPABILITY" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_TABLE_SIZE" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR" value=""/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_PBA_OFFSET" value="0"/>
+				<user_parameter name="CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR" value=""/>
+				<user_parameter name="CONFIG.PSU__PSS_REF_CLK__FREQMHZ" value="30"/>
+				<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__IO" value="MIO 0 .. 5"/>
+				<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__MODE" value="Single"/>
+				<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE" value="x4"/>
+				<user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__IO" value="MIO 6"/>
+				<user_parameter name="CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD" value="0"/>
+				<user_parameter name="CONFIG.PSU__QSPI_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__GRP_CD__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__GRP_POW__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__GRP_WP__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0__RESET__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0_ROUTE_THROUGH_FPD" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD0_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD1__DATA_TRANSFER_MODE" value="8Bit"/>
+				<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__IO" value="MIO 39 .. 51"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_CD__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_CD__IO" value="MIO 45"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_POW__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_POW__IO" value="MIO 43"/>
+				<user_parameter name="CONFIG.PSU__SD1__GRP_WP__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD1__SLOT_TYPE" value="SD 3.0"/>
+				<user_parameter name="CONFIG.PSU__SD1__RESET__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD1_ROUTE_THROUGH_FPD" value="0"/>
+				<user_parameter name="CONFIG.PSU__SD1_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SPI0__PERIPHERAL__IO" value="MIO 12 .. 17"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS0__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS0__IO" value="MIO 15"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS1__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS1__IO" value="MIO 14"/>
+				<user_parameter name="CONFIG.PSU__SPI0__GRP_SS2__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI1__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI1__GRP_SS0__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI1__GRP_SS1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__SPI1__GRP_SS2__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__TTC0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__TTC0__CLOCK__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__TTC0__WAVEOUT__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__TTC0__PERIPHERAL__IO" value="NA"/>
+				<user_parameter name="CONFIG.PSU__UART0__BAUD_RATE" value="115200"/>
+				<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__IO" value="MIO 18 .. 19"/>
+				<user_parameter name="CONFIG.PSU__UART0__MODEM__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__UART0_LOOP_UART1__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__UART1__BAUD_RATE" value="115200"/>
+				<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__IO" value="EMIO"/>
+				<user_parameter name="CONFIG.PSU__UART1__MODEM__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB0__REF_CLK_SEL" value="Ref Clk0"/>
+				<user_parameter name="CONFIG.PSU__USB0__REF_CLK_FREQ" value="100"/>
+				<user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__IO" value="MIO 52 .. 63"/>
+				<user_parameter name="CONFIG.PSU__USB0__RESET__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB0_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB1__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__USB1__PERIPHERAL__IO" value="MIO 64 .. 75"/>
+				<user_parameter name="CONFIG.PSU__USB1__RESET__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB1_COHERENCY" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE" value="1"/>
+				<user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__IO" value="GT Lane1"/>
+				<user_parameter name="CONFIG.PSU__USB3_0__EMIO__ENABLE" value="0"/>
+				<user_parameter name="CONFIG.PSU__USB__RESET__MODE" value="Disable"/>
+				<user_parameter name="CONFIG.PSU__USE__IRQ0" value="1"/>
+				<user_parameter name="CONFIG.PSU__USE__S_AXI_GP0" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	
+	<ip_preset preset_proc_name="btn_5bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="switch_4bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="rgbled_3bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="led_4bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/board.xml
new file mode 100644
index 0000000..67547b9
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/board.xml
@@ -0,0 +1,535 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.1" vendor="digilentinc.com" name="gzu_5ev" display_name="Genesys ZU-5EV" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">
+<compatible_board_revisions>
+	<revision id="0">C.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Genesys ZU-5EV</description>
+
+<components>
+	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
+	<component name="part0" display_name="Genesys ZU-5EV" type="fpga" part_name="xczu5ev-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">
+		<interfaces>
+			<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset"> 
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
+				</preferred_ips>
+			</interface>
+			<interface mode="master" name="btn_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_5bits" preset_proc="btn_5bits_preset">
+				<description>5 PL Buttons (Ordered "UCDLR")</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="btn_5bits_tri_i" dir="in" left="4" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="btn_5bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="btn_5bits_tri_i_1"/> 
+							<pin_map port_index="2" component_pin="btn_5bits_tri_i_2"/> 
+							<pin_map port_index="3" component_pin="btn_5bits_tri_i_3"/> 
+							<pin_map port_index="4" component_pin="btn_5bits_tri_i_4"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="switch_4bits" preset_proc="switch_4bits_preset">
+				<description>4 PL Switches</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="switch_4bits_tri_i" dir="in" left="3" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="switch_4bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="switch_4bits_tri_i_1"/> 
+							<pin_map port_index="2" component_pin="switch_4bits_tri_i_2"/> 
+							<pin_map port_index="3" component_pin="switch_4bits_tri_i_3"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="rgbled_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_3bits" preset_proc="rgbled_3bits_preset">
+				<description>PL RGB LED (ordered RGB)</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="rgbled_3bits_tri_o" dir="out" left="2" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="rgbled_3bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="rgbled_3bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="rgbled_3bits_tri_o_2"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+				<description>4 LEDs</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+							<pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jc">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JC10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jd">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JD10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+		</interfaces>
+	</component>
+	
+	<!-- Descriptions of components that will appear in the IPI Board tab -->
+	<component name="ps8_fixedio" display_name="PS8 Fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
+	<component name="btn_5bits" display_name="5 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+		<description>5 Buttons (Ordered "UCDLR")</description>
+	</component>
+	<component name="switch_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+		<description>4 Switches</description>
+	</component>
+	<component name="rgbled_3bits" display_name="1 RGB LED" type="chip" sub_type="led" major_group="GPIO">
+		<description>1 RGB LED (Ordered "RGB")</description>
+	</component>
+	<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+		<description>4 LEDs</description>
+	</component>
+	<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JB</description>
+	</component>
+	<component name="pmod_jc" display_name="Pmod Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JC</description>
+	</component>
+	<component name="pmod_jd" display_name="Pmod Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JD</description>
+	</component>
+</components>
+
+<jtag_chains>
+	<jtag_chain name="chain1">
+		<position name="0" component="part0"/>
+	</jtag_chain>
+</jtag_chains>
+
+<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
+	<connection name="part0_btn_5bits" component1="part0" component2="btn_5bits">
+		<connection_map name="part0_btn_5bits_map"    c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
+	</connection>
+	<connection name="part0_switch_4bits" component1="part0" component2="switch_4bits">
+		<connection_map name="part0_switch_4bits_map" c1_st_index="5" c1_end_index="8" c2_st_index="0" c2_end_index="3"/>
+	</connection>
+	<connection name="rgbled_3bits" component1="part0" component2="rgbled_3bits">
+		<connection_map name="part0_rgbled_3bits_map"    c1_st_index="9" c1_end_index="11" c2_st_index="0" c2_end_index="2"/>
+	</connection>
+	<connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+		<connection_map name="part0_led_4bits_map" c1_st_index="12" c1_end_index="15" c2_st_index="0" c2_end_index="3"/>
+	</connection>
+	<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
+		<connection_map name="part0_pmod_jb_map" c1_st_index="16" c1_end_index="23" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jc" component1="part0" component2="pmod_jc">
+		<connection_map name="part0_pmod_jc_map" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jd" component1="part0" component2="pmod_jd">
+		<connection_map name="part0_pmod_jd_map" c1_st_index="32" c1_end_index="39" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+</connections>
+
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/changelog.txt b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/changelog.txt
new file mode 100644
index 0000000..dfd51fb
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/changelog.txt
@@ -0,0 +1,2 @@
+1.1 Fixed PSU__DDRC__DDR4_ADDR_MAPPING appearing twice and with conflicting values that was causing a silent FSBL failure in the boot process.
+1.0. Genesys ZU-ZU5EV initial board support for rev C. 
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/part0_pins.xml
new file mode 100644
index 0000000..e219652
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/part0_pins.xml
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xczu5ev-sfvc784-1-e">
+<pins>
+	<pin index="0" name="btn_5bits_tri_i_0" iostandard="LVCMOS18" loc="A12"/> <!-- Sch=BTNR -->
+    <pin index="1" name="btn_5bits_tri_i_1" iostandard="LVCMOS18" loc="F12"/> <!-- Sch=BTNL -->
+	<pin index="2" name="btn_5bits_tri_i_2" iostandard="LVCMOS18" loc="J12"/> <!-- Sch=BTND -->
+    <pin index="3" name="btn_5bits_tri_i_3" iostandard="LVCMOS18" loc="H12"/> <!-- Sch=BTNC -->
+    <pin index="4" name="btn_5bits_tri_i_4" iostandard="LVCMOS18" loc="B10"/> <!-- Sch=BTNU -->
+
+    <pin index="5" name="switch_4bits_tri_i_0" iostandard="LVCMOS33" loc="AB15"/> <!-- Sch=SW0 -->
+    <pin index="6" name="switch_4bits_tri_i_1" iostandard="LVCMOS33" loc="W12"/>  <!-- Sch=SW1 -->
+    <pin index="7" name="switch_4bits_tri_i_2" iostandard="LVCMOS33" loc="Y13"/>  <!-- Sch=SW2 -->
+    <pin index="8" name="switch_4bits_tri_i_3" iostandard="LVCMOS33" loc="AB14"/> <!-- Sch=SW3 -->
+    
+	<pin index="9"  name="rgbled_3bits_tri_o_0" iostandard="LVCMOS12" loc="A8"/> <!-- Sch=LD5_B -->
+    <pin index="10" name="rgbled_3bits_tri_o_1" iostandard="LVCMOS12" loc="B9"/> <!-- Sch=LD5_G -->
+    <pin index="11" name="rgbled_3bits_tri_o_2" iostandard="LVCMOS12" loc="C9"/> <!-- Sch=LD5_R -->
+
+    <pin index="12" name="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="J14"/> <!-- Sch=LD1 -->
+    <pin index="13" name="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="K14"/> <!-- Sch=LD2 -->
+    <pin index="14" name="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="L13"/> <!-- Sch=LD3 -->
+    <pin index="15" name="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="L14"/> <!-- Sch=LD4 -->
+
+    <pin index="16" name="JB1"  iostandard="LVCMOS33" loc="AE13"/> <!-- Sch=JB1  -->
+    <pin index="17" name="JB2"  iostandard="LVCMOS33" loc="AG14"/> <!-- Sch=JB2  -->
+    <pin index="18" name="JB3"  iostandard="LVCMOS33" loc="AH14"/> <!-- Sch=JB3  -->
+    <pin index="19" name="JB4"  iostandard="LVCMOS33" loc="AG13"/> <!-- Sch=JB4  -->
+    <pin index="20" name="JB7"  iostandard="LVCMOS33" loc="AE14"/> <!-- Sch=JB7  -->
+    <pin index="21" name="JB8"  iostandard="LVCMOS33" loc="AF13"/> <!-- Sch=JB8  -->
+    <pin index="22" name="JB9"  iostandard="LVCMOS33" loc="AE15"/> <!-- Sch=JB9  -->
+    <pin index="23" name="JB10" iostandard="LVCMOS33" loc="AH13"/> <!-- Sch=JB10 -->
+    
+	<pin index="24" name="JC1"  iostandard="LVCMOS33" loc="E13"/> <!-- Sch=JC1  -->
+    <pin index="25" name="JC2"  iostandard="LVCMOS33" loc="G13"/> <!-- Sch=JC2  -->
+    <pin index="26" name="JC3"  iostandard="LVCMOS33" loc="B13"/> <!-- Sch=JC3  -->
+    <pin index="27" name="JC4"  iostandard="LVCMOS33" loc="D14"/> <!-- Sch=JC4  -->
+    <pin index="28" name="JC7"  iostandard="LVCMOS33" loc="F13"/> <!-- Sch=JC7  -->
+    <pin index="29" name="JC8"  iostandard="LVCMOS33" loc="C13"/> <!-- Sch=JC8  -->
+    <pin index="30" name="JC9"  iostandard="LVCMOS33" loc="C14"/> <!-- Sch=JC9  -->
+    <pin index="31" name="JC10" iostandard="LVCMOS33" loc="A13"/> <!-- Sch=JC10 -->
+    
+	<pin index="32" name="JD1"  iostandard="LVCMOS33" loc="E15"/> <!-- Sch=JD1  -->
+    <pin index="33" name="JD2"  iostandard="LVCMOS33" loc="A14"/> <!-- Sch=JD2  -->
+    <pin index="34" name="JD3"  iostandard="LVCMOS33" loc="B15"/> <!-- Sch=JD3  -->
+    <pin index="35" name="JD4"  iostandard="LVCMOS33" loc="F15"/> <!-- Sch=JD4  -->
+    <pin index="36" name="JD7"  iostandard="LVCMOS33" loc="E14"/> <!-- Sch=JD7  -->
+    <pin index="37" name="JD8"  iostandard="LVCMOS33" loc="B14"/> <!-- Sch=JD8  -->
+    <pin index="38" name="JD9"  iostandard="LVCMOS33" loc="D15"/> <!-- Sch=JD9  -->
+    <pin index="39" name="JD10" iostandard="LVCMOS33" loc="A15"/> <!-- Sch=JD10 -->
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/preset.xml
new file mode 100644
index 0000000..6b68a75
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/preset.xml
@@ -0,0 +1,1215 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<!-- Contains IP configurations for Block/Connection Automation flows -->
+<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
+<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
+<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="zynq_ultra_ps_e_preset">
+		<ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" version="*">
+			<user_parameters>
+		<user_parameter name="CONFIG.PSU__PRESET_APPLIED" value="1"/> 
+		<user_parameter name="CONFIG.PSU_BANK_0_IO_STANDARD" value="LVCMOS33"/>
+		<user_parameter name="CONFIG.PSU_BANK_1_IO_STANDARD" value="LVCMOS18"/>
+		<user_parameter name="CONFIG.PSU_BANK_2_IO_STANDARD" value="LVCMOS18"/>
+		<user_parameter name="CONFIG.PSU_BANK_3_IO_STANDARD" value="LVCMOS33"/>
+		<user_parameter name="CONFIG.PSU_DDR_RAM_HIGHADDR" value="0xFFFFFFFF"/>
+		<user_parameter name="CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET" value="0x800000000"/>
+		<user_parameter name="CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET" value="0x80000000"/>
+		<user_parameter name="CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN" value="1"/>
+		<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ENABLE" value="1"/> 
+		<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO" value="MIO 7"/>		
+		<user_parameter name="CONFIG.PSU__PCIE__LANE0__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__PCIE__LANE0__IO" value="GT Lane0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__LANE1__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__LANE2__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__LANE3__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__RESET__POLARITY" value="Active Low"/>
+		<user_parameter name="CONFIG.PSU__PCIE__DEVICE_PORT_TYPE" value="Root Port"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH" value="x1"/>
+		<user_parameter name="CONFIG.PSU__PCIE__LINK_SPEED" value="5.0 Gb/s"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR0_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR0_64BIT" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR0_VAL" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR0_PREFETCHABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR1_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR1_64BIT" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR1_VAL" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR1_PREFETCHABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR2_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR2_64BIT" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR2_VAL" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR2_PREFETCHABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR3_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR3_64BIT" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR3_VAL" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR3_PREFETCHABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR4_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR4_64BIT" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR4_VAL" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR4_PREFETCHABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR5_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR5_64BIT" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR5_VAL" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__BAR5_PREFETCHABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__EROM_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__EROM_VAL" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE" value="256 bytes"/>
+		<user_parameter name="CONFIG.PSU__PCIE__VENDOR_ID" value="0x10EE"/>
+		<user_parameter name="CONFIG.PSU__PCIE__DEVICE_ID" value="0xD011"/>
+		<user_parameter name="CONFIG.PSU__PCIE__REVISION_ID" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID" value="0x10EE"/>
+		<user_parameter name="CONFIG.PSU__PCIE__SUBSYSTEM_ID" value="0x7"/>
+		<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_BASE" value="0x06"/>
+		<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_SUB" value="0x04"/>
+		<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE" value="0x0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__CLASS_CODE_VALUE" value="0x60400"/>
+		<user_parameter name="CONFIG.PSU__PCIE__AER_CAPABILITY" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__RECEIVER_ERR" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__SURPRISE_DOWN" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__FLOW_CONTROL_ERR" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__COMPLTION_TIMEOUT" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__COMPLETER_ABORT" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__RECEIVER_OVERFLOW" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__ECRC_ERR" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__ACS_VIOLAION" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MC_BLOCKED_TLP" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__ACS_VIOLATION" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MULTIHEADER" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__ECRC_CHECK" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__ECRC_GEN" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__CRS_SW_VISIBILITY" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__INTX_GENERATION" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MSI_CAPABILITY" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MSIX_CAPABILITY" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MSIX_TABLE_SIZE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR" value=""/>
+		<user_parameter name="CONFIG.PSU__PCIE__MSIX_PBA_OFFSET" value="0"/>
+		<user_parameter name="CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR" value=""/>
+		<user_parameter name="CONFIG.PSU_MIO_0_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_0_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_0_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_0_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_0_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_0_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_1_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_1_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_1_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_1_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_1_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_1_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_2_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_2_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_2_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_2_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_2_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_2_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_3_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_3_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_3_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_3_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_3_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_3_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_4_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_4_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_4_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_4_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_4_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_4_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_5_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_5_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_5_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_5_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_5_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_5_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_6_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_6_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_6_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_6_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_6_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_6_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_7_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_7_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_7_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_7_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_7_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_7_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_8_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_8_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_8_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_8_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_8_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_8_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_9_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_9_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_9_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_9_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_9_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_9_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_10_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_10_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_10_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_10_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_10_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_10_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_11_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_11_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_11_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_11_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_11_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_11_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_12_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_12_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_12_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_12_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_12_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_12_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_13_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_13_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_13_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_13_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_13_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_13_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_14_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_14_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_14_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_14_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_14_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_14_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_15_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_15_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_15_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_15_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_15_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_15_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_16_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_16_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_16_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_16_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_16_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_16_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_17_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_17_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_17_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_17_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_17_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_17_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_18_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_18_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_18_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_18_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_18_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_18_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_19_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_19_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_19_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_19_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_19_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_19_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_20_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_20_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_20_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_20_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_20_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_20_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_21_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_21_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_21_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_21_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_21_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_21_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_22_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_22_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_22_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_22_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_22_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_22_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_23_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_23_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_23_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_23_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_23_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_23_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_24_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_24_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_24_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_24_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_24_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_24_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_25_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_25_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_25_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_25_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_25_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_25_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_26_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_26_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_26_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_26_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_26_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_26_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_27_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_27_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_27_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_27_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_27_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_27_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_28_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_28_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_28_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_28_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_28_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_28_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_29_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_29_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_29_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_29_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_29_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_29_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_30_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_30_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_30_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_30_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_30_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_30_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_31_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_31_DRIVE_STRENGTH" value="8"/>
+		<user_parameter name="CONFIG.PSU_MIO_31_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_31_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_31_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_31_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_32_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_32_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_32_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_32_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_32_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_32_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_33_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_33_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_33_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_33_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_33_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_33_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_34_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_34_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_34_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_34_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_34_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_34_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_35_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_35_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_35_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_35_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_35_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_35_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_36_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_36_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_36_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_36_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_36_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_36_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_37_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_37_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_37_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_37_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_37_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_37_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_38_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_38_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_38_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_38_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_38_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_38_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_39_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_39_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_39_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_39_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_39_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_39_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_40_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_40_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_40_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_40_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_40_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_40_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_41_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_41_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_41_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_41_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_41_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_41_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_42_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_42_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_42_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_42_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_42_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_42_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_43_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_43_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_43_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_43_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_43_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_43_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_44_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_44_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_44_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_44_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_44_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_44_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_45_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_45_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_45_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_45_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_45_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_45_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_46_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_46_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_46_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_46_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_46_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_46_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_47_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_47_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_47_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_47_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_47_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_47_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_48_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_48_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_48_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_48_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_48_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_48_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_49_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_49_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_49_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_49_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_49_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_49_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_50_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_50_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_50_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_50_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_50_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_50_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_51_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_51_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_51_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_51_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_51_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_51_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_52_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_52_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_52_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_52_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_52_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_52_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_53_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_53_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_53_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_53_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_53_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_53_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_54_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_54_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_54_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_54_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_54_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_54_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_55_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_55_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_55_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_55_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_55_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_55_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_56_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_56_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_56_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_56_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_56_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_56_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_57_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_57_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_57_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_57_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_57_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_57_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_58_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_58_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_58_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_58_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_58_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_58_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_59_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_59_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_59_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_59_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_59_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_59_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_60_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_60_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_60_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_60_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_60_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_60_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_61_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_61_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_61_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_61_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_61_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_61_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_62_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_62_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_62_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_62_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_62_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_62_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_63_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_63_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_63_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_63_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_63_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_63_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_64_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_64_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_64_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_64_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_64_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_64_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_65_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_65_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_65_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_65_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_65_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_65_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_66_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_66_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_66_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_66_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_66_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_66_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_67_PULLUPDOWN" value="pulldown"/>
+		<user_parameter name="CONFIG.PSU_MIO_67_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_67_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_67_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_67_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_67_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PSU_MIO_68_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_68_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_68_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_68_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_68_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_68_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_69_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_69_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_69_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_69_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_69_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_69_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_70_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_70_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_70_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_70_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_70_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_70_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_71_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_71_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_71_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_71_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_71_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_71_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_72_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_72_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_72_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_72_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_72_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_72_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_73_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_73_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_73_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_73_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_73_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_73_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_74_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_74_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_74_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_74_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_74_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_74_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_75_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_75_DRIVE_STRENGTH" value="12"/>
+		<user_parameter name="CONFIG.PSU_MIO_75_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_75_INPUT_TYPE" value="schmitt"/>
+		<user_parameter name="CONFIG.PSU_MIO_75_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PSU_MIO_75_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU_MIO_76_PULLUPDOWN" value="pullup"/>
+		<user_parameter name="CONFIG.PSU_MIO_76_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_76_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_76_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_76_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_76_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PSU_MIO_77_PULLUPDOWN" value="disable"/>
+		<user_parameter name="CONFIG.PSU_MIO_77_DRIVE_STRENGTH" value="4"/>
+		<user_parameter name="CONFIG.PSU_MIO_77_POLARITY" value="Default"/>
+		<user_parameter name="CONFIG.PSU_MIO_77_INPUT_TYPE" value="cmos"/>
+		<user_parameter name="CONFIG.PSU_MIO_77_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PSU_MIO_77_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PSU__CAN1__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CAN1__GRP_CLK__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET0__GRP_MDIO__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__ACT_DDR_FREQ_MHZ" value="1065.000000"/>
+		<user_parameter name="CONFIG.PSU__ENET0__GRP_MDIO__IO" value="MIO 76 .. 77"/>
+		<user_parameter name="CONFIG.PSU__GEM__TSU__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__ENET0__FIFO__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET0__PTP__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET0__PERIPHERAL__IO" value="MIO 26 .. 37"/>
+		<user_parameter name="CONFIG.PSU__ENET1__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET1__FIFO__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET1__PTP__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET1__GRP_MDIO__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET2__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET2__FIFO__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET2__PTP__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET2__GRP_MDIO__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET3__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET3__FIFO__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET3__PTP__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__ENET3__GRP_MDIO__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO" value="3"/>
+		<user_parameter name="CONFIG.PSU__GPIO_EMIO_WIDTH" value="3"/>
+		<user_parameter name="CONFIG.PSU__GPIO_EMIO__WIDTH" value="[94:0]"/>
+		<user_parameter name="CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__GPIO0_MIO__IO" value="MIO 0 .. 25"/>
+		<user_parameter name="CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__GPIO1_MIO__IO" value="MIO 26 .. 51"/>
+		<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__IO" value="MIO 22 .. 23"/>
+		<user_parameter name="CONFIG.PSU__I2C0__GRP_INT__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__IO" value="MIO 8 .. 9"/>
+		<user_parameter name="CONFIG.PSU__I2C1__GRP_INT__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__GT_REF_CLK__FREQMHZ" value="33.333"/>
+		<user_parameter name="CONFIG.PSU__GT__LINK_SPEED" value="HBR"/>
+		<user_parameter name="CONFIG.PSU__GT__VLT_SWNG_LVL_4" value="0"/> 
+		<user_parameter name="CONFIG.PSU__GT__PRE_EMPH_LVL_4" value="0"/>
+		<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__IO" value="MIO 0 .. 5"/>
+		<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__MODE" value="Single"/>
+		<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE" value="x4"/>
+		<user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__IO" value="MIO 6"/>
+		<user_parameter name="CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD" value="0"/>
+		<user_parameter name="CONFIG.PSU__QSPI_COHERENCY" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD0__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD0__GRP_CD__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD0__GRP_POW__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD0__GRP_WP__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD0__RESET__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__IO" value="MIO 39 .. 51"/>
+		<user_parameter name="CONFIG.PSU__SD1__GRP_CD__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SD1__GRP_CD__IO" value="MIO 45"/>
+		<user_parameter name="CONFIG.PSU__SD1__GRP_POW__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SD1__GRP_POW__IO" value="MIO 43"/>
+		<user_parameter name="CONFIG.PSU__SD1__GRP_WP__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD1__SLOT_TYPE" value="SD 3.0"/>
+		<user_parameter name="CONFIG.PSU__SD1__RESET__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD1__DATA_TRANSFER_MODE" value="8Bit"/>
+		<user_parameter name="CONFIG.PSU__SD1_ROUTE_THROUGH_FPD" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD1_COHERENCY" value="0"/>
+		<user_parameter name="CONFIG.PSU__UART0__BAUD_RATE" value="115200"/>
+		<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__IO" value="MIO 18 .. 19"/>
+		<user_parameter name="CONFIG.PSU__UART0__MODEM__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__UART1__BAUD_RATE" value="115200"/>
+		<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__IO" value="EMIO"/>
+		<user_parameter name="CONFIG.PSU__UART1__MODEM__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__UART0_LOOP_UART1__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__IO" value="MIO 52 .. 63"/>
+		<user_parameter name="CONFIG.PSU__USB0__RESET__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__USB1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__USB1__PERIPHERAL__IO" value="MIO 64 .. 75"/>
+		<user_parameter name="CONFIG.PSU__USB1__RESET__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SPI0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SPI0__PERIPHERAL__IO" value="MIO 12 .. 17"/>
+		<user_parameter name="CONFIG.PSU__SPI0__GRP_SS0__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SPI0__GRP_SS0__IO" value="MIO 15"/>
+		<user_parameter name="CONFIG.PSU__SPI0__GRP_SS1__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SPI0__GRP_SS1__IO" value="MIO 14"/>
+		<user_parameter name="CONFIG.PSU__SPI0__GRP_SS2__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SPI1__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SPI1__GRP_SS0__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SPI1__GRP_SS1__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SPI1__GRP_SS2__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__DDR_INTF_REQUESTED" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__USB3_0_HUB" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__USB3_1_HUB" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__ADMA" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__M_AXI_GP0" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__M_AXI_GP1" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__M_AXI_GP2" value="1"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_ACP" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_GP0" value="1"/>
+		<user_parameter name="CONFIG.PSU__USE_DIFF_RW_CLK_GP0" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_GP1" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE_DIFF_RW_CLK_GP1" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_GP2" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE_DIFF_RW_CLK_GP2" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_GP3" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE_DIFF_RW_CLK_GP3" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_GP4" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE_DIFF_RW_CLK_GP4" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_GP5" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE_DIFF_RW_CLK_GP5" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_GP6" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE_DIFF_RW_CLK_GP6" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__S_AXI_ACE" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__AUDIO" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__VIDEO" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__PROC_EVENT_BUS" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__FTM" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__CROSS_TRIGGER" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__GDMA" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__IRQ" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__IRQ0" value="1"/>
+		<user_parameter name="CONFIG.PSU__USE__IRQ1" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__CLK0" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__CLK1" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__CLK2" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__CLK3" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__RST0" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__RST1" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__RST2" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__RST3" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__FABRIC__RST" value="1"/>
+		<user_parameter name="CONFIG.PSU__USE__RTC" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__EVENT_RPU" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__APU_LEGACY_INTERRUPT" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__STM" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__DEBUG__TEST" value="0"/>
+		<user_parameter name="CONFIG.PSU__USE__CLK" value="0"/>
+		<user_parameter name="CONFIG.PSU__SATA__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SATA__LANE0__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SATA__LANE1__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__IO" value="GT Lane1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__AL" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__BANK_ADDR_COUNT" value="2"/>
+		<user_parameter name="CONFIG.PSU__DDRC__BUS_WIDTH" value="64 Bit"/>
+		<user_parameter name="CONFIG.PSU__DDRC__CL" value="15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__CLOCK_STOP_EN" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__COL_ADDR_COUNT" value="10"/>
+		<user_parameter name="CONFIG.PSU__DDRC__RANK_ADDR_COUNT" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__CWL" value="14"/>
+		<user_parameter name="CONFIG.PSU__DDRC__BG_ADDR_COUNT" value="2"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DEVICE_CAPACITY" value="4096 MBits"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DRAM_WIDTH" value="8 Bits"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ECC" value="Disabled"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ECC_SCRUB" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__FREQ_MHZ" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__MEMORY_TYPE" value="DDR 4"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ROW_ADDR_COUNT" value="15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__SPEED_BIN" value="DDR4_2133P"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_FAW" value="30.0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_RAS_MIN" value="33"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_RC" value="47.06"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_RCD" value="15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_RP" value="15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__TRAIN_DATA_EYE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__TRAIN_READ_GATE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__VREF" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__BRC_MAPPING" value="ROW_BANK_COL"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__STATIC_RD_MODE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__PWR_DOWN_EN" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__PLL_BYPASS" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_T_REF_MODE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_T_REF_RANGE" value="Normal (0-85)"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR3_T_REF_RANGE" value="NA"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE" value="NA"/>
+		<user_parameter name="CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE" value="NA"/>
+		<user_parameter name="CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE" value="NA"/>
+		<user_parameter name="CONFIG.PSU__DDRC__PHY_DBI_MODE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DM_DBI" value="DM_NO_DBI"/>
+		<user_parameter name="CONFIG.PSU__DDRC__COMPONENTS" value="UDIMM"/>
+		<user_parameter name="CONFIG.PSU__DDRC__PARITY_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_CRC_CONTROL" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__FGRM" value="1X"/>
+		<user_parameter name="CONFIG.PSU__DDRC__VENDOR_PART" value="OTHERS"/>
+		<user_parameter name="CONFIG.PSU__DDRC__SB_TARGET" value="15-15-15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__LP_ASR" value="manual normal"/>
+		<user_parameter name="CONFIG.PSU__DDRC__SELF_REF_ABORT" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ADDR_MIRROR" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__EN_2ND_CLK" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__PER_BANK_REFRESH" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ENABLE_DP_SWITCH" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ENABLE_2T_TIMING" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__RD_DQS_CENTER" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_0_3" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_4_7" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_8_11" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_12_15" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_16_19" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_20_23" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_24_27" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_28_31" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_32_35" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_36_39" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_40_43" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_44_47" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_48_51" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_52_55" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_56_59" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_60_63" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_64_67" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DQMAP_68_71" value="0"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__IO" value="GT Lane3"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__IO" value="GT Lane2"/>
+		<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__IO" value="EMIO"/>
+		<user_parameter name="CONFIG.PSU__DP__LANE_SEL" value="Dual Higher"/>
+		<user_parameter name="CONFIG.PSU__DP__REF_CLK_FREQ" value="108"/>
+		<user_parameter name="CONFIG.PSU__DP__REF_CLK_SEL" value="Ref Clk2"/>
+		<user_parameter name="CONFIG.PSU__PSS_REF_CLK__FREQMHZ" value="30"/>
+		<user_parameter name="CONFIG.PSU__USB0__REF_CLK_SEL" value="Ref Clk0"/>
+		<user_parameter name="CONFIG.PSU__USB0__REF_CLK_FREQ" value="100"/>
+		<user_parameter name="CONFIG.PSU__OVERRIDE__BASIC_CLOCK" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ" value="1200"/> 
+		<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ" value="27.138"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ" value="27.138"/> 
+		<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA" value="0.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA" value="0.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0" value="4"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0" value="4"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0" value="4"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0" value="30"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AFI6__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0" value="25"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB3__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV" value="53"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0" value="12"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ" value="125.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ" value="125"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0" value="12"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ" value="125"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ" value="125"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0" value="12"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ" value="125"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ" value="125"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0" value="12"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ" value="125"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0" value="6"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0" value="6"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0" value="6"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" value="6"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0" value="7"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0" value="8"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0" value="4"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0" value="7"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0" value="6"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0" value="8"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0" value="6"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ" value="500.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ" value="187.500000"/>  
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ" value="198.750000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ" value="214"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ" value="1000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ" value="1000"/>
+		<user_parameter name="CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__TTC0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL" value="APB"/>
+		<user_parameter name="CONFIG.PSU__TTC1__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL" value="APB"/>
+		<user_parameter name="CONFIG.PSU__TTC2__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL" value="APB"/>
+		<user_parameter name="CONFIG.PSU__TTC3__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL" value="APB"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ" value="20.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ" value="20"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__FPGA_PL0_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__FPGA_PL1_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__FPGA_PL2_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__FPGA_PL3_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA" value="0.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA" value="0.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA" value="0.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV" value="80"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV" value="71"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0" value="5"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0" value="5"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0" value="16"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ" value="1200.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL" value="APLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ" value="1200"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ" value="500.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ" value="532.500000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ" value="1066"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" value="600"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0" value="5"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ" value="250.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ" value="265.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" value="267"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL" value="SysOsc"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ" value="180"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ" value="180"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ" value="500.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ" value="100.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ" value="30.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ" value="27"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ" value="26.500000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ" value="25"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ" value="24.843750"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ" value="187.500000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ" value="500.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ" value="1500.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ" value="1500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ" value="50.000000"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ" value="50"/>		
+		<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" value="APLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ" value="600.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ" value="600"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL" value="APLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ" value="600.000000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ" value="600"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ" value="532.500000"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ" value="533.333"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0" value="5"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" value="VPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ" value="300"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ" value="300.000000"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	
+	<ip_preset preset_proc_name="btn_5bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="switch_4bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="rgbled_3bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="led_4bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/board.xml
new file mode 100644
index 0000000..3def773
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/board.xml
@@ -0,0 +1,1574 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="genesys2" display_name="Genesys2" url="https://reference.digilentinc.com/reference/programmable-logic/genesys-2/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">H</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Genesys2</description>
+<components>
+  <component name="part0" display_name="Genesys2" type="fpga" part_name="xc7k325tffg900-2" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/genesys-2/start">
+    <interfaces>
+      <interface mode="master" name="audio_codec_iic" type="xilinx.com:interface:iic_rtl:1.0" of_component="audio_codec_iic">
+        <description>I2C bus to communicate with the Audio Codec</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+        </preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="aud_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="aud_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="aud_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="aud_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="aud_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="aud_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="aud_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="aud_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="aud_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="aud_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="aud_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="aud_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+      <description>DDR3 board interface, it can use MIG IP for connection.</description>
+	  <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_8bits" preset_proc="dip_switches_8bits_preset">
+        <description>8 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_8bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_8bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_8bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_8bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_8bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_8bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_8bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_8bits_tri_i_7"/> 
+            </pin_maps>
+          </port_map>
+		  
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <description>HDMI DDC</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+        <description>HDMI Out</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+        <description>Secondary interface to communicate with ethernet phy. </description>
+		<port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
+        <description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
+		<port_maps>
+          <port_map logical_port="TD" physical_port="eth_rgmii_td" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_td_0"/> 
+              <pin_map port_index="1" component_pin="eth_rgmii_td_1"/> 
+              <pin_map port_index="2" component_pin="eth_rgmii_td_2"/> 
+              <pin_map port_index="3" component_pin="eth_rgmii_td_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RD" physical_port="eth_rgmii_rd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_rd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rgmii_rd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rgmii_rd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rgmii_rd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CTL" physical_port="eth_rgmii_rx_ctl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_rx_ctl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CTL" physical_port="eth_rgmii_tx_ctl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_tx_ctl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TXC" physical_port="eth_rgmii_txc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_txc"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXC" physical_port="eth_rgmii_rxc" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_rxc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="phy_reset_out" type="xilinx.com:signal:reset_rtl:1.0" of_component="phy_onboard">
+          <description>Onboard Reset Button</description>
+		  <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernet" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="RESET" physical_port="phy_reset_n" dir="out">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="phy_reset_n"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+      <interface mode="master" name="iic_bus" type="xilinx.com:interface:iic_rtl:1.0" of_component="iic_bus">
+        <description>System I2C</description>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_8bits" preset_proc="led_8bits_preset">
+        <description>8 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_8bits_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RESET" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="sd_spi_mode" type="xilinx.com:interface:spi_rtl:1.0" of_component="sd_spi_mode" preset_proc="spi_preset">
+        <description>SD Card reader in SPI Mode</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="sd_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="sd_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="sd_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="sd_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="sd_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="sd_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="sd_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="sd_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="sd_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="sd_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="sd_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="sd_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sd_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <!--<interface mode="master" name="usb_otg_master" type="xilinx.com:interface:ulpi_rtl:1.0" of_component="usb_otg_master">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="otg_clk_m" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="otg_clk_m"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RST" physical_port="otg_rst_m" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="otg_rst_m"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DIR" physical_port="otg_dir_m" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="otg_dir_m"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="NEXT" physical_port="otg_next_m" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="otg_next_m"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="STOP" physical_port="otg_stop_m" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="otg_stop_m"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_I" physical_port="otg_data_i" dir="in" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="otg_data_i_0"/> 
+              <pin_map port_index="1" component_pin="otg_data_i_1"/> 
+              <pin_map port_index="2" component_pin="otg_data_i_2"/> 
+              <pin_map port_index="3" component_pin="otg_data_i_3"/> 
+              <pin_map port_index="4" component_pin="otg_data_i_4"/> 
+              <pin_map port_index="5" component_pin="otg_data_i_5"/> 
+              <pin_map port_index="6" component_pin="otg_data_i_6"/> 
+              <pin_map port_index="7" component_pin="otg_data_i_7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_O" physical_port="otg_data_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="otg_data_i_0"/> 
+              <pin_map port_index="1" component_pin="otg_data_i_1"/> 
+              <pin_map port_index="2" component_pin="otg_data_i_2"/> 
+              <pin_map port_index="3" component_pin="otg_data_i_3"/> 
+              <pin_map port_index="4" component_pin="otg_data_i_4"/> 
+              <pin_map port_index="5" component_pin="otg_data_i_5"/> 
+              <pin_map port_index="6" component_pin="otg_data_i_6"/> 
+              <pin_map port_index="7" component_pin="otg_data_i_7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_T" physical_port="otg_data_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="otg_data_i_0"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>-->
+	  
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>	  
+	   <interface mode="master" name="oled" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="oled" preset_proc="oled_preset">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+		  <port_map logical_port="PIN2_I" physical_port="OLED2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="OLED2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="OLED2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="OLED4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="OLED4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="OLED4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="OLED7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="OLED7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="OLED7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="OLED8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="OLED8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="OLED8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="OLED9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="OLED9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="OLED9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="OLED10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="OLED10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="OLED10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="slave" name="sys_diff_clock" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sys_diff_clock" preset_proc="sys_diff_clock_preset">
+          <parameters>
+            <parameter name="frequency" value="200000000"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="CLK_P" physical_port="clk_p" dir="in">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="clk_p"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="CLK_N" physical_port="clk_n" dir="in">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="clk_n"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+    </interfaces>
+  </component>
+  <component name="audio_codec_iic" display_name="Audio Codec I2C" type="chip" sub_type="mux" major_group="Audio">
+	<description>I2C bus to communicate with the Audio Codec</description>
+  </component>
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>1 GB 1800Mt/s on-board DDR3 </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="1GB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_8bits" display_name="8 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 7 to 0</description>
+  </component>
+  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI input (Requires Digilent's TMDS interface)</description>
+	<component_modes>
+        <component_mode name="HDMI_IN" display_name="HDMI In">
+		  <interfaces>
+            <interface name="hdmi_in" order="0"/>
+            <interface name="hdmi_in_ddc" order="1"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI in HPD (Connected to LD8)</description>
+  </component>
+  <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
+  </component>
+  <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI out HPD</description>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	 <component_modes>
+        <component_mode name="rgmii" display_name="RGMII mode">
+		  <interfaces>
+            <interface name="eth_rgmii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1"/>
+			<interface name="phy_reset_out" order="2" optional="true"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="iic_bus" display_name="I2C" type="chip" sub_type="mux" major_group="I2C">
+	<description>I2C bus</description>
+  </component>
+  <component name="led_8bits" display_name="8 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 7 to 0</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>System Reset Button</description>
+  </component>
+  <component name="sd_spi_mode" display_name="SD Card (SPI)" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>SD Card in SPI Mode</description>
+  </component>
+  <!--<component name="usb_otg_master" display_name="USB OTG" type="chip" sub_type="uart" major_group="UART">
+	<description>USB OTG (Needs work)</description>
+	<preferred_ips>
+		<preferred_ip vendor="xilinx.com" library="ip" name="axi_usb2_device" order="0"/>
+	</preferred_ips>
+  </component>-->
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="sd" display_name="Micro SD Card" type="chip" sub_type="chip" major_group="External Memory">
+	<description>Micro SD Card Reader</description>
+	<component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+  </component>
+  <component name="oled" display_name="Onboard OLED" type="chip" sub_type="chip" major_group="GPIO">
+  <component_modes>
+	<component_mode name="apmodoled" display_name="Digilent PmodOLED IP">
+	  <interfaces>
+		<interface name="oled"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="oled"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+  
+	<description>Onboard OLED (DISP1)</description>
+  </component>
+  
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="sys_diff_clock" display_name="System differential clock" type="chip" sub_type="system_clock" major_group="Clock Sources" >
+      <description>3.3V LVDS differential 200 MHz oscillator used as system differential clock on the board</description>
+      <parameters>
+        <parameter name="frequency" value="200000000"/>
+      </parameters>
+    </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_audio_codec_iic" component1="part0" component2="audio_codec_iic">
+    <connection_map name="part0_audio_codec_iic_1" c1_st_index="0" c1_end_index="1" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_dip_switches_8bits" component1="part0" component2="dip_switches_8bits">
+    <connection_map name="part0_dip_switches_8bits_1" c1_st_index="4" c1_end_index="11" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+    <connection_map name="part0_hdmi_in_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+	<connection_map name="part0_hdmi_in_ddc" c1_st_index="89" c1_end_index="90" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+    <connection_map name="part0_hdmi_out_1" c1_st_index="81" c1_end_index="88" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+    <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="21" c1_end_index="21" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_dspi" component1="part0" component2="dspi">
+    <connection_map name="part0_dspi_1" c1_st_index="44" c1_end_index="77" c2_st_index="0" c2_end_index="33"/>
+  </connection>
+  <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+	<connection_map name="part0_eth_rgmii_1" c1_st_index="24" c1_end_index="35" c2_st_index="0" c2_end_index="11"/>
+    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="22" c1_end_index="23" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_eth_phy_reset_n" c1_st_index="80" c1_end_index="80" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_iic_bus" component1="part0" component2="iic_bus">
+    <connection_map name="part0_iic_bus_1" c1_st_index="71" c1_end_index="72" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_led_8bits" component1="part0" component2="led_8bits">
+    <connection_map name="part0_led_8bits_1" c1_st_index="36" c1_end_index="43" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="64" c1_end_index="68" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="69" c1_end_index="69" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_sd_spi_mode" component1="part0" component2="sd_spi_mode">
+    <connection_map name="part0_sd_spi_mode_1" c1_st_index="73" c1_end_index="76" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <!--<connection name="part0_usb_otg_master" component1="part0" component2="usb_otg_master">
+    <connection_map name="part0_usb_otg_master_1" c1_st_index="46" c1_end_index="58" c2_st_index="0" c2_end_index="12"/>
+  </connection>-->
+  
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="129" c1_end_index="135" c2_st_index="0" c2_end_index="6"/>
+  </connection>
+  <connection name="part0_oled" component1="part0" component2="oled">
+    <connection_map name="part0_oled_1" c1_st_index="123" c1_end_index="128" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="78" c1_end_index="79" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_sysclk" component1="part0" component2="sys_diff_clock">
+    <connection_map name="part0_sys_clk_1" c1_st_index="2" c1_end_index="3" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/part0_pins.xml
new file mode 100644
index 0000000..d35b32b
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/part0_pins.xml
@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7k325tffg900-2">
+<pins>
+  <pin index="0" name ="aud_scl_i" iostandard="LVCMOS18" loc="AE19"/>
+  <pin index="1" name ="aud_sda_i" iostandard="LVCMOS18" loc="AF18"/>
+  <pin index="2" name ="clk_n" iostandard="LVDS" loc="AD11"/>
+  <pin index="3" name ="clk_p" iostandard="LVDS" loc="AD12"/>
+  <pin index="4" name ="dip_switches_8bits_tri_i_0" iostandard="LVCMOS12" loc="G19"/>
+  <pin index="5" name ="dip_switches_8bits_tri_i_1" iostandard="LVCMOS12" loc="G25"/>
+  <pin index="6" name ="dip_switches_8bits_tri_i_2" iostandard="LVCMOS12" loc="H24"/>
+  <pin index="7" name ="dip_switches_8bits_tri_i_3" iostandard="LVCMOS12" loc="K19"/>
+  <pin index="8" name ="dip_switches_8bits_tri_i_4" iostandard="LVCMOS12" loc="N19"/>
+  <pin index="9" name ="dip_switches_8bits_tri_i_5" iostandard="LVCMOS12" loc="P19"/>
+  <pin index="10" name ="dip_switches_8bits_tri_i_6" iostandard="LVCMOS33" loc="P26"/>
+  <pin index="11" name ="dip_switches_8bits_tri_i_7" iostandard="LVCMOS33" loc="P27"/>
+  <pin index="12" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="AH29"/>
+  <pin index="13" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="AE28"/>
+  <pin index="14" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="AF28"/>
+  <pin index="15" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="AJ26"/>
+  <pin index="16" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="AG27"/>
+  <pin index="17" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="AH26"/>
+  <pin index="18" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="AK26"/>
+  <pin index="19" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="AG28"/>
+  <pin index="20" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="AH27"/>
+  <pin index="21" name ="hdmi_tx_hpd" iostandard="LVCMOS18" loc="AG29"/>
+  <pin index="22" name ="eth_mdc" iostandard="LVCMOS15" loc="AF12"/>
+  <pin index="23" name ="eth_mdio_i" iostandard="LVCMOS15" loc="AG12"/>
+  <pin index="24" name ="eth_rgmii_rd_0" iostandard="LVCMOS15" loc="AJ14"/>
+  <pin index="25" name ="eth_rgmii_rd_1" iostandard="LVCMOS15" loc="AH14"/>
+  <pin index="26" name ="eth_rgmii_rd_2" iostandard="LVCMOS15" loc="AK13"/>
+  <pin index="27" name ="eth_rgmii_rd_3" iostandard="LVCMOS15" loc="AJ13"/>
+  <pin index="28" name ="eth_rgmii_rxc" iostandard="LVCMOS15" loc="AG10"/>
+  <pin index="29" name ="eth_rgmii_rx_ctl" iostandard="LVCMOS15" loc="AH11"/>
+  <pin index="30" name ="eth_rgmii_td_0" iostandard="LVCMOS15" loc="AJ12"/>
+  <pin index="31" name ="eth_rgmii_td_1" iostandard="LVCMOS15" loc="AK11"/>
+  <pin index="32" name ="eth_rgmii_td_2" iostandard="LVCMOS15" loc="AJ11"/>
+  <pin index="33" name ="eth_rgmii_td_3" iostandard="LVCMOS15" loc="AK10"/>
+  <pin index="34" name ="eth_rgmii_txc" iostandard="LVCMOS15" loc="AE10"/>
+  <pin index="35" name ="eth_rgmii_tx_ctl" iostandard="LVCMOS15" loc="AK14"/>
+  <pin index="36" name ="led_8bits_tri_o_0" iostandard="LVCMOS33" loc="T28"/>
+  <pin index="37" name ="led_8bits_tri_o_1" iostandard="LVCMOS33" loc="V19"/>
+  <pin index="38" name ="led_8bits_tri_o_2" iostandard="LVCMOS33" loc="U30"/>
+  <pin index="39" name ="led_8bits_tri_o_3" iostandard="LVCMOS33" loc="U29"/>
+  <pin index="40" name ="led_8bits_tri_o_4" iostandard="LVCMOS33" loc="V20"/>
+  <pin index="41" name ="led_8bits_tri_o_5" iostandard="LVCMOS33" loc="V26"/>
+  <pin index="42" name ="led_8bits_tri_o_6" iostandard="LVCMOS33" loc="W24"/>
+  <pin index="43" name ="led_8bits_tri_o_7" iostandard="LVCMOS33" loc="W23"/>
+  <pin index="44" name ="miso_i" iostandard="LVCMOS33" loc="W28"/>
+  <pin index="45" name ="mosi_i" iostandard="LVCMOS33" loc="W27"/>
+  <pin index="46" name ="otg_clk_m" iostandard="LVCMOS18" loc="AD18"/>
+  <pin index="47" name ="otg_data_i_0" iostandard="LVCMOS18" loc="AE14"/>
+  <pin index="48" name ="otg_data_i_1" iostandard="LVCMOS18" loc="AE15"/>
+  <pin index="49" name ="otg_data_i_2" iostandard="LVCMOS18" loc="AC15"/>
+  <pin index="50" name ="otg_data_i_3" iostandard="LVCMOS18" loc="AC16"/>
+  <pin index="51" name ="otg_data_i_4" iostandard="LVCMOS18" loc="AB15"/>
+  <pin index="52" name ="otg_data_i_5" iostandard="LVCMOS18" loc="AA15"/>
+  <pin index="53" name ="otg_data_i_6" iostandard="LVCMOS18" loc="AD14"/>
+  <pin index="54" name ="otg_data_i_7" iostandard="LVCMOS18" loc="AC14"/>
+  <pin index="55" name ="otg_dir_m" iostandard="LVCMOS18" loc="Y16"/>
+  <pin index="56" name ="otg_next_m" iostandard="LVCMOS18" loc="AA16"/>
+  <pin index="57" name ="otg_rst_m" iostandard="LVCMOS18" loc="AB14"/>
+  <pin index="58" name ="otg_stop_m" iostandard="LVCMOS18" loc="AA17"/>
+  <pin index="59" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS12" loc="E18"/>
+  <pin index="60" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS12" loc="B19"/>
+  <pin index="61" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS12" loc="M20"/>
+  <pin index="62" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS12" loc="C19"/>
+  <pin index="63" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS12" loc="M19"/>
+  <pin index="64" name ="qspi_csn_i" iostandard="LVCMOS33" loc="U19"/>
+  <pin index="65" name ="qspi_db0_i" iostandard="LVCMOS33" loc="P24"/>
+  <pin index="66" name ="qspi_db1_i" iostandard="LVCMOS33" loc="R25"/>
+  <pin index="67" name ="qspi_db2_i" iostandard="LVCMOS33" loc="R20"/>
+  <pin index="68" name ="qspi_db3_i" iostandard="LVCMOS33" loc="R21"/>
+  <pin index="69" name ="reset" iostandard="LVCMOS33" loc="R19"/>
+  <pin index="70" name ="sclk_i" iostandard="LVCMOS33" loc="AD27"/>
+  <pin index="71" name ="scl_i" iostandard="LVCMOS33" loc="AE30"/>
+  <pin index="72" name ="sda_i" iostandard="LVCMOS33" loc="AF30"/>
+  <pin index="73" name ="sd_miso_i" iostandard="LVCMOS33" loc="R26"/>
+  <pin index="74" name ="sd_mosi_i" iostandard="LVCMOS33" loc="R29"/>
+  <pin index="75" name ="sd_sclk_i" iostandard="LVCMOS33" loc="R28"/>
+  <pin index="76" name ="sd_ss_i" iostandard="LVCMOS33" loc="T30"/>
+  <pin index="77" name ="ss_i" iostandard="LVCMOS33" loc="W29"/>
+  <pin index="78" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="Y20"/>
+  <pin index="79" name ="usb_uart_txd" iostandard="LVCMOS33" loc="Y23"/>
+  <pin index="80" name ="phy_reset_n" iostandard="LVCMOS33" loc="AH24"/>
+  <pin index="81" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="AA20"/>
+  <pin index="82" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="AB20"/>
+  <pin index="83" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="AC20"/>
+  <pin index="84" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="AA22"/>
+  <pin index="85" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="AB24"/>
+  <pin index="86" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="AC21"/>
+  <pin index="87" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="AA23"/>
+  <pin index="88" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="AC25"/>
+  <pin index="89" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="AJ28"/>
+  <pin index="90" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="AJ29"/>
+  <pin index="91" name ="JC1" iostandard="LVCMOS33" loc="AC26"/>
+  <pin index="92" name ="JC2" iostandard="LVCMOS33" loc="AJ27"/>
+  <pin index="93" name ="JC3" iostandard="LVCMOS33" loc="AH30"/>
+  <pin index="94" name ="JC4" iostandard="LVCMOS33" loc="AK29"/>
+  <pin index="95" name ="JC7" iostandard="LVCMOS33" loc="AD26"/>
+  <pin index="96" name ="JC8" iostandard="LVCMOS33" loc="AG30"/>
+  <pin index="97" name ="JC9" iostandard="LVCMOS33" loc="AK30"/>
+  <pin index="98" name ="JC10" iostandard="LVCMOS33" loc="AK28"/>
+  <pin index="99" name ="JD1" iostandard="LVCMOS33"  loc="V27"/>
+  <pin index="100" name ="JD2" iostandard="LVCMOS33" loc="Y30"/>
+  <pin index="101" name ="JD3" iostandard="LVCMOS33" loc="V24"/>
+  <pin index="102" name ="JD4" iostandard="LVCMOS33" loc="W22"/>
+  <pin index="103" name ="JD7" iostandard="LVCMOS33" loc="U24"/>
+  <pin index="104" name ="JD8" iostandard="LVCMOS33" loc="Y26"/>
+  <pin index="105" name ="JD9" iostandard="LVCMOS33" loc="V22"/>
+  <pin index="106" name ="JD10" iostandard="LVCMOS33" loc="W21"/>
+  <pin index="107" name ="JB1" iostandard="LVCMOS33" loc="V29"/>
+  <pin index="108" name ="JB2" iostandard="LVCMOS33" loc="V30"/>
+  <pin index="109" name ="JB3" iostandard="LVCMOS33" loc="V25"/>
+  <pin index="110" name ="JB4" iostandard="LVCMOS33" loc="W26"/>
+  <pin index="111" name ="JB7" iostandard="LVCMOS33" loc="T25"/>
+  <pin index="112" name ="JB8" iostandard="LVCMOS33" loc="U25"/>
+  <pin index="113" name ="JB9" iostandard="LVCMOS33" loc="U22"/>
+  <pin index="114" name ="JB10" iostandard="LVCMOS33" loc="U23"/>
+  <pin index="115" name ="JA1" iostandard="LVCMOS33" loc="U27"/>
+  <pin index="116" name ="JA2" iostandard="LVCMOS33" loc="U28"/>
+  <pin index="117" name ="JA3" iostandard="LVCMOS33" loc="T26"/>
+  <pin index="118" name ="JA4" iostandard="LVCMOS33" loc="T27"/>
+  <pin index="119" name ="JA7" iostandard="LVCMOS33" loc="T22"/>
+  <pin index="120" name ="JA8" iostandard="LVCMOS33" loc="T23"/>
+  <pin index="121" name ="JA9" iostandard="LVCMOS33" loc="T20"/>
+  <pin index="122" name ="JA10" iostandard="LVCMOS33" loc="T21"/>
+  <pin index="123" name ="OLED2" iostandard="LVCMOS18" loc="Y15"/>
+  <pin index="124" name ="OLED4" iostandard="LVCMOS18" loc="AF17"/>
+  <pin index="125" name ="OLED7" iostandard="LVCMOS18" loc="AC17"/>
+  <pin index="126" name ="OLED8" iostandard="LVCMOS18" loc="AB17"/>
+  <pin index="127" name ="OLED9" iostandard="LVCMOS33" loc="AB22"/>
+  <pin index="128" name ="OLED10" iostandard="LVCMOS18" loc="AG17"/>
+  <pin index="129" name ="SD1" iostandard="LVCMOS33" loc="T30"/>
+  <pin index="130" name ="SD2" iostandard="LVCMOS33" loc="R29"/>
+  <pin index="131" name ="SD3" iostandard="LVCMOS33" loc="R26"/>
+  <pin index="132" name ="SD4" iostandard="LVCMOS33" loc="R28"/>
+  <pin index="133" name ="SD7" iostandard="LVCMOS33" loc="R30"/>
+  <pin index="134" name ="SD8" iostandard="LVCMOS33" loc="P29"/>
+  <pin index="135" name ="SD9" iostandard="LVCMOS33" loc="P28"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/preset.xml
new file mode 100644
index 0000000..2ab1d3e
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/preset.xml
@@ -0,0 +1,337 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="oled_preset">
+    <ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
+        <user_parameters>
+          <user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/> 
+          <user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="1"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="led_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="mii_preset">
+	  <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.PHY_TYPE" value="MII"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.Physical_Interface" value="MII"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_diff_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="200"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN2_D">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="200"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Differential_clock_capable_pin"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="hdmi_in_preset">
+    <ip vendor="digilentinc.com" library="ip" name="dvi2rgb">
+        <user_parameters>
+          <user_parameter name="CONFIG.kRstActiveHigh" value="false"/> 
+          <user_parameter name="CONFIG.kClkRange" value="2"/> 
+		  <user_parameter name="CONFIG.kAddBUFG" value="false"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/board.xml
new file mode 100644
index 0000000..74e1500
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/board.xml
@@ -0,0 +1,1370 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys-a7-100t" display_name="Nexys A7-100T" url="https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">D.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Nexys A7-100T</description>
+<components>
+  <component name="part0" display_name="Nexys A7-100T" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start">
+    <interfaces>
+      <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+        <description>Accelerometer control through SPI</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ddr2_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr2_sdram" preset_proc="ddr2_sdram_preset"> 
+      <description>DDR2 board interface, it can use MIG IP for connection.</description>
+	  <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <description>16 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+        <description>Dual 7 Seg LED Segments</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="eth_mdio_mdc">
+        <description>Secondary interface to communicate with ethernet phy. </description>
+		<port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_rmii" type="xilinx.com:interface:rmii_rtl:1.0" of_component="eth_rmii">
+        <description>Primary interface to communicate with ethernet phy in RMII mode. </description>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_rmii_txd" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rmii_txd_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rmii_rxd" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rmii_rxd_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_rmii_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rmii_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS_DV" physical_port="eth_rmii_crs_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_crs_dv"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+        <description>16 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <port_maps>
+          <port_map logical_port="RESET" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+        <description>7 Segment Display Anodes</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+        <port_maps>
+          <port_map logical_port="clk" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+        <description>Temperature Sensor connected to I2C</description>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="RTSn" physical_port="usb_uart_rts" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rts"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="CTSn" physical_port="usb_uart_cts" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_cts"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="SD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+	<description>Accelerometer controlled through SPI</description>
+  </component>
+  <component name="ddr2_sdram" display_name="DDR2 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+  <description>256 MB Onboard DDR Memory </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr2"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>16 Switches</description>
+  </component>
+  <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Segment Control</description>
+  </component>
+  <component name="eth_rmii" display_name="Ethernet RMII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>Ethernet RMII Signals</description> 
+  </component>
+  <component name="eth_mdio_mdc" display_name="Ethernet MDIO MDC" type="chip" sub_type="ethernet" major_group="Ethernet">
+  <description>Ethernet MDIO/MDC Signals</description> 
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>16 LEDs</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>Onboard Reset Button</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>2 RGB LEDs</description>
+  </component>
+  <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Anodes</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+	<description>SPI Controlled Temperature Sensor</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+  <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+    <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="5" c1_end_index="20" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+    <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="21" c1_end_index="28" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_eth_mdio_mdc" component1="part0" component2="eth_mdio_mdc">
+    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="29" c1_end_index="30" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_eth_rmii" component1="part0" component2="eth_rmii">
+    <connection_map name="part0_eth_rmii_1" c1_st_index="31" c1_end_index="37" c2_st_index="0" c2_end_index="6"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="38" c1_end_index="53" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="54" c1_end_index="58" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="64" c1_end_index="64" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="65" c1_end_index="70" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+    <connection_map name="part0_seven_seg_led_an_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="4" c1_end_index="4" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+    <connection_map name="part0_temp_sensor_1" c1_st_index="79" c1_end_index="80" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="81" c1_end_index="82" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_usb_uart_rts_cts" c1_st_index="179" c1_end_index="180" c2_st_index="2" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  
+ 
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/part0_pins.xml
new file mode 100644
index 0000000..55f9b06
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/part0_pins.xml
@@ -0,0 +1,162 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="E15"/>
+  <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="4" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="5" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="6" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="7" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="8" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="9" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="10" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="11" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="12" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="13" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="T8"/>
+  <pin index="14" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="U8"/>
+  <pin index="15" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="16" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T13"/>
+  <pin index="17" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="18" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="19" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="20" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="21" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="22" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="23" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="24" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="25" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="26" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="27" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="28" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="29" name ="eth_mdc" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="30" name ="eth_mdio_i" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="31" name ="eth_rmii_crs_dv" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="32" name ="eth_rmii_rxd_0" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="33" name ="eth_rmii_rxd_1" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="34" name ="eth_rmii_rx_er" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="35" name ="eth_rmii_txd_0" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="36" name ="eth_rmii_txd_1" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="37" name ="eth_rmii_tx_en" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="38" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="39" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="K15"/>
+  <pin index="40" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="41" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="42" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="43" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="44" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="45" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="46" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="47" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="48" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="49" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="50" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="51" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="52" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="53" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="V11"/>
+  <pin index="54" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="55" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="56" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="57" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="58" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="59" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="60" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="61" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="62" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="63" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="64" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+  <pin index="65" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="66" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="67" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="68" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="69" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="70" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="71" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="72" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="73" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="74" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="75" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="76" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="77" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="78" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="79" name ="temp_scl_i" iostandard="LVCMOS33" loc="C14"/>
+  <pin index="80" name ="temp_sda_i" iostandard="LVCMOS33" loc="C15"/>
+  <pin index="81" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+  <pin index="82" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+  <pin index="83" name ="JA1" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="84" name ="JA2" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="85" name ="JA3" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="86" name ="JA4" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="87" name ="JA7" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="88" name ="JA8" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="89" name ="JA9" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="90" name ="JA10" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="91" name ="JB1" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="92" name ="JB2" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="93" name ="JB3" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="94" name ="JB4" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="95" name ="JB7" iostandard="LVCMOS33" loc="E16"/>
+  <pin index="96" name ="JB8" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="97" name ="JB9" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="98" name ="JB10" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="99" name ="JC1"  iostandard="LVCMOS33" loc="K1"/>
+  <pin index="100" name ="JC2" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="101" name ="JC3" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="102" name ="JC4" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="103" name ="JC7" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="104" name ="JC8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="105" name ="JC9" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="106" name ="JC10" iostandard="LVCMOS33" loc="E6"/>
+  <pin index="107" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="108" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="109" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="110" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="111" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+  <pin index="112" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="113" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+  <pin index="114" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+  <pin index="115" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="116" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+  <pin index="117" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="118" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="119" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="120" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="121" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="122" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+  <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+  <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+  <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+  <pin index="179" name ="usb_uart_rts" iostandard="LVCMOS33" loc="E5"/>
+  <pin index="180" name ="usb_uart_cts" iostandard="LVCMOS33" loc="D3"/>
+  
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/preset.xml
new file mode 100644
index 0000000..7128cce
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.0/preset.xml
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr2_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="output_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/board.xml
new file mode 100644
index 0000000..09247aa
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/board.xml
@@ -0,0 +1,1301 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys-a7-100t" display_name="Nexys A7-100T" url="https://digilent.com/reference/programmable-logic/nexys-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">D.0</revision>
+</compatible_board_revisions>
+<file_version>1.2</file_version>
+<description>Nexys A7-100T</description>
+<components>
+  <component name="part0" display_name="Nexys A7-100T" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/nexys-a7/start">
+    <interfaces>
+      <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+        <description>Accelerometer control through SPI</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ddr2_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr2_sdram" preset_proc="ddr2_sdram_preset"> 
+      <description>DDR2 board interface, it can use MIG IP for connection.</description>
+	  <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <description>16 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+        <description>Dual 7 Seg LED Segments</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+        <description>16 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+        <description>7 Segment Display Anodes</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+        <description>Temperature Sensor connected to I2C</description>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="RTSn" physical_port="usb_uart_rts" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rts"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="CTSn" physical_port="usb_uart_cts" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_cts"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="SD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+	<description>Accelerometer controlled through SPI</description>
+  </component>
+  <component name="ddr2_sdram" display_name="DDR2 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+  <description>256 MB Onboard DDR Memory </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr2"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>16 Switches</description>
+  </component>
+  <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Segment Control</description>
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>16 LEDs</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>Onboard Reset Button</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>2 RGB LEDs</description>
+  </component>
+  <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Anodes</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+	<description>SPI Controlled Temperature Sensor</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+  <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+    <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="5" c1_end_index="20" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+    <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="21" c1_end_index="28" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="38" c1_end_index="53" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="54" c1_end_index="58" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="64" c1_end_index="64" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="65" c1_end_index="70" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+    <connection_map name="part0_seven_seg_led_an_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="4" c1_end_index="4" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+    <connection_map name="part0_temp_sensor_1" c1_st_index="79" c1_end_index="80" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="81" c1_end_index="82" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_usb_uart_rts_cts" c1_st_index="179" c1_end_index="180" c2_st_index="2" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  
+ 
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/part0_pins.xml
new file mode 100644
index 0000000..43f20b5
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/part0_pins.xml
@@ -0,0 +1,153 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="E15"/>
+  <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="4" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="5" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="6" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="7" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="8" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="9" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="10" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="11" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="12" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="13" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="T8"/>
+  <pin index="14" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="U8"/>
+  <pin index="15" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="16" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T13"/>
+  <pin index="17" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="18" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="19" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="20" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="21" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="22" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="23" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="24" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="25" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="26" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="27" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="28" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="38" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="39" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="K15"/>
+  <pin index="40" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="41" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="42" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="43" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="44" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="45" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="46" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="47" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="48" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="49" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="50" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="51" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="52" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="53" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="V11"/>
+  <pin index="54" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="55" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="56" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="57" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="58" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="59" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="60" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="61" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="62" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="63" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="64" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+  <pin index="65" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="66" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="67" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="68" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="69" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="70" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="71" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="72" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="73" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="74" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="75" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="76" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="77" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="78" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="79" name ="temp_scl_i" iostandard="LVCMOS33" loc="C14"/>
+  <pin index="80" name ="temp_sda_i" iostandard="LVCMOS33" loc="C15"/>
+  <pin index="81" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+  <pin index="82" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+  <pin index="83" name ="JA1" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="84" name ="JA2" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="85" name ="JA3" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="86" name ="JA4" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="87" name ="JA7" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="88" name ="JA8" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="89" name ="JA9" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="90" name ="JA10" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="91" name ="JB1" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="92" name ="JB2" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="93" name ="JB3" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="94" name ="JB4" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="95" name ="JB7" iostandard="LVCMOS33" loc="E16"/>
+  <pin index="96" name ="JB8" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="97" name ="JB9" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="98" name ="JB10" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="99" name ="JC1"  iostandard="LVCMOS33" loc="K1"/>
+  <pin index="100" name ="JC2" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="101" name ="JC3" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="102" name ="JC4" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="103" name ="JC7" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="104" name ="JC8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="105" name ="JC9" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="106" name ="JC10" iostandard="LVCMOS33" loc="E6"/>
+  <pin index="107" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="108" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="109" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="110" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="111" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+  <pin index="112" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="113" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+  <pin index="114" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+  <pin index="115" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="116" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+  <pin index="117" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="118" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="119" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="120" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="121" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="122" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+  <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+  <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+  <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+  <pin index="179" name ="usb_uart_rts" iostandard="LVCMOS33" loc="E5"/>
+  <pin index="180" name ="usb_uart_cts" iostandard="LVCMOS33" loc="D3"/>
+  
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/preset.xml
new file mode 100644
index 0000000..7128cce
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/preset.xml
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr2_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="output_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/board.xml
new file mode 100644
index 0000000..8f02906
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/board.xml
@@ -0,0 +1,1347 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys-a7-50t" display_name="Nexys A7-50T" url="https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">D.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Nexys A7-50T</description>
+<components>
+  <component name="part0" display_name="Nexys A7-50T" type="fpga" part_name="xc7a50ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start">
+    <interfaces>
+      <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+        <description>Accelerometer control through SPI</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ddr2_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr2_sdram" preset_proc="ddr2_sdram_preset"> 
+      <description>DDR2 board interface, it can use MIG IP for connection.</description>
+	  <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <description>16 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+        <description>Dual 7 Seg LED Segments</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="eth_mdio_mdc">
+        <description>Secondary interface to communicate with ethernet phy. </description>
+		<port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_rmii" type="xilinx.com:interface:rmii_rtl:1.0" of_component="eth_rmii">
+        <description>Primary interface to communicate with ethernet phy in RMII mode. </description>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_rmii_txd" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rmii_txd_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rmii_rxd" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rmii_rxd_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_rmii_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rmii_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS_DV" physical_port="eth_rmii_crs_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_crs_dv"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+        <description>16 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <port_maps>
+          <port_map logical_port="RESET" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+        <description>7 Segment Display Anodes</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+        <port_maps>
+          <port_map logical_port="clk" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+        <description>Temperature Sensor connected to I2C</description>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="RTSn" physical_port="usb_uart_rts" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rts"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="CTSn" physical_port="usb_uart_cts" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_cts"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="SD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+	<description>Accelerometer controlled through SPI</description>
+  </component>
+  <component name="ddr2_sdram" display_name="DDR2 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+  <description>256 MB Onboard DDR Memory </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr2"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>16 Switches</description>
+  </component>
+  <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Segment Control</description>
+  </component>
+  <component name="eth_rmii" display_name="Ethernet RMII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>Ethernet RMII Signals</description> 
+  </component>
+  <component name="eth_mdio_mdc" display_name="Ethernet MDIO MDC" type="chip" sub_type="ethernet" major_group="Ethernet">
+  <description>Ethernet MDIO/MDC Signals</description> 
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>16 LEDs</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>Onboard Reset Button</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>2 RGB LEDs</description>
+  </component>
+  <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Anodes</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+	<description>SPI Controlled Temperature Sensor</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+  <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+    <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="5" c1_end_index="20" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+    <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="21" c1_end_index="28" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_eth_mdio_mdc" component1="part0" component2="eth_mdio_mdc">
+    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="29" c1_end_index="30" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_eth_rmii" component1="part0" component2="eth_rmii">
+    <connection_map name="part0_eth_rmii_1" c1_st_index="31" c1_end_index="37" c2_st_index="0" c2_end_index="6"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="38" c1_end_index="53" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="54" c1_end_index="58" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="64" c1_end_index="64" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="65" c1_end_index="70" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+    <connection_map name="part0_seven_seg_led_an_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="4" c1_end_index="4" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+    <connection_map name="part0_temp_sensor_1" c1_st_index="79" c1_end_index="80" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="81" c1_end_index="82" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_usb_uart_rts_cts" c1_st_index="179" c1_end_index="180" c2_st_index="2" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  
+ 
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/part0_pins.xml
new file mode 100644
index 0000000..0de1b2f
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/part0_pins.xml
@@ -0,0 +1,139 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<part_info part_name="xc7a50ticsg324-1L">
+<pins>
+  <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="E15"/>
+  <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="4" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="5" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="6" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="7" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="8" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="9" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="10" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="11" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="12" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="13" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="T8"/>
+  <pin index="14" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="U8"/>
+  <pin index="15" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="16" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T13"/>
+  <pin index="17" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="18" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="19" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="20" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="21" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="22" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="23" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="24" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="25" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="26" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="27" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="28" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="29" name ="eth_mdc" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="30" name ="eth_mdio_i" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="31" name ="eth_rmii_crs_dv" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="32" name ="eth_rmii_rxd_0" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="33" name ="eth_rmii_rxd_1" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="34" name ="eth_rmii_rx_er" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="35" name ="eth_rmii_txd_0" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="36" name ="eth_rmii_txd_1" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="37" name ="eth_rmii_tx_en" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="38" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="39" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="K15"/>
+  <pin index="40" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="41" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="42" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="43" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="44" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="45" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="46" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="47" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="48" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="49" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="50" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="51" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="52" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="53" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="V11"/>
+  <pin index="54" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="55" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="56" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="57" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="58" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="59" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="60" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="61" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="62" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="63" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="64" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+  <pin index="65" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="66" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="67" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="68" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="69" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="70" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="71" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="72" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="73" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="74" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="75" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="76" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="77" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="78" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="79" name ="temp_scl_i" iostandard="LVCMOS33" loc="C14"/>
+  <pin index="80" name ="temp_sda_i" iostandard="LVCMOS33" loc="C15"/>
+  <pin index="81" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+  <pin index="82" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+  <pin index="83" name ="JA1" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="84" name ="JA2" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="85" name ="JA3" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="86" name ="JA4" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="87" name ="JA7" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="88" name ="JA8" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="89" name ="JA9" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="90" name ="JA10" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="91" name ="JB1" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="92" name ="JB2" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="93" name ="JB3" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="94" name ="JB4" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="95" name ="JB7" iostandard="LVCMOS33" loc="E16"/>
+  <pin index="96" name ="JB8" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="97" name ="JB9" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="98" name ="JB10" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="99" name ="JC1"  iostandard="LVCMOS33" loc="K1"/>
+  <pin index="100" name ="JC2" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="101" name ="JC3" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="102" name ="JC4" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="103" name ="JC7" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="104" name ="JC8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="105" name ="JC9" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="106" name ="JC10" iostandard="LVCMOS33" loc="E6"/>
+  <pin index="107" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="108" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="109" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="110" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="111" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+  <pin index="112" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="113" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+  <pin index="114" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+  <pin index="115" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="116" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+  <pin index="117" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="118" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="119" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="120" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="121" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="122" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+  <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+  <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+  <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+  <pin index="179" name ="usb_uart_rts" iostandard="LVCMOS33" loc="E5"/>
+  <pin index="180" name ="usb_uart_cts" iostandard="LVCMOS33" loc="D3"/>
+  
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/preset.xml
new file mode 100644
index 0000000..4e3b670
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.0/preset.xml
@@ -0,0 +1,375 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr2_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="output_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/board.xml
new file mode 100644
index 0000000..67d2db2
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/board.xml
@@ -0,0 +1,1301 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys-a7-50t" display_name="Nexys A7-50T" url="https://digilent.com/reference/programmable-logic/nexys-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">D.0</revision>
+</compatible_board_revisions>
+<file_version>1.2</file_version>
+<description>Nexys A7-50T</description>
+<components>
+  <component name="part0" display_name="Nexys A7-50T" type="fpga" part_name="xc7a50ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/nexys-a7/start">
+    <interfaces>
+      <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+        <description>Accelerometer control through SPI</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+        </preferred_ips>
+		    <port_maps>
+          <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ddr2_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr2_sdram" preset_proc="ddr2_sdram_preset"> 
+        <description>DDR2 board interface, it can use MIG IP for connection.</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+        </preferred_ips>
+	    </interface>
+      <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <description>16 DIP Switches</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+		    <port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+        <description>Dual 7 Seg LED Segments</description>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+          </preferred_ips>
+          <port_maps>
+          <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+        <description>16 LEDs</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+        <description>7 Segment Display Anodes</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+        <description>Temperature Sensor connected to I2C</description>
+		    <port_maps>
+          <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		    <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+		      <port_map logical_port="RTSn" physical_port="usb_uart_rts" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rts"/> 
+            </pin_maps>
+          </port_map>
+		      <port_map logical_port="CTSn" physical_port="usb_uart_cts" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_cts"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="SD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+	<description>Accelerometer controlled through SPI</description>
+  </component>
+  <component name="ddr2_sdram" display_name="DDR2 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+  <description>256 MB Onboard DDR Memory </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr2"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>16 Switches</description>
+  </component>
+  <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Segment Control</description>
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>16 LEDs</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>Onboard Reset Button</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>2 RGB LEDs</description>
+  </component>
+  <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Anodes</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+	<description>SPI Controlled Temperature Sensor</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+  <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+    <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="5" c1_end_index="20" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+    <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="21" c1_end_index="28" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="38" c1_end_index="53" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="54" c1_end_index="58" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="64" c1_end_index="64" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="65" c1_end_index="70" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+    <connection_map name="part0_seven_seg_led_an_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="4" c1_end_index="4" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+    <connection_map name="part0_temp_sensor_1" c1_st_index="79" c1_end_index="80" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="81" c1_end_index="82" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_usb_uart_rts_cts" c1_st_index="179" c1_end_index="180" c2_st_index="2" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  
+ 
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/part0_pins.xml
new file mode 100644
index 0000000..d90ebcf
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/part0_pins.xml
@@ -0,0 +1,153 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a50ticsg324-1L">
+<pins>
+  <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="E15"/>
+  <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="4" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="5" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="6" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="7" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="8" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="9" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="10" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="11" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="12" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="13" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="T8"/>
+  <pin index="14" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="U8"/>
+  <pin index="15" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="16" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T13"/>
+  <pin index="17" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="18" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="19" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="20" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="21" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="22" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="23" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="24" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="25" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="26" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="27" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="28" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="38" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="39" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="K15"/>
+  <pin index="40" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="41" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="42" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="43" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="44" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="45" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="46" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="47" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="48" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="49" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="50" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="51" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="52" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="53" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="V11"/>
+  <pin index="54" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="55" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="56" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="57" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="58" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="59" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="60" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="61" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="62" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="63" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="64" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+  <pin index="65" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="66" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="67" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="68" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="69" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="70" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="71" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="72" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="73" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="74" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="75" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="76" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="77" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="78" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="79" name ="temp_scl_i" iostandard="LVCMOS33" loc="C14"/>
+  <pin index="80" name ="temp_sda_i" iostandard="LVCMOS33" loc="C15"/>
+  <pin index="81" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+  <pin index="82" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+  <pin index="83" name ="JA1" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="84" name ="JA2" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="85" name ="JA3" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="86" name ="JA4" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="87" name ="JA7" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="88" name ="JA8" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="89" name ="JA9" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="90" name ="JA10" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="91" name ="JB1" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="92" name ="JB2" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="93" name ="JB3" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="94" name ="JB4" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="95" name ="JB7" iostandard="LVCMOS33" loc="E16"/>
+  <pin index="96" name ="JB8" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="97" name ="JB9" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="98" name ="JB10" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="99" name ="JC1"  iostandard="LVCMOS33" loc="K1"/>
+  <pin index="100" name ="JC2" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="101" name ="JC3" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="102" name ="JC4" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="103" name ="JC7" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="104" name ="JC8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="105" name ="JC9" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="106" name ="JC10" iostandard="LVCMOS33" loc="E6"/>
+  <pin index="107" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="108" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="109" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="110" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="111" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+  <pin index="112" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="113" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+  <pin index="114" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+  <pin index="115" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="116" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+  <pin index="117" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="118" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="119" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="120" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="121" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="122" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+  <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+  <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+  <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+  <pin index="179" name ="usb_uart_rts" iostandard="LVCMOS33" loc="E5"/>
+  <pin index="180" name ="usb_uart_cts" iostandard="LVCMOS33" loc="D3"/>
+  
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/preset.xml
new file mode 100644
index 0000000..7128cce
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-50t/D.0/1.2/preset.xml
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr2_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="output_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/board.xml
new file mode 100644
index 0000000..f463814
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/board.xml
@@ -0,0 +1,1478 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys4" display_name="Nexys4" url="https://digilent.com/reference/programmable-logic/nexys-4/start"  preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.1</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Nexys4</description>
+<components>
+  <component name="part0" display_name="Nexys4" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/nexys-4/start">
+    <interfaces>
+      <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+        <description>Accelerometer control through SPI</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="emc_preset">
+        <description>16MB of Cell RAM</description>
+		<port_maps>
+          <port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="22" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_addr_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_addr_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_addr_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_addr_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_addr_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_addr_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_addr_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_addr_7"/> 
+              <pin_map port_index="8" component_pin="cellular_ram_addr_8"/> 
+              <pin_map port_index="9" component_pin="cellular_ram_addr_9"/> 
+              <pin_map port_index="10" component_pin="cellular_ram_addr_10"/> 
+              <pin_map port_index="11" component_pin="cellular_ram_addr_11"/> 
+              <pin_map port_index="12" component_pin="cellular_ram_addr_12"/> 
+              <pin_map port_index="13" component_pin="cellular_ram_addr_13"/> 
+              <pin_map port_index="14" component_pin="cellular_ram_addr_14"/> 
+              <pin_map port_index="15" component_pin="cellular_ram_addr_15"/> 
+              <pin_map port_index="16" component_pin="cellular_ram_addr_16"/> 
+              <pin_map port_index="17" component_pin="cellular_ram_addr_17"/> 
+              <pin_map port_index="18" component_pin="cellular_ram_addr_18"/> 
+              <pin_map port_index="19" component_pin="cellular_ram_addr_19"/> 
+              <pin_map port_index="20" component_pin="cellular_ram_addr_20"/> 
+              <pin_map port_index="21" component_pin="cellular_ram_addr_21"/> 
+              <pin_map port_index="22" component_pin="cellular_ram_addr_22"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_i_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_i_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_i_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_i_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_i_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_i_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_i_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_i_7"/> 
+              <pin_map port_index="8" component_pin="cellular_ram_dq_i_8"/> 
+              <pin_map port_index="9" component_pin="cellular_ram_dq_i_9"/> 
+              <pin_map port_index="10" component_pin="cellular_ram_dq_i_10"/> 
+              <pin_map port_index="11" component_pin="cellular_ram_dq_i_11"/> 
+              <pin_map port_index="12" component_pin="cellular_ram_dq_i_12"/> 
+              <pin_map port_index="13" component_pin="cellular_ram_dq_i_13"/> 
+              <pin_map port_index="14" component_pin="cellular_ram_dq_i_14"/> 
+              <pin_map port_index="15" component_pin="cellular_ram_dq_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_i_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_i_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_i_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_i_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_i_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_i_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_i_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_i_7"/> 
+              <pin_map port_index="8" component_pin="cellular_ram_dq_i_8"/> 
+              <pin_map port_index="9" component_pin="cellular_ram_dq_i_9"/> 
+              <pin_map port_index="10" component_pin="cellular_ram_dq_i_10"/> 
+              <pin_map port_index="11" component_pin="cellular_ram_dq_i_11"/> 
+              <pin_map port_index="12" component_pin="cellular_ram_dq_i_12"/> 
+              <pin_map port_index="13" component_pin="cellular_ram_dq_i_13"/> 
+              <pin_map port_index="14" component_pin="cellular_ram_dq_i_14"/> 
+              <pin_map port_index="15" component_pin="cellular_ram_dq_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_dq_i_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_dq_i_1"/> 
+              <pin_map port_index="2" component_pin="cellular_ram_dq_i_2"/> 
+              <pin_map port_index="3" component_pin="cellular_ram_dq_i_3"/> 
+              <pin_map port_index="4" component_pin="cellular_ram_dq_i_4"/> 
+              <pin_map port_index="5" component_pin="cellular_ram_dq_i_5"/> 
+              <pin_map port_index="6" component_pin="cellular_ram_dq_i_6"/> 
+              <pin_map port_index="7" component_pin="cellular_ram_dq_i_7"/> 
+              <pin_map port_index="8" component_pin="cellular_ram_dq_i_8"/> 
+              <pin_map port_index="9" component_pin="cellular_ram_dq_i_9"/> 
+              <pin_map port_index="10" component_pin="cellular_ram_dq_i_10"/> 
+              <pin_map port_index="11" component_pin="cellular_ram_dq_i_11"/> 
+              <pin_map port_index="12" component_pin="cellular_ram_dq_i_12"/> 
+              <pin_map port_index="13" component_pin="cellular_ram_dq_i_13"/> 
+              <pin_map port_index="14" component_pin="cellular_ram_dq_i_14"/> 
+              <pin_map port_index="15" component_pin="cellular_ram_dq_i_15"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="ADV_LDN" physical_port="cellular_ram_adv_ldn" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_adv_ldn"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_oen"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_wen"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_ce_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRE" physical_port="cellular_ram_cre" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_cre"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="BEN" physical_port="cellular_ram_ben" dir="inout" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_ben_0"/> 
+              <pin_map port_index="1" component_pin="cellular_ram_ben_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="WAIT" physical_port="cellular_ram_wait" dir="inout">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="cellular_ram_wait"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <description>16 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+        <description>Dual 7 Seg LED Segments</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="eth_mdio_mdc">
+        <description>Secondary interface to communicate with ethernet phy. </description>
+		<port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_rmii" type="xilinx.com:interface:rmii_rtl:1.0" of_component="eth_rmii">
+        <description>Primary interface to communicate with ethernet phy in RMII mode. </description>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_rmii_txd" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rmii_txd_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rmii_rxd" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rmii_rxd_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_rmii_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rmii_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS_DV" physical_port="eth_rmii_crs_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_crs_dv"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+        <description>16 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <port_maps>
+          <port_map logical_port="RESET" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+        <description>7 Segment Display Anodes</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+        <description>Temperature Sensor connected to I2C</description>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="SD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+	
+  </component>
+  <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+	<description>Accelerometer controlled through SPI</description>
+  </component>
+  <component name="cellular_ram" display_name="Block RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">
+	<description>16MB Cell RAM</description>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>16 Switches</description>
+  </component>
+  <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Segment Control</description>
+  </component>
+  <component name="eth_rmii" display_name="Ethernet RMII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>Ethernet RMII Signals</description> 
+  </component>
+  <component name="eth_mdio_mdc" display_name="Ethernet MDIO MDC" type="chip" sub_type="ethernet" major_group="Ethernet">
+  <description>Ethernet MDIO/MDC Signals</description> 
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>16 LEDs</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>Onboard Reset Button</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>2 RGB LEDs</description>
+  </component>
+  <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Anodes</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+	<description>SPI Controlled Temperature Sensor</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+  <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+    <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">
+    <connection_map name="part0_cellular_ram_1" c1_st_index="4" c1_end_index="50" c2_st_index="0" c2_end_index="46"/>
+  </connection>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="52" c1_end_index="67" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+    <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="68" c1_end_index="75" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_rmii" component1="part0" component2="eth_rmii">
+	<connection_map name="part0_eth_rmii_1" c1_st_index="78" c1_end_index="84" c2_st_index="0" c2_end_index="6"/>
+  </connection>
+  <connection name="part0_mdio_mdc" component1="part0" component2="eth_mdio_mdc">
+    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="76" c1_end_index="77" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="85" c1_end_index="100" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="101" c1_end_index="105" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="106" c1_end_index="110" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="112" c1_end_index="112" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="113" c1_end_index="118" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+    <connection_map name="part0_seven_seg_led_an_1" c1_st_index="119" c1_end_index="126" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="51" c1_end_index="51" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+    <connection_map name="part0_temp_sensor_1" c1_st_index="127" c1_end_index="128" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="129" c1_end_index="130" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="131" c1_end_index="138" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="139" c1_end_index="146" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="147" c1_end_index="154" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="155" c1_end_index="162" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="163" c1_end_index="170" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/part0_pins.xml
new file mode 100644
index 0000000..79ab8f1
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/part0_pins.xml
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="D13"/>
+  <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="B14"/>
+  <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="C15"/>
+  <pin index="4" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="5" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="6" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="7" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="8" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="9" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="K15"/>
+  <pin index="10" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="11" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="12" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="13" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="14" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="15" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="16" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="17" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="18" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="19" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="20" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="21" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="22" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="23" name ="cellular_ram_addr_19" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="24" name ="cellular_ram_addr_20" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="25" name ="cellular_ram_addr_21" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="26" name ="cellular_ram_addr_22" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="27" name ="cellular_ram_adv_ldn" iostandard="LVCMOS33" loc="T13"/>
+  <pin index="28" name ="cellular_ram_ben_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="29" name ="cellular_ram_ben_1" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="31" name ="cellular_ram_cre" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="32" name ="cellular_ram_dq_i_0" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="33" name ="cellular_ram_dq_i_1" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="34" name ="cellular_ram_dq_i_2" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="35" name ="cellular_ram_dq_i_3" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="36" name ="cellular_ram_dq_i_4" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="37" name ="cellular_ram_dq_i_5" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="38" name ="cellular_ram_dq_i_6" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="39" name ="cellular_ram_dq_i_7" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="40" name ="cellular_ram_dq_i_8" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="41" name ="cellular_ram_dq_i_9" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="42" name ="cellular_ram_dq_i_10" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="43" name ="cellular_ram_dq_i_11" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="44" name ="cellular_ram_dq_i_12" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="45" name ="cellular_ram_dq_i_13" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="46" name ="cellular_ram_dq_i_14" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="47" name ="cellular_ram_dq_i_15" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="48" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="49" name ="cellular_ram_wait" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="50" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="51" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="52" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="U9"/>
+  <pin index="53" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="U8"/>
+  <pin index="54" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="R7"/>
+  <pin index="55" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R6"/>
+  <pin index="56" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R5"/>
+  <pin index="57" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="V7"/>
+  <pin index="58" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="V6"/>
+  <pin index="59" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="V5"/>
+  <pin index="60" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS33" loc="U4"/>
+  <pin index="61" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS33" loc="V2"/>
+  <pin index="62" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="U2"/>
+  <pin index="63" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T3"/>
+  <pin index="64" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="T1"/>
+  <pin index="65" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="R3"/>
+  <pin index="66" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="P3"/>
+  <pin index="67" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="P4"/>
+  <pin index="68" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="L3"/>
+  <pin index="69" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="N1"/>
+  <pin index="70" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="L5"/>
+  <pin index="71" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="L4"/>
+  <pin index="72" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="K3"/>
+  <pin index="73" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="M2"/>
+  <pin index="74" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L6"/>
+  <pin index="75" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="M4"/>
+  <pin index="76" name ="eth_mdc" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="77" name ="eth_mdio_i" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="78" name ="eth_rmii_crs_dv" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="79" name ="eth_rmii_rxd_0" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="80" name ="eth_rmii_rxd_1" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="81" name ="eth_rmii_rx_er" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="82" name ="eth_rmii_txd_0" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="83" name ="eth_rmii_txd_1" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="84" name ="eth_rmii_tx_en" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="85" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="T8"/>
+  <pin index="86" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="V9"/>
+  <pin index="87" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="R8"/>
+  <pin index="88" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="T6"/>
+  <pin index="89" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="T5"/>
+  <pin index="90" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="T4"/>
+  <pin index="91" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U7"/>
+  <pin index="92" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U6"/>
+  <pin index="93" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V4"/>
+  <pin index="94" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="U3"/>
+  <pin index="95" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="V1"/>
+  <pin index="96" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="R1"/>
+  <pin index="97" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="P5"/>
+  <pin index="98" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="U1"/>
+  <pin index="99" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="R2"/>
+  <pin index="100" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="P2"/>
+  <pin index="101" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="102" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="103" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="104" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="105" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="E16"/>
+  <pin index="106" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="107" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="108" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="109" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="110" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="111" name ="qspi_sck_i" iostandard="LVCMOS33" loc="E9"/>
+  <pin index="112" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+  <pin index="113" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="K5"/>
+  <pin index="114" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="115" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="116" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="K6"/>
+  <pin index="117" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="118" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="119" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="N6"/>
+  <pin index="120" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="M6"/>
+  <pin index="121" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="M3"/>
+  <pin index="122" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="N5"/>
+  <pin index="123" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="N2"/>
+  <pin index="124" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="N4"/>
+  <pin index="125" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="L1"/>
+  <pin index="126" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="M1"/>
+  <pin index="127" name ="temp_scl_i" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="128" name ="temp_sda_i" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="129" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+  <pin index="130" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+  <pin index="131" name ="JA1" iostandard="LVCMOS33" loc="B13"/>
+  <pin index="132" name ="JA2" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="133" name ="JA3" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="134" name ="JA4" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="135" name ="JA7" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="136" name ="JA8" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="137" name ="JA9" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="138" name ="JA10" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="139" name ="JB1" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="140" name ="JB2" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="141" name ="JB3" iostandard="LVCMOS33" loc="V11"/>
+  <pin index="142" name ="JB4" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="143" name ="JB7" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="144" name ="JB8" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="145" name ="JB9" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="146" name ="JB10" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="147" name ="JC1" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="148" name ="JC2" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="149" name ="JC3" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="150" name ="JC4" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="151" name ="JC7" iostandard="LVCMOS33" loc="K1"/>
+  <pin index="152" name ="JC8" iostandard="LVCMOS33" loc="E6"/>
+  <pin index="153" name ="JC9" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="154" name ="JC10" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="155" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="156" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="157" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="158" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="159" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+  <pin index="160" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="161" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+  <pin index="162" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+  <pin index="163" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="164" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+  <pin index="165" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="166" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="167" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="168" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="169" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="170" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+  <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+  <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+  <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/preset.xml
new file mode 100644
index 0000000..97ec555
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4/B.1/preset.xml
@@ -0,0 +1,408 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="emc_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_emc">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_TWPH_PS_MEM_0" value="10000"/>
+			<user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="55000"/>
+			<user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="85000"/>
+			<user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="8000"/>
+			<user_parameter name="CONFIG.C_TPACC_PS_FLASH_0" value="70000"/>
+			<user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="70000"/>
+			<user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="70000"/>
+			<user_parameter name="CONFIG.C_MEM0_TYPE" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="output_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/board.xml
new file mode 100644
index 0000000..1846bf3
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/board.xml
@@ -0,0 +1,1370 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys4_ddr" display_name="Nexys4 DDR" url="https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">C.1</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Nexys4 DDR</description>
+<components>
+  <component name="part0" display_name="Nexys4 DDR" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start">
+    <interfaces>
+      <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+        <description>Accelerometer control through SPI</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ddr2_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr2_sdram" preset_proc="ddr2_sdram_preset"> 
+      <description>DDR2 board interface, it can use MIG IP for connection.</description>
+	  <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <description>16 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+        <description>Dual 7 Seg LED Segments</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="eth_mdio_mdc">
+        <description>Secondary interface to communicate with ethernet phy. </description>
+		<port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_rmii" type="xilinx.com:interface:rmii_rtl:1.0" of_component="eth_rmii">
+        <description>Primary interface to communicate with ethernet phy in RMII mode. </description>
+		<port_maps>
+          <port_map logical_port="TXD" physical_port="eth_rmii_txd" dir="out" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rmii_txd_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXD" physical_port="eth_rmii_rxd" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rmii_rxd_1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_EN" physical_port="eth_rmii_tx_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_tx_en"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_ER" physical_port="eth_rmii_rx_er" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_rx_er"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CRS_DV" physical_port="eth_rmii_crs_dv" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rmii_crs_dv"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+        <description>16 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <port_maps>
+          <port_map logical_port="RESET" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+        <description>7 Segment Display Anodes</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+        <description>Temperature Sensor connected to I2C</description>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="RTSn" physical_port="usb_uart_rts" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rts"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="CTSn" physical_port="usb_uart_cts" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_cts"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="SD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+	<description>Accelerometer controlled through SPI</description>
+  </component>
+  <component name="ddr2_sdram" display_name="DDR2 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+  <description>256 MB Onboard DDR Memory </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr2"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>16 Switches</description>
+  </component>
+  <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Segment Control</description>
+  </component>
+  <component name="eth_rmii" display_name="Ethernet RMII" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>Ethernet RMII Signals</description> 
+  </component>
+  <component name="eth_mdio_mdc" display_name="Ethernet MDIO MDC" type="chip" sub_type="ethernet" major_group="Ethernet">
+  <description>Ethernet MDIO/MDC Signals</description> 
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>16 LEDs</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>Onboard Reset Button</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>2 RGB LEDs</description>
+  </component>
+  <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Anodes</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+	<description>SPI Controlled Temperature Sensor</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+  <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+    <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="5" c1_end_index="20" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+    <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="21" c1_end_index="28" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_eth_mdio_mdc" component1="part0" component2="eth_mdio_mdc">
+    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="29" c1_end_index="30" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_eth_rmii" component1="part0" component2="eth_rmii">
+    <connection_map name="part0_eth_rmii_1" c1_st_index="31" c1_end_index="37" c2_st_index="0" c2_end_index="6"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="38" c1_end_index="53" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="54" c1_end_index="58" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="64" c1_end_index="64" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="65" c1_end_index="70" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+    <connection_map name="part0_seven_seg_led_an_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="4" c1_end_index="4" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+    <connection_map name="part0_temp_sensor_1" c1_st_index="79" c1_end_index="80" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="81" c1_end_index="82" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_usb_uart_rts_cts" c1_st_index="179" c1_end_index="180" c2_st_index="2" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  
+ 
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/part0_pins.xml
new file mode 100644
index 0000000..55f9b06
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/part0_pins.xml
@@ -0,0 +1,162 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="E15"/>
+  <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="4" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="5" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="6" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="7" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="8" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="9" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="10" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="11" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="12" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="13" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="T8"/>
+  <pin index="14" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="U8"/>
+  <pin index="15" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="16" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T13"/>
+  <pin index="17" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="18" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="19" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="20" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="21" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="22" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="23" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="24" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="25" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="26" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="27" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="28" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="29" name ="eth_mdc" iostandard="LVCMOS33" loc="C9"/>
+  <pin index="30" name ="eth_mdio_i" iostandard="LVCMOS33" loc="A9"/>
+  <pin index="31" name ="eth_rmii_crs_dv" iostandard="LVCMOS33" loc="D9"/>
+  <pin index="32" name ="eth_rmii_rxd_0" iostandard="LVCMOS33" loc="C11"/>
+  <pin index="33" name ="eth_rmii_rxd_1" iostandard="LVCMOS33" loc="D10"/>
+  <pin index="34" name ="eth_rmii_rx_er" iostandard="LVCMOS33" loc="C10"/>
+  <pin index="35" name ="eth_rmii_txd_0" iostandard="LVCMOS33" loc="A10"/>
+  <pin index="36" name ="eth_rmii_txd_1" iostandard="LVCMOS33" loc="A8"/>
+  <pin index="37" name ="eth_rmii_tx_en" iostandard="LVCMOS33" loc="B9"/>
+  <pin index="38" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="39" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="K15"/>
+  <pin index="40" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="41" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="42" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="43" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="44" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="45" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="46" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="47" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="48" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="49" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="50" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="51" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="52" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="53" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="V11"/>
+  <pin index="54" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="55" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="56" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="57" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="58" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="59" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="60" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="61" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="62" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="63" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="64" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+  <pin index="65" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="66" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="67" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="68" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="69" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="70" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="71" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="72" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="73" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="74" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="75" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="76" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="77" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="78" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="79" name ="temp_scl_i" iostandard="LVCMOS33" loc="C14"/>
+  <pin index="80" name ="temp_sda_i" iostandard="LVCMOS33" loc="C15"/>
+  <pin index="81" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+  <pin index="82" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+  <pin index="83" name ="JA1" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="84" name ="JA2" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="85" name ="JA3" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="86" name ="JA4" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="87" name ="JA7" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="88" name ="JA8" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="89" name ="JA9" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="90" name ="JA10" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="91" name ="JB1" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="92" name ="JB2" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="93" name ="JB3" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="94" name ="JB4" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="95" name ="JB7" iostandard="LVCMOS33" loc="E16"/>
+  <pin index="96" name ="JB8" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="97" name ="JB9" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="98" name ="JB10" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="99" name ="JC1"  iostandard="LVCMOS33" loc="K1"/>
+  <pin index="100" name ="JC2" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="101" name ="JC3" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="102" name ="JC4" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="103" name ="JC7" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="104" name ="JC8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="105" name ="JC9" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="106" name ="JC10" iostandard="LVCMOS33" loc="E6"/>
+  <pin index="107" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="108" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="109" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="110" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="111" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+  <pin index="112" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="113" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+  <pin index="114" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+  <pin index="115" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="116" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+  <pin index="117" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="118" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="119" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="120" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="121" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="122" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+  <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+  <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+  <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+  <pin index="179" name ="usb_uart_rts" iostandard="LVCMOS33" loc="E5"/>
+  <pin index="180" name ="usb_uart_cts" iostandard="LVCMOS33" loc="D3"/>
+  
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/preset.xml
new file mode 100644
index 0000000..7128cce
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys4_ddr/C.1/preset.xml
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr2_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="output_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/board.xml
new file mode 100644
index 0000000..85ad708
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/board.xml
@@ -0,0 +1,1331 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys_video" display_name="Nexys Video" url="https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Nexys Video</description>
+<components>
+  <component name="part0" display_name="Nexys Video" type="fpga" part_name="xc7a200tsbg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+      <description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_8bits" preset_proc="dip_switches_8bits_preset">
+        <description>8 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_8bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_8bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_8bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_8bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_8bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_8bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_8bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_8bits_tri_i_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+        <description>Secondary interface to communicate with ethernet phy. </description>
+		<port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
+        <description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
+		<port_maps>
+          <port_map logical_port="TD" physical_port="eth_txd" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_txd_1"/> 
+              <pin_map port_index="2" component_pin="eth_txd_2"/> 
+              <pin_map port_index="3" component_pin="eth_txd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CTL" physical_port="eth_tx_ctl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_ctl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TXC" physical_port="eth_tx_clk" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RD" physical_port="eth_rxd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rxd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rxd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rxd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CTL" physical_port="eth_rx_ctl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_ctl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXC" physical_port="eth_rx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="phy_reset_out" type="xilinx.com:signal:reset_rtl:1.0" of_component="phy_onboard">
+          <description>Onboard Reset Button</description>
+		  <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernet" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="RESET" physical_port="phy_reset_n" dir="out">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="phy_reset_n"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+      <interface mode="master" name="led_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_8bits" preset_proc="led_8bits_preset">
+        <description>8 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_8bits_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RESET" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset">
+        <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+		<port_maps>
+          <port_map logical_port="clk" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <description>HDMI DDC</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+        <description>HDMI Out</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  
+	   <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="oled" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="oled" preset_proc="oled_preset">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+		  <port_map logical_port="PIN2_I" physical_port="OLED2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="OLED2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="OLED2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="OLED4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="OLED4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="OLED4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="OLED7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="OLED7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="OLED7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="OLED8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="OLED8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="OLED8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="OLED9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="OLED9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="OLED9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="OLED10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="OLED10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="OLED10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>512MB 800Mt/s on-board DDR3 </description>
+  </component>
+  <component name="dip_switches_8bits" display_name="8 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>Switches 7 to 0</description>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	 <component_modes>
+        <component_mode name="rgmii" display_name="RGMII mode">
+		  <interfaces>
+            <interface name="eth_rgmii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1"/>
+			<interface name="phy_reset_out" order="2" optional="true"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+   <component name="oled" display_name="Onboard OLED" type="chip" sub_type="chip" major_group="GPIO">
+  <component_modes>
+	<component_mode name="apmodoled" display_name="Digilent PmodOLED IP">
+	  <interfaces>
+		<interface name="oled"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="oled"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard OLED (DISP1)</description>
+  </component>
+  <component name="led_8bits" display_name="8 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 7 to 0</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>System Reset Button</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI input (Requires Digilent's TMDS interface)</description>
+	<component_modes>
+        <component_mode name="HDMI_IN" display_name="HDMI In">
+		  <interfaces>
+            <interface name="hdmi_in" order="0"/>
+            <interface name="hdmi_in_ddc" order="1"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI in HPD (Connected to LD8)</description>
+  </component>
+  <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
+  </component>
+  <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI out HPD</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+ <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_8bits" component1="part0" component2="dip_switches_8bits">
+    <connection_map name="part0_dip_switches_8bits_1" c1_st_index="1" c1_end_index="8" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_eth_mdio_mdc" component1="part0" component2="phy_onboard">
+	<connection_map name="part0_eth_rgmii_1" c1_st_index="12" c1_end_index="23" c2_st_index="0" c2_end_index="11"/>
+    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="9" c1_end_index="10" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_eth_phy_reset_n" c1_st_index="45" c1_end_index="45" c2_st_index="0" c2_end_index="0"/> 
+  </connection>
+  <connection name="part0_led_8bits" component1="part0" component2="led_8bits">
+    <connection_map name="part0_led_8bits_1" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_phy_reset_out" component1="part0" component2="phy_reset_out">
+    <connection_map name="part0_phy_reset_out_1" c1_st_index="11" c1_end_index="11" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="32" c1_end_index="36" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="37" c1_end_index="41" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="42" c1_end_index="42" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+    <connection_map name="part0_hdmi_in_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+	<connection_map name="part0_hdmi_in_ddc" c1_st_index="64" c1_end_index="65" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="46" c1_end_index="46" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+    <connection_map name="part0_hdmi_out_1" c1_st_index="56" c1_end_index="63" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+    <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="55" c1_end_index="55" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="66" c1_end_index="73" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="74" c1_end_index="81" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+   <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="82" c1_end_index="89" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="90" c1_end_index="97" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_oled" component1="part0" component2="oled">
+    <connection_map name="part0_oled_1" c1_st_index="98" c1_end_index="103" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="104" c1_end_index="110" c2_st_index="0" c2_end_index="6"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/part0_pins.xml
new file mode 100644
index 0000000..bcd4d04
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/part0_pins.xml
@@ -0,0 +1,139 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a200tsbg484-1">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="R4"/>
+  <pin index="1" name ="dip_switches_8bits_tri_i_0" iostandard="LVCMOS33" loc="E22"/>
+  <pin index="2" name ="dip_switches_8bits_tri_i_1" iostandard="LVCMOS33" loc="F21"/>
+  <pin index="3" name ="dip_switches_8bits_tri_i_2" iostandard="LVCMOS33" loc="G21"/>
+  <pin index="4" name ="dip_switches_8bits_tri_i_3" iostandard="LVCMOS33" loc="G22"/>
+  <pin index="5" name ="dip_switches_8bits_tri_i_4" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="6" name ="dip_switches_8bits_tri_i_5" iostandard="LVCMOS33" loc="J16"/>
+  <pin index="7" name ="dip_switches_8bits_tri_i_6" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="8" name ="dip_switches_8bits_tri_i_7" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="9" name ="eth_mdc" iostandard="LVCMOS25" loc="AA16"/>
+  <pin index="10" name ="eth_mdio_i" iostandard="LVCMOS25" loc="Y16"/>
+  <pin index="11" name ="eth_rst" iostandard="LVCMOS33" loc="U7"/>
+  <pin index="12" name ="eth_rxd_0" iostandard="LVCMOS25" loc="AB16"/>
+  <pin index="13" name ="eth_rxd_1" iostandard="LVCMOS25" loc="AA15"/>
+  <pin index="14" name ="eth_rxd_2" iostandard="LVCMOS25" loc="AB15"/>
+  <pin index="15" name ="eth_rxd_3" iostandard="LVCMOS25" loc="AB11"/>
+  <pin index="16" name ="eth_rx_clk" iostandard="LVCMOS25" loc="V13"/>
+  <pin index="17" name ="eth_rx_ctl" iostandard="LVCMOS25" loc="W10"/>
+  <pin index="18" name ="eth_txd_0" iostandard="LVCMOS25" loc="Y12"/>
+  <pin index="19" name ="eth_txd_1" iostandard="LVCMOS25" loc="W12"/>
+  <pin index="20" name ="eth_txd_2" iostandard="LVCMOS25" loc="W11"/>
+  <pin index="21" name ="eth_txd_3" iostandard="LVCMOS25" loc="Y11"/>
+  <pin index="22" name ="eth_tx_clk" iostandard="LVCMOS25" loc="AA14"/>
+  <pin index="23" name ="eth_tx_ctl" iostandard="LVCMOS25" loc="V10"/>
+  <pin index="24" name ="led_8bits_tri_o_0" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="25" name ="led_8bits_tri_o_1" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="26" name ="led_8bits_tri_o_2" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="27" name ="led_8bits_tri_o_3" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="28" name ="led_8bits_tri_o_4" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="29" name ="led_8bits_tri_o_5" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="30" name ="led_8bits_tri_o_6" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="31" name ="led_8bits_tri_o_7" iostandard="LVCMOS33" loc="Y13"/>
+  <pin index="32" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="B22"/>
+  <pin index="33" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="34" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="C22"/>
+  <pin index="35" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="36" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="D22"/>
+  <pin index="37" name ="qspi_csn_i" iostandard="LVCMOS33" loc="T19"/>
+  <pin index="38" name ="qspi_db0_i" iostandard="LVCMOS33" loc="P22"/>
+  <pin index="39" name ="qspi_db1_i" iostandard="LVCMOS33" loc="R22"/>
+  <pin index="40" name ="qspi_db2_i" iostandard="LVCMOS33" loc="P21"/>
+  <pin index="41" name ="qspi_db3_i" iostandard="LVCMOS33" loc="R21"/>
+  <pin index="42" name ="reset" iostandard="LVCMOS15" loc="G4"/>
+  <pin index="43" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V18"/>
+  <pin index="44" name ="usb_uart_txd" iostandard="LVCMOS33" loc="AA19"/>
+  <pin index="45" name ="phy_reset_n" iostandard="LVCMOS33" loc="U7"/>
+  <pin index="46" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="AB12"/>
+  <pin index="47" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="V4"/>
+  <pin index="48" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="W4"/>
+  <pin index="49" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="Y3"/>
+  <pin index="50" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="W2"/>
+  <pin index="51" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="U2"/>
+  <pin index="52" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="AA3"/>
+  <pin index="53" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="Y2"/>
+  <pin index="54" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="V2"/>
+  <pin index="55" name ="hdmi_tx_hpd" iostandard="LVCMOS18" loc="AB13"/>
+  <pin index="56" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="T1"/>
+  <pin index="57" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="U1"/>
+  <pin index="58" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="W1"/>
+  <pin index="59" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="AA1"/>
+  <pin index="60" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="AB3"/>
+  <pin index="61" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="Y1"/>
+  <pin index="62" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="AB1"/>
+  <pin index="63" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="AB2"/>
+  <pin index="64" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="Y4"/>
+  <pin index="65" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="AB5"/>
+  <pin index="66" name ="JA1" iostandard="LVCMOS33" loc="AB22"/>
+  <pin index="67" name ="JA2" iostandard="LVCMOS33" loc="AB21"/>
+  <pin index="68" name ="JA3" iostandard="LVCMOS33" loc="AB20"/>
+  <pin index="69" name ="JA4" iostandard="LVCMOS33" loc="AB18"/>
+  <pin index="70" name ="JA7" iostandard="LVCMOS33" loc="Y21"/>
+  <pin index="71" name ="JA8" iostandard="LVCMOS33" loc="AA21"/>
+  <pin index="72" name ="JA9" iostandard="LVCMOS33" loc="AA20"/>
+  <pin index="73" name ="JA10" iostandard="LVCMOS33" loc="AA18"/>
+  <pin index="74" name ="JB1" iostandard="LVCMOS33" loc="V9"/>
+  <pin index="75" name ="JB2" iostandard="LVCMOS33" loc="V8"/>
+  <pin index="76" name ="JB3" iostandard="LVCMOS33" loc="V7"/>
+  <pin index="77" name ="JB4" iostandard="LVCMOS33" loc="W7"/>
+  <pin index="78" name ="JB7" iostandard="LVCMOS33" loc="W9"/>
+  <pin index="79" name ="JB8" iostandard="LVCMOS33" loc="Y9"/>
+  <pin index="80" name ="JB9" iostandard="LVCMOS33" loc="Y8"/>
+  <pin index="81" name ="JB10" iostandard="LVCMOS33" loc="Y7"/>
+  <pin index="82" name ="JC1" iostandard="LVCMOS33" loc="Y6"/>
+  <pin index="83" name ="JC2" iostandard="LVCMOS33" loc="AA6"/>
+  <pin index="84" name ="JC3" iostandard="LVCMOS33" loc="AA8"/>
+  <pin index="85" name ="JC4" iostandard="LVCMOS33" loc="AB8"/>
+  <pin index="86" name ="JC7" iostandard="LVCMOS33" loc="R6"/>
+  <pin index="87" name ="JC8" iostandard="LVCMOS33" loc="T6"/>
+  <pin index="88" name ="JC9" iostandard="LVCMOS33" loc="AB7"/>
+  <pin index="89" name ="JC10" iostandard="LVCMOS33" loc="AB6"/>
+  <pin index="90" name ="JXADC1" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="91" name ="JXADC2" iostandard="LVCMOS33" loc="H13"/>
+  <pin index="92" name ="JXADC3" iostandard="LVCMOS33" loc="G15"/>
+  <pin index="93" name ="JXADC4" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="94" name ="JXADC7" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="95" name ="JXADC8" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="96" name ="JXADC9" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="97" name ="JXADC10" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="98" name ="OLED2" iostandard="LVCMOS33" loc="Y22"/>
+  <pin index="99" name ="OLED4" iostandard="LVCMOS33" loc="W21"/>
+  <pin index="100" name ="OLED7" iostandard="LVCMOS33" loc="W22"/>
+  <pin index="101" name ="OLED8" iostandard="LVCMOS33" loc="U21"/>
+  <pin index="102" name ="OLED9" iostandard="LVCMOS33" loc="P20"/>
+  <pin index="103" name ="OLED10" iostandard="LVCMOS33" loc="V22"/>
+  <pin index="104" name ="SD1" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="105" name ="SD2" iostandard="LVCMOS33" loc="W20"/>
+  <pin index="106" name ="SD3" iostandard="LVCMOS33" loc="V19"/>
+  <pin index="107" name ="SD4" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="108" name ="SD7" iostandard="LVCMOS33" loc="T21"/>
+  <pin index="109" name ="SD8" iostandard="LVCMOS33" loc="T20"/>
+  <pin index="110" name ="SD9" iostandard="LVCMOS33" loc="T18"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/preset.xml
new file mode 100644
index 0000000..2d64584
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.1/preset.xml
@@ -0,0 +1,349 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="oled_preset">
+    <ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
+        <user_parameters>
+          <user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/> 
+          <user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="led_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_diff_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="200"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN2_D">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="200"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Differential_clock_capable_pin"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/board.xml
new file mode 100644
index 0000000..5f1a94e
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/board.xml
@@ -0,0 +1,1331 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys_video" display_name="Nexys Video" url="https://digilent.com/reference/programmable-logic/nexys-video/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.2</file_version>
+<description>Nexys Video</description>
+<components>
+  <component name="part0" display_name="Nexys Video" type="fpga" part_name="xc7a200tsbg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/nexys-video/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+      <description>DDR3 board interface, it can use MIG IP for connection.</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_8bits" preset_proc="dip_switches_8bits_preset">
+        <description>8 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_8bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_8bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_8bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_8bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_8bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_8bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_8bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_8bits_tri_i_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+        <description>Secondary interface to communicate with ethernet phy. </description>
+		<port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
+        <description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
+		<port_maps>
+          <port_map logical_port="TD" physical_port="eth_txd" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_txd_0"/> 
+              <pin_map port_index="1" component_pin="eth_txd_1"/> 
+              <pin_map port_index="2" component_pin="eth_txd_2"/> 
+              <pin_map port_index="3" component_pin="eth_txd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CTL" physical_port="eth_tx_ctl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_ctl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TXC" physical_port="eth_tx_clk" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_tx_clk"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RD" physical_port="eth_rxd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rxd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rxd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rxd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rxd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CTL" physical_port="eth_rx_ctl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_ctl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXC" physical_port="eth_rx_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rx_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	    <interface mode="master" name="phy_reset_out" type="xilinx.com:signal:reset_rtl:1.0" of_component="phy_onboard">
+        <description>Ethernet PHY Reset</description>
+		      <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernet" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="RST" physical_port="phy_reset_n" dir="out">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="phy_reset_n"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+      <interface mode="master" name="led_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_8bits" preset_proc="led_8bits_preset">
+        <description>8 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_8bits_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Onboard Reset Button</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset">
+        <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+		<port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <description>HDMI DDC</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+        <description>HDMI Out</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  
+	   <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="oled" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="oled" preset_proc="oled_preset">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+		  <port_map logical_port="PIN2_I" physical_port="OLED2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="OLED2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="OLED2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="OLED4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="OLED4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="OLED4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="OLED7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="OLED7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="OLED7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="OLED8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="OLED8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="OLED8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="OLED9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="OLED9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="OLED9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="OLED10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="OLED10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="OLED10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>512MB 800Mt/s on-board DDR3 </description>
+  </component>
+  <component name="dip_switches_8bits" display_name="8 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>Switches 7 to 0</description>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	 <component_modes>
+        <component_mode name="rgmii" display_name="RGMII mode">
+		  <interfaces>
+            <interface name="eth_rgmii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1"/>
+			<interface name="phy_reset_out" order="2" optional="true"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+   <component name="oled" display_name="Onboard OLED" type="chip" sub_type="chip" major_group="GPIO">
+  <component_modes>
+	<component_mode name="apmodoled" display_name="Digilent PmodOLED IP">
+	  <interfaces>
+		<interface name="oled"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="oled"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard OLED (DISP1)</description>
+  </component>
+  <component name="led_8bits" display_name="8 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 7 to 0</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>System Reset Button</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI input (Requires Digilent's TMDS interface)</description>
+	<component_modes>
+        <component_mode name="HDMI_IN" display_name="HDMI In">
+		  <interfaces>
+            <interface name="hdmi_in" order="0"/>
+            <interface name="hdmi_in_ddc" order="1"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI in HPD (Connected to LD8)</description>
+  </component>
+  <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
+  </component>
+  <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI out HPD</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+ <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_dip_switches_8bits" component1="part0" component2="dip_switches_8bits">
+    <connection_map name="part0_dip_switches_8bits_1" c1_st_index="1" c1_end_index="8" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_eth_mdio_mdc" component1="part0" component2="phy_onboard">
+	<connection_map name="part0_eth_rgmii_1" c1_st_index="12" c1_end_index="23" c2_st_index="0" c2_end_index="11"/>
+    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="9" c1_end_index="10" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_eth_phy_reset_n" c1_st_index="45" c1_end_index="45" c2_st_index="0" c2_end_index="0"/> 
+  </connection>
+  <connection name="part0_led_8bits" component1="part0" component2="led_8bits">
+    <connection_map name="part0_led_8bits_1" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_phy_reset_out" component1="part0" component2="phy_reset_out">
+    <connection_map name="part0_phy_reset_out_1" c1_st_index="11" c1_end_index="11" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="32" c1_end_index="36" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="37" c1_end_index="41" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="42" c1_end_index="42" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+    <connection_map name="part0_hdmi_in_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+	<connection_map name="part0_hdmi_in_ddc" c1_st_index="64" c1_end_index="65" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="46" c1_end_index="46" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+    <connection_map name="part0_hdmi_out_1" c1_st_index="56" c1_end_index="63" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+    <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="55" c1_end_index="55" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="66" c1_end_index="73" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="74" c1_end_index="81" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+   <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="82" c1_end_index="89" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="90" c1_end_index="97" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_oled" component1="part0" component2="oled">
+    <connection_map name="part0_oled_1" c1_st_index="98" c1_end_index="103" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="104" c1_end_index="110" c2_st_index="0" c2_end_index="6"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/part0_pins.xml
new file mode 100644
index 0000000..bcd4d04
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/part0_pins.xml
@@ -0,0 +1,139 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a200tsbg484-1">
+<pins>
+  <pin index="0" name ="clk" iostandard="LVCMOS33" loc="R4"/>
+  <pin index="1" name ="dip_switches_8bits_tri_i_0" iostandard="LVCMOS33" loc="E22"/>
+  <pin index="2" name ="dip_switches_8bits_tri_i_1" iostandard="LVCMOS33" loc="F21"/>
+  <pin index="3" name ="dip_switches_8bits_tri_i_2" iostandard="LVCMOS33" loc="G21"/>
+  <pin index="4" name ="dip_switches_8bits_tri_i_3" iostandard="LVCMOS33" loc="G22"/>
+  <pin index="5" name ="dip_switches_8bits_tri_i_4" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="6" name ="dip_switches_8bits_tri_i_5" iostandard="LVCMOS33" loc="J16"/>
+  <pin index="7" name ="dip_switches_8bits_tri_i_6" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="8" name ="dip_switches_8bits_tri_i_7" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="9" name ="eth_mdc" iostandard="LVCMOS25" loc="AA16"/>
+  <pin index="10" name ="eth_mdio_i" iostandard="LVCMOS25" loc="Y16"/>
+  <pin index="11" name ="eth_rst" iostandard="LVCMOS33" loc="U7"/>
+  <pin index="12" name ="eth_rxd_0" iostandard="LVCMOS25" loc="AB16"/>
+  <pin index="13" name ="eth_rxd_1" iostandard="LVCMOS25" loc="AA15"/>
+  <pin index="14" name ="eth_rxd_2" iostandard="LVCMOS25" loc="AB15"/>
+  <pin index="15" name ="eth_rxd_3" iostandard="LVCMOS25" loc="AB11"/>
+  <pin index="16" name ="eth_rx_clk" iostandard="LVCMOS25" loc="V13"/>
+  <pin index="17" name ="eth_rx_ctl" iostandard="LVCMOS25" loc="W10"/>
+  <pin index="18" name ="eth_txd_0" iostandard="LVCMOS25" loc="Y12"/>
+  <pin index="19" name ="eth_txd_1" iostandard="LVCMOS25" loc="W12"/>
+  <pin index="20" name ="eth_txd_2" iostandard="LVCMOS25" loc="W11"/>
+  <pin index="21" name ="eth_txd_3" iostandard="LVCMOS25" loc="Y11"/>
+  <pin index="22" name ="eth_tx_clk" iostandard="LVCMOS25" loc="AA14"/>
+  <pin index="23" name ="eth_tx_ctl" iostandard="LVCMOS25" loc="V10"/>
+  <pin index="24" name ="led_8bits_tri_o_0" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="25" name ="led_8bits_tri_o_1" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="26" name ="led_8bits_tri_o_2" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="27" name ="led_8bits_tri_o_3" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="28" name ="led_8bits_tri_o_4" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="29" name ="led_8bits_tri_o_5" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="30" name ="led_8bits_tri_o_6" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="31" name ="led_8bits_tri_o_7" iostandard="LVCMOS33" loc="Y13"/>
+  <pin index="32" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="B22"/>
+  <pin index="33" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="34" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="C22"/>
+  <pin index="35" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="36" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="D22"/>
+  <pin index="37" name ="qspi_csn_i" iostandard="LVCMOS33" loc="T19"/>
+  <pin index="38" name ="qspi_db0_i" iostandard="LVCMOS33" loc="P22"/>
+  <pin index="39" name ="qspi_db1_i" iostandard="LVCMOS33" loc="R22"/>
+  <pin index="40" name ="qspi_db2_i" iostandard="LVCMOS33" loc="P21"/>
+  <pin index="41" name ="qspi_db3_i" iostandard="LVCMOS33" loc="R21"/>
+  <pin index="42" name ="reset" iostandard="LVCMOS15" loc="G4"/>
+  <pin index="43" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V18"/>
+  <pin index="44" name ="usb_uart_txd" iostandard="LVCMOS33" loc="AA19"/>
+  <pin index="45" name ="phy_reset_n" iostandard="LVCMOS33" loc="U7"/>
+  <pin index="46" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="AB12"/>
+  <pin index="47" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="V4"/>
+  <pin index="48" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="W4"/>
+  <pin index="49" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="Y3"/>
+  <pin index="50" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="W2"/>
+  <pin index="51" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="U2"/>
+  <pin index="52" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="AA3"/>
+  <pin index="53" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="Y2"/>
+  <pin index="54" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="V2"/>
+  <pin index="55" name ="hdmi_tx_hpd" iostandard="LVCMOS18" loc="AB13"/>
+  <pin index="56" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="T1"/>
+  <pin index="57" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="U1"/>
+  <pin index="58" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="W1"/>
+  <pin index="59" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="AA1"/>
+  <pin index="60" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="AB3"/>
+  <pin index="61" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="Y1"/>
+  <pin index="62" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="AB1"/>
+  <pin index="63" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="AB2"/>
+  <pin index="64" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="Y4"/>
+  <pin index="65" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="AB5"/>
+  <pin index="66" name ="JA1" iostandard="LVCMOS33" loc="AB22"/>
+  <pin index="67" name ="JA2" iostandard="LVCMOS33" loc="AB21"/>
+  <pin index="68" name ="JA3" iostandard="LVCMOS33" loc="AB20"/>
+  <pin index="69" name ="JA4" iostandard="LVCMOS33" loc="AB18"/>
+  <pin index="70" name ="JA7" iostandard="LVCMOS33" loc="Y21"/>
+  <pin index="71" name ="JA8" iostandard="LVCMOS33" loc="AA21"/>
+  <pin index="72" name ="JA9" iostandard="LVCMOS33" loc="AA20"/>
+  <pin index="73" name ="JA10" iostandard="LVCMOS33" loc="AA18"/>
+  <pin index="74" name ="JB1" iostandard="LVCMOS33" loc="V9"/>
+  <pin index="75" name ="JB2" iostandard="LVCMOS33" loc="V8"/>
+  <pin index="76" name ="JB3" iostandard="LVCMOS33" loc="V7"/>
+  <pin index="77" name ="JB4" iostandard="LVCMOS33" loc="W7"/>
+  <pin index="78" name ="JB7" iostandard="LVCMOS33" loc="W9"/>
+  <pin index="79" name ="JB8" iostandard="LVCMOS33" loc="Y9"/>
+  <pin index="80" name ="JB9" iostandard="LVCMOS33" loc="Y8"/>
+  <pin index="81" name ="JB10" iostandard="LVCMOS33" loc="Y7"/>
+  <pin index="82" name ="JC1" iostandard="LVCMOS33" loc="Y6"/>
+  <pin index="83" name ="JC2" iostandard="LVCMOS33" loc="AA6"/>
+  <pin index="84" name ="JC3" iostandard="LVCMOS33" loc="AA8"/>
+  <pin index="85" name ="JC4" iostandard="LVCMOS33" loc="AB8"/>
+  <pin index="86" name ="JC7" iostandard="LVCMOS33" loc="R6"/>
+  <pin index="87" name ="JC8" iostandard="LVCMOS33" loc="T6"/>
+  <pin index="88" name ="JC9" iostandard="LVCMOS33" loc="AB7"/>
+  <pin index="89" name ="JC10" iostandard="LVCMOS33" loc="AB6"/>
+  <pin index="90" name ="JXADC1" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="91" name ="JXADC2" iostandard="LVCMOS33" loc="H13"/>
+  <pin index="92" name ="JXADC3" iostandard="LVCMOS33" loc="G15"/>
+  <pin index="93" name ="JXADC4" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="94" name ="JXADC7" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="95" name ="JXADC8" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="96" name ="JXADC9" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="97" name ="JXADC10" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="98" name ="OLED2" iostandard="LVCMOS33" loc="Y22"/>
+  <pin index="99" name ="OLED4" iostandard="LVCMOS33" loc="W21"/>
+  <pin index="100" name ="OLED7" iostandard="LVCMOS33" loc="W22"/>
+  <pin index="101" name ="OLED8" iostandard="LVCMOS33" loc="U21"/>
+  <pin index="102" name ="OLED9" iostandard="LVCMOS33" loc="P20"/>
+  <pin index="103" name ="OLED10" iostandard="LVCMOS33" loc="V22"/>
+  <pin index="104" name ="SD1" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="105" name ="SD2" iostandard="LVCMOS33" loc="W20"/>
+  <pin index="106" name ="SD3" iostandard="LVCMOS33" loc="V19"/>
+  <pin index="107" name ="SD4" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="108" name ="SD7" iostandard="LVCMOS33" loc="T21"/>
+  <pin index="109" name ="SD8" iostandard="LVCMOS33" loc="T20"/>
+  <pin index="110" name ="SD9" iostandard="LVCMOS33" loc="T18"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/preset.xml
new file mode 100644
index 0000000..2d64584
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys_video/A.0/1.2/preset.xml
@@ -0,0 +1,349 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="oled_preset">
+    <ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
+        <user_parameters>
+          <user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/> 
+          <user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="output_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+   <ip_preset preset_proc_name="led_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="sys_diff_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="200"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN2_D">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="200"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Differential_clock_capable_pin"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/board.xml
new file mode 100644
index 0000000..b7164f2
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/board.xml
@@ -0,0 +1,1020 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<!-- confirm url -->
+<board schema_version="2.0" vendor="digilentinc.com" name="sword" display_name="Sword" url="https://reference.digilentinc.com/reference/programmable-logic/sword/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">C.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Sword</description>
+<components>
+  <component name="part0" display_name="Sword" type="fpga" part_name="xc7k325tffg900-2" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/sword/start">
+    <interfaces>
+	  <!-- Clock Signal -->
+	  <interface mode="slave" name="sys_diff_clock" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sys_diff_clock" preset_proc="sys_diff_clock_preset">
+        <description>Differential System Clock</description>
+	    <parameters>
+	      <parameter name="frequency" value="200000000"/>
+	    </parameters>
+	    <preferred_ips>
+	      <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+	    </preferred_ips>
+	    <port_maps>
+	      <port_map logical_port="CLK_P" physical_port="clk_p" dir="in">
+	        <pin_maps>
+	          <pin_map port_index="0" component_pin="clk_p"/>
+	        </pin_maps>
+	      </port_map>
+	      <port_map logical_port="CLK_N" physical_port="clk_n" dir="in">
+	        <pin_maps>
+	          <pin_map port_index="0" component_pin="clk_n"/>
+	        </pin_maps>
+	      </port_map>
+	    </port_maps>
+	  </interface>
+      <!-- User Reset Button-->
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>User Reset Button</description>
+		<preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+		<port_maps>
+          <port_map logical_port="RESET" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+        </parameters>
+      </interface>
+      <!-- Switches -->
+	  <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <description>16 DIP Switches</description>
+		<preferred_ips>
+	      <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1"  component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2"  component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3"  component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4"  component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5"  component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6"  component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7"  component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8"  component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9"  component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <!-- LEDs -->
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="led_16bits_preset">
+        <description>16 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1"  component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2"  component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3"  component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4"  component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5"  component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6"  component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7"  component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8"  component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9"  component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <!-- RGB LEDs -->
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+		  <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1"  component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2"  component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3"  component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4"  component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5"  component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <!-- Twenty-Five Button Keypad -->
+      <interface mode="master" name="keypad" type="xilinx.com:interface:gpio_rtl:1.0" of_component="keypad" preset_proc="keypad_preset">
+        <description>25 Button Keypad</description>
+		<preferred_ips>
+		  <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="keypad_tri_o" dir="out" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="keypad_col_0"/> 
+              <pin_map port_index="1"  component_pin="keypad_col_1"/> 
+              <pin_map port_index="2"  component_pin="keypad_col_2"/> 
+              <pin_map port_index="3"  component_pin="keypad_col_3"/> 
+              <pin_map port_index="4"  component_pin="keypad_col_4"/> 
+              <pin_map port_index="5"  component_pin="keypad_row_0"/> 
+              <pin_map port_index="6"  component_pin="keypad_row_1"/> 
+              <pin_map port_index="7"  component_pin="keypad_row_2"/> 
+              <pin_map port_index="8"  component_pin="keypad_row_3"/> 
+              <pin_map port_index="9"  component_pin="keypad_row_4"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="keypad_tri_o" dir="in" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="keypad_col_0"/> 
+              <pin_map port_index="1"  component_pin="keypad_col_1"/> 
+              <pin_map port_index="2"  component_pin="keypad_col_2"/> 
+              <pin_map port_index="3"  component_pin="keypad_col_3"/> 
+              <pin_map port_index="4"  component_pin="keypad_col_4"/> 
+              <pin_map port_index="5"  component_pin="keypad_row_0"/> 
+              <pin_map port_index="6"  component_pin="keypad_row_1"/> 
+              <pin_map port_index="7"  component_pin="keypad_row_2"/> 
+              <pin_map port_index="8"  component_pin="keypad_row_3"/> 
+              <pin_map port_index="9"  component_pin="keypad_row_4"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="keypad_tri_o" dir="in" left="9" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="keypad_col_0"/> 
+              <pin_map port_index="1"  component_pin="keypad_col_1"/> 
+              <pin_map port_index="2"  component_pin="keypad_col_2"/> 
+              <pin_map port_index="3"  component_pin="keypad_col_3"/> 
+              <pin_map port_index="4"  component_pin="keypad_col_4"/> 
+              <pin_map port_index="5"  component_pin="keypad_row_0"/> 
+              <pin_map port_index="6"  component_pin="keypad_row_1"/> 
+              <pin_map port_index="7"  component_pin="keypad_row_2"/> 
+              <pin_map port_index="8"  component_pin="keypad_row_3"/> 
+              <pin_map port_index="9"  component_pin="keypad_row_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <!-- Seven Segment Display -->
+      <interface mode="master" name="sseg" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sseg" preset_proc="sseg_preset">
+        <description>7 Segment Display</description>
+		<preferred_ips>
+		  <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="sseg_o" dir="out" left="2" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="sseg_clk"/> 
+              <pin_map port_index="1"  component_pin="sseg_en"/> 
+              <pin_map port_index="2"  component_pin="sseg_sdo"/>
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="sseg_o" dir="in" left="2" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="sseg_clk"/> 
+              <pin_map port_index="1"  component_pin="sseg_en"/> 
+              <pin_map port_index="2"  component_pin="sseg_sdo"/>
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="sseg_o" dir="in" left="2" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0"  component_pin="sseg_clk"/> 
+              <pin_map port_index="1"  component_pin="sseg_en"/> 
+              <pin_map port_index="2"  component_pin="sseg_sdo"/>
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <!-- Pmod Header JA -->
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+      <!-- Pmod Header JB -->
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+      <!-- Pmod Header JC -->
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+      <!-- Pmod Header JD -->
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+      <!-- USB-UART Interface -->
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="usb_uart_preset">
+        <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <!-- QSPI Flash -->
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <!-- DDR3 SDRAM -->
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+        <description>DDR3 Interface</description>
+	    <preferred_ips>
+		  <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	    </preferred_ips>
+	  </interface>
+	  <!-- Ethernet PHY -->
+      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+        <description>Secondary interface to communicate with ethernet phy. </description>
+		<port_maps>
+          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_mdc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
+        <description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
+		<port_maps>
+          <port_map logical_port="TD" physical_port="eth_rgmii_td" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_td_0"/> 
+              <pin_map port_index="1" component_pin="eth_rgmii_td_1"/> 
+              <pin_map port_index="2" component_pin="eth_rgmii_td_2"/> 
+              <pin_map port_index="3" component_pin="eth_rgmii_td_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RD" physical_port="eth_rgmii_rd" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_rd_0"/> 
+              <pin_map port_index="1" component_pin="eth_rgmii_rd_1"/> 
+              <pin_map port_index="2" component_pin="eth_rgmii_rd_2"/> 
+              <pin_map port_index="3" component_pin="eth_rgmii_rd_3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RX_CTL" physical_port="eth_rgmii_rx_ctl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_rx_ctl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TX_CTL" physical_port="eth_rgmii_tx_ctl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_tx_ctl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="TXC" physical_port="eth_rgmii_txc" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_txc"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RXC" physical_port="eth_rgmii_rxc" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="eth_rgmii_rxc"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	</interfaces>
+  </component>
+  
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+	<description>1 GB 1800Mt/s on-board DDR3 </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="1GB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 15 to 0</description>
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 15 to 0</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>RGB LEDs 16 and 17</description>
+  </component>
+  <component name="keypad" display_name="25 Button Keypad" type="chip" sub_type="switch" major_group="GPIO">
+	<description>25 Button Keypad</description>
+  </component>
+  <component name="sseg" display_name="7 Segment Display" type="chip" sub_type="led" major_group="GPIO">
+	<description>7 Segment Display</description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>System Reset Button</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="sys_diff_clock" display_name="System Differential Clock" type="chip" sub_type="system_clock" major_group="Clock Sources" >
+    <description>3.3V LVDS differential 200 MHz oscillator used as system differential clock source</description>
+    <parameters>
+      <parameter name="frequency" value="200000000"/>
+    </parameters>
+  </component>
+  <component name="phy_onboard" display_name="Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
+	<description>PHY Ethernet on the board</description>
+	  <component_modes>
+        <component_mode name="rgmii" display_name="RGMII mode">
+		  <interfaces>
+            <interface name="eth_rgmii" order="0"/>
+            <interface name="eth_mdio_mdc" order="1"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_sysclk" component1="part0" component2="sys_diff_clock">
+    <connection_map name="part0_sys_clk_1" c1_st_index="0" c1_end_index="1" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="2" c1_end_index="2" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="3" c1_end_index="18" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="19" c1_end_index="34" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_keypad" component1="part0" component2="keypad">
+    <connection_map name="part0_keypad_1" c1_st_index="41" c1_end_index="50" c2_st_index="0" c2_end_index="9"/>
+  </connection>
+  <connection name="part0_sseg" component1="part0" component2="sseg">
+    <connection_map name="part0_sseg_1" c1_st_index="51" c1_end_index="53" c2_st_index="0" c2_end_index="2"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="54" c1_end_index="61" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="62" c1_end_index="69" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="70" c1_end_index="77" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="78" c1_end_index="85" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="86" c1_end_index="87" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="88" c1_end_index="92" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+	<connection_map name="part0_eth_rgmii_1" c1_st_index="95" c1_end_index="106" c2_st_index="0" c2_end_index="11"/>
+    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="93" c1_end_index="94" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/part0_pins.xml
new file mode 100644
index 0000000..a95106a
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/part0_pins.xml
@@ -0,0 +1,149 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7k325tffg900-2">
+<pins>
+  <!-- Clock Signal -->
+  <pin index="0"  name="clk_n"  iostandard="LVDS"  loc="AD11"/>
+  <pin index="1"  name="clk_p"  iostandard="LVDS"  loc="AD12"/>
+  <!-- User Reset Button-->
+  <pin index="2"  name="reset"  iostandard="LVCMOS15"  loc="Y13"/>
+  <!-- Switches -->
+  <pin index="3"   name="dip_switches_16bits_tri_i_0"   iostandard="LVCMOS18"  loc="AG19"/>
+  <pin index="4"   name="dip_switches_16bits_tri_i_1"   iostandard="LVCMOS18"  loc="AH19"/>
+  <pin index="5"   name="dip_switches_16bits_tri_i_2"   iostandard="LVCMOS18"  loc="AH17"/>
+  <pin index="6"   name="dip_switches_16bits_tri_i_3"   iostandard="LVCMOS18"  loc="AF16"/>
+  <pin index="7"   name="dip_switches_16bits_tri_i_4"   iostandard="LVCMOS18"  loc="AH16"/>
+  <pin index="8"   name="dip_switches_16bits_tri_i_5"   iostandard="LVCMOS18"  loc="AE16"/>
+  <pin index="9"   name="dip_switches_16bits_tri_i_6"   iostandard="LVCMOS18"  loc="AJ19"/>
+  <pin index="10"  name="dip_switches_16bits_tri_i_7"   iostandard="LVCMOS18"  loc="AK19"/>
+  <pin index="11"  name="dip_switches_16bits_tri_i_8"   iostandard="LVCMOS18"  loc="AJ17"/>
+  <pin index="12"  name="dip_switches_16bits_tri_i_9"   iostandard="LVCMOS18"  loc="AJ16"/>
+  <pin index="13"  name="dip_switches_16bits_tri_i_10"  iostandard="LVCMOS18"  loc="AK16"/>
+  <pin index="14"  name="dip_switches_16bits_tri_i_11"  iostandard="LVCMOS18"  loc="AK15"/>
+  <pin index="15"  name="dip_switches_16bits_tri_i_12"  iostandard="LVCMOS18"  loc="AG15"/>
+  <pin index="16"  name="dip_switches_16bits_tri_i_13"  iostandard="LVCMOS18"  loc="AH15"/>
+  <pin index="17"  name="dip_switches_16bits_tri_i_14"  iostandard="LVCMOS18"  loc="AG14"/>
+  <pin index="18"  name="dip_switches_16bits_tri_i_15"  iostandard="LVCMOS18"  loc="AF15"/>
+  <!-- LEDs -->
+  <pin index="19"  name="led_16bits_tri_o_0"   iostandard="LVCMOS33"  loc="J16"/>
+  <pin index="20"  name="led_16bits_tri_o_1"   iostandard="LVCMOS33"  loc="H16"/>
+  <pin index="21"  name="led_16bits_tri_o_2"   iostandard="LVCMOS33"  loc="H11"/>
+  <pin index="22"  name="led_16bits_tri_o_3"   iostandard="LVCMOS33"  loc="H12"/>
+  <pin index="23"  name="led_16bits_tri_o_4"   iostandard="LVCMOS33"  loc="H14"/>
+  <pin index="24"  name="led_16bits_tri_o_5"   iostandard="LVCMOS33"  loc="G14"/>
+  <pin index="25"  name="led_16bits_tri_o_6"   iostandard="LVCMOS33"  loc="G13"/>
+  <pin index="26"  name="led_16bits_tri_o_7"   iostandard="LVCMOS33"  loc="F13"/>
+  <pin index="27"  name="led_16bits_tri_o_8"   iostandard="LVCMOS33"  loc="F12"/>
+  <pin index="28"  name="led_16bits_tri_o_9"   iostandard="LVCMOS33"  loc="E13"/>
+  <pin index="29"  name="led_16bits_tri_o_10"  iostandard="LVCMOS33"  loc="C12"/>
+  <pin index="30"  name="led_16bits_tri_o_11"  iostandard="LVCMOS33"  loc="B12"/>
+  <pin index="31"  name="led_16bits_tri_o_12"  iostandard="LVCMOS33"  loc="F11"/>
+  <pin index="32"  name="led_16bits_tri_o_13"  iostandard="LVCMOS33"  loc="AB27"/>
+  <pin index="33"  name="led_16bits_tri_o_14"  iostandard="LVCMOS33"  loc="AC27"/>
+  <pin index="34"  name="led_16bits_tri_o_15"  iostandard="LVCMOS33"  loc="G30"/>
+  <!-- RGB LEDs -->
+  <pin index="35"  name="rgb_led_tri_o_0"  iostandard="LVCMOS33"  loc="F15"/> <!-- LED16_B -->
+  <pin index="36"  name="rgb_led_tri_o_1"  iostandard="LVCMOS33"  loc="E14"/> <!-- LED16_G -->
+  <pin index="37"  name="rgb_led_tri_o_2"  iostandard="LVCMOS33"  loc="E16"/> <!-- LED16_R -->
+  <pin index="38"  name="rgb_led_tri_o_3"  iostandard="LVCMOS33"  loc="E15"/> <!-- LED16_B -->
+  <pin index="39"  name="rgb_led_tri_o_4"  iostandard="LVCMOS33"  loc="C14"/> <!-- LED16_G -->
+  <pin index="40"  name="rgb_led_tri_o_5"  iostandard="LVCMOS33"  loc="D14"/> <!-- LED16_R -->
+  <!-- Twenty-Five Button Keypad -->
+  <pin index="41"  name="keypad_col_0"  iostandard="LVCMOS15"  loc="AE13"/>
+  <pin index="42"  name="keypad_col_1"  iostandard="LVCMOS15"  loc="AJ14"/>
+  <pin index="43"  name="keypad_col_2"  iostandard="LVCMOS15"  loc="AJ13"/>
+  <pin index="44"  name="keypad_col_3"  iostandard="LVCMOS15"  loc="AH14"/>
+  <pin index="45"  name="keypad_col_4"  iostandard="LVCMOS15"  loc="AG12"/>
+  <pin index="46"  name="keypad_row_0"  iostandard="LVCMOS15"  loc="AK14"/>
+  <pin index="47"  name="keypad_row_1"  iostandard="LVCMOS15"  loc="AK13"/>
+  <pin index="48"  name="keypad_row_2"  iostandard="LVCMOS15"  loc="AJ12"/>
+  <pin index="49"  name="keypad_row_3"  iostandard="LVCMOS15"  loc="AF12"/>
+  <pin index="50"  name="keypad_row_4"  iostandard="LVCMOS15"  loc="AH10"/>
+    <!-- Seven Segment Display -->
+  <pin index="51"  name="sseg_clk"  iostandard="LVCMOS33"  loc="A11"/>
+  <pin index="52"  name="sseg_en"   iostandard="LVCMOS33"  loc="A12"/>
+  <pin index="53"  name="sseg_sdo"  iostandard="LVCMOS33"  loc="E11"/>
+  <!-- Pmod Header JA -->
+  <pin index="54"  name="JA1"   iostandard="LVCMOS33"  loc="D24"/>
+  <pin index="55"  name="JA2"   iostandard="LVCMOS33"  loc="E24"/>
+  <pin index="56"  name="JA3"   iostandard="LVCMOS33"  loc="G24"/>
+  <pin index="57"  name="JA4"   iostandard="LVCMOS33"  loc="G23"/>
+  <pin index="58"  name="JA7"   iostandard="LVCMOS33"  loc="E26"/>
+  <pin index="59"  name="JA8"   iostandard="LVCMOS33"  loc="F26"/>
+  <pin index="60"  name="JA9"   iostandard="LVCMOS33"  loc="A27"/>
+  <pin index="61"  name="JA10"  iostandard="LVCMOS33"  loc="B27"/>
+  <!-- Pmod Header JB -->
+  <pin index="62"  name="JB1"   iostandard="LVCMOS33"  loc="A28"/>
+  <pin index="63"  name="JB2"   iostandard="LVCMOS33"  loc="B28"/>
+  <pin index="64"  name="JB3"   iostandard="LVCMOS33"  loc="A26"/>
+  <pin index="65"  name="JB4"   iostandard="LVCMOS33"  loc="A25"/>
+  <pin index="66"  name="JB7"   iostandard="LVCMOS33"  loc="C26"/>
+  <pin index="67"  name="JB8"   iostandard="LVCMOS33"  loc="D26"/>
+  <pin index="68"  name="JB9"   iostandard="LVCMOS33"  loc="B25"/>
+  <pin index="69"  name="JB10"  iostandard="LVCMOS33"  loc="C25"/>
+  <!-- Pmod Header JC -->
+  <pin index="70"  name="JC1"   iostandard="LVCMOS33"  loc="E28"/>
+  <pin index="71"  name="JC2"   iostandard="LVCMOS33"  loc="D28"/>
+  <pin index="72"  name="JC3"   iostandard="LVCMOS33"  loc="C29"/>
+  <pin index="73"  name="JC4"   iostandard="LVCMOS33"  loc="B29"/>
+  <pin index="74"  name="JC7"   iostandard="LVCMOS33"  loc="D29"/>
+  <pin index="75"  name="JC8"   iostandard="LVCMOS33"  loc="C30"/>
+  <pin index="76"  name="JC9"   iostandard="LVCMOS33"  loc="B30"/>
+  <pin index="77"  name="JC10"  iostandard="LVCMOS33"  loc="A30"/>
+  <!-- Pmod Header JD -->
+  <pin index="78"  name="JD1"   iostandard="LVCMOS33"  loc="E29"/>
+  <pin index="79"  name="JD2"   iostandard="LVCMOS33"  loc="E30"/>
+  <pin index="80"  name="JD3"   iostandard="LVCMOS33"  loc="H24"/>
+  <pin index="81"  name="JD4"   iostandard="LVCMOS33"  loc="H25"/>
+  <pin index="82"  name="JD7"   iostandard="LVCMOS33"  loc="G28"/>
+  <pin index="83"  name="JD8"   iostandard="LVCMOS33"  loc="F28"/>
+  <pin index="84"  name="JD9"   iostandard="LVCMOS33"  loc="G27"/>
+  <pin index="85"  name="JD10"  iostandard="LVCMOS33"  loc="F27"/>
+  <!-- USB-UART Interface -->
+  <pin index="86"  name="usb_uart_rxd"  iostandard="LVCMOS33"  loc="G29"/>
+  <pin index="87"  name="usb_uart_txd"  iostandard="LVCMOS33"  loc="F30"/>
+  <!-- QSPI Flash -->
+  <pin index="88"  name="qspi_csn_i"  iostandard="LVCMOS33" loc="U19"/>
+  <pin index="89"  name="qspi_db0_i"  iostandard="LVCMOS33" loc="P24"/>
+  <pin index="90"  name="qspi_db1_i"  iostandard="LVCMOS33" loc="R25"/>
+  <pin index="91"  name="qspi_db2_i"  iostandard="LVCMOS33" loc="R20"/>
+  <pin index="92"  name="qspi_db3_i"  iostandard="LVCMOS33" loc="R21"/>
+  <!-- Ethernet PHY -->
+  <pin index="93"  name="eth_mdc"           iostandard="LVCMOS18" loc="AA18"/>
+  <pin index="94"  name="eth_mdio_i"        iostandard="LVCMOS18" loc="Y18"/>
+  <pin index="95"  name="eth_rgmii_rd_0"    iostandard="LVCMOS18" loc="AE15"/>
+  <pin index="96"  name="eth_rgmii_rd_1"    iostandard="LVCMOS18" loc="AE18"/>
+  <pin index="97"  name="eth_rgmii_rd_2"    iostandard="LVCMOS18" loc="AD16"/>
+  <pin index="98"  name="eth_rgmii_rd_3"    iostandard="LVCMOS18" loc="AC19"/>
+  <pin index="99"  name="eth_rgmii_rxc"     iostandard="LVCMOS18" loc="AD18"/>
+  <pin index="100" name="eth_rgmii_rx_ctl"  iostandard="LVCMOS18" loc="AE14"/>
+  <pin index="101" name="eth_rgmii_td_0"    iostandard="LVCMOS18" loc="AA15"/>
+  <pin index="102" name="eth_rgmii_td_1"    iostandard="LVCMOS18" loc="AD17"/>
+  <pin index="103" name="eth_rgmii_td_2"    iostandard="LVCMOS18" loc="AG17"/>
+  <pin index="104" name="eth_rgmii_td_3"    iostandard="LVCMOS18" loc="AC17"/>
+  <pin index="105" name="eth_rgmii_txc"     iostandard="LVCMOS18" loc="AB15"/>
+  <pin index="106" name="eth_rgmii_tx_ctl"  iostandard="LVCMOS18" loc="AB17"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/preset.xml
new file mode 100644
index 0000000..5e4d8c4
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/sword/C.0/preset.xml
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+	  <user_parameters>
+		<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+		<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+		<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+		<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+		<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+	  </user_parameters>
+	</ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+        <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+        <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	    <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+        <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+        <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	    <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+      </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+        <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+        <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="led_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+        <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+		<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+      </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+        <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+        <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="rgb_led_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+        <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+		<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+      </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+        <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+        <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+        <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+        <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+        <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+        <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sseg_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+        <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
+      </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI1_SIZE" value="3"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI2_SIZE" value="3"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+        <user_parameter name="CONFIG.C_GPI3_SIZE" value="3"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+        <user_parameter name="CONFIG.C_GPI4_SIZE" value="3"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+        <user_parameter name="CONFIG.GPI1_SIZE" value="3"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+        <user_parameter name="CONFIG.GPI2_SIZE" value="3"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+        <user_parameter name="CONFIG.GPI1_SIZE" value="3"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+        <user_parameter name="CONFIG.GPI2_SIZE" value="3"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="keypad_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+        <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
+      </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI1_SIZE" value="10"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI2_SIZE" value="10"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+        <user_parameter name="CONFIG.C_GPI3_SIZE" value="10"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+        <user_parameter name="CONFIG.C_GPI4_SIZE" value="10"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+        <user_parameter name="CONFIG.GPI1_SIZE" value="10"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+        <user_parameter name="CONFIG.GPI2_SIZE" value="10"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+        <user_parameter name="CONFIG.GPI1_SIZE" value="10"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+        <user_parameter name="CONFIG.GPI2_SIZE" value="10"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="usb_uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.USE_UART_TX" value="1"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_diff_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
+      <user_parameters>
+        <user_parameter name="CONFIG.PRIM_IN_FREQ" value="200"/> 
+        <user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN2_D">
+      <user_parameters>
+	    <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="200"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Differential_clock_capable_pin"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="hdmi_in_preset">
+    <ip vendor="digilentinc.com" library="ip" name="dvi2rgb">
+      <user_parameters>
+        <user_parameter name="CONFIG.kRstActiveHigh" value="false"/> 
+        <user_parameter name="CONFIG.kClkRange" value="2"/> 
+        <user_parameter name="CONFIG.kAddBUFG" value="false"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="mii_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.PHY_TYPE" value="MII"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+      <user_parameters>
+        <user_parameter name="CONFIG.Physical_Interface" value="MII"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/board.xml
new file mode 100644
index 0000000..242e3f3
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/board.xml
@@ -0,0 +1,653 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="usb104-a7" display_name="USB104 A7" url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>USB104 A7</description>
+<components>
+  <component name="part0" display_name="USB104 A7" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+        <description>DDR3 board interface, it can use MIG IP for connection.</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+        </preferred_ips>
+      </interface>
+
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
+        <description>4 Push Buttons</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btn_2bits_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="clk" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_dq0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_dq0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_dq0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_dq1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_dq1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_dq1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_dq2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_dq2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_dq2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_dq3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_dq3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_dq3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_cs_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_cs_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_cs_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="qspi_sck_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sck_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sck_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+    <description>256 MB DDR3L memory SODIMM (FIXME) </description>
+    <parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="256MB"/>
+    </parameters>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+    <description>LEDs 3 to 0</description>
+  </component>
+  <component name="btn_2bits" display_name="2 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+      <description>Push buttons 1 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+      <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+      <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+    <preferred_ips>
+      <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+    </preferred_ips>
+  </component>
+   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JC</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="S25FL128SAGNFI00" vendor="Cypress" spec_url="https://www.cypress.com/products/serial-nor-flash-memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
+    <connection_map name="part0_btn_2bits_1" c1_st_index="5" c1_end_index="6" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="25" c1_end_index="32" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/part0_pins.xml
new file mode 100644
index 0000000..7f179a9
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/part0_pins.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0"  name ="clk" iostandard="LVCMOS33" loc="E3"/>
+
+  <pin index="1"  name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="2"  name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="3"  name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="4"  name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T14"/>
+
+  <pin index="5"  name ="btn_2bits_tri_i_0" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="6"  name ="btn_2bits_tri_i_1" iostandard="LVCMOS33" loc="U17"/>
+
+  <pin index="7"  name ="usb_uart_rxd" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="8"  name ="usb_uart_txd" iostandard="LVCMOS33" loc="V12"/>
+
+  <pin index="9"  name ="JA1"  iostandard="LVCMOS33" loc="F4"/>
+  <pin index="10" name ="JA2"  iostandard="LVCMOS33" loc="F3"/>
+  <pin index="11" name ="JA3"  iostandard="LVCMOS33" loc="E2"/>
+  <pin index="12" name ="JA4"  iostandard="LVCMOS33" loc="D2"/>
+  <pin index="13" name ="JA7"  iostandard="LVCMOS33" loc="H2"/>
+  <pin index="14" name ="JA8"  iostandard="LVCMOS33" loc="G2"/>
+  <pin index="15" name ="JA9"  iostandard="LVCMOS33" loc="C2"/>
+  <pin index="16" name ="JA10" iostandard="LVCMOS33" loc="C1"/>
+
+  <pin index="17" name ="JB1"  iostandard="LVCMOS33" loc="C4"/>
+  <pin index="18" name ="JB2"  iostandard="LVCMOS33" loc="B2"/>
+  <pin index="19" name ="JB3"  iostandard="LVCMOS33" loc="B3"/>
+  <pin index="20" name ="JB4"  iostandard="LVCMOS33" loc="B4"/>
+  <pin index="21" name ="JB7"  iostandard="LVCMOS33" loc="B1"/>
+  <pin index="22" name ="JB8"  iostandard="LVCMOS33" loc="A1"/>
+  <pin index="23" name ="JB9"  iostandard="LVCMOS33" loc="A3"/>
+  <pin index="24" name ="JB10" iostandard="LVCMOS33" loc="A4"/>
+  
+  <pin index="25" name ="JC1"  iostandard="LVCMOS33" loc="C5"/>
+  <pin index="26" name ="JC2"  iostandard="LVCMOS33" loc="C6"/>
+  <pin index="27" name ="JC3"  iostandard="LVCMOS33" loc="B6"/>
+  <pin index="28" name ="JC4"  iostandard="LVCMOS33" loc="C7"/>
+  <pin index="29" name ="JC7"  iostandard="LVCMOS33" loc="A5"/>
+  <pin index="30" name ="JC8"  iostandard="LVCMOS33" loc="A6"/>
+  <pin index="31" name ="JC9"  iostandard="LVCMOS33" loc="B7"/>
+  <pin index="32" name ="JC10" iostandard="LVCMOS33" loc="D8"/>
+  
+  <pin index="33" name="qspi_cs_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="34" name="qspi_sck_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="35" name="qspi_dq0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="36" name="qspi_dq1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="37" name="qspi_dq2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="38" name="qspi_dq3_i" iostandard="LVCMOS33" loc="M14"/>
+
+</pins>
+</part_info>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/preset.xml
new file mode 100644
index 0000000..2760658
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.0/preset.xml
@@ -0,0 +1,210 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="btn_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+      <user_parameters>
+        <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+        <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+      <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="qspi_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+        <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+        <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+        <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+        <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/board.xml
new file mode 100644
index 0000000..56adf02
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/board.xml
@@ -0,0 +1,650 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="usb104-a7" display_name="USB104 A7" url="https://reference.digilentinc.com/reference/programmable-logic/usb104a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.2</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>USB104 A7</description>
+<components>
+  <component name="part0" display_name="USB104 A7" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/usb104a7/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+        <description>DDR3 board interface, it can use MIG IP for connection.</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+        </preferred_ips>
+      </interface>
+
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
+        <description>2 Push Buttons</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btn_2bits_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="clk" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_dq0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_dq0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_dq0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_dq1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_dq1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_dq1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_dq2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_dq2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_dq2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_dq3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_dq3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_dq3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_cs_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_cs_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_cs_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="qspi_sck_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sck_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sck_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+    <description>512 MB DDR3/DDR3L memory </description>
+    <parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="512MB"/>
+    </parameters>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+    <description>LEDs 3 to 0</description>
+  </component>
+  <component name="btn_2bits" display_name="2 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+      <description>Push buttons 1 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+      <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+      <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+    <preferred_ips>
+      <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+    </preferred_ips>
+  </component>
+   <component name="ja" display_name="PMOD A" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector PMOD A</description>
+  </component>
+  <component name="jb" display_name="PMOD B" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="PMOD C" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JC</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="S25FL128SAGNFI00" vendor="Cypress" spec_url="https://www.cypress.com/products/serial-nor-flash-memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
+    <connection_map name="part0_btn_2bits_1" c1_st_index="5" c1_end_index="6" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="25" c1_end_index="32" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/part0_pins.xml
new file mode 100644
index 0000000..7f179a9
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/part0_pins.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0"  name ="clk" iostandard="LVCMOS33" loc="E3"/>
+
+  <pin index="1"  name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="2"  name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="3"  name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="4"  name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T14"/>
+
+  <pin index="5"  name ="btn_2bits_tri_i_0" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="6"  name ="btn_2bits_tri_i_1" iostandard="LVCMOS33" loc="U17"/>
+
+  <pin index="7"  name ="usb_uart_rxd" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="8"  name ="usb_uart_txd" iostandard="LVCMOS33" loc="V12"/>
+
+  <pin index="9"  name ="JA1"  iostandard="LVCMOS33" loc="F4"/>
+  <pin index="10" name ="JA2"  iostandard="LVCMOS33" loc="F3"/>
+  <pin index="11" name ="JA3"  iostandard="LVCMOS33" loc="E2"/>
+  <pin index="12" name ="JA4"  iostandard="LVCMOS33" loc="D2"/>
+  <pin index="13" name ="JA7"  iostandard="LVCMOS33" loc="H2"/>
+  <pin index="14" name ="JA8"  iostandard="LVCMOS33" loc="G2"/>
+  <pin index="15" name ="JA9"  iostandard="LVCMOS33" loc="C2"/>
+  <pin index="16" name ="JA10" iostandard="LVCMOS33" loc="C1"/>
+
+  <pin index="17" name ="JB1"  iostandard="LVCMOS33" loc="C4"/>
+  <pin index="18" name ="JB2"  iostandard="LVCMOS33" loc="B2"/>
+  <pin index="19" name ="JB3"  iostandard="LVCMOS33" loc="B3"/>
+  <pin index="20" name ="JB4"  iostandard="LVCMOS33" loc="B4"/>
+  <pin index="21" name ="JB7"  iostandard="LVCMOS33" loc="B1"/>
+  <pin index="22" name ="JB8"  iostandard="LVCMOS33" loc="A1"/>
+  <pin index="23" name ="JB9"  iostandard="LVCMOS33" loc="A3"/>
+  <pin index="24" name ="JB10" iostandard="LVCMOS33" loc="A4"/>
+  
+  <pin index="25" name ="JC1"  iostandard="LVCMOS33" loc="C5"/>
+  <pin index="26" name ="JC2"  iostandard="LVCMOS33" loc="C6"/>
+  <pin index="27" name ="JC3"  iostandard="LVCMOS33" loc="B6"/>
+  <pin index="28" name ="JC4"  iostandard="LVCMOS33" loc="C7"/>
+  <pin index="29" name ="JC7"  iostandard="LVCMOS33" loc="A5"/>
+  <pin index="30" name ="JC8"  iostandard="LVCMOS33" loc="A6"/>
+  <pin index="31" name ="JC9"  iostandard="LVCMOS33" loc="B7"/>
+  <pin index="32" name ="JC10" iostandard="LVCMOS33" loc="D8"/>
+  
+  <pin index="33" name="qspi_cs_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="34" name="qspi_sck_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="35" name="qspi_dq0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="36" name="qspi_dq1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="37" name="qspi_dq2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="38" name="qspi_dq3_i" iostandard="LVCMOS33" loc="M14"/>
+
+</pins>
+</part_info>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/preset.xml
new file mode 100644
index 0000000..2760658
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.1/preset.xml
@@ -0,0 +1,210 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="btn_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+      <user_parameters>
+        <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+        <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+      <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="qspi_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+        <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+        <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+        <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+        <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/board.xml
new file mode 100644
index 0000000..8fca1da
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/board.xml
@@ -0,0 +1,650 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="usb104-a7" display_name="USB104 A7" url="https://reference.digilentinc.com/reference/programmable-logic/usb104a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.2</revision>
+</compatible_board_revisions>
+<file_version>1.2</file_version>
+<description>USB104 A7</description>
+<components>
+  <component name="part0" display_name="USB104 A7" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/usb104a7/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+        <description>DDR3 board interface, it can use MIG IP for connection.</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+        </preferred_ips>
+      </interface>
+
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
+        <description>2 Push Buttons</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btn_2bits_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="clk" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_dq0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_dq0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_dq0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_dq1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_dq1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_dq1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_dq2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_dq2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_dq2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_dq3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_dq3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_dq3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_cs_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_cs_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_cs_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="qspi_sck_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sck_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sck_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+    <description>512 MB DDR3/DDR3L memory </description>
+    <parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="512MB"/>
+    </parameters>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+    <description>LEDs 3 to 0</description>
+  </component>
+  <component name="btn_2bits" display_name="2 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+      <description>Push buttons 1 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+      <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+      <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+    <preferred_ips>
+      <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+    </preferred_ips>
+  </component>
+   <component name="ja" display_name="PMOD A" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector PMOD A</description>
+  </component>
+  <component name="jb" display_name="PMOD B" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="PMOD C" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JC</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="S25FL128SAGNFI00" vendor="Cypress" spec_url="https://www.cypress.com/products/serial-nor-flash-memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
+    <connection_map name="part0_btn_2bits_1" c1_st_index="5" c1_end_index="6" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+   <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="25" c1_end_index="32" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/part0_pins.xml
new file mode 100644
index 0000000..7f179a9
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/part0_pins.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0"  name ="clk" iostandard="LVCMOS33" loc="E3"/>
+
+  <pin index="1"  name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="2"  name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="3"  name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="4"  name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T14"/>
+
+  <pin index="5"  name ="btn_2bits_tri_i_0" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="6"  name ="btn_2bits_tri_i_1" iostandard="LVCMOS33" loc="U17"/>
+
+  <pin index="7"  name ="usb_uart_rxd" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="8"  name ="usb_uart_txd" iostandard="LVCMOS33" loc="V12"/>
+
+  <pin index="9"  name ="JA1"  iostandard="LVCMOS33" loc="F4"/>
+  <pin index="10" name ="JA2"  iostandard="LVCMOS33" loc="F3"/>
+  <pin index="11" name ="JA3"  iostandard="LVCMOS33" loc="E2"/>
+  <pin index="12" name ="JA4"  iostandard="LVCMOS33" loc="D2"/>
+  <pin index="13" name ="JA7"  iostandard="LVCMOS33" loc="H2"/>
+  <pin index="14" name ="JA8"  iostandard="LVCMOS33" loc="G2"/>
+  <pin index="15" name ="JA9"  iostandard="LVCMOS33" loc="C2"/>
+  <pin index="16" name ="JA10" iostandard="LVCMOS33" loc="C1"/>
+
+  <pin index="17" name ="JB1"  iostandard="LVCMOS33" loc="C4"/>
+  <pin index="18" name ="JB2"  iostandard="LVCMOS33" loc="B2"/>
+  <pin index="19" name ="JB3"  iostandard="LVCMOS33" loc="B3"/>
+  <pin index="20" name ="JB4"  iostandard="LVCMOS33" loc="B4"/>
+  <pin index="21" name ="JB7"  iostandard="LVCMOS33" loc="B1"/>
+  <pin index="22" name ="JB8"  iostandard="LVCMOS33" loc="A1"/>
+  <pin index="23" name ="JB9"  iostandard="LVCMOS33" loc="A3"/>
+  <pin index="24" name ="JB10" iostandard="LVCMOS33" loc="A4"/>
+  
+  <pin index="25" name ="JC1"  iostandard="LVCMOS33" loc="C5"/>
+  <pin index="26" name ="JC2"  iostandard="LVCMOS33" loc="C6"/>
+  <pin index="27" name ="JC3"  iostandard="LVCMOS33" loc="B6"/>
+  <pin index="28" name ="JC4"  iostandard="LVCMOS33" loc="C7"/>
+  <pin index="29" name ="JC7"  iostandard="LVCMOS33" loc="A5"/>
+  <pin index="30" name ="JC8"  iostandard="LVCMOS33" loc="A6"/>
+  <pin index="31" name ="JC9"  iostandard="LVCMOS33" loc="B7"/>
+  <pin index="32" name ="JC10" iostandard="LVCMOS33" loc="D8"/>
+  
+  <pin index="33" name="qspi_cs_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="34" name="qspi_sck_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="35" name="qspi_dq0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="36" name="qspi_dq1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="37" name="qspi_dq2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="38" name="qspi_dq3_i" iostandard="LVCMOS33" loc="M14"/>
+
+</pins>
+</part_info>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/preset.xml
new file mode 100644
index 0000000..2760658
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.2/preset.xml
@@ -0,0 +1,210 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="btn_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+      <user_parameters>
+        <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+        <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+      <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="qspi_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+        <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+        <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+        <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+        <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/board.xml
new file mode 100644
index 0000000..1ab0e8e
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/board.xml
@@ -0,0 +1,694 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="usb104-a7" display_name="USB104 A7" url="https://digilent.com/reference/programmable-logic/usb104a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.2</revision>
+</compatible_board_revisions>
+<file_version>1.3</file_version>
+<description>USB104 A7</description>
+<components>
+  <component name="part0" display_name="USB104 A7" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/usb104a7/start">
+    <interfaces>
+      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
+        <description>DDR3 board interface, it can use MIG IP for connection.</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+        </preferred_ips>
+      </interface>
+
+      <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+        <description>4 LEDs</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <!-- Two-button variant interface for when button 0 is not used as a reset -->
+      <interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
+        <description>2 Push Buttons</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btn_2bits_tri_i" dir="in" left="1" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <!-- One-button variant interface for when button 0 is used as a reset -->
+      <interface mode="master" name="btn_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btn_2bits_tri_i" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btn_2bits_tri_i_1"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <!-- Reset interface that can only be used when btn_2bits is not used -->
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <description>Use BTN0 as System Reset, active high</description>
+        <port_maps>
+          <port_map logical_port="RST" physical_port="reset_btn0" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="1" />
+        </parameters>
+      </interface>
+
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <parameters>
+          <parameter name="frequency" value="100000000"/>
+        </parameters>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+        <preferred_ips>
+          <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+        </preferred_ips>
+        <port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_dq0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_dq0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_dq0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_dq1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_dq1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_dq1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_dq2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_dq2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_dq2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_dq3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_dq3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_dq3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_dq3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_cs_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_cs_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_cs_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_cs_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="qspi_sck_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="qspi_sck_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="qspi_sck_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_sck_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+    <description>512 MB DDR3/DDR3L memory </description>
+    <parameters>
+        <parameter name="ddr_type" value="ddr3"/>
+        <parameter name="size" value="512MB"/>
+    </parameters>
+  </component>
+  <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+    <description>LEDs 3 to 0</description>
+  </component>
+
+  <component name="btn_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+    <description>Push buttons 1 to 0</description>
+    <component_modes>
+      <component_mode name="2_btns" display_name="2 Buttons (No Reset)">
+        <interfaces>
+          <interface name="btn_2bits" order="0"/>
+        </interfaces>
+      </component_mode>
+      <component_mode name="1_btn" display_name="Only use BTN1">
+        <interfaces>
+          <interface name="btn_1bit" order="0"/>
+        </interfaces>
+      </component_mode>
+    </component_modes>
+  </component>
+  <component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
+    <description>Configure BTN0 as System Reset button, active high</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+    <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+    <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="ja" display_name="PMOD A" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector PMOD A</description>
+  </component>
+  <component name="jb" display_name="PMOD B" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="PMOD C" type="chip" sub_type="chip" major_group="Pmod">
+    <description>Pmod Connector JC</description>
+  </component>
+  <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="S25FL128SAGNFI00" vendor="Cypress" spec_url="https://www.cypress.com/products/serial-nor-flash-memory">
+  	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+  </component>
+</components>
+
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+
+<connections>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+    <connection_map name="part0_led_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
+    <connection_map name="part0_btn_2bits_1" c1_st_index="5" c1_end_index="6" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="5" c1_end_index="5" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="25" c1_end_index="32" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/part0_pins.xml
new file mode 100644
index 0000000..e463c87
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/part0_pins.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0"  name ="clk" iostandard="LVCMOS33" loc="E3"/>
+
+  <pin index="1"  name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="2"  name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="3"  name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="4"  name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T14"/>
+
+  <pin index="5"  name ="btn_2bits_tri_i_0" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="6"  name ="btn_2bits_tri_i_1" iostandard="LVCMOS33" loc="U17"/>
+
+  <pin index="7"  name ="usb_uart_rxd" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="8"  name ="usb_uart_txd" iostandard="LVCMOS33" loc="V12"/>
+
+  <pin index="9"  name ="JA1"  iostandard="LVCMOS33" loc="F4"/>
+  <pin index="10" name ="JA2"  iostandard="LVCMOS33" loc="F3"/>
+  <pin index="11" name ="JA3"  iostandard="LVCMOS33" loc="E2"/>
+  <pin index="12" name ="JA4"  iostandard="LVCMOS33" loc="D2"/>
+  <pin index="13" name ="JA7"  iostandard="LVCMOS33" loc="H2"/>
+  <pin index="14" name ="JA8"  iostandard="LVCMOS33" loc="G2"/>
+  <pin index="15" name ="JA9"  iostandard="LVCMOS33" loc="C2"/>
+  <pin index="16" name ="JA10" iostandard="LVCMOS33" loc="C1"/>
+
+  <pin index="17" name ="JB1"  iostandard="LVCMOS33" loc="C4"/>
+  <pin index="18" name ="JB2"  iostandard="LVCMOS33" loc="B2"/>
+  <pin index="19" name ="JB3"  iostandard="LVCMOS33" loc="B3"/>
+  <pin index="20" name ="JB4"  iostandard="LVCMOS33" loc="B4"/>
+  <pin index="21" name ="JB7"  iostandard="LVCMOS33" loc="B1"/>
+  <pin index="22" name ="JB8"  iostandard="LVCMOS33" loc="A1"/>
+  <pin index="23" name ="JB9"  iostandard="LVCMOS33" loc="A3"/>
+  <pin index="24" name ="JB10" iostandard="LVCMOS33" loc="A4"/>
+  
+  <pin index="25" name ="JC1"  iostandard="LVCMOS33" loc="C5"/>
+  <pin index="26" name ="JC2"  iostandard="LVCMOS33" loc="C6"/>
+  <pin index="27" name ="JC3"  iostandard="LVCMOS33" loc="B6"/>
+  <pin index="28" name ="JC4"  iostandard="LVCMOS33" loc="C7"/>
+  <pin index="29" name ="JC7"  iostandard="LVCMOS33" loc="A5"/>
+  <pin index="30" name ="JC8"  iostandard="LVCMOS33" loc="A6"/>
+  <pin index="31" name ="JC9"  iostandard="LVCMOS33" loc="B7"/>
+  <pin index="32" name ="JC10" iostandard="LVCMOS33" loc="D8"/>
+  
+  <pin index="33" name="qspi_cs_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="34" name="qspi_sck_i" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="35" name="qspi_dq0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="36" name="qspi_dq1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="37" name="qspi_dq2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="38" name="qspi_dq3_i" iostandard="LVCMOS33" loc="M14"/>
+
+</pins>
+</part_info>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/preset.xml
new file mode 100644
index 0000000..dbd09e5
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/usb104-a7/B/1.3/preset.xml
@@ -0,0 +1,276 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2022 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr3_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="btn_2bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	  <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset> 
+  
+   <ip_preset preset_proc_name="btn_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+        <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+        <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+        <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+        <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+        <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+      </user_parameters>
+    </ip>
+	  <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+        <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+        <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+        <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+        <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+        <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset> 
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+      <user_parameters>
+        <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+        <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+      <user_parameters>
+		<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="qspi_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+        <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+        <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+        <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+        <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/board.xml
new file mode 100644
index 0000000..2c95799
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/board.xml
@@ -0,0 +1,811 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="zedboard" display_name="Zedboard" url="https://reference.digilentinc.com/reference/programmable-logic/zedboard/start" preset_file="preset.xml">
+  <images>
+    <image name="zed_board.jpg" display_name="ZED BOARD" sub_type="board">
+      <description>ZED Board File Image</description>
+    </image>
+  </images>
+  <compatible_board_revisions>
+    <revision id="0">D.3</revision>
+  </compatible_board_revisions>
+  <file_version>1.0</file_version>
+  <description>ZedBoard Zynq Evaluation and Development Kit</description>
+  <components>
+    <component name="part0" display_name="ZedBoard" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/zedboard/start">
+      <description>FPGA part on the board</description>
+      <interfaces>
+        <interface mode="master" name="btns_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_5bits" preset_proc="btns_5bits_preset">
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="TRI_I" physical_port="btns_5bits_tri_i" dir="in" left="4" right="0"> 
+              <pin_maps>
+                <pin_map port_index="0" component_pin="btns_5bits_tri_i_0"/> 
+                <pin_map port_index="1" component_pin="btns_5bits_tri_i_1"/> 
+                <pin_map port_index="2" component_pin="btns_5bits_tri_i_2"/> 
+                <pin_map port_index="3" component_pin="btns_5bits_tri_i_3"/> 
+                <pin_map port_index="4" component_pin="btns_5bits_tri_i_4"/> 
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+        <interface mode="master" name="leds_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_8bits" preset_proc="leds_8bits_preset">
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="TRI_O" physical_port="leds_8bits_tri_o" dir="out" left="7" right="0"> 
+              <pin_maps>
+                <pin_map port_index="0" component_pin="leds_8bits_tri_o_0"/> 
+                <pin_map port_index="1" component_pin="leds_8bits_tri_o_1"/> 
+                <pin_map port_index="2" component_pin="leds_8bits_tri_o_2"/> 
+                <pin_map port_index="3" component_pin="leds_8bits_tri_o_3"/> 
+                <pin_map port_index="4" component_pin="leds_8bits_tri_o_4"/> 
+                <pin_map port_index="5" component_pin="leds_8bits_tri_o_5"/> 
+                <pin_map port_index="6" component_pin="leds_8bits_tri_o_6"/> 
+                <pin_map port_index="7" component_pin="leds_8bits_tri_o_7"/> 
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+        <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+        </interface>
+        <interface mode="master" name="sws_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_8bits" preset_proc="sws_8bits_preset">
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="TRI_I" physical_port="sws_8bits_tri_i" dir="in" left="7" right="0"> 
+              <pin_maps>
+                <pin_map port_index="0" component_pin="sws_8bits_tri_i_0"/> 
+                <pin_map port_index="1" component_pin="sws_8bits_tri_i_1"/> 
+                <pin_map port_index="2" component_pin="sws_8bits_tri_i_2"/> 
+                <pin_map port_index="3" component_pin="sws_8bits_tri_i_3"/> 
+                <pin_map port_index="4" component_pin="sws_8bits_tri_i_4"/> 
+                <pin_map port_index="5" component_pin="sws_8bits_tri_i_5"/> 
+                <pin_map port_index="6" component_pin="sws_8bits_tri_i_6"/> 
+                <pin_map port_index="7" component_pin="sws_8bits_tri_i_7"/> 
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+        <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="sys_clk"/> 
+              </pin_maps>
+            </port_map>
+          </port_maps>
+          <parameters>
+            <parameter name="frequency" value="100000000" />
+          </parameters>
+        </interface>
+		<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="oled" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="oled" preset_proc="oled_preset">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+		  <port_map logical_port="PIN2_I" physical_port="OLED2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="OLED2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="OLED2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="OLED4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="OLED4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="OLED4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="OLED7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="OLED7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="OLED7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="OLED8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="OLED8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="OLED8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="OLED9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="OLED9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="OLED9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="OLED10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="OLED10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="OLED10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="OLED10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      </interfaces>
+    </component>
+    <component name="btns_5bits" display_name="Push buttons" type="chip" sub_type="push_button" major_group="General Purpose Input or Output">
+      <description>Push Buttons, U R L D C, Active High</description>
+    </component>
+    <component name="leds_8bits" display_name="LED" type="chip" sub_type="led" major_group="General Purpose Input or Output">
+      <description>LEDs, 7 to 0, Active High</description>
+    </component>
+    <component name="ps7_fixedio" display_name="PS7 fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
+    <component name="sws_8bits" display_name="DIP switches" type="chip" sub_type="switch" major_group="General Purpose Input or Output">
+      <description>DIP Switches, 7 to 0</description>
+    </component>
+    <component name="sys_clock" display_name="System clock" type="chip" sub_type="system_clock" major_group="Clock Sources">
+      <description>System Clock, 100 MHz</description>
+    </component>
+	<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	  <description>Pmod Connector JA</description>
+    </component>
+    <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	  <description>Pmod Connector JB</description>
+    </component>
+    <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	  <description>Pmod Connector JC</description>
+    </component>
+    <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	  <description>Pmod Connector JD</description>
+    </component>
+    <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+	  <description>Pmod Connector JE</description>
+    </component>
+	<component name="oled" display_name="Onboard OLED" type="chip" sub_type="chip" major_group="GPIO">
+    <component_modes>
+  	<component_mode name="apmodoled" display_name="Digilent PmodOLED IP">
+  	  <interfaces>
+  	  	<interface name="oled"/>
+  	    </interfaces>
+  	    <preferred_ips>
+  	  		<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+  	    </preferred_ips>
+  	</component_mode>
+  	  <component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+  	    <interfaces>
+  	  	<interface name="oled"/>
+  	    </interfaces>
+  	    <preferred_ips>
+  	  	  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+  	    </preferred_ips>
+  	  </component_mode>
+    </component_modes>    
+  	<description>Onboard OLED (DISP1)</description>
+    </component>
+	<component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	  <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+    </component>
+  </components>
+  <jtag_chains>
+    <jtag_chain name="chain1">
+      <position name="0" component="part0"/>
+    </jtag_chain>
+  </jtag_chains>
+  <connections>
+    <connection name="part0_btns_5bits" component1="part0" component2="btns_5bits">
+      <connection_map name="part0_btns_5bits_1" c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
+    </connection>
+    <connection name="part0_leds_8bits" component1="part0" component2="leds_8bits">
+      <connection_map name="part0_leds_8bits_1" c1_st_index="5" c1_end_index="12" c2_st_index="0" c2_end_index="7"/>
+    </connection>
+    <connection name="part0_sws_8bits" component1="part0" component2="sws_8bits">
+      <connection_map name="part0_sws_8bits_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+    </connection>
+    <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+      <connection_map name="part0_sys_clock_1" c1_st_index="21" c1_end_index="21" c2_st_index="0" c2_end_index="0"/>
+    </connection>
+	<connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="38" c1_end_index="45" c2_st_index="0" c2_end_index="7"/>
+    </connection>
+    <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="22" c1_end_index="29" c2_st_index="0" c2_end_index="7"/>
+    </connection>
+    <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="30" c1_end_index="37" c2_st_index="0" c2_end_index="7"/>
+    </connection>
+    <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="46" c1_end_index="53" c2_st_index="0" c2_end_index="7"/>
+    </connection>
+    <connection name="part0_oled" component1="part0" component2="oled">
+    <connection_map name="part0_oled_1" c1_st_index="54" c1_end_index="59" c2_st_index="0" c2_end_index="5"/>
+    </connection>
+	<connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="60" c1_end_index="61" c2_st_index="0" c2_end_index="1"/>
+    </connection>
+  </connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/part0_pins.xml
new file mode 100644
index 0000000..dd47024
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/part0_pins.xml
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z020clg484-1">
+<pins>
+  <pin index="0" name ="btns_5bits_tri_i_0" iostandard="LVCMOS25" loc="P16"/>
+  <pin index="1" name ="btns_5bits_tri_i_1" iostandard="LVCMOS25" loc="R16"/>
+  <pin index="2" name ="btns_5bits_tri_i_2" iostandard="LVCMOS25" loc="N15"/>
+  <pin index="3" name ="btns_5bits_tri_i_3" iostandard="LVCMOS25" loc="R18"/>
+  <pin index="4" name ="btns_5bits_tri_i_4" iostandard="LVCMOS25" loc="T18"/>
+  <pin index="5" name ="leds_8bits_tri_o_0" iostandard="LVCMOS33" loc="T22"/>
+  <pin index="6" name ="leds_8bits_tri_o_1" iostandard="LVCMOS33" loc="T21"/>
+  <pin index="7" name ="leds_8bits_tri_o_2" iostandard="LVCMOS33" loc="U22"/>
+  <pin index="8" name ="leds_8bits_tri_o_3" iostandard="LVCMOS33" loc="U21"/>
+  <pin index="9" name ="leds_8bits_tri_o_4" iostandard="LVCMOS33" loc="V22"/>
+  <pin index="10" name ="leds_8bits_tri_o_5" iostandard="LVCMOS33" loc="W22"/>
+  <pin index="11" name ="leds_8bits_tri_o_6" iostandard="LVCMOS33" loc="U19"/>
+  <pin index="12" name ="leds_8bits_tri_o_7" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="13" name ="sws_8bits_tri_i_0" iostandard="LVCMOS25" loc="F22"/>
+  <pin index="14" name ="sws_8bits_tri_i_1" iostandard="LVCMOS25" loc="G22"/>
+  <pin index="15" name ="sws_8bits_tri_i_2" iostandard="LVCMOS25" loc="H22"/>
+  <pin index="16" name ="sws_8bits_tri_i_3" iostandard="LVCMOS25" loc="F21"/>
+  <pin index="17" name ="sws_8bits_tri_i_4" iostandard="LVCMOS25" loc="H19"/>
+  <pin index="18" name ="sws_8bits_tri_i_5" iostandard="LVCMOS25" loc="H18"/>
+  <pin index="19" name ="sws_8bits_tri_i_6" iostandard="LVCMOS25" loc="H17"/>
+  <pin index="20" name ="sws_8bits_tri_i_7" iostandard="LVCMOS25" loc="M15"/>
+  <pin index="21" name ="sys_clk" iostandard="LVCMOS33" loc="Y9"/>
+  <pin index="22" name ="JB1" iostandard="LVCMOS33" loc="W12"/>
+  <pin index="23" name ="JB2" iostandard="LVCMOS33" loc="W11"/>
+  <pin index="24" name ="JB3" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="25" name ="JB4" iostandard="LVCMOS33" loc="W8"/>
+  <pin index="26" name ="JB7" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="27" name ="JB8" iostandard="LVCMOS33" loc="W10"/>
+  <pin index="28" name ="JB9" iostandard="LVCMOS33" loc="V9"/>
+  <pin index="29" name ="JB10" iostandard="LVCMOS33" loc="V8"/>
+  <pin index="30" name ="JC1" iostandard="LVCMOS33" loc="AB7"/>
+  <pin index="31" name ="JC2" iostandard="LVCMOS33" loc="AB6"/>
+  <pin index="32" name ="JC3" iostandard="LVCMOS33" loc="Y4"/>
+  <pin index="33" name ="JC4" iostandard="LVCMOS33" loc="AA4"/>
+  <pin index="34" name ="JC7" iostandard="LVCMOS33" loc="R6"/>
+  <pin index="35" name ="JC8" iostandard="LVCMOS33" loc="T6"/>
+  <pin index="36" name ="JC9" iostandard="LVCMOS33" loc="T4"/>
+  <pin index="37" name ="JC10" iostandard="LVCMOS33" loc="U4"/>
+  <pin index="38" name ="JA1" iostandard="LVCMOS33" loc="Y11"/>
+  <pin index="39" name ="JA2" iostandard="LVCMOS33" loc="AA11"/>
+  <pin index="40" name ="JA3" iostandard="LVCMOS33" loc="Y10"/>
+  <pin index="41" name ="JA4" iostandard="LVCMOS33" loc="AA9"/>
+  <pin index="42" name ="JA7" iostandard="LVCMOS33" loc="AB11"/>
+  <pin index="43" name ="JA8" iostandard="LVCMOS33" loc="AB10"/>
+  <pin index="44" name ="JA9" iostandard="LVCMOS33" loc="AB9"/>
+  <pin index="45" name ="JA10" iostandard="LVCMOS33" loc="AA8"/>
+  <pin index="46" name ="JD1" iostandard="LVCMOS33" loc="V7"/>
+  <pin index="47" name ="JD2" iostandard="LVCMOS33" loc="W7"/>
+  <pin index="48" name ="JD3" iostandard="LVCMOS33" loc="V5"/>
+  <pin index="49" name ="JD4" iostandard="LVCMOS33" loc="V4"/>
+  <pin index="50" name ="JD7" iostandard="LVCMOS33" loc="W6"/>
+  <pin index="51" name ="JD8" iostandard="LVCMOS33" loc="W5"/>
+  <pin index="52" name ="JD9" iostandard="LVCMOS33" loc="U6"/>
+  <pin index="53" name ="JD10" iostandard="LVCMOS33" loc="U5"/>   
+  <pin index="54" name ="OLED2" iostandard="LVCMOS33" loc="AA12"/>
+  <pin index="55" name ="OLED4" iostandard="LVCMOS33" loc="AB12"/>
+  <pin index="56" name ="OLED7" iostandard="LVCMOS33" loc="U10"/>
+  <pin index="57" name ="OLED8" iostandard="LVCMOS33" loc="U9"/>
+  <pin index="58" name ="OLED9" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="59" name ="OLED10" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="60" name ="usb_uart_rxd" iostandard="LVCMOS18" loc="D11"/>
+  <pin index="61" name ="usb_uart_txd" iostandard="LVCMOS18" loc="C14"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/preset.xml
new file mode 100644
index 0000000..ab044ff
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/preset.xml
@@ -0,0 +1,324 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+<ip_preset preset_proc_name="ps7_preset"> 
+  <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*"> 
+    <user_parameters>
+     <user_parameter name="CONFIG.preset" value="ZedBoard" /> 
+   </user_parameters>
+  </ip>
+</ip_preset>
+  <ip_preset preset_proc_name="oled_preset">
+    <ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
+        <user_parameters>
+          <user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/> 
+          <user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="leds_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPO1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPO1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPO2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPO2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPO3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPO3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPO4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPO4_SIZE" value="8"/> 
+        </user_parameters>
+     </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="sws_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+          <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+          <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="btns_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+          <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+          <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+        </ip>    
+  </ip_preset>
+<ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/> 
+	  <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+        <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+	<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+        </user_parameters>
+    </ip>
+  </ip_preset>  
+     <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+    <ip_preset preset_proc_name="ps7_preset">
+    <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+      <user_parameters>
+        <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/> 
+        <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.176"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.159"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.162"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.187"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.073"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.034"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.03"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.082"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K128M16 JT-125"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/zed_board.jpg b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/zed_board.jpg
new file mode 100644
index 0000000..56dc99f
Binary files /dev/null and b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zedboard/1.3/zed_board.jpg differ
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/board.xml
new file mode 100644
index 0000000..3f6626c
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/board.xml
@@ -0,0 +1,854 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="zybo-z7-10" display_name="Zybo Z7-10" url="https://digilent.com/reference/programmable-logic/zybo-z7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.2</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Zybo Z7-10</description>
+<components>
+  <component name="part0" display_name="Zybo Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/zybo-z7/start">
+    <interfaces>
+      <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+      </interface>
+      <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sys_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="125000000" />
+       </parameters>
+      </interface>
+	   
+	  	  <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <description>HDMI DDC</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+        <description>HDMI Out</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JE1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JE1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JE1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JE2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JE2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JE2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JE3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JE3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JE3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JE4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JE4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JE4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JE7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JE7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JE7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JE8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JE8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JE8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JE9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JE9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JE9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JE10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JE10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JE10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0"> 
+            <pin_maps> 
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Buttons 3 to 0</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JE</description>
+  </component>
+  <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+  <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+	<description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
+	<description>RGB leds 2 to 0 (3 per LED, Ordered "RGBRGB")</description>
+  </component>  
+  
+  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI input (Requires Digilent's TMDS interface)</description>
+	<component_modes>
+        <component_mode name="HDMI_IN" display_name="HDMI In">
+		  <interfaces>
+            <interface name="hdmi_in" order="0"/>
+            <interface name="hdmi_in_ddc" order="1"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI in HPD (Connected to LD8)</description>
+  </component>
+  <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
+  </component>
+  <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI out HPD</description>
+  </component>
+
+  
+  
+  
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+    <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+    <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
+    <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  
+   
+  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+    <connection_map name="part0_hdmi_in_1" c1_st_index="14" c1_end_index="21" c2_st_index="0" c2_end_index="7"/>
+	
+	<connection_map name="part0_hdmi_in_ddc" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  
+  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="13" c1_end_index="13" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  
+  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+    <connection_map name="part0_hdmi_out_1" c1_st_index="23" c1_end_index="30" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  
+  <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+    <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="22" c1_end_index="22" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+   
+  
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="39" c1_end_index="46" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="55" c1_end_index="62" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="63" c1_end_index="70" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_je" component1="part0" component2="je">
+    <connection_map name="part0_je_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="36" c1_end_index="38" c2_st_index="0" c2_end_index="2"/>
+  </connection>  
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/part0_pins.xml
new file mode 100644
index 0000000..c44207b
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/part0_pins.xml
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z010clg400-1">
+<pins>
+  <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="P16"/>
+  <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="K19"/>
+  <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="Y16"/>
+  <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="M15"/>
+  <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="8" name ="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+  <pin index="9" name ="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="10" name ="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="11" name ="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="12" name ="sys_clk" iostandard="LVCMOS33" loc="K17"/>
+  
+  <pin index="13" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="W19"/>
+  
+  <pin index="14" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="U18"/>
+  <pin index="15" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="U19"/>
+  <pin index="16" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="V20"/>
+  <pin index="17" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="T20"/>
+  <pin index="18" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="N20"/>
+  <pin index="19" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="W20"/>
+  <pin index="20" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="U20"/>
+  <pin index="21" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="P20"/> 
+  
+  <pin index="22" name ="hdmi_tx_hpd" iostandard="LVCMOS33" loc="E18"/>
+  
+  <pin index="23" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="24" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="25" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="D19"/>
+  <pin index="26" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="C20"/>
+  <pin index="27" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="B19"/>
+  <pin index="28" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="D20"/>
+  <pin index="29" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="B20"/>
+  <pin index="30" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="A20"/>
+  
+  <pin index="31" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="32" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="Y19"/> 
+  
+  <pin index="36" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="M17"/>	
+  <pin index="37" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F17"/>  
+  <pin index="38" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="V16"/> 
+  
+  <pin index="39" name ="JA1" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="40" name ="JA2" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="41" name ="JA3" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="42" name ="JA4" iostandard="LVCMOS33" loc="K14"/>
+  <pin index="43" name ="JA7" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="44" name ="JA8" iostandard="LVCMOS33" loc="L15"/>
+  <pin index="45" name ="JA9" iostandard="LVCMOS33" loc="J16"/>
+  <pin index="46" name ="JA10" iostandard="LVCMOS33" loc="J14"/>
+  
+  <pin index="55" name ="JC1" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="56" name ="JC2" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="57" name ="JC3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="58" name ="JC4" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="59" name ="JC7" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="60" name ="JC8" iostandard="LVCMOS33" loc="Y14"/>
+  <pin index="61" name ="JC9" iostandard="LVCMOS33" loc="T12"/>
+  <pin index="62" name ="JC10" iostandard="LVCMOS33" loc="U12"/>
+  
+  <pin index="63" name ="JD1" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="64" name ="JD2" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="65" name ="JD3" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="66" name ="JD4" iostandard="LVCMOS33" loc="R14"/>
+  <pin index="67" name ="JD7" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="68" name ="JD8" iostandard="LVCMOS33" loc="U15"/>
+  <pin index="69" name ="JD9" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="70" name ="JD10" iostandard="LVCMOS33" loc="V18"/>
+  
+  <pin index="71" name ="JE1" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="72" name ="JE2" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="73" name ="JE3" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="74" name ="JE4" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="75" name ="JE7" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="76" name ="JE8" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="77" name ="JE9" iostandard="LVCMOS33" loc="T17"/>
+  <pin index="78" name ="JE10" iostandard="LVCMOS33" loc="Y17"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/preset.xml
new file mode 100644
index 0000000..4bc4b99
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-10/A.0/preset.xml
@@ -0,0 +1,761 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ps7_preset">
+    <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+      <user_parameters>
+		<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF"/> 
+		<user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+		<user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="39"/>
+		<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+		<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+		<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="33.333333"/>
+		<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+		<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="7"/>
+		<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+		<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="32"/>
+		<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1066.667"/>
+		<user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+		<user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+		<user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+		<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+		<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+		<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+		<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+		<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+		<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+		<user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+		<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+		<user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="30"/>
+		<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+		<user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+		<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+		<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/>
+		<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/>
+		<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/>
+		<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+		<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+		<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/>
+		<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+		<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+		<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="0"/> <!--Without this, UART1 is disabled in 2019.2-->
+		<user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/>
+		<user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_UART1_UART1_IO" value="MIO 48 .. 49"/>
+		<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+		<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.221"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.222"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.217"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.244"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="32 Bit"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="18.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="18.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="18.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="18.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="22.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="27.9"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="22.9"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="29.4"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.050"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.044"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.035"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.100"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="22.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="27.9"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="22.9"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="29.4"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="533.333333"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+		<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+		<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+		<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+		<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+		<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+		<user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+		<user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+		<user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="rgb_led_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="3"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="3"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="3"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="3"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="3"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="3"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="3"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="3"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/board.xml
new file mode 100644
index 0000000..ece794f
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/board.xml
@@ -0,0 +1,981 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="zybo-z7-20" display_name="Zybo Z7-20" url="https://digilent.com/reference/programmable-logic/zybo-z7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.2</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Zybo Z7-20</description>
+<components>
+  <component name="part0" display_name="Zybo Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/zybo-z7/start">
+    <interfaces>
+      <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+      </interface>
+      <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sys_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="125000000" />
+       </parameters>
+      </interface>
+	   
+	  	  <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <description>HDMI DDC</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+        <description>HDMI Out</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JE1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JE1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JE1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JE2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JE2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JE2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JE3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JE3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JE3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JE4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JE4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JE4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JE7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JE7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JE7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JE8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JE8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JE8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JE9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JE9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JE9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JE10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JE10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JE10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Buttons 3 to 0</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JE</description>
+  </component>
+  <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+  <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+	<description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+	<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+  </component>  
+  
+  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI input (Requires Digilent's TMDS interface)</description>
+	<component_modes>
+        <component_mode name="HDMI_IN" display_name="HDMI In">
+		  <interfaces>
+            <interface name="hdmi_in" order="0"/>
+            <interface name="hdmi_in_ddc" order="1"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI in HPD (Connected to LD8)</description>
+  </component>
+  <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
+  </component>
+  <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI out HPD</description>
+  </component>
+
+  
+  
+  
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+    <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+    <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
+    <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  
+   
+  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+    <connection_map name="part0_hdmi_in_1" c1_st_index="14" c1_end_index="21" c2_st_index="0" c2_end_index="7"/>
+	
+	<connection_map name="part0_hdmi_in_ddc" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  
+  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="13" c1_end_index="13" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  
+  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+    <connection_map name="part0_hdmi_out_1" c1_st_index="23" c1_end_index="30" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  
+  <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+    <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="22" c1_end_index="22" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+   
+  
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="39" c1_end_index="46" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="55" c1_end_index="62" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="63" c1_end_index="70" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_je" component1="part0" component2="je">
+    <connection_map name="part0_je_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
+  </connection>  
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/part0_pins.xml
new file mode 100644
index 0000000..9df4979
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/part0_pins.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z020clg400-1">
+<pins>
+  <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="P16"/>
+  <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="K19"/>
+  <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="Y16"/>
+  <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="M15"/>
+  <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="8" name ="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+  <pin index="9" name ="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="10" name ="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="11" name ="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="12" name ="sys_clk" iostandard="LVCMOS33" loc="K17"/>
+  
+  <pin index="13" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="W19"/>
+  
+  <pin index="14" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="U18"/>
+  <pin index="15" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="U19"/>
+  <pin index="16" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="V20"/>
+  <pin index="17" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="T20"/>
+  <pin index="18" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="N20"/>
+  <pin index="19" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="W20"/>
+  <pin index="20" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="U20"/>
+  <pin index="21" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="P20"/> 
+  
+  
+  <pin index="22" name ="hdmi_tx_hpd" iostandard="LVCMOS33" loc="E18"/>
+  
+  <pin index="23" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="24" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="25" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="D19"/>
+  <pin index="26" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="C20"/>
+  <pin index="27" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="B19"/>
+  <pin index="28" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="D20"/>
+  <pin index="29" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="B20"/>
+  <pin index="30" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="A20"/>
+  
+  <pin index="31" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="32" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="Y19"/> 
+  
+  
+  
+  <pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="Y12"/>	
+  <pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="T5"/>	
+  <pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="Y11"/>	
+  <pin index="36" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="M17"/>	
+  <pin index="37" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F17"/>  
+  <pin index="38" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="V16"/> 
+  
+  
+  <pin index="39" name ="JA1" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="40" name ="JA2" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="41" name ="JA3" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="42" name ="JA4" iostandard="LVCMOS33" loc="K14"/>
+  <pin index="43" name ="JA7" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="44" name ="JA8" iostandard="LVCMOS33" loc="L15"/>
+  <pin index="45" name ="JA9" iostandard="LVCMOS33" loc="J16"/>
+  <pin index="46" name ="JA10" iostandard="LVCMOS33" loc="J14"/>
+  
+  <pin index="47" name ="JB1" iostandard="LVCMOS33" loc="V8"/>
+  <pin index="48" name ="JB2" iostandard="LVCMOS33" loc="W8"/>
+  <pin index="49" name ="JB3" iostandard="LVCMOS33" loc="U7"/>
+  <pin index="50" name ="JB4" iostandard="LVCMOS33" loc="V7"/>
+  <pin index="51" name ="JB7" iostandard="LVCMOS33" loc="Y7"/>
+  <pin index="52" name ="JB8" iostandard="LVCMOS33" loc="Y6"/>
+  <pin index="53" name ="JB9" iostandard="LVCMOS33" loc="V6"/>
+  <pin index="54" name ="JB10" iostandard="LVCMOS33" loc="W6"/>
+  
+  <pin index="55" name ="JC1" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="56" name ="JC2" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="57" name ="JC3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="58" name ="JC4" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="59" name ="JC7" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="60" name ="JC8" iostandard="LVCMOS33" loc="Y14"/>
+  <pin index="61" name ="JC9" iostandard="LVCMOS33" loc="T12"/>
+  <pin index="62" name ="JC10" iostandard="LVCMOS33" loc="U12"/>
+  
+  <pin index="63" name ="JD1" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="64" name ="JD2" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="65" name ="JD3" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="66" name ="JD4" iostandard="LVCMOS33" loc="R14"/>
+  <pin index="67" name ="JD7" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="68" name ="JD8" iostandard="LVCMOS33" loc="U15"/>
+  <pin index="69" name ="JD9" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="70" name ="JD10" iostandard="LVCMOS33" loc="V18"/>
+  
+  <pin index="71" name ="JE1" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="72" name ="JE2" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="73" name ="JE3" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="74" name ="JE4" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="75" name ="JE7" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="76" name ="JE8" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="77" name ="JE9" iostandard="LVCMOS33" loc="T17"/>
+  <pin index="78" name ="JE10" iostandard="LVCMOS33" loc="Y17"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/preset.xml
new file mode 100644
index 0000000..5393972
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo-z7-20/A.0/preset.xml
@@ -0,0 +1,760 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ps7_preset">
+    <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+      <user_parameters>
+		<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF"/> 
+		<user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+		<user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="667"/>
+		<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="39"/>
+		<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+		<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+		<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="33.333333"/>
+		<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+		<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="15"/>
+		<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="7"/>
+		<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+		<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="32"/>
+		<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1066.667"/>
+		<user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+		<user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+		<user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+		<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+		<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+		<user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+		<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+		<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>	
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+		<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+		<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+		<user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+		<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+		<user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="30"/>
+		<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+		<user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+		<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="in"/>
+		<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+		<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="inout"/>
+		<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+		<user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+		<user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+		<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+		<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+		<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/>
+		<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/>
+		<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/>
+		<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/>
+		<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+		<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+		<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/>
+		<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+		<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+		<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+		<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="0"/> <!--Without this, UART1 is disabled in 2019.2-->
+		<user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/>
+		<user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_UART1_UART1_IO" value="MIO 48 .. 49"/>
+		<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+		<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+		<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.221"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.222"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.217"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.244"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="32 Bit"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="18.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="18.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="18.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="18.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="22.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="27.9"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="22.9"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="29.4"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.050"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.044"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.035"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.100"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="22.8"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="27.9"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="22.9"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="29.4"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="533.333333"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+		<user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+		<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+		<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+		<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+		<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+		<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+		<user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+		<user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+		<user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="rgb_led_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/board.xml
new file mode 100644
index 0000000..28a6475
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/board.xml
@@ -0,0 +1,944 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="zybo" display_name="Zybo" url="https://reference.digilentinc.com/reference/programmable-logic/zybo/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.3</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Zybo</description>
+<components>
+  <component name="part0" display_name="Zybo" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/zybo/start">
+    <interfaces>
+      <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+      </interface>
+      <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sys_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="125000000" />
+       </parameters>
+      </interface>
+	  <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_clk_p" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_clk_n" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_D_P" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_D_N" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <description>HDMI DDC</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="hdmi_ddc_sda" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="hdmi_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="hdmi_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="hdmi_ddc_scl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="hdmi_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="hdmi_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_hpd" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_hpd" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="hdmi_out_en" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_en" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_out_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_out_en"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_out_en" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_out_en"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_out_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_out_en"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+        <description>HDMI Out</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_clk_p" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_clk_n" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_D_P" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_D_N" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JE1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JE1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JE1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JE2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JE2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JE2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JE3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JE3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JE3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JE4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JE4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JE4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JE7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JE7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JE7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JE8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JE8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JE8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JE9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JE9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JE9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JE10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JE10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JE10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Buttons 3 to 0</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JE</description>
+  </component>
+  <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+  <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  <description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI input (Requires Digilent's TMDS interface)</description>
+	<component_modes>
+        <component_mode name="HDMI_IN" display_name="HDMI In">
+		  <interfaces>
+            <interface name="hdmi_in" order="0"/>
+            <interface name="hdmi_in_ddc" order="1"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="hdmi_hpd" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI in HPD</description>
+  </component>
+  <component name="hdmi_out_en" display_name="HDMI Out Enable" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI out enable, 1 for HDMI out, 0 for HDMI in</description>
+  </component>
+  <component name="hdmi_out" display_name="HDMI Out" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
+  </component>
+
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+    <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+    <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
+    <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+    <connection_map name="part0_hdmi_in_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+	<connection_map name="part0_hdmi_in_ddc" c1_st_index="21" c1_end_index="22" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+    <connection_map name="part0_hdmi_out_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+	<connection_map name="part0_hdmi_out_ddc" c1_st_index="21" c1_end_index="22" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="23" c1_end_index="23" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_hdmi_out_en" component1="part0" component2="hdmi_out_en">
+    <connection_map name="part0_hdmi_out_en_1" c1_st_index="24" c1_end_index="24" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="41" c1_end_index="48" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="25" c1_end_index="32" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="33" c1_end_index="40" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="49" c1_end_index="56" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_je" component1="part0" component2="je">
+    <connection_map name="part0_je_1" c1_st_index="57" c1_end_index="64" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/part0_pins.xml
new file mode 100644
index 0000000..7707192
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/part0_pins.xml
@@ -0,0 +1,93 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z010clg400-1">
+<pins>
+  <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="P16"/>
+  <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="Y16"/>
+  <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="M15"/>
+  <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="8" name ="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+  <pin index="9" name ="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="10" name ="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="11" name ="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="12" name ="sys_clk" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="13" name ="TMDS_clk_p" iostandard="TMDS_33" loc="H16"/>
+  <pin index="14" name ="TMDS_clk_n" iostandard="TMDS_33" loc="H17"/>
+  <pin index="15" name ="TMDS_data_p_0" iostandard="TMDS_33" loc="D19"/>
+  <pin index="16" name ="TMDS_data_p_1" iostandard="TMDS_33" loc="C20"/>
+  <pin index="17" name ="TMDS_data_p_2" iostandard="TMDS_33" loc="B19"/>
+  <pin index="18" name ="TMDS_data_n_0" iostandard="TMDS_33" loc="D20"/>
+  <pin index="19" name ="TMDS_data_n_1" iostandard="TMDS_33" loc="B20"/>
+  <pin index="20" name ="TMDS_data_n_2" iostandard="TMDS_33" loc="A20"/>
+  <pin index="21" name ="hdmi_ddc_sda" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="22" name ="hdmi_ddc_scl" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="23" name ="hdmi_hpd" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="24" name ="hdmi_out_en" iostandard="LVCMOS33" loc="F17"/>
+  <pin index="25" name ="JB1" iostandard="LVCMOS33" loc="T20"/>
+  <pin index="26" name ="JB2" iostandard="LVCMOS33" loc="U20"/>
+  <pin index="27" name ="JB3" iostandard="LVCMOS33" loc="V20"/>
+  <pin index="28" name ="JB4" iostandard="LVCMOS33" loc="W20"/>
+  <pin index="29" name ="JB7" iostandard="LVCMOS33" loc="Y18"/>
+  <pin index="30" name ="JB8" iostandard="LVCMOS33" loc="Y19"/>
+  <pin index="31" name ="JB9" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="32" name ="JB10" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="33" name ="JC1" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="34" name ="JC2" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="35" name ="JC3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="36" name ="JC4" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="37" name ="JC7" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="38" name ="JC8" iostandard="LVCMOS33" loc="Y14"/>
+  <pin index="39" name ="JC9" iostandard="LVCMOS33" loc="T12"/>
+  <pin index="40" name ="JC10" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="41" name ="JA1" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="42" name ="JA2" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="43" name ="JA3" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="44" name ="JA4" iostandard="LVCMOS33" loc="K14"/>
+  <pin index="45" name ="JA7" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="46" name ="JA8" iostandard="LVCMOS33" loc="L15"/>
+  <pin index="47" name ="JA9" iostandard="LVCMOS33" loc="J16"/>
+  <pin index="48" name ="JA10" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="49" name ="JD1" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="50" name ="JD2" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="51" name ="JD3" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="52" name ="JD4" iostandard="LVCMOS33" loc="R14"/>
+  <pin index="53" name ="JD7" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="54" name ="JD8" iostandard="LVCMOS33" loc="U15"/>
+  <pin index="55" name ="JD9" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="56" name ="JD10" iostandard="LVCMOS33" loc="V18"/>
+  <pin index="57" name ="JE1" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="58" name ="JE2" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="59" name ="JE3" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="60" name ="JE4" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="61" name ="JE7" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="62" name ="JE8" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="63" name ="JE9" iostandard="LVCMOS33" loc="T17"/>
+  <pin index="64" name ="JE10" iostandard="LVCMOS33" loc="Y17"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/preset.xml
new file mode 100644
index 0000000..60da029
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.3/preset.xml
@@ -0,0 +1,441 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ps7_preset">
+    <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+      <user_parameters>
+        <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/> 
+        <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50.000000"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="0"/> 
+        <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/> 
+        <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="HSTL 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/> 
+        <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="disabled"/> 
+        <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/> 
+        <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="fast"/> 
+        <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/> 
+        <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/> 
+        <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/> 
+        <user_parameter name="CONFIG.PCW_TTC0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.176"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.159"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.162"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.187"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.073"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.034"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.03"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.082"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K128M16 JT-125"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/board.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/board.xml
new file mode 100644
index 0000000..b3b9741
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/board.xml
@@ -0,0 +1,944 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="zybo" display_name="Zybo" url="https://reference.digilentinc.com/reference/programmable-logic/zybo/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">B.4</revision>
+</compatible_board_revisions>
+<file_version>2.0</file_version>
+<description>Zybo</description>
+<components>
+  <component name="part0" display_name="Zybo" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/zybo/start">
+    <interfaces>
+      <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+      </interface>
+      <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="sys_clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="125000000" />
+       </parameters>
+      </interface>
+	  <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_clk_p" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_clk_n" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_D_P" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_D_N" dir="in" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+        <description>HDMI DDC</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="hdmi_ddc_sda" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="hdmi_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="hdmi_ddc_sda" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_sda"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="hdmi_ddc_scl" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="hdmi_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="hdmi_ddc_scl" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_ddc_scl"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_hpd" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_hpd" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_hpd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_hpd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_hpd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_hpd"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="hdmi_out_en" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_en" preset_proc="output_1bit_preset">
+        <port_maps>
+          <port_map logical_port="TRI_O" physical_port="hdmi_out_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_out_en"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_I" physical_port="hdmi_out_en" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_out_en"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="TRI_T" physical_port="hdmi_out_en" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="hdmi_out_en"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+        <description>HDMI Out</description>
+		<preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="CLK_P" physical_port="TMDS_clk_p" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_clk_p"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="CLK_N" physical_port="TMDS_clk_n" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_clk_n"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_P" physical_port="TMDS_D_P" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_data_p_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_data_p_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_data_p_2"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="DATA_N" physical_port="TMDS_D_N" dir="out" left="2" right="0">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="TMDS_data_n_0"/> 
+			  <pin_map port_index="1" component_pin="TMDS_data_n_1"/> 
+			  <pin_map port_index="2" component_pin="TMDS_data_n_2"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JE1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JE1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JE1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JE2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JE2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JE2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JE3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JE3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JE3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JE4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JE4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JE4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JE7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JE7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JE7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JE8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JE8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JE8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JE9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JE9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JE9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JE10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JE10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JE10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JE10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  
+  <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Buttons 3 to 0</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JE</description>
+  </component>
+  <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>LEDs 3 to 0</description>
+  </component>
+  <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+  <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>DIP Switches 3 to 0</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+  <description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
+  </component>
+  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI input (Requires Digilent's TMDS interface)</description>
+	<component_modes>
+        <component_mode name="HDMI_IN" display_name="HDMI In">
+		  <interfaces>
+            <interface name="hdmi_in" order="0"/>
+            <interface name="hdmi_in_ddc" order="1"/>
+          </interfaces>
+		</component_mode>
+	 </component_modes>
+  </component>
+  <component name="hdmi_hpd" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI in HPD</description>
+  </component>
+  <component name="hdmi_out_en" display_name="HDMI Out Enable" type="chip" sub_type="led" major_group="HDMI">
+	<description>HDMI out enable, 1 for HDMI out, 0 for HDMI in</description>
+  </component>
+  <component name="hdmi_out" display_name="HDMI Out" type="chip" sub_type="fixed_io" major_group="HDMI">
+	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
+  </component>
+
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+    <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+    <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
+    <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+    <connection_map name="part0_hdmi_in_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+	<connection_map name="part0_hdmi_in_ddc" c1_st_index="21" c1_end_index="22" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+    <connection_map name="part0_hdmi_out_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+	<connection_map name="part0_hdmi_out_ddc" c1_st_index="21" c1_end_index="22" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="23" c1_end_index="23" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_hdmi_out_en" component1="part0" component2="hdmi_out_en">
+    <connection_map name="part0_hdmi_out_en_1" c1_st_index="24" c1_end_index="24" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="41" c1_end_index="48" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="25" c1_end_index="32" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="33" c1_end_index="40" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="49" c1_end_index="56" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_je" component1="part0" component2="je">
+    <connection_map name="part0_je_1" c1_st_index="57" c1_end_index="64" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+</connections>
+</board>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/part0_pins.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/part0_pins.xml
new file mode 100644
index 0000000..7707192
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/part0_pins.xml
@@ -0,0 +1,93 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z010clg400-1">
+<pins>
+  <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="P16"/>
+  <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="Y16"/>
+  <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="M15"/>
+  <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="8" name ="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+  <pin index="9" name ="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="10" name ="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="W13"/>
+  <pin index="11" name ="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="12" name ="sys_clk" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="13" name ="TMDS_clk_p" iostandard="TMDS_33" loc="H16"/>
+  <pin index="14" name ="TMDS_clk_n" iostandard="TMDS_33" loc="H17"/>
+  <pin index="15" name ="TMDS_data_p_0" iostandard="TMDS_33" loc="D19"/>
+  <pin index="16" name ="TMDS_data_p_1" iostandard="TMDS_33" loc="C20"/>
+  <pin index="17" name ="TMDS_data_p_2" iostandard="TMDS_33" loc="B19"/>
+  <pin index="18" name ="TMDS_data_n_0" iostandard="TMDS_33" loc="D20"/>
+  <pin index="19" name ="TMDS_data_n_1" iostandard="TMDS_33" loc="B20"/>
+  <pin index="20" name ="TMDS_data_n_2" iostandard="TMDS_33" loc="A20"/>
+  <pin index="21" name ="hdmi_ddc_sda" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="22" name ="hdmi_ddc_scl" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="23" name ="hdmi_hpd" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="24" name ="hdmi_out_en" iostandard="LVCMOS33" loc="F17"/>
+  <pin index="25" name ="JB1" iostandard="LVCMOS33" loc="T20"/>
+  <pin index="26" name ="JB2" iostandard="LVCMOS33" loc="U20"/>
+  <pin index="27" name ="JB3" iostandard="LVCMOS33" loc="V20"/>
+  <pin index="28" name ="JB4" iostandard="LVCMOS33" loc="W20"/>
+  <pin index="29" name ="JB7" iostandard="LVCMOS33" loc="Y18"/>
+  <pin index="30" name ="JB8" iostandard="LVCMOS33" loc="Y19"/>
+  <pin index="31" name ="JB9" iostandard="LVCMOS33" loc="W18"/>
+  <pin index="32" name ="JB10" iostandard="LVCMOS33" loc="W19"/>
+  <pin index="33" name ="JC1" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="34" name ="JC2" iostandard="LVCMOS33" loc="W15"/>
+  <pin index="35" name ="JC3" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="36" name ="JC4" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="37" name ="JC7" iostandard="LVCMOS33" loc="W14"/>
+  <pin index="38" name ="JC8" iostandard="LVCMOS33" loc="Y14"/>
+  <pin index="39" name ="JC9" iostandard="LVCMOS33" loc="T12"/>
+  <pin index="40" name ="JC10" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="41" name ="JA1" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="42" name ="JA2" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="43" name ="JA3" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="44" name ="JA4" iostandard="LVCMOS33" loc="K14"/>
+  <pin index="45" name ="JA7" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="46" name ="JA8" iostandard="LVCMOS33" loc="L15"/>
+  <pin index="47" name ="JA9" iostandard="LVCMOS33" loc="J16"/>
+  <pin index="48" name ="JA10" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="49" name ="JD1" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="50" name ="JD2" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="51" name ="JD3" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="52" name ="JD4" iostandard="LVCMOS33" loc="R14"/>
+  <pin index="53" name ="JD7" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="54" name ="JD8" iostandard="LVCMOS33" loc="U15"/>
+  <pin index="55" name ="JD9" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="56" name ="JD10" iostandard="LVCMOS33" loc="V18"/>
+  <pin index="57" name ="JE1" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="58" name ="JE2" iostandard="LVCMOS33" loc="W16"/>
+  <pin index="59" name ="JE3" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="60" name ="JE4" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="61" name ="JE7" iostandard="LVCMOS33" loc="V13"/>
+  <pin index="62" name ="JE8" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="63" name ="JE9" iostandard="LVCMOS33" loc="T17"/>
+  <pin index="64" name ="JE10" iostandard="LVCMOS33" loc="Y17"/>
+</pins>
+</part_info>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/preset.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/preset.xml
new file mode 100644
index 0000000..443049d
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/zybo/B.4/preset.xml
@@ -0,0 +1,860 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ps7_preset">
+    <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+      <user_parameters>
+	   <user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" value="650.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" value="23.8095"/>
+	   <user_parameter name="CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" value="23.8095"/>
+	   <user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" value="10.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" value="10.096154"/>
+	   <user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" value="125.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" value="10.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" value="100.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" value="10.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" value="10.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" value="10.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ" value="50"/>
+	   <user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" value="200.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" value="200.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" value="50.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ" value="10.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ" value="10.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" value="200.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/>
+	   <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/>
+	   <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/>
+	   <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/>
+	   <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/>
+	   <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/>
+	   <user_parameter name="CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ" value="50"/>
+	   <user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ" value="100.000000"/>
+	   <user_parameter name="CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+	   <user_parameter name="CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ" value="60"/>
+	   <user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" value="108.333336"/>
+	   <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+	   <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+	   <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC" value="External"/>
+	   <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC" value="External"/>
+	   <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_VALID" value="0"/>
+	   <user_parameter name="CONFIG.PCW_CLK0_FREQ" value="100000000"/>
+	   <user_parameter name="CONFIG.PCW_CLK1_FREQ" value="10000000"/>
+	   <user_parameter name="CONFIG.PCW_CLK2_FREQ" value="10000000"/>
+	   <user_parameter name="CONFIG.PCW_CLK3_FREQ" value="10000000"/>
+	   <user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
+	   <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+	   <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50.000000"/>
+	   <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+	   <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+	   <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+	   <user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/>
+	   <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
+	   <user_parameter name="CONFIG.PCW_DM_WIDTH" value="4"/>
+	   <user_parameter name="CONFIG.PCW_DQS_WIDTH" value="4"/>
+	   <user_parameter name="CONFIG.PCW_DQ_WIDTH" value="32"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_BASEADDR" value="0xE000B000"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_HIGHADDR" value="0xE000BFFF"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+	   <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+	   <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+	   <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CAN0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CAN1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CLK0_PORT" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_CLK1_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CLK2_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CLK3_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CLKTRIG0_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CLKTRIG1_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CLKTRIG2_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_CLKTRIG3_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_DDR" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_CAN0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_CAN1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_ENET0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_ENET1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_GPIO" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_I2C0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_I2C1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_PJTAG" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_SPI0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_SPI1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_SRAM_INT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_TRACE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_TTC0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_TTC1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_UART0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_UART1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_WDT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_ENET0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_ENET1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_GPIO" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_I2C0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_I2C1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_MODEM_UART0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_MODEM_UART1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_PJTAG" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_PTP_ENET0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_PTP_ENET1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_QSPI" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_RST0_PORT" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_RST1_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_RST2_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_RST3_PORT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_SDIO0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_SDIO1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_SMC" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_SPI0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_SPI1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_TRACE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_TTC0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_TTC1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_UART0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_UART1" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_USB0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_EN_USB1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_EN_WDT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_FCLK_CLK0_BUF" value="TRUE"/>
+	   <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/>
+	   <user_parameter name="CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ" value="50"/>
+	   <user_parameter name="CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ" value="50"/>
+	   <user_parameter name="CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ" value="50"/>
+	   <user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_GP0_EN_MODIFIABLE_TXN" value="0"/>
+	   <user_parameter name="CONFIG.PCW_GP0_NUM_READ_THREADS" value="4"/>
+	   <user_parameter name="CONFIG.PCW_GP0_NUM_WRITE_THREADS" value="4"/>
+	   <user_parameter name="CONFIG.PCW_GP1_EN_MODIFIABLE_TXN" value="0"/>
+	   <user_parameter name="CONFIG.PCW_GP1_NUM_READ_THREADS" value="4"/>
+	   <user_parameter name="CONFIG.PCW_GP1_NUM_WRITE_THREADS" value="4"/>
+	   <user_parameter name="CONFIG.PCW_GPIO_BASEADDR" value="0xE000A000"/>
+	   <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_GPIO_HIGHADDR" value="0xE000AFFF"/>
+	   <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+	   <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_I2C0_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_I2C_RESET_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_I2C_RESET_POLARITY" value="Active Low"/>
+	   <user_parameter name="CONFIG.PCW_IMPORT_BOARD_PRESET" value="None"/>
+	   <user_parameter name="CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK" value="0"/>
+	   <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+	   <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="HSTL 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+	   <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+	   <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="disabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="fast"/>
+	   <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+	   <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+	   <user_parameter name="CONFIG.PCW_MIO_PRIMITIVE" value="54"/>
+	   <user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0"/>
+	   <user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio"/>
+	   <user_parameter name="CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" value="0"/>
+	   <user_parameter name="CONFIG.PCW_M_AXI_GP0_ID_WIDTH" value="12"/>
+	   <user_parameter name="CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" value="0"/>
+	   <user_parameter name="CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH" value="12"/>
+	   <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_AR" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_CLR" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_REA" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RR" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WP" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS0_T_CEOE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS0_T_PC" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS0_T_RC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS0_T_TR" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS0_T_WC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS0_T_WP" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS0_WE_TIME" value="0"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS1_T_CEOE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS1_T_PC" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS1_T_RC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS1_T_TR" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS1_T_WC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS1_T_WP" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_CS1_WE_TIME" value="0"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_CEOE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_PC" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_RC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_TR" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WP" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_WE_TIME" value="0"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_CEOE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_PC" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_RC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_TR" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WC" value="11"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WP" value="1"/>
+	   <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_WE_TIME" value="0"/>
+	   <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" value="0.080"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" value="0.063"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" value="0.057"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" value="0.068"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" value="-0.047"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" value="-0.025"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" value="-0.006"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" value="-0.017"/>
+	   <user_parameter name="CONFIG.PCW_PACKAGE_NAME" value="clg400"/>
+	   <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+	   <user_parameter name="CONFIG.PCW_PERIPHERAL_BOARD_PRESET" value="part0"/>
+	   <user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+	   <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+	   <user_parameter name="CONFIG.PCW_PS7_SI_REV" value="PRODUCTION"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/>
+	   <user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/>
+	   <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+	   <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_SD0_GRP_WP_IO" value="EMIO"/>
+	   <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+	   <user_parameter name="CONFIG.PCW_SD1_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_SDIO0_BASEADDR" value="0xE0100000"/>
+	   <user_parameter name="CONFIG.PCW_SDIO0_HIGHADDR" value="0xE0100FFF"/>
+	   <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+	   <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" value="1"/>
+	   <user_parameter name="CONFIG.PCW_SINGLE_QSPI_DATA_MODE" value="x4"/>
+	   <user_parameter name="CONFIG.PCW_SMC_CYCLE_T0" value="NA"/>
+	   <user_parameter name="CONFIG.PCW_SMC_CYCLE_T1" value="NA"/>
+	   <user_parameter name="CONFIG.PCW_SMC_CYCLE_T2" value="NA"/>
+	   <user_parameter name="CONFIG.PCW_SMC_CYCLE_T3" value="NA"/>
+	   <user_parameter name="CONFIG.PCW_SMC_CYCLE_T4" value="NA"/>
+	   <user_parameter name="CONFIG.PCW_SMC_CYCLE_T5" value="NA"/>
+	   <user_parameter name="CONFIG.PCW_SMC_CYCLE_T6" value="NA"/>
+	   <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_VALID" value="0"/>
+	   <user_parameter name="CONFIG.PCW_SPI0_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_SPI1_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_VALID" value="0"/>
+	   <user_parameter name="CONFIG.PCW_S_AXI_HP0_DATA_WIDTH" value="64"/>
+	   <user_parameter name="CONFIG.PCW_S_AXI_HP1_DATA_WIDTH" value="64"/>
+	   <user_parameter name="CONFIG.PCW_S_AXI_HP2_DATA_WIDTH" value="64"/>
+	   <user_parameter name="CONFIG.PCW_S_AXI_HP3_DATA_WIDTH" value="64"/>
+	   <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+	   <user_parameter name="CONFIG.PCW_TRACE_INTERNAL_WIDTH" value="2"/>
+	   <user_parameter name="CONFIG.PCW_TRACE_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_BASEADDR" value="0xE0104000"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_HIGHADDR" value="0xE0104fff"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_PERIPHERAL_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_TTC0_TTC0_IO" value="EMIO"/>
+	   <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+	   <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+	   <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+	   <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_TTC1_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ" value="50"/>
+	   <user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UART1_BASEADDR" value="0xE0001000"/>
+	   <user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/>
+	   <user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UART1_HIGHADDR" value="0xE0001FFF"/>
+	   <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_UART1_UART1_IO" value="MIO 48 .. 49"/>
+	   <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+	   <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+	   <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" value="1"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" value="525.000000"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.176"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.159"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.162"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.187"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="32 Bit"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="54.563"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="54.563"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="54.563"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="54.563"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="101.239"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="79.5025"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="60.536"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="71.7715"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.073"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.034"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.03"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.082"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="104.5365"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="70.676"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="59.1615"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="81.319"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K128M16 JT-125"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+	   <user_parameter name="CONFIG.PCW_UIPARAM_GENERATE_SUMMARY" value="NA"/>
+	   <user_parameter name="CONFIG.PCW_USB0_BASEADDR" value="0xE0102000"/>
+	   <user_parameter name="CONFIG.PCW_USB0_HIGHADDR" value="0xE0102fff"/>
+	   <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+	   <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+	   <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_ENABLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+	   <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+	   <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+	   <user_parameter name="CONFIG.PCW_USE_AXI_FABRIC_IDLE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_CORESIGHT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_CR_FABRIC" value="1"/>
+	   <user_parameter name="CONFIG.PCW_USE_DDR_BYPASS" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_DEBUG" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_DMA0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_DMA1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_DMA2" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_DMA3" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_EXPANDED_IOP" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_FABRIC_INTERRUPT" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_HIGH_OCM" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_USE_M_AXI_GP1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_PROC_EVENT_BUS" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_PS_SLCR_REGISTERS" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_S_AXI_ACP" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_S_AXI_GP0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_S_AXI_GP1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_S_AXI_HP0" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_S_AXI_HP1" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_S_AXI_HP2" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_S_AXI_HP3" value="0"/>
+	   <user_parameter name="CONFIG.PCW_USE_TRACE" value="0"/>
+	   <user_parameter name="CONFIG.PCW_VALUE_SILVERSION" value="3"/>
+	   <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+	   <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0" value="1"/>
+	   <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_ENABLE" value="0"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="dip_switches_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="led_4bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_1bit_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="sys_clock_preset">
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+        <user_parameters>
+          <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/> 
+          <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		  <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+        <user_parameters>
+	<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+        <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+        <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/> 
+		<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/arty/C.0/board_part.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/arty/C.0/board_part.xml
new file mode 100644
index 0000000..d7e39d2
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/arty/C.0/board_part.xml
@@ -0,0 +1,704 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Arty" board_revision="C.0" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+  <part_info part_name="xc7a35ticsg324-1L" device="xc7a35t" family="artix7" jtag_position="1" package="csg324" silicon_version="1.0" speed_grade="1L"/>
+
+  <board_info description="Arty" display_name="Arty" url="www.digilentinc.com/Arty"/>
+
+  
+  <interfaces>
+   
+	<interface mode="master" name="DDR3_SDRAM" type="xilinx.com:interface:ddrx_rtl:1.0">
+      <preset_file name="mig.prj"/>
+    </interface>
+	
+    <interface mode="master" name="DIP_Switches_4Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="DIP_Switches_4Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface> 
+	
+    <interface mode="master" name="LED_4Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="LED_4Bits_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="RGB_LED" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="RGB_LED_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+
+	
+    <interface mode="master" name="Push_Buttons_4Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="Push_Buttons_4Bits_TRI_I"/>
+      </port_maps>
+    </interface>
+	
+    <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+        <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+      </port_maps>
+    </interface>
+	
+    <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+     
+	 <port_maps>
+		
+        <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+        <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+        <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+        <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+        <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+		
+		    <port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+        <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+        <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+		
+		    <port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+        <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+        <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+		
+		    <port_map logical_port="SCK_I" physical_port="Qspi_CSn_i"/>
+        <port_map logical_port="SCK_O" physical_port="Qspi_CSn_o"/>
+        <port_map logical_port="SCK_T" physical_port="Qspi_CSn_t"/>
+		
+		    <port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+        <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+        <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+		
+		
+      </port_maps> 
+	  </interface>
+
+	  <interface mode="master" name="I2C" type="xilinx.com:interface:iic_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="SDA_I" physical_port="I2C_SDA_i"/>
+        <port_map logical_port="SDA_O" physical_port="I2C_SDA_o"/>
+        <port_map logical_port="SDA_T" physical_port="I2C_SDA_t"/>
+        <port_map logical_port="SCL_I" physical_port="I2C_SCL_i"/>
+        <port_map logical_port="SCL_O" physical_port="I2C_SCL_o"/>
+        <port_map logical_port="SCL_T" physical_port="I2C_SCL_t"/>
+      </port_maps>
+    </interface>
+
+	  <interface mode="master" name="I2C_PULLUPS" type="xilinx.com:interface:gpio_rtl:1.0"> 
+    <port_maps>
+        <port_map logical_port="TRI_O" physical_port="I2C_PULLUP"/>
+      </port_maps>
+    </interface>
+	
+
+	  <interface mode="master" name="SPI" type="xilinx.com:interface:spi_rtl:1.0">
+	 <port_maps>
+		<port_map logical_port="IO0_I" physical_port="SPI_MISO_i"/>
+        <port_map logical_port="IO0_O" physical_port="SPI_MISO_o"/>
+        <port_map logical_port="IO0_T" physical_port="SPI_MISO_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="SPI_MOSI_i"/>
+        <port_map logical_port="IO1_O" physical_port="SPI_MOSI_o"/>
+        <port_map logical_port="IO1_T" physical_port="SPI_MOSI_t"/>
+
+        <port_map logical_port="SCK_I" physical_port="SPI_SCLK_i"/>
+        <port_map logical_port="SCK_O" physical_port="SPI_SCLK_o"/>
+        <port_map logical_port="SCK_T" physical_port="SPI_SCLK_t"/>
+
+        <port_map logical_port="SS_I" physical_port="SPI_SS_i"/>
+        <port_map logical_port="SS_O" physical_port="SPI_SS_o"/>
+        <port_map logical_port="SS_T" physical_port="SPI_SS_t"/>
+      
+      </port_maps>
+    </interface>
+	
+
+	 <interface mode="master" name="ETH_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="MDIO_I" physical_port="ETH_mdio_i"/>
+        <port_map logical_port="MDIO_O" physical_port="ETH_mdio_o"/>
+        <port_map logical_port="MDIO_T" physical_port="ETH_mdio_t"/>
+        <port_map logical_port="MDC" physical_port="ETH_mdc"/>
+      </port_maps>
+    </interface>
+	
+	
+
+<interface mode="master" name="ETH_mii" type="xilinx.com:interface:mii_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="TXD" physical_port="ETH_txd"/>
+        <port_map logical_port="TX_EN" physical_port="ETH_tx_en"/>
+        <port_map logical_port="RXD" physical_port="ETH_rxd"/>
+        <port_map logical_port="RX_DV" physical_port="ETH_rx_dv"/>      
+        <port_map logical_port="RX_ER" physical_port="ETH_rx_er"/>
+        <port_map logical_port="CRS" physical_port="ETH_crs"/>
+        <port_map logical_port="COL" physical_port="ETH_col"/>
+        <port_map logical_port="TX_CLK" physical_port="ETH_tx_clk"/>
+        <port_map logical_port="RX_CLK" physical_port="ETH_rx_clk"/>
+        <port_map logical_port="RST_N" physical_port="ETH_rstn"/>
+      </port_maps>
+   </interface>
+
+
+
+    <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0">
+     
+	 <port_maps>
+        <port_map logical_port="clk" physical_port="clk"/>
+      </port_maps>
+	  
+      <parameters>
+        <parameter name="frequency" value="100000000"/>
+      </parameters>
+	  
+	</interface>
+  
+    <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="RESET" physical_port="RESET"/>
+      </port_maps>
+      <parameters>
+        <parameter name="RST_POLARITY" value="0"/>
+      </parameters>
+    </interface>
+	
+	<interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="SHEILD_dp0_dp19_TRI_I"/>
+		<port_map logical_port="TRI_O" physical_port="SHEILD_dp0_dp19_TRI_O"/>
+		<port_map logical_port="TRI_T" physical_port="SHEILD_dp0_dp19_TRI_T"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="SHEILD_dp26_dp41_TRI_I"/>
+		<port_map logical_port="TRI_O" physical_port="SHEILD_dp26_dp41_TRI_O"/>
+		<port_map logical_port="TRI_T" physical_port="SHEILD_dp26_dp41_TRI_T"/>
+      </port_maps>
+	  
+    </interface>
+	
+	
+  </interfaces>
+
+  
+  <ports>
+    
+	<port name="DIP_Switches_4Bits_TRI_I" dir="in" left="3"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="A8"/>
+        <pin index="1" iostandard="LVCMOS33" loc="C11"/>
+        <pin index="2" iostandard="LVCMOS33" loc="C10"/>
+        <pin index="3" iostandard="LVCMOS33" loc="A10"/>
+      </pins>
+    </port>
+
+    <port name="LED_4Bits_TRI_O" dir="out" left="3"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="H5"/>
+        <pin index="1" iostandard="LVCMOS33" loc="J5"/>
+        <pin index="2" iostandard="LVCMOS33" loc="T9"/>
+        <pin index="3" iostandard="LVCMOS33" loc="T10"/>
+      </pins>
+    </port>
+
+
+	<port dir="out" left="11" name="RGB_LED_TRI_O" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="E1"/>
+        <pin index="1" iostandard="LVCMOS33" loc="F6"/>
+        <pin index="2" iostandard="LVCMOS33" loc="G6"/>
+        <pin index="3" iostandard="LVCMOS33" loc="G4"/>
+        <pin index="4" iostandard="LVCMOS33" loc="J4"/>
+        <pin index="5" iostandard="LVCMOS33" loc="G3"/>
+        <pin index="6" iostandard="LVCMOS33" loc="H4"/>
+        <pin index="7" iostandard="LVCMOS33" loc="J2"/>
+        <pin index="8" iostandard="LVCMOS33" loc="J3"/>
+        <pin index="9" iostandard="LVCMOS33" loc="K2"/>
+        <pin index="10" iostandard="LVCMOS33" loc="H6"/>
+        <pin index="11" iostandard="LVCMOS33" loc="K1"/>
+      </pins>
+    </port>	
+
+    <port name="Push_Buttons_4Bits_TRI_I" dir="in" left="3"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="D9"/>
+        <pin index="1" iostandard="LVCMOS33" loc="C9"/>
+        <pin index="2" iostandard="LVCMOS33" loc="B9"/>
+        <pin index="3" iostandard="LVCMOS33" loc="B8"/>
+      </pins>
+    </port>
+	<port name="RESET" dir="in" >
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C2"/>
+      </pins>
+    </port>
+	
+
+    <port dir="in" name="USB_Uart_RxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="A9"/>
+      </pins>
+    </port>
+    <port dir="out" name="USB_Uart_TxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D10"/>
+      </pins>
+    </port>
+  
+	
+    <port dir="in" name="Qspi_DB0_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB1_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB2_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB3_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_sclk_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L16"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_sclk_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L16"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_sclk_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L16"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_CSn_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+
+
+    <port dir="in" name="I2C_SCL_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L18"/>
+      </pins>
+    </port>
+    <port dir="out" name="I2C_SCL_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L18"/>
+      </pins>
+    </port>
+    <port dir="out" name="I2C_SCL_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L18"/>
+      </pins>
+    </port>
+
+    <port dir="in" name="I2C_SDA_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M18"/>
+      </pins>
+    </port>
+    <port dir="out" name="I2C_SDA_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M18"/>
+      </pins>
+    </port>
+    <port dir="out" name="I2C_SDA_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M18"/>
+      </pins>
+    </port>
+
+  <port dir="out" left="1" name="I2C_PULLUP" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="A14"/>
+        <pin index="1" iostandard="LVCMOS33" loc="A13"/>
+      </pins>
+    </port> 
+
+
+  <port dir="in" name="SPI_MISO_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G1"/>
+      </pins>
+    </port>
+    <port dir="out" name="SPI_MISO_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G1"/>
+      </pins>
+    </port>
+    <port dir="out" name="SPI_MISO_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G1"/>
+      </pins>
+    </port>
+  <port dir="in" name="SPI_MOSI_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="H1"/>
+      </pins>
+    </port>
+    <port dir="out" name="SPI_MOSI_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="H1"/>
+      </pins>
+    </port>
+    <port dir="out" name="SPI_MOSI_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="H1"/>
+      </pins>
+    </port>
+  <port dir="in" name="SPI_SCLK_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F1"/>
+      </pins>
+    </port>
+    <port dir="out" name="SPI_SCLK_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F1"/>
+      </pins>
+    </port>
+    <port dir="out" name="SPI_SCLK_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F1"/>
+      </pins>
+    </port>
+    <port dir="in" name="SPI_SS_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C1"/>
+      </pins>
+    </port>
+    <port dir="out" name="SPI_SS_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C1"/>
+      </pins>
+    </port>
+    <port dir="out" name="SPI_SS_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C1"/>
+      </pins>
+    </port>
+
+
+
+	<port dir="out" name="ETH_mdc">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F16"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="ETH_mdio_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K13"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_mdio_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K13"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_mdio_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K13"/>
+      </pins>
+    </port>
+
+
+	<port dir="out" left="3" name="ETH_txd" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="H14"/>
+        <pin index="1" iostandard="LVCMOS33" loc="J14"/>
+        <pin index="2" iostandard="LVCMOS33" loc="J13"/>
+        <pin index="3" iostandard="LVCMOS33" loc="H17"/>
+      </pins>
+	</port>
+	
+	<port dir="in" left="3" name="ETH_rxd" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="D18"/>
+        <pin index="1" iostandard="LVCMOS33" loc="E17"/>
+        <pin index="2" iostandard="LVCMOS33" loc="E18"/>
+        <pin index="3" iostandard="LVCMOS33" loc="G17"/>
+      </pins>
+	</port>
+
+  <port dir="out" name="ETH_tx_en">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="H15"/>
+      </pins>
+    </port>
+  <port dir="in" name="ETH_rx_dv">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G16"/>
+      </pins>
+    </port>
+  
+  <port dir="in" name="ETH_rx_er">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C17"/>
+      </pins>
+    </port>
+  
+  <port dir="in" name="ETH_crs">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G14"/>
+      </pins>
+    </port> 
+
+    <port dir="in" name="ETH_col">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D17"/>
+      </pins>
+    </port>
+
+    <port dir="in" name="ETH_tx_clk">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="H16"/>
+      </pins>
+    </port>
+
+    <port dir="in" name="ETH_rx_clk">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F15"/>
+      </pins>
+    </port>
+
+    <port dir="out" name="ETH_rstn">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C16"/>
+      </pins>
+    </port>
+
+
+    <port dir="in" name="clk">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E3"/>
+      </pins>
+    </port>
+	
+	<port name="SHEILD_dp0_dp19_TRI_I" dir="in" left="19"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="V15"/>
+        <pin index="1" iostandard="LVCMOS33" loc="U16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="P14"/>
+        <pin index="3" iostandard="LVCMOS33" loc="T11"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R12"/>
+        <pin index="5" iostandard="LVCMOS33" loc="T14"/>
+        <pin index="6" iostandard="LVCMOS33" loc="T15"/>
+        <pin index="7" iostandard="LVCMOS33" loc="T16"/>
+        <pin index="8" iostandard="LVCMOS33" loc="N15"/>
+        <pin index="9" iostandard="LVCMOS33" loc="M16"/>
+        <pin index="10" iostandard="LVCMOS33" loc="V17"/>
+        <pin index="11" iostandard="LVCMOS33" loc="U18"/>
+        <pin index="12" iostandard="LVCMOS33" loc="R17"/>
+        <pin index="13" iostandard="LVCMOS33" loc="P17"/>
+        <pin index="14" iostandard="LVCMOS33" loc="F5"/>
+        <pin index="15" iostandard="LVCMOS33" loc="D8"/>
+        <pin index="16" iostandard="LVCMOS33" loc="C7"/>
+        <pin index="17" iostandard="LVCMOS33" loc="E7"/>
+        <pin index="18" iostandard="LVCMOS33" loc="D7"/>
+        <pin index="19" iostandard="LVCMOS33" loc="D5"/>
+      </pins>
+    </port>
+	
+	<port name="SHEILD_dp0_dp19_TRI_O" dir="out" left="19"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="V15"/>
+        <pin index="1" iostandard="LVCMOS33" loc="U16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="P14"/>
+        <pin index="3" iostandard="LVCMOS33" loc="T11"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R12"/>
+        <pin index="5" iostandard="LVCMOS33" loc="T14"/>
+        <pin index="6" iostandard="LVCMOS33" loc="T15"/>
+        <pin index="7" iostandard="LVCMOS33" loc="T16"/>
+        <pin index="8" iostandard="LVCMOS33" loc="N15"/>
+        <pin index="9" iostandard="LVCMOS33" loc="M16"/>
+        <pin index="10" iostandard="LVCMOS33" loc="V17"/>
+        <pin index="11" iostandard="LVCMOS33" loc="U18"/>
+        <pin index="12" iostandard="LVCMOS33" loc="R17"/>
+        <pin index="13" iostandard="LVCMOS33" loc="P17"/>
+        <pin index="14" iostandard="LVCMOS33" loc="F5"/>
+        <pin index="15" iostandard="LVCMOS33" loc="D8"/>
+        <pin index="16" iostandard="LVCMOS33" loc="C7"/>
+        <pin index="17" iostandard="LVCMOS33" loc="E7"/>
+        <pin index="18" iostandard="LVCMOS33" loc="D7"/>
+        <pin index="19" iostandard="LVCMOS33" loc="D5"/>
+      </pins>
+    </port>
+	
+	<port name="SHEILD_dp0_dp19_TRI_T" dir="out" left="19"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="V15"/>
+        <pin index="1" iostandard="LVCMOS33" loc="U16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="P14"/>
+        <pin index="3" iostandard="LVCMOS33" loc="T11"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R12"/>
+        <pin index="5" iostandard="LVCMOS33" loc="T14"/>
+        <pin index="6" iostandard="LVCMOS33" loc="T15"/>
+        <pin index="7" iostandard="LVCMOS33" loc="T16"/>
+        <pin index="8" iostandard="LVCMOS33" loc="N15"/>
+        <pin index="9" iostandard="LVCMOS33" loc="M16"/>
+        <pin index="10" iostandard="LVCMOS33" loc="V17"/>
+        <pin index="11" iostandard="LVCMOS33" loc="U18"/>
+        <pin index="12" iostandard="LVCMOS33" loc="R17"/>
+        <pin index="13" iostandard="LVCMOS33" loc="P17"/>
+        <pin index="14" iostandard="LVCMOS33" loc="F5"/>
+        <pin index="15" iostandard="LVCMOS33" loc="D8"/>
+        <pin index="16" iostandard="LVCMOS33" loc="C7"/>
+        <pin index="17" iostandard="LVCMOS33" loc="E7"/>
+        <pin index="18" iostandard="LVCMOS33" loc="D7"/>
+        <pin index="19" iostandard="LVCMOS33" loc="D5"/>
+      </pins>
+    </port>
+	
+	<port name="SHEILD_dp26_dp41_TRI_I" dir="in" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="U11"/>
+        <pin index="1" iostandard="LVCMOS33" loc="V16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="M13"/>
+        <pin index="3" iostandard="LVCMOS33" loc="R10"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R11"/>
+        <pin index="5" iostandard="LVCMOS33" loc="R13"/>
+        <pin index="6" iostandard="LVCMOS33" loc="R15"/>
+        <pin index="7" iostandard="LVCMOS33" loc="P15"/>
+        <pin index="8" iostandard="LVCMOS33" loc="R16"/>
+        <pin index="9" iostandard="LVCMOS33" loc="N16"/>
+        <pin index="10" iostandard="LVCMOS33" loc="N14"/>
+        <pin index="11" iostandard="LVCMOS33" loc="U17"/>
+        <pin index="12" iostandard="LVCMOS33" loc="T18"/>
+        <pin index="13" iostandard="LVCMOS33" loc="R18"/>
+        <pin index="14" iostandard="LVCMOS33" loc="P18"/>
+        <pin index="15" iostandard="LVCMOS33" loc="N17"/>
+      </pins>
+    </port>
+	
+	<port name="SHEILD_dp26_dp41_TRI_O" dir="out" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="U11"/>
+        <pin index="1" iostandard="LVCMOS33" loc="V16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="M13"/>
+        <pin index="3" iostandard="LVCMOS33" loc="R10"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R11"/>
+        <pin index="5" iostandard="LVCMOS33" loc="R13"/>
+        <pin index="6" iostandard="LVCMOS33" loc="R15"/>
+        <pin index="7" iostandard="LVCMOS33" loc="P15"/>
+        <pin index="8" iostandard="LVCMOS33" loc="R16"/>
+        <pin index="9" iostandard="LVCMOS33" loc="N16"/>
+        <pin index="10" iostandard="LVCMOS33" loc="N14"/>
+        <pin index="11" iostandard="LVCMOS33" loc="U17"/>
+        <pin index="12" iostandard="LVCMOS33" loc="T18"/>
+        <pin index="13" iostandard="LVCMOS33" loc="R18"/>
+        <pin index="14" iostandard="LVCMOS33" loc="P18"/>
+        <pin index="15" iostandard="LVCMOS33" loc="N17"/>
+      </pins>
+    </port>
+	
+	<port name="SHEILD_dp26_dp41_TRI_T" dir="out" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="U11"/>
+        <pin index="1" iostandard="LVCMOS33" loc="V16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="M13"/>
+        <pin index="3" iostandard="LVCMOS33" loc="R10"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R11"/>
+        <pin index="5" iostandard="LVCMOS33" loc="R13"/>
+        <pin index="6" iostandard="LVCMOS33" loc="R15"/>
+        <pin index="7" iostandard="LVCMOS33" loc="P15"/>
+        <pin index="8" iostandard="LVCMOS33" loc="R16"/>
+        <pin index="9" iostandard="LVCMOS33" loc="N16"/>
+        <pin index="10" iostandard="LVCMOS33" loc="N14"/>
+        <pin index="11" iostandard="LVCMOS33" loc="U17"/>
+        <pin index="12" iostandard="LVCMOS33" loc="T18"/>
+        <pin index="13" iostandard="LVCMOS33" loc="R18"/>
+        <pin index="14" iostandard="LVCMOS33" loc="P18"/>
+        <pin index="15" iostandard="LVCMOS33" loc="N17"/>
+      </pins>
+    </port>
+	
+	</ports>
+
+</board_part>
+
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/arty/desktop.ini b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/arty/desktop.ini
new file mode 100644
index 0000000..d957fd1
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/arty/desktop.ini
@@ -0,0 +1,4 @@
+[ViewState]
+Mode=
+Vid=
+FolderType=Generic
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/basys3/1.1/board_part.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/basys3/1.1/board_part.xml
new file mode 100644
index 0000000..cd473b4
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/basys3/1.1/board_part.xml
@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Basys3" board_revision="1.1" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+  <part_info part_name="xc7a35tcpg236-1" device="xc7a35t" family="artix7" jtag_position="1" package="cpg236" silicon_version="1.0" speed_grade="1"/>
+
+  <board_info description="Basys3 Artix-7 FPGA Board" display_name="Basys3 Artix-7 FPGA Board" url="www.digilentinc.com/basys3"/>
+
+  
+  <interfaces>
+   
+	
+    <interface mode="master" name="DIP_Switches_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="DIP_Switches_16Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="LED_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="LED_16Bits_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="Push_Buttons_5Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="Push_Buttons_5Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="SEVEN_SEG_LED_DISP" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="SEVEN_SEG_LED_DISP_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="SEVEN_SEG_LED_AN" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="SEVEN_SEG_LED_AN_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+        <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+     
+	 <port_maps>
+        <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+        <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+        <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+        <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+        <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+		
+		
+		<port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+        <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+        <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+		
+		<port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+        <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+        <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+		
+		<port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+        <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+        <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+		
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="slave" name="sys_clock" type="xilinx.com:interface:clock_rtl:1.0">
+     
+	 <port_maps>
+        <port_map logical_port="CLK" physical_port="clk"/>
+      </port_maps>
+	  
+      <parameters>
+        <parameter name="frequency" value="100000000"/>
+      </parameters>
+	  
+	</interface>
+  
+    <interface mode="slave" name="Reset" type="xilinx.com:signal:reset_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="RST" physical_port="RESET"/>
+      </port_maps>
+      <parameters>
+        <parameter name="RST_POLARITY" value="1"/>
+      </parameters>
+    </interface>
+	
+  </interfaces>
+
+  
+  <ports>
+    
+	<port name="DIP_Switches_16Bits_TRI_I" dir="in" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="V17"/>
+        <pin index="1" iostandard="LVCMOS33" loc="V16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="W16"/>
+        <pin index="3" iostandard="LVCMOS33" loc="W17"/>
+		<pin index="4" iostandard="LVCMOS33" loc="W15"/>
+        <pin index="5" iostandard="LVCMOS33" loc="V15"/>
+        <pin index="6" iostandard="LVCMOS33" loc="W14"/>
+        <pin index="7" iostandard="LVCMOS33" loc="W13"/>
+		<pin index="8" iostandard="LVCMOS33" loc="V2"/>
+        <pin index="9" iostandard="LVCMOS33" loc="T3"/>
+        <pin index="10" iostandard="LVCMOS33" loc="T2"/>
+        <pin index="11" iostandard="LVCMOS33" loc="R3"/>
+		<pin index="12" iostandard="LVCMOS33" loc="W2"/>
+        <pin index="13" iostandard="LVCMOS33" loc="U1"/>
+        <pin index="14" iostandard="LVCMOS33" loc="T1"/>
+        <pin index="15" iostandard="LVCMOS33" loc="R2"/>
+      </pins>
+    </port>
+		
+    <port name="LED_16Bits_TRI_O" dir="out" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="U16"/>
+        <pin index="1" iostandard="LVCMOS33" loc="E19"/>
+        <pin index="2" iostandard="LVCMOS33" loc="U19"/>
+        <pin index="3" iostandard="LVCMOS33" loc="V19"/>
+		<pin index="4" iostandard="LVCMOS33" loc="W18"/>
+        <pin index="5" iostandard="LVCMOS33" loc="U15"/>
+        <pin index="6" iostandard="LVCMOS33" loc="U14"/>
+        <pin index="7" iostandard="LVCMOS33" loc="V14"/>
+		<pin index="8" iostandard="LVCMOS33" loc="V13"/>
+        <pin index="9" iostandard="LVCMOS33" loc="V3"/>
+        <pin index="10" iostandard="LVCMOS33" loc="W3"/>
+        <pin index="11" iostandard="LVCMOS33" loc="U3"/>
+		<pin index="12" iostandard="LVCMOS33" loc="P3"/>
+        <pin index="13" iostandard="LVCMOS33" loc="N3"/>
+        <pin index="14" iostandard="LVCMOS33" loc="P1"/>
+        <pin index="15" iostandard="LVCMOS33" loc="L1"/>
+      </pins>
+    </port>
+	    
+    <port name="Push_Buttons_5Bits_TRI_I" dir="in" left="3"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="T18"/>
+        <pin index="1" iostandard="LVCMOS33" loc="W19"/>
+        <pin index="2" iostandard="LVCMOS33" loc="T17"/>
+        <pin index="3" iostandard="LVCMOS33" loc="U17"/>
+      </pins>
+    </port>
+
+	<port name="RESET" dir="in" >
+      <pins>
+        <pin iostandard="LVCMOS33" loc="U18"/>
+      </pins>
+    </port>
+	
+
+   <port name="SEVEN_SEG_LED_DISP_TRI_O" dir="out" left="7"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="W7"/>
+        <pin index="1" iostandard="LVCMOS33" loc="W6"/>
+        <pin index="2" iostandard="LVCMOS33" loc="U8"/>
+        <pin index="3" iostandard="LVCMOS33" loc="V8"/>
+		<pin index="4" iostandard="LVCMOS33" loc="U5"/>
+        <pin index="5" iostandard="LVCMOS33" loc="V5"/>
+        <pin index="6" iostandard="LVCMOS33" loc="U7"/>
+		<pin index="7" iostandard="LVCMOS33" loc="V7"/>
+      </pins>
+    </port>		
+	
+   <port name="SEVEN_SEG_LED_AN_TRI_O" dir="out" left="3"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="U2"/>
+        <pin index="1" iostandard="LVCMOS33" loc="U4"/>
+        <pin index="2" iostandard="LVCMOS33" loc="V4"/>
+        <pin index="3" iostandard="LVCMOS33" loc="W4"/>
+      </pins>
+    </port>	
+
+    <port dir="in" name="USB_Uart_RxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="B18"/>
+      </pins>
+    </port>
+    <port dir="out" name="USB_Uart_TxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="A18"/>
+      </pins>
+    </port>
+    
+    <port dir="in" name="Qspi_DB0_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D18"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB1_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D19"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D19"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D19"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB2_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G18"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB3_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F18"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_CSn_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K19"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K19"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K19"/>
+      </pins>
+    </port>
+	
+    <port dir="in" name="clk">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W5"/>
+      </pins>
+    </port>
+	
+	</ports>
+
+</board_part>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/nexys4/1.1/board_part.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/nexys4/1.1/board_part.xml
new file mode 100644
index 0000000..639fec2
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/nexys4/1.1/board_part.xml
@@ -0,0 +1,654 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Nexys4" board_revision="1.1" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+  <part_info part_name="xc7a100tcsg324-1" device="xc7a100t" family="artix7" jtag_position="1" package="csg324" silicon_version="1.0" speed_grade="1"/>
+
+  <board_info description="Nexys4 FPGA Board" display_name="Nexys4 FPGA Board" url="www.digilentinc.com/nexys4"/>
+
+  
+  <interfaces>
+	
+    <interface mode="master" name="DIP_Switches_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="DIP_Switches_16Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface> 
+	
+    <interface mode="master" name="LED_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="LED_16Bits_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="Push_Buttons_5Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="Push_Buttons_5Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="DUAL_SEVEN_SEG_LED_DISP" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="DUAL_SEVEN_SEG_LED_DISP_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="SEVEN_SEG_LED_AN" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="SEVEN_SEG_LED_AN_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+        <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+     
+	 <port_maps>
+	 
+		<port_map logical_port="SCK_I" physical_port="Qspi_SCK_i"/>
+        <port_map logical_port="SCK_O" physical_port="Qspi_SCK_o"/>
+        <port_map logical_port="SCK_T" physical_port="Qspi_SCK_t"/>
+		
+        <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+        <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+        <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+        <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+        <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+		
+		
+		<port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+        <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+        <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+		
+		<port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+        <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+        <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+		
+		<port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+        <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+        <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+		
+      </port_maps>
+	  
+	  </interface>
+	  
+	  
+	  <interface mode="master" name="TEMP_SENSOR" type="xilinx.com:interface:iic_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="SDA_I" physical_port="TEMP_SDA_i"/>
+        <port_map logical_port="SDA_O" physical_port="TEMP_SDA_o"/>
+        <port_map logical_port="SDA_T" physical_port="TEMP_SDA_t"/>
+        <port_map logical_port="SCL_I" physical_port="TEMP_SCL_i"/>
+        <port_map logical_port="SCL_O" physical_port="TEMP_SCL_o"/>
+        <port_map logical_port="SCL_T" physical_port="TEMP_SCL_t"/>
+      </port_maps>
+    </interface>
+	  
+	  
+	  <interface mode="master" name="ACL_SPI" type="xilinx.com:interface:spi_rtl:1.0">
+     
+	 <port_maps>
+	 
+		<port_map logical_port="IO0_I" physical_port="ACL_MISO_i"/>
+        <port_map logical_port="IO0_O" physical_port="ACL_MISO_o"/>
+        <port_map logical_port="IO0_T" physical_port="ACL_MISO_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="ACL_MOSI_i"/>
+        <port_map logical_port="IO1_O" physical_port="ACL_MOSI_o"/>
+        <port_map logical_port="IO1_T" physical_port="ACL_MOSI_t"/>
+		
+        <port_map logical_port="SCK_I" physical_port="ACL_SCLK_i"/>
+        <port_map logical_port="SCK_O" physical_port="ACL_SCLK_o"/>
+        <port_map logical_port="SCK_T" physical_port="ACL_SCLK_t"/>
+		
+		
+		<port_map logical_port="SS_I" physical_port="ACL_SS_i"/>
+        <port_map logical_port="SS_O" physical_port="ACL_SS_o"/>
+        <port_map logical_port="SS_T" physical_port="ACL_SS_t"/>
+		
+      </port_maps>
+
+    </interface>
+	
+	 <interface mode="master" name="ETH_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="MDIO_I" physical_port="ETH_mdio_i"/>
+        <port_map logical_port="MDIO_O" physical_port="ETH_mdio_o"/>
+        <port_map logical_port="MDIO_T" physical_port="ETH_mdio_t"/>
+        <port_map logical_port="MDC" physical_port="ETH_mdc"/>
+      </port_maps>
+    </interface>
+	
+	<interface mode="master" name="ETH_rmii" type="xilinx.com:interface:rmii_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="TXD" physical_port="ETH_rmii_txd"/>
+		<port_map logical_port="RXD" physical_port="ETH_rmii_rxd"/>		       
+	    <port_map logical_port="TX_EN" physical_port="ETH_rmii_tx_en"/>
+		<port_map logical_port="RX_ER" physical_port="ETH_rmii_rx_er"/>
+        <port_map logical_port="CRS_DV" physical_port="ETH_rmii_crs_dv"/>
+      </port_maps>
+	</interface>
+	
+	<interface mode="master" name="cellular_RAM" type="xilinx.com:interface:emc_rtl:1.0" preset_proc_name="emc_preset">
+      <port_maps>
+        <port_map logical_port="ADDR" physical_port="cellular_RAM_addr"/>
+        <port_map logical_port="DQ_O" physical_port="cellular_RAM_dq_o"/>
+        <port_map logical_port="DQ_I" physical_port="cellular_RAM_dq_i"/>
+        <port_map logical_port="DQ_T" physical_port="cellular_RAM_dq_t"/>
+        <port_map logical_port="ADV_LDN" physical_port="cellular_RAM_adv_ldn"/>
+        <port_map logical_port="OEN" physical_port="cellular_RAM_oen"/>
+        <port_map logical_port="WEN" physical_port="cellular_RAM_wen"/>
+        <port_map logical_port="CE_N" physical_port="cellular_RAM_ce_n"/>
+		<port_map logical_port="CRE" physical_port="cellular_RAM_cre"/>
+		<port_map logical_port="BEN" physical_port="cellular_RAM_ben"/>
+		<port_map logical_port="WAIT" physical_port="cellular_RAM_wait"/>
+      </port_maps>
+    </interface>
+	
+
+    <interface mode="slave" name="sys_clock" type="xilinx.com:interface:clock_rtl:1.0">
+	 <port_maps>
+        <port_map logical_port="clk" physical_port="clk"/>
+      </port_maps>
+      <parameters>
+        <parameter name="frequency" value="100000000"/>
+      </parameters>
+	</interface>
+  
+    <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="RESET" physical_port="RESET"/>
+      </port_maps>
+      <parameters>
+        <parameter name="RST_POLARITY" value="1"/>
+      </parameters>
+    </interface>
+	
+  </interfaces>
+
+  
+  <ports>
+    
+	<port name="DIP_Switches_16Bits_TRI_I" dir="in" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="U9"/>
+        <pin index="1" iostandard="LVCMOS33" loc="U8"/>
+        <pin index="2" iostandard="LVCMOS33" loc="R7"/>
+        <pin index="3" iostandard="LVCMOS33" loc="R6"/>
+		<pin index="4" iostandard="LVCMOS33" loc="R5"/>
+        <pin index="5" iostandard="LVCMOS33" loc="V7"/>
+        <pin index="6" iostandard="LVCMOS33" loc="V6"/>
+        <pin index="7" iostandard="LVCMOS33" loc="V5"/>
+		<pin index="8" iostandard="LVCMOS33" loc="U4"/>
+        <pin index="9" iostandard="LVCMOS33" loc="V2"/>
+        <pin index="10" iostandard="LVCMOS33" loc="U2"/>
+        <pin index="11" iostandard="LVCMOS33" loc="T3"/>
+		<pin index="12" iostandard="LVCMOS33" loc="T1"/>
+        <pin index="13" iostandard="LVCMOS33" loc="R3"/>
+        <pin index="14" iostandard="LVCMOS33" loc="P3"/>
+        <pin index="15" iostandard="LVCMOS33" loc="P4"/>
+      </pins>
+    </port>
+		
+    <port name="LED_16Bits_TRI_O" dir="out" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="T8"/>
+        <pin index="1" iostandard="LVCMOS33" loc="V9"/>
+        <pin index="2" iostandard="LVCMOS33" loc="R8"/>
+        <pin index="3" iostandard="LVCMOS33" loc="T6"/>
+		<pin index="4" iostandard="LVCMOS33" loc="T5"/>
+        <pin index="5" iostandard="LVCMOS33" loc="T4"/>
+        <pin index="6" iostandard="LVCMOS33" loc="U7"/>
+        <pin index="7" iostandard="LVCMOS33" loc="U6"/>
+		<pin index="8" iostandard="LVCMOS33" loc="V4"/>
+        <pin index="9" iostandard="LVCMOS33" loc="U3"/>
+        <pin index="10" iostandard="LVCMOS33" loc="V1"/>
+        <pin index="11" iostandard="LVCMOS33" loc="R1"/>
+		<pin index="12" iostandard="LVCMOS33" loc="P5"/>
+        <pin index="13" iostandard="LVCMOS33" loc="U1"/>
+        <pin index="14" iostandard="LVCMOS33" loc="R2"/>
+        <pin index="15" iostandard="LVCMOS33" loc="P2"/>
+      </pins>
+    </port>
+	    
+    <port name="Push_Buttons_5Bits_TRI_I" dir="in" left="3"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="F15"/>
+        <pin index="1" iostandard="LVCMOS33" loc="T16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="V10"/>
+        <pin index="3" iostandard="LVCMOS33" loc="R10"/>
+      </pins>
+    </port>
+
+	<port name="RESET" dir="in" >
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E16"/>
+      </pins>
+    </port>
+	
+
+   <port name="DUAL_SEVEN_SEG_LED_DISP_TRI_O" dir="out" left="7"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="L3"/>
+        <pin index="1" iostandard="LVCMOS33" loc="N1"/>
+        <pin index="2" iostandard="LVCMOS33" loc="L5"/>
+        <pin index="3" iostandard="LVCMOS33" loc="L4"/>
+		<pin index="4" iostandard="LVCMOS33" loc="K3"/>
+        <pin index="5" iostandard="LVCMOS33" loc="M2"/>
+        <pin index="6" iostandard="LVCMOS33" loc="L6"/>
+		<pin index="7" iostandard="LVCMOS33" loc="M4"/>
+      </pins>
+    </port>		
+	
+   <port name="SEVEN_SEG_LED_AN_TRI_O" dir="out" left="7"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="N6"/>
+        <pin index="1" iostandard="LVCMOS33" loc="M6"/>
+        <pin index="2" iostandard="LVCMOS33" loc="M3"/>
+        <pin index="3" iostandard="LVCMOS33" loc="N5"/>
+		<pin index="4" iostandard="LVCMOS33" loc="N2"/>
+        <pin index="5" iostandard="LVCMOS33" loc="N4"/>
+        <pin index="6" iostandard="LVCMOS33" loc="L1"/>
+		<pin index="7" iostandard="LVCMOS33" loc="M1"/>
+      </pins>
+    </port>	
+
+    <port dir="in" name="USB_Uart_RxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C4"/>
+      </pins>
+    </port>
+    <port dir="out" name="USB_Uart_TxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D4"/>
+      </pins>
+    </port>
+    
+	
+	<port dir="in" name="Qspi_SCK_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E9"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_SCK_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E9"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_SCK_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E9"/>
+      </pins>
+    </port>
+    <port dir="in" name="Qspi_DB0_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+	<port dir="in" name="Qspi_DB1_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+	<port dir="in" name="Qspi_DB2_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+	<port dir="in" name="Qspi_DB3_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+	<port dir="in" name="Qspi_CSn_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+	
+	
+	<port dir="in" name="TEMP_SDA_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G16"/>
+      </pins>
+    </port>
+    <port dir="out" name="TEMP_SDA_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G16"/>
+      </pins>
+    </port>
+    <port dir="out" name="TEMP_SDA_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="G16"/>
+      </pins>
+    </port>
+	<port dir="in" name="TEMP_SCL_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F16"/>
+      </pins>
+    </port>
+    <port dir="out" name="TEMP_SCL_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F16"/>
+      </pins>
+    </port>
+    <port dir="out" name="TEMP_SCL_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F16"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="ACL_MISO_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D13"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_MISO_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D13"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_MISO_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D13"/>
+      </pins>
+    </port>
+	<port dir="in" name="ACL_MOSI_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="B14"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_MOSI_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="B14"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_MOSI_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="B14"/>
+      </pins>
+    </port>
+	<port dir="in" name="ACL_SCLK_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_SCLK_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_SCLK_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D15"/>
+      </pins>
+    </port>
+		<port dir="in" name="ACL_SS_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_SS_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_SS_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C15"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_mdc">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C9"/>
+      </pins>
+    </port>
+	<port dir="in" name="ETH_mdio_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="A9"/>
+      </pins>
+    </port>
+	<port dir="out" name="ETH_mdio_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="A9"/>
+      </pins>
+    </port>
+	<port dir="out" name="ETH_mdio_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="A9"/>
+      </pins>
+    </port>
+	<port dir="out" left="1" name="ETH_rmii_txd" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="A10"/>
+        <pin index="1" iostandard="LVCMOS33" loc="A8"/>
+      </pins>
+	</port>
+	<port dir="in" left="1" name="ETH_rmii_rxd" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="D10"/>
+        <pin index="1" iostandard="LVCMOS33" loc="C11"/>
+      </pins>
+	</port>
+	<port dir="out" name="ETH_rmii_tx_en">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="B9"/>
+      </pins>
+    </port>
+	<port dir="in" name="ETH_rmii_rx_er">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C10"/>
+      </pins>
+    </port>
+	<port dir="in" name="ETH_rmii_crs_dv">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D9"/>
+      </pins>
+    </port> 
+	
+	
+	
+	<port dir="inout" name="cellular_RAM_adv_ldn">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="T13"/>
+      </pins>
+    </port>
+	<port dir="inout" name="cellular_RAM_oen">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="H14"/>
+      </pins>
+    </port>
+	<port dir="inout" name="cellular_RAM_ce_n">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L18"/>
+      </pins>
+    </port>
+	<port dir="inout" name="cellular_RAM_wen">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R11"/>
+      </pins>
+    </port>
+	<port dir="inout" name="cellular_RAM_cre">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="J14"/>
+      </pins>
+    </port>
+	<port dir="inout" left="1" name="cellular_RAM_ben" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="J15"/>
+        <pin index="1" iostandard="LVCMOS33" loc="J13"/>
+      </pins>
+	  </port>
+	<port dir="inout" name="cellular_RAM_wait">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="T14"/>
+      </pins>
+    </port>
+<port dir="inout" left="22" name="cellular_RAM_addr" right="0"> 
+<pins> 
+<pin index="0" iostandard="LVCMOS33" loc="J18"/>
+<pin index="1" iostandard="LVCMOS33" loc="H17"/> 
+<pin index="2" iostandard="LVCMOS33" loc="H15"/> 
+<pin index="3" iostandard="LVCMOS33" loc="J17"/> 
+<pin index="4" iostandard="LVCMOS33" loc="H16"/> 
+<pin index="5" iostandard="LVCMOS33" loc="K15"/> 
+<pin index="6" iostandard="LVCMOS33" loc="K13"/> 
+<pin index="7" iostandard="LVCMOS33" loc="N15"/> 
+<pin index="8" iostandard="LVCMOS33" loc="V16"/> 
+<pin index="9" iostandard="LVCMOS33" loc="U14"/> 
+<pin index="10" iostandard="LVCMOS33" loc="V14"/> 
+<pin index="11" iostandard="LVCMOS33" loc="V12"/> 
+<pin index="12" iostandard="LVCMOS33" loc="P14"/> 
+<pin index="13" iostandard="LVCMOS33" loc="U16"/> 
+<pin index="14" iostandard="LVCMOS33" loc="R15"/> 
+<pin index="15" iostandard="LVCMOS33" loc="N14"/> 
+<pin index="16" iostandard="LVCMOS33" loc="N16"/> 
+<pin index="17" iostandard="LVCMOS33" loc="M13"/> 
+<pin index="18" iostandard="LVCMOS33" loc="V17"/> 
+<pin index="19" iostandard="LVCMOS33" loc="U17"/> 
+<pin index="20" iostandard="LVCMOS33" loc="T10"/> 
+<pin index="21" iostandard="LVCMOS33" loc="M16"/> 
+<pin index="22" iostandard="LVCMOS33" loc="U13"/>  
+</pins> 
+</port> 
+<port dir="in" left="15" name="cellular_RAM_dq_i" right="0"> 
+<pins> 
+<pin index="0" iostandard="LVCMOS33" loc="R12"/> 
+<pin index="1" iostandard="LVCMOS33" loc="T11"/> 
+<pin index="2" iostandard="LVCMOS33" loc="U12"/> 
+<pin index="3" iostandard="LVCMOS33" loc="R13"/> 
+<pin index="4" iostandard="LVCMOS33" loc="U18"/> 
+<pin index="5" iostandard="LVCMOS33" loc="R17"/> 
+<pin index="6" iostandard="LVCMOS33" loc="T18"/> 
+<pin index="7" iostandard="LVCMOS33" loc="R18"/> 
+<pin index="8" iostandard="LVCMOS33" loc="F18"/> 
+<pin index="9" iostandard="LVCMOS33" loc="G18"/> 
+<pin index="10" iostandard="LVCMOS33" loc="G17"/> 
+<pin index="11" iostandard="LVCMOS33" loc="M18"/> 
+<pin index="12" iostandard="LVCMOS33" loc="M17"/> 
+<pin index="13" iostandard="LVCMOS33" loc="P18"/> 
+<pin index="14" iostandard="LVCMOS33" loc="N17"/> 
+<pin index="15" iostandard="LVCMOS33" loc="P17"/> 
+</pins> 
+</port> 
+<port dir="out" left="15" name="cellular_RAM_dq_o" right="0"> 
+<pins> 
+<pin index="0" iostandard="LVCMOS33" loc="R12"/> 
+<pin index="1" iostandard="LVCMOS33" loc="T11"/> 
+<pin index="2" iostandard="LVCMOS33" loc="U12"/> 
+<pin index="3" iostandard="LVCMOS33" loc="R13"/> 
+<pin index="4" iostandard="LVCMOS33" loc="U18"/> 
+<pin index="5" iostandard="LVCMOS33" loc="R17"/> 
+<pin index="6" iostandard="LVCMOS33" loc="T18"/> 
+<pin index="7" iostandard="LVCMOS33" loc="R18"/> 
+<pin index="8" iostandard="LVCMOS33" loc="F18"/> 
+<pin index="9" iostandard="LVCMOS33" loc="G18"/> 
+<pin index="10" iostandard="LVCMOS33" loc="G17"/> 
+<pin index="11" iostandard="LVCMOS33" loc="M18"/> 
+<pin index="12" iostandard="LVCMOS33" loc="M17"/> 
+<pin index="13" iostandard="LVCMOS33" loc="P18"/> 
+<pin index="14" iostandard="LVCMOS33" loc="N17"/> 
+<pin index="15" iostandard="LVCMOS33" loc="P17"/> 
+</pins> 
+</port> 
+<port dir="out" left="15" name="cellular_RAM_dq_t" right="0"> 
+<pins> 
+<pin index="0" iostandard="LVCMOS33" loc="R12"/> 
+<pin index="1" iostandard="LVCMOS33" loc="T11"/> 
+<pin index="2" iostandard="LVCMOS33" loc="U12"/> 
+<pin index="3" iostandard="LVCMOS33" loc="R13"/> 
+<pin index="4" iostandard="LVCMOS33" loc="U18"/> 
+<pin index="5" iostandard="LVCMOS33" loc="R17"/> 
+<pin index="6" iostandard="LVCMOS33" loc="T18"/> 
+<pin index="7" iostandard="LVCMOS33" loc="R18"/> 
+<pin index="8" iostandard="LVCMOS33" loc="F18"/> 
+<pin index="9" iostandard="LVCMOS33" loc="G18"/> 
+<pin index="10" iostandard="LVCMOS33" loc="G17"/> 
+<pin index="11" iostandard="LVCMOS33" loc="M18"/> 
+<pin index="12" iostandard="LVCMOS33" loc="M17"/> 
+<pin index="13" iostandard="LVCMOS33" loc="P18"/> 
+<pin index="14" iostandard="LVCMOS33" loc="N17"/> 
+<pin index="15" iostandard="LVCMOS33" loc="P17"/> 
+</pins> 
+</port> 
+	
+	
+    <port dir="in" name="clk">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E3"/>
+      </pins>
+    </port>
+	
+	</ports>
+
+</board_part>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/board_part.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/board_part.xml
new file mode 100644
index 0000000..698b5bd
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/board_part.xml
@@ -0,0 +1,539 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Nexys4_DDR" board_revision="1.1" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+  <part_info part_name="xc7a100tcsg324-1" device="xc7a100t" family="artix7" jtag_position="1" package="csg324" silicon_version="1.0" speed_grade="1"/>
+
+  <board_info description="Nexys4 DDR" display_name="Nexys4 DDR" url="www.digilentinc.com/nexys4"/>
+
+  
+  <interfaces>
+   
+	<interface mode="master" name="DDR2_SDRAM" type="xilinx.com:interface:ddrx_rtl:1.0">
+      <preset_file name="mig.prj"/>
+    </interface>
+	
+    <interface mode="master" name="DIP_Switches_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="DIP_Switches_16Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface> 
+	
+    <interface mode="master" name="LED_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="LED_16Bits_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="RGB_LED" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="RGB_LED_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+
+	
+    <interface mode="master" name="Push_Buttons_5Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="Push_Buttons_5Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="DUAL_SEVEN_SEG_LED_DISP" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="DUAL_SEVEN_SEG_LED_DISP_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="master" name="SEVEN_SEG_LED_AN" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="SEVEN_SEG_LED_AN_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+        <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+     
+	 <port_maps>
+		
+        <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+        <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+        <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+        <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+        <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+		
+		<port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+        <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+        <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+		
+		<port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+        <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+        <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+		
+		<port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+        <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+        <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+		
+      </port_maps>
+	  
+	  </interface>
+	  
+	  
+	  <interface mode="master" name="TEMP_SENSOR" type="xilinx.com:interface:iic_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="SDA_I" physical_port="TEMP_SDA_i"/>
+        <port_map logical_port="SDA_O" physical_port="TEMP_SDA_o"/>
+        <port_map logical_port="SDA_T" physical_port="TEMP_SDA_t"/>
+        <port_map logical_port="SCL_I" physical_port="TEMP_SCL_i"/>
+        <port_map logical_port="SCL_O" physical_port="TEMP_SCL_o"/>
+        <port_map logical_port="SCL_T" physical_port="TEMP_SCL_t"/>
+      </port_maps>
+    </interface>
+	  
+	  
+	  <interface mode="master" name="ACL_SPI" type="xilinx.com:interface:spi_rtl:1.0">
+     
+	 <port_maps>
+	 
+		<port_map logical_port="IO0_I" physical_port="ACL_MISO_i"/>
+        <port_map logical_port="IO0_O" physical_port="ACL_MISO_o"/>
+        <port_map logical_port="IO0_T" physical_port="ACL_MISO_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="ACL_MOSI_i"/>
+        <port_map logical_port="IO1_O" physical_port="ACL_MOSI_o"/>
+        <port_map logical_port="IO1_T" physical_port="ACL_MOSI_t"/>
+		
+        <port_map logical_port="SCK_I" physical_port="ACL_SCLK_i"/>
+        <port_map logical_port="SCK_O" physical_port="ACL_SCLK_o"/>
+        <port_map logical_port="SCK_T" physical_port="ACL_SCLK_t"/>
+		
+		
+		<port_map logical_port="SS_I" physical_port="ACL_SS_i"/>
+        <port_map logical_port="SS_O" physical_port="ACL_SS_o"/>
+        <port_map logical_port="SS_T" physical_port="ACL_SS_t"/>
+		
+      </port_maps>
+
+    </interface>
+	
+	 <interface mode="master" name="ETH_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="MDIO_I" physical_port="ETH_mdio_i"/>
+        <port_map logical_port="MDIO_O" physical_port="ETH_mdio_o"/>
+        <port_map logical_port="MDIO_T" physical_port="ETH_mdio_t"/>
+        <port_map logical_port="MDC" physical_port="ETH_mdc"/>
+      </port_maps>
+    </interface>
+	
+	<interface mode="master" name="ETH_rmii" type="xilinx.com:interface:rmii_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="TXD" physical_port="ETH_rmii_txd"/>
+		<port_map logical_port="RXD" physical_port="ETH_rmii_rxd"/>		       
+	    <port_map logical_port="TX_EN" physical_port="ETH_rmii_tx_en"/>
+		<port_map logical_port="RX_ER" physical_port="ETH_rmii_rx_er"/>
+        <port_map logical_port="CRS_DV" physical_port="ETH_rmii_crs_dv"/>
+      </port_maps>
+	 </interface>
+	
+    <interface mode="slave" name="sys_clock" type="xilinx.com:interface:clock_rtl:1.0">
+     
+	 <port_maps>
+        <port_map logical_port="clk" physical_port="clk"/>
+      </port_maps>
+	  
+      <parameters>
+        <parameter name="frequency" value="100000000"/>
+      </parameters>
+	  
+	</interface>
+  
+    <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="RESET" physical_port="RESET"/>
+      </port_maps>
+      <parameters>
+        <parameter name="RST_POLARITY" value="0"/>
+      </parameters>
+    </interface>
+	
+	
+	
+	
+  </interfaces>
+
+  
+  <ports>
+    
+	<port name="DIP_Switches_16Bits_TRI_I" dir="in" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="J15"/>
+        <pin index="1" iostandard="LVCMOS33" loc="L16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="M13"/>
+        <pin index="3" iostandard="LVCMOS33" loc="R15"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R17"/>
+        <pin index="5" iostandard="LVCMOS33" loc="T18"/>
+        <pin index="6" iostandard="LVCMOS33" loc="U18"/>
+        <pin index="7" iostandard="LVCMOS33" loc="R13"/>
+        <pin index="8" iostandard="LVCMOS18" loc="T8"/>
+        <pin index="9" iostandard="LVCMOS18" loc="U8"/>
+        <pin index="10" iostandard="LVCMOS33" loc="R16"/>
+        <pin index="11" iostandard="LVCMOS33" loc="T13"/>
+        <pin index="12" iostandard="LVCMOS33" loc="H6"/>
+        <pin index="13" iostandard="LVCMOS33" loc="U12"/>
+        <pin index="14" iostandard="LVCMOS33" loc="U11"/>
+        <pin index="15" iostandard="LVCMOS33" loc="V10"/>
+      </pins>
+    </port>
+		
+    <port name="LED_16Bits_TRI_O" dir="out" left="15"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="H17"/>
+        <pin index="1" iostandard="LVCMOS33" loc="K15"/>
+        <pin index="2" iostandard="LVCMOS33" loc="J13"/>
+        <pin index="3" iostandard="LVCMOS33" loc="N14"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R18"/>
+        <pin index="5" iostandard="LVCMOS33" loc="V17"/>
+        <pin index="6" iostandard="LVCMOS33" loc="U17"/>
+        <pin index="7" iostandard="LVCMOS33" loc="U16"/>
+        <pin index="8" iostandard="LVCMOS33" loc="V16"/>
+        <pin index="9" iostandard="LVCMOS33" loc="T15"/>
+        <pin index="10" iostandard="LVCMOS33" loc="U14"/>
+        <pin index="11" iostandard="LVCMOS33" loc="T16"/>
+        <pin index="12" iostandard="LVCMOS33" loc="V15"/>
+        <pin index="13" iostandard="LVCMOS33" loc="V14"/>
+        <pin index="14" iostandard="LVCMOS33" loc="V12"/>
+        <pin index="15" iostandard="LVCMOS33" loc="V11"/>
+      </pins>
+    </port>
+	    
+	<port dir="out" left="5" name="RGB_LED_TRI_O" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="R12"/>
+        <pin index="1" iostandard="LVCMOS33" loc="M16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="N15"/>
+        <pin index="3" iostandard="LVCMOS33" loc="G14"/>
+        <pin index="4" iostandard="LVCMOS33" loc="R11"/>
+        <pin index="5" iostandard="LVCMOS33" loc="N16"/>
+      </pins>
+    </port>	
+		
+    <port name="Push_Buttons_5Bits_TRI_I" dir="in" left="4"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="N17"/>
+        <pin index="1" iostandard="LVCMOS33" loc="M18"/>
+        <pin index="2" iostandard="LVCMOS33" loc="P17"/>
+        <pin index="3" iostandard="LVCMOS33" loc="M17"/>
+        <pin index="4" iostandard="LVCMOS33" loc="P18"/>
+      </pins>
+    </port>
+
+	<port name="RESET" dir="in" >
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C12"/>
+      </pins>
+    </port>
+	
+
+   <port name="DUAL_SEVEN_SEG_LED_DISP_TRI_O" dir="out" left="7"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="T10"/>
+        <pin index="1" iostandard="LVCMOS33" loc="R10"/>
+        <pin index="2" iostandard="LVCMOS33" loc="K16"/>
+        <pin index="3" iostandard="LVCMOS33" loc="K13"/>
+		<pin index="4" iostandard="LVCMOS33" loc="P15"/>
+        <pin index="5" iostandard="LVCMOS33" loc="T11"/>
+        <pin index="6" iostandard="LVCMOS33" loc="L18"/>
+		<pin index="7" iostandard="LVCMOS33" loc="H15"/>
+      </pins>
+    </port>		
+	
+   <port name="SEVEN_SEG_LED_AN_TRI_O" dir="out" left="7"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="J17"/>
+        <pin index="1" iostandard="LVCMOS33" loc="J18"/>
+        <pin index="2" iostandard="LVCMOS33" loc="T9"/>
+        <pin index="3" iostandard="LVCMOS33" loc="J14"/>
+		<pin index="4" iostandard="LVCMOS33" loc="P14"/>
+        <pin index="5" iostandard="LVCMOS33" loc="T14"/>
+        <pin index="6" iostandard="LVCMOS33" loc="K2"/>
+		<pin index="7" iostandard="LVCMOS33" loc="U13"/>
+      </pins>
+    </port>	
+
+    <port dir="in" name="USB_Uart_RxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C4"/>
+      </pins>
+    </port>
+    <port dir="out" name="USB_Uart_TxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D4"/>
+      </pins>
+    </port>
+    
+	
+	
+    <port dir="in" name="Qspi_DB0_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K17"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB1_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="K18"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB2_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L14"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_DB3_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="M14"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="Qspi_CSn_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L13"/>
+      </pins>
+    </port>
+	
+	
+	
+	<port dir="in" name="TEMP_SDA_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C15"/>
+      </pins>
+    </port>
+    <port dir="out" name="TEMP_SDA_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C15"/>
+      </pins>
+    </port>
+    <port dir="out" name="TEMP_SDA_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C15"/>
+      </pins>
+    </port>
+	<port dir="in" name="TEMP_SCL_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C14"/>
+      </pins>
+    </port>
+    <port dir="out" name="TEMP_SCL_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C14"/>
+      </pins>
+    </port>
+    <port dir="out" name="TEMP_SCL_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C14"/>
+      </pins>
+    </port>
+	
+	
+	
+	<port dir="in" name="ACL_MISO_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_MISO_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_MISO_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E15"/>
+      </pins>
+    </port>
+	<port dir="in" name="ACL_MOSI_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F14"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_MOSI_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F14"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_MOSI_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F14"/>
+      </pins>
+    </port>
+	<port dir="in" name="ACL_SCLK_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_SCLK_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_SCLK_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="F15"/>
+      </pins>
+    </port>
+		<port dir="in" name="ACL_SS_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_SS_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D15"/>
+      </pins>
+    </port>
+    <port dir="out" name="ACL_SS_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D15"/>
+      </pins>
+    </port>
+	
+	
+	<port dir="out" name="ETH_mdc">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C9"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="ETH_mdio_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="A9"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_mdio_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="A9"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_mdio_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="A9"/>
+      </pins>
+    </port>
+	
+	<port dir="out" left="1" name="ETH_rmii_txd" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="A10"/>
+        <pin index="1" iostandard="LVCMOS33" loc="A8"/>
+      </pins>
+	</port>
+	
+	<port dir="in" left="1" name="ETH_rmii_rxd" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="C11"/>
+        <pin index="1" iostandard="LVCMOS33" loc="D10"/>
+      </pins>
+	</port>
+	
+	<port dir="out" name="ETH_rmii_tx_en">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="B9"/>
+      </pins>
+    </port>
+	
+	
+	<port dir="in" name="ETH_rmii_rx_er">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="C10"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="ETH_rmii_crs_dv">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="D9"/>
+      </pins>
+    </port> 
+	
+    <port dir="in" name="clk">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="E3"/>
+      </pins>
+    </port>
+	
+	</ports>
+
+</board_part>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/kintex7/genesys2/H/board_part.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/kintex7/genesys2/H/board_part.xml
new file mode 100644
index 0000000..79f38d2
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/kintex7/genesys2/H/board_part.xml
@@ -0,0 +1,766 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Genesys2" board_revision="H" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+  <part_info part_name="xc7k325tffg900-2" device="xc7k325t" family="kintex7" jtag_position="1" package="ffg900" silicon_version="1.0" speed_grade="-2"/>
+
+  <board_info description="Genesys2" display_name="Genesys2" url="www.digilentinc.com/genesys2"/>
+
+  
+  <interfaces>
+   
+	<interface mode="master" name="DDR3_SDRAM" type="xilinx.com:interface:ddrx_rtl:1.0">
+      <preset_file name="mig.prj"/>
+    </interface>
+	
+    <interface mode="master" name="DIP_Switches_8Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="DIP_Switches_8Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface> 
+	
+    <interface mode="master" name="LED_8Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="LED_8Bits_TRI_O"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="Push_Buttons_5Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_I" physical_port="Push_Buttons_5Bits_TRI_I"/>
+      </port_maps>
+	  
+    </interface>
+
+    <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+        <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+      </port_maps>
+	  
+    </interface>
+	
+    <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+     
+	 <port_maps>
+		
+        <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+        <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+        <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+        <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+        <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+		
+		<port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+        <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+        <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+		
+		<port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+        <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+        <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+		
+		<port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+        <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+        <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+		
+      </port_maps>
+	  
+	  </interface>
+	  
+	  
+	<interface mode="master" name="IIC_Bus" type="xilinx.com:interface:iic_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="SDA_I" physical_port="SDA_i"/>
+        <port_map logical_port="SDA_O" physical_port="SDA_o"/>
+        <port_map logical_port="SDA_T" physical_port="SDA_t"/>
+        <port_map logical_port="SCL_I" physical_port="SCL_i"/>
+        <port_map logical_port="SCL_O" physical_port="SCL_o"/>
+        <port_map logical_port="SCL_T" physical_port="SCL_t"/>
+      </port_maps>
+    </interface>
+	  
+	  
+	<interface mode="master" name="Audio_Codec_IIC" type="xilinx.com:interface:iic_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="SDA_I" physical_port="AUD_SDA_i"/>
+        <port_map logical_port="SDA_O" physical_port="AUD_SDA_o"/>
+        <port_map logical_port="SDA_T" physical_port="AUD_SDA_t"/>
+        <port_map logical_port="SCL_I" physical_port="AUD_SCL_i"/>
+        <port_map logical_port="SCL_O" physical_port="AUD_SCL_o"/>
+        <port_map logical_port="SCL_T" physical_port="AUD_SCL_t"/>
+      </port_maps>
+    </interface>
+	  
+	<interface mode="master" name="DSPI" type="xilinx.com:interface:spi_rtl:1.0">
+     
+	 <port_maps>
+	 
+		<port_map logical_port="IO0_I" physical_port="MISO_i"/>
+        <port_map logical_port="IO0_O" physical_port="MISO_o"/>
+        <port_map logical_port="IO0_T" physical_port="MISO_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="MOSI_i"/>
+        <port_map logical_port="IO1_O" physical_port="MOSI_o"/>
+        <port_map logical_port="IO1_T" physical_port="MOSI_t"/>
+		
+        <port_map logical_port="SCK_I" physical_port="SCLK_i"/>
+        <port_map logical_port="SCK_O" physical_port="SCLK_o"/>
+        <port_map logical_port="SCK_T" physical_port="SCLK_t"/>
+		
+		
+		<port_map logical_port="SS_I" physical_port="SS_i"/>
+        <port_map logical_port="SS_O" physical_port="SS_o"/>
+        <port_map logical_port="SS_T" physical_port="SS_t"/>
+		
+      </port_maps>
+
+    </interface>
+	
+	<interface mode="master" name="SD_SPI_MODE" type="xilinx.com:interface:spi_rtl:1.0">
+	 <port_maps>
+	 
+		<port_map logical_port="IO0_I" physical_port="SD_MISO_i"/>
+        <port_map logical_port="IO0_O" physical_port="SD_MISO_o"/>
+        <port_map logical_port="IO0_T" physical_port="SD_MISO_t"/>
+		
+        <port_map logical_port="IO1_I" physical_port="SD_MOSI_i"/>
+        <port_map logical_port="IO1_O" physical_port="SD_MOSI_o"/>
+        <port_map logical_port="IO1_T" physical_port="SD_MOSI_t"/>
+		
+        <port_map logical_port="SCK_I" physical_port="SD_SCLK_i"/>
+        <port_map logical_port="SCK_O" physical_port="SD_SCLK_o"/>
+        <port_map logical_port="SCK_T" physical_port="SD_SCLK_t"/>
+		
+		
+		<port_map logical_port="SS_I" physical_port="SD_SS_i"/>
+        <port_map logical_port="SS_O" physical_port="SD_SS_o"/>
+        <port_map logical_port="SS_T" physical_port="SD_SS_t"/>
+		
+      </port_maps>
+    </interface>
+	
+	<interface mode="master" name="ETH_mdio_io" type="xilinx.com:interface:mdio_io:1.0">
+      <port_maps>
+        <port_map logical_port="IO" physical_port="ETH_io"/>
+        <port_map logical_port="MDC" physical_port="ETH_mdc1"/>
+      </port_maps>
+    </interface>
+	
+	<interface mode="master" name="ETH_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="MDIO_I" physical_port="ETH_mdio_i"/>
+        <port_map logical_port="MDIO_O" physical_port="ETH_mdio_o"/>
+        <port_map logical_port="MDIO_T" physical_port="ETH_mdio_t"/>
+        <port_map logical_port="MDC" physical_port="ETH_mdc"/>
+      </port_maps>
+    </interface>
+  
+	<interface mode="master" name="ETH_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="TD" physical_port="ETH_rgmii_td"/>
+		<port_map logical_port="RD" physical_port="ETH_rgmii_rd"/>
+		<port_map logical_port="RX_CTL" physical_port="ETH_rgmii_rx_ctl"/>
+	    <port_map logical_port="TX_CTL" physical_port="ETH_rgmii_tx_ctl"/>
+		<port_map logical_port="TXC" physical_port="ETH_rgmii_txc"/>
+        <port_map logical_port="RXC" physical_port="ETH_rgmii_rxc"/>
+      </port_maps>
+	 </interface>
+	
+    <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="RESET" physical_port="RESET"/>
+      </port_maps>
+      <parameters>
+        <parameter name="RST_POLARITY" value="0"/>
+      </parameters>
+    </interface>
+	
+	<interface mode="master" name="Displayport_in_HPD_led" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="dp_rx_hpd"/>
+      </port_maps>
+	  
+    </interface>
+	<interface mode="master" name="Displayport_out_HPD_led" type="xilinx.com:interface:gpio_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="TRI_O" physical_port="dp_tx_hpd"/>
+      </port_maps>
+	  
+    </interface>
+	<interface mode="master" name="Displayport_out" type="xilinx.com:interface:dp_aux_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="AUX_TX_CHANNEL_OUT_P" physical_port="dp_tx_out_p"/>
+		<port_map logical_port="AUX_TX_CHANNEL_OUT_N" physical_port="dp_tx_out_n"/>
+		<port_map logical_port="AUX_TX_CHANNEL_IN_P" physical_port="dp_tx_in_p"/>
+		<port_map logical_port="AUX_TX_CHANNEL_IN_N" physical_port="dp_tx_in_n"/>
+      </port_maps>
+	  
+    </interface>
+	
+	<interface mode="slave" name="Displayport_in" type="xilinx.com:interface:dp_aux_rtl:1.0">
+      
+	  <port_maps>
+        <port_map logical_port="AUX_TX_CHANNEL_OUT_P" physical_port="dp_rx_out_p"/>
+		<port_map logical_port="AUX_TX_CHANNEL_OUT_N" physical_port="dp_rx_out_n"/>
+		<port_map logical_port="AUX_TX_CHANNEL_IN_P" physical_port="dp_rx_in_p"/>
+		<port_map logical_port="AUX_TX_CHANNEL_IN_N" physical_port="dp_rx_in_n"/>
+      </port_maps>
+	  
+    </interface>
+	
+
+	<interface mode="master" name="USB_OTG_master" type="xilinx.com:interface:ulpi_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="CLK" physical_port="otg_clk_m"/>
+        <port_map logical_port="RST" physical_port="otg_rst_m"/>
+		<port_map logical_port="DIR" physical_port="otg_dir_m"/>
+		<port_map logical_port="NEXT" physical_port="otg_next_m"/>
+		<port_map logical_port="STOP" physical_port="otg_stop_m"/>
+		<port_map logical_port="DATA_I" physical_port="otg_data_i"/>
+		<port_map logical_port="DATA_O" physical_port="otg_data_o"/>
+		<port_map logical_port="DATA_T" physical_port="otg_data_t"/>
+      </port_maps>
+    </interface>
+	
+
+	
+  </interfaces>
+
+  
+  <ports>
+    
+	<port name="DIP_Switches_8Bits_TRI_I" dir="in" left="7"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS12" loc="G19"/>
+        <pin index="1" iostandard="LVCMOS12" loc="G25"/>
+        <pin index="2" iostandard="LVCMOS12" loc="H24"/>
+        <pin index="3" iostandard="LVCMOS12" loc="K19"/>
+        <pin index="4" iostandard="LVCMOS12" loc="N19"/>
+        <pin index="5" iostandard="LVCMOS12" loc="P19"/>
+        <pin index="6" iostandard="LVCMOS33" loc="P26"/>
+        <pin index="7" iostandard="LVCMOS33" loc="P27"/>
+      </pins>
+    </port>
+		
+    <port name="LED_8Bits_TRI_O" dir="out" left="7"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="T28"/>
+        <pin index="1" iostandard="LVCMOS33" loc="V19"/>
+        <pin index="2" iostandard="LVCMOS33" loc="U30"/>
+        <pin index="3" iostandard="LVCMOS33" loc="U29"/>
+        <pin index="4" iostandard="LVCMOS33" loc="V20"/>
+        <pin index="5" iostandard="LVCMOS33" loc="V26"/>
+        <pin index="6" iostandard="LVCMOS33" loc="W24"/>
+        <pin index="7" iostandard="LVCMOS33" loc="W23"/>
+      </pins>
+    </port>
+		
+    <port name="Push_Buttons_5Bits_TRI_I" dir="in" left="4"  right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS12" loc="E18"/>
+        <pin index="1" iostandard="LVCMOS12" loc="B19"/>
+        <pin index="2" iostandard="LVCMOS12" loc="M20"/>
+        <pin index="3" iostandard="LVCMOS12" loc="C19"/>
+        <pin index="4" iostandard="LVCMOS12" loc="M19"/>
+      </pins>
+    </port>
+
+	<port name="RESET" dir="in" >
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R19"/>
+      </pins>
+    </port>
+
+    <port dir="in" name="USB_Uart_RxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="Y20"/>
+      </pins>
+    </port>
+    <port dir="out" name="USB_Uart_TxD">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="Y23"/>
+      </pins>
+    </port>
+    
+	
+	
+    <port dir="in" name="Qspi_DB0_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="P24"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="P24"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB0_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="P24"/>
+      </pins>
+    </port>
+	<port dir="in" name="Qspi_DB1_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R25"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R25"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB1_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R25"/>
+      </pins>
+    </port>
+	<port dir="in" name="Qspi_DB2_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R20"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R20"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB2_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R20"/>
+      </pins>
+    </port>
+	<port dir="in" name="Qspi_DB3_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R21"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R21"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_DB3_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R21"/>
+      </pins>
+    </port>
+	<port dir="in" name="Qspi_CSn_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="U19"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="U19"/>
+      </pins>
+    </port>
+    <port dir="out" name="Qspi_CSn_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="U19"/>
+      </pins>
+    </port>
+	
+	
+	
+	<port dir="in" name="SDA_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AF30"/>
+      </pins>
+    </port>
+    <port dir="out" name="SDA_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AF30"/>
+      </pins>
+    </port>
+    <port dir="out" name="SDA_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AF30"/>
+      </pins>
+    </port>
+	<port dir="in" name="SCL_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AE30"/>
+      </pins>
+    </port>
+    <port dir="out" name="SCL_o">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AE30"/>
+      </pins>
+    </port>
+    <port dir="out" name="SCL_t">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AE30"/>
+      </pins>
+    </port>
+	
+	
+	
+	<port dir="in" name="AUD_SDA_i">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AF18"/>
+      </pins>
+    </port>
+    <port dir="out" name="AUD_SDA_o">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AF18"/>
+      </pins>
+    </port>
+    <port dir="out" name="AUD_SDA_t">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AF18"/>
+      </pins>
+    </port>
+	<port dir="in" name="AUD_SCL_i">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AE19"/>
+      </pins>
+    </port>
+    <port dir="out" name="AUD_SCL_o">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AE19"/>
+      </pins>
+    </port>
+    <port dir="out" name="AUD_SCL_t">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AE19"/>
+      </pins>
+    </port>	
+	
+	
+	<port dir="in" name="MISO_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W28"/>
+      </pins>
+    </port>
+    <port dir="out" name="MISO_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W28"/>
+      </pins>
+    </port>
+    <port dir="out" name="MISO_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W28"/>
+      </pins>
+    </port>
+	<port dir="in" name="MOSI_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W27"/>
+      </pins>
+    </port>
+    <port dir="out" name="MOSI_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W27"/>
+      </pins>
+    </port>
+    <port dir="out" name="MOSI_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W27"/>
+      </pins>
+    </port>
+	<port dir="in" name="SCLK_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AD27"/>
+      </pins>
+    </port>
+    <port dir="out" name="SCLK_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AD27"/>
+      </pins>
+    </port>
+    <port dir="out" name="SCLK_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AD27"/>
+      </pins>
+    </port>
+		<port dir="in" name="SS_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W29"/>
+      </pins>
+    </port>
+    <port dir="out" name="SS_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W29"/>
+      </pins>
+    </port>
+    <port dir="out" name="SS_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="W29"/>
+      </pins>
+    </port>
+	
+	
+	
+	<port dir="in" name="SD_MISO_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R26"/>
+      </pins>
+    </port>
+    <port dir="out" name="SD_MISO_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R26"/>
+      </pins>
+    </port>
+    <port dir="out" name="SD_MISO_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R26"/>
+      </pins>
+    </port>
+	<port dir="in" name="SD_MOSI_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R29"/>
+      </pins>
+    </port>
+    <port dir="out" name="SD_MOSI_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R29"/>
+      </pins>
+    </port>
+    <port dir="out" name="SD_MOSI_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R29"/>
+      </pins>
+    </port>
+	<port dir="in" name="SD_SCLK_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R28"/>
+      </pins>
+    </port>
+    <port dir="out" name="SD_SCLK_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R28"/>
+      </pins>
+    </port>
+    <port dir="out" name="SD_SCLK_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="R28"/>
+      </pins>
+    </port>
+		<port dir="in" name="SD_SS_i">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="T30"/>
+      </pins>
+    </port>
+    <port dir="out" name="SD_SS_o">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="T30"/>
+      </pins>
+    </port>
+    <port dir="out" name="SD_SS_t">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="T30"/>
+      </pins>
+    </port>
+	
+	<port dir="inout" name="ETH_io">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AG12"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_mdc1">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AF12"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_mdc">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AF12"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="ETH_mdio_i">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AG12"/>
+      </pins>
+    </port>
+	<port dir="out" name="ETH_mdio_o">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AG12"/>
+      </pins>
+    </port>
+	<port dir="out" name="ETH_mdio_t">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AG12"/>
+      </pins>
+    </port>
+	
+	<port dir="out" left="3" name="ETH_rgmii_td" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS15" loc="AJ12"/>
+        <pin index="1" iostandard="LVCMOS15" loc="AK11"/>
+		<pin index="2" iostandard="LVCMOS15" loc="AJ11"/>
+        <pin index="3" iostandard="LVCMOS15" loc="AK10"/>
+      </pins>
+	</port>
+	
+	<port dir="in" left="3" name="ETH_rgmii_rd" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS15" loc="AJ14"/>
+        <pin index="1" iostandard="LVCMOS15" loc="AH14"/>
+		<pin index="2" iostandard="LVCMOS15" loc="AK13"/>
+        <pin index="3" iostandard="LVCMOS15" loc="AJ13"/>
+      </pins>
+	</port>
+	
+	<port dir="in" name="ETH_rgmii_rx_ctl">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AH11"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_rgmii_tx_ctl">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AK14"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="ETH_rgmii_txc">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AE10"/>
+      </pins>
+    </port>
+	
+	<port dir="in" name="ETH_rgmii_rxc">
+      <pins>
+        <pin iostandard="LVCMOS15" loc="AG10"/>
+      </pins>
+    </port>
+	
+    <port dir="in" name="clk_p">
+      <pins>
+        <pin iostandard="TMDS_33" loc="AD12"/>
+      </pins>
+    </port>
+	<port dir="in" name="clk_n">
+      <pins>
+        <pin iostandard="TMDS_33" loc="AD11"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="dp_tx_hpd">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AD21"/>
+      </pins>
+    </port>
+	<port dir="out" name="dp_tx_out_p">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AA18"/>
+      </pins>
+    </port>
+	<port dir="out" name="dp_tx_out_n">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AB18"/>
+      </pins>
+    </port>
+	<port dir="in" name="dp_tx_in_p">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AD17"/>
+      </pins>
+    </port>
+	<port dir="in" name="dp_tx_in_n">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AD16"/>
+      </pins>
+    </port>
+	
+	<port dir="out" name="dp_rx_hpd">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="AE21"/>
+      </pins>
+    </port>
+	<port dir="in" name="dp_rx_out_p">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="Y19"/>
+      </pins>
+    </port>
+	<port dir="in" name="dp_rx_out_n">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="Y18"/>
+      </pins>
+    </port>
+	<port dir="out" name="dp_rx_in_p">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AB19"/>
+      </pins>
+    </port>
+	<port dir="out" name="dp_rx_in_n">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AC19"/>
+      </pins>
+    </port>
+
+	
+	<port dir="out" name="otg_clk_m">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AD18"/>
+      </pins>
+    </port>
+	<port dir="in" name="otg_rst_m">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AB14"/>
+      </pins>
+    </port>
+
+	<port dir="out" name="otg_dir_m">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="Y16"/>
+      </pins>
+    </port>
+
+	<port dir="out" name="otg_next_m">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AA16"/>
+      </pins>
+    </port>
+
+	<port dir="in" name="otg_stop_m">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AA17"/>
+      </pins>
+    </port>
+
+	<port dir="in" left="7" name="otg_data_i" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS18" loc="AE14"/>
+        <pin index="1" iostandard="LVCMOS18" loc="AE15"/>
+		<pin index="2" iostandard="LVCMOS18" loc="AC15"/>
+        <pin index="3" iostandard="LVCMOS18" loc="AC16"/>
+		<pin index="4" iostandard="LVCMOS18" loc="AB15"/>
+        <pin index="5" iostandard="LVCMOS18" loc="AA15"/>
+		<pin index="6" iostandard="LVCMOS18" loc="AD14"/>
+        <pin index="7" iostandard="LVCMOS18" loc="AC14"/>
+      </pins>
+	</port>
+	<port dir="out" left="7" name="otg_data_o" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS18" loc="AE14"/>
+        <pin index="1" iostandard="LVCMOS18" loc="AE15"/>
+		<pin index="2" iostandard="LVCMOS18" loc="AC15"/>
+        <pin index="3" iostandard="LVCMOS18" loc="AC16"/>
+		<pin index="4" iostandard="LVCMOS18" loc="AB15"/>
+        <pin index="5" iostandard="LVCMOS18" loc="AA15"/>
+		<pin index="6" iostandard="LVCMOS18" loc="AD14"/>
+        <pin index="7" iostandard="LVCMOS18" loc="AC14"/>
+      </pins>
+	</port>
+	<port dir="out" name="otg_data_t">
+      <pins>
+        <pin iostandard="LVCMOS18" loc="AE14"/>
+      </pins>
+	</port>
+
+	
+	</ports>
+
+</board_part>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/zynq/zybo/1.0/board_part.xml b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/zynq/zybo/1.0/board_part.xml
new file mode 100644
index 0000000..1419a2d
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/zynq/zybo/1.0/board_part.xml
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<board_part board_name="zybo" board_revision="b" board_part="part0" schema_version="1.0" vendor="digilentinc.com" version="1.0">
+
+  <part_info part_name="xc7z010clg400-1" jtag_position="1" silicon_version="1.0" />
+
+  <board_info description="Zybo" display_name="Zybo" url="http://www.digilentinc.com"/>
+
+  <interfaces>
+    <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i"/>
+      </port_maps>
+    </interface>
+    <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o"/>
+      </port_maps>
+    </interface>
+    <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0">
+      <preset_file name="ps7.tcl"/>
+    </interface>
+    <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i"/>
+      </port_maps>
+    </interface>
+    <interface mode="slave" name="sys_clock" type="xilinx.com:interface:clock_rtl:1.0">
+      <port_maps>
+        <port_map logical_port="CLK" physical_port="sys_clk"/>
+      </port_maps>
+      <parameters>
+        <parameter name="frequency" value="125000000"/>
+      </parameters>
+    </interface>
+  </interfaces>
+
+  <ports>
+    <port dir="in" left="3" name="btns_4bits_tri_i" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="R18"/>
+        <pin index="1" iostandard="LVCMOS33" loc="P16"/>
+        <pin index="2" iostandard="LVCMOS33" loc="V16"/>
+        <pin index="3" iostandard="LVCMOS33" loc="Y16"/>
+      </pins>
+    </port>
+    <port dir="out" left="3" name="leds_4bits_tri_o" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="M14"/>
+        <pin index="1" iostandard="LVCMOS33" loc="M15"/>
+        <pin index="2" iostandard="LVCMOS33" loc="G14"/>
+        <pin index="3" iostandard="LVCMOS33" loc="D18"/>
+      </pins>
+    </port>
+    <port dir="in" left="3" name="sws_4bits_tri_i" right="0">
+      <pins>
+        <pin index="0" iostandard="LVCMOS33" loc="G15"/>
+        <pin index="1" iostandard="LVCMOS33" loc="P15"/>
+        <pin index="2" iostandard="LVCMOS33" loc="W13"/>
+        <pin index="3" iostandard="LVCMOS33" loc="T16"/>
+      </pins>
+    </port>
+    <port dir="in" name="sys_clk">
+      <pins>
+        <pin iostandard="LVCMOS33" loc="L16"/>
+      </pins>
+    </port>
+  </ports>
+
+</board_part>
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/zynq/zybo/1.0/ps7.tcl b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/zynq/zybo/1.0/ps7.tcl
new file mode 100644
index 0000000..4527e79
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/old/board_parts/zynq/zybo/1.0/ps7.tcl
@@ -0,0 +1,4 @@
+proc apply_ps7_board_setting { ps7_ip } {
+	  set_property -dict [ list CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50.000000} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET0_RESET_ENABLE {0} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} CONFIG.PCW_MIO_0_PULLUP {enabled} CONFIG.PCW_MIO_10_PULLUP {enabled} CONFIG.PCW_MIO_11_PULLUP {enabled} CONFIG.PCW_MIO_12_PULLUP {enabled} CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_16_PULLUP {disabled} CONFIG.PCW_MIO_16_SLEW {fast} CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_17_PULLUP {disabled} CONFIG.PCW_MIO_17_SLEW {fast} CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_18_PULLUP {disabled} CONFIG.PCW_MIO_18_SLEW {fast} CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_19_PULLUP {disabled} CONFIG.PCW_MIO_19_SLEW {fast} CONFIG.PCW_MIO_1_PULLUP {disabled} CONFIG.PCW_MIO_1_SLEW {fast} CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_20_PULLUP {disabled} CONFIG.PCW_MIO_20_SLEW {fast} CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_21_PULLUP {disabled} CONFIG.PCW_MIO_21_SLEW {fast} CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_22_PULLUP {disabled} CONFIG.PCW_MIO_22_SLEW {fast} CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_23_PULLUP {disabled} CONFIG.PCW_MIO_23_SLEW {fast} CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_24_PULLUP {disabled} CONFIG.PCW_MIO_24_SLEW {fast} CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_25_PULLUP {disabled} CONFIG.PCW_MIO_25_SLEW {fast} CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_26_PULLUP {disabled} CONFIG.PCW_MIO_26_SLEW {fast} CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_27_PULLUP {disabled} CONFIG.PCW_MIO_27_SLEW {fast} CONFIG.PCW_MIO_28_PULLUP {disabled} CONFIG.PCW_MIO_28_SLEW {fast} CONFIG.PCW_MIO_29_PULLUP {disabled} CONFIG.PCW_MIO_29_SLEW {fast} CONFIG.PCW_MIO_2_SLEW {fast} CONFIG.PCW_MIO_30_PULLUP {disabled} CONFIG.PCW_MIO_30_SLEW {fast} CONFIG.PCW_MIO_31_PULLUP {disabled} CONFIG.PCW_MIO_31_SLEW {fast} CONFIG.PCW_MIO_32_PULLUP {disabled} CONFIG.PCW_MIO_32_SLEW {fast} CONFIG.PCW_MIO_33_PULLUP {disabled} CONFIG.PCW_MIO_33_SLEW {fast} CONFIG.PCW_MIO_34_PULLUP {disabled} CONFIG.PCW_MIO_34_SLEW {fast} CONFIG.PCW_MIO_35_PULLUP {disabled} CONFIG.PCW_MIO_35_SLEW {fast} CONFIG.PCW_MIO_36_PULLUP {disabled} CONFIG.PCW_MIO_36_SLEW {fast} CONFIG.PCW_MIO_37_PULLUP {disabled} CONFIG.PCW_MIO_37_SLEW {fast} CONFIG.PCW_MIO_38_PULLUP {disabled} CONFIG.PCW_MIO_38_SLEW {fast} CONFIG.PCW_MIO_39_PULLUP {disabled} CONFIG.PCW_MIO_39_SLEW {fast} CONFIG.PCW_MIO_3_SLEW {fast} CONFIG.PCW_MIO_40_PULLUP {disabled} CONFIG.PCW_MIO_40_SLEW {fast} CONFIG.PCW_MIO_41_PULLUP {disabled} CONFIG.PCW_MIO_41_SLEW {fast} CONFIG.PCW_MIO_42_PULLUP {disabled} CONFIG.PCW_MIO_42_SLEW {fast} CONFIG.PCW_MIO_43_PULLUP {disabled} CONFIG.PCW_MIO_43_SLEW {fast} CONFIG.PCW_MIO_44_PULLUP {disabled} CONFIG.PCW_MIO_44_SLEW {fast} CONFIG.PCW_MIO_45_PULLUP {disabled} CONFIG.PCW_MIO_45_SLEW {fast} CONFIG.PCW_MIO_47_PULLUP {disabled} CONFIG.PCW_MIO_48_PULLUP {disabled} CONFIG.PCW_MIO_49_PULLUP {disabled} CONFIG.PCW_MIO_4_SLEW {fast} CONFIG.PCW_MIO_50_DIRECTION {inout} CONFIG.PCW_MIO_50_PULLUP {disabled} CONFIG.PCW_MIO_51_DIRECTION {inout} CONFIG.PCW_MIO_51_PULLUP {disabled} CONFIG.PCW_MIO_52_PULLUP {disabled} CONFIG.PCW_MIO_52_SLEW {slow} CONFIG.PCW_MIO_53_PULLUP {disabled} CONFIG.PCW_MIO_53_SLEW {slow} CONFIG.PCW_MIO_5_SLEW {fast} CONFIG.PCW_MIO_6_SLEW {fast} CONFIG.PCW_MIO_8_SLEW {fast} CONFIG.PCW_MIO_9_PULLUP {enabled} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} CONFIG.PCW_SD0_GRP_WP_ENABLE {1} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.176} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.159} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.162} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.187} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.073} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.034} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.03} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.082} CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB0_RESET_ENABLE {1} CONFIG.PCW_USB0_RESET_IO {MIO 46}  ] [get_bd_cells $ps7_ip]
+}
+
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/utility/Vivado_init.tcl b/Bibliotheken/vivado-boards-master/vivado-boards-master/utility/Vivado_init.tcl
new file mode 100644
index 0000000..50ca892
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/utility/Vivado_init.tcl
@@ -0,0 +1 @@
+set_param board.repoPaths [list "<extracted path>/vivado-boards/new/board_files"]
diff --git a/Bibliotheken/vivado-boards-master/vivado-boards-master/utility/init.tcl b/Bibliotheken/vivado-boards-master/vivado-boards-master/utility/init.tcl
new file mode 100644
index 0000000..50ca892
--- /dev/null
+++ b/Bibliotheken/vivado-boards-master/vivado-boards-master/utility/init.tcl
@@ -0,0 +1 @@
+set_param board.repoPaths [list "<extracted path>/vivado-boards/new/board_files"]
diff --git a/Coraz7_Test/Coraz7_Test.cache/sim/ssm.db b/Coraz7_Test/Coraz7_Test.cache/sim/ssm.db
new file mode 100644
index 0000000..7cec227
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.cache/sim/ssm.db
@@ -0,0 +1,10 @@
+################################################################################
+#                            DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Mar 16 19:55:41 2022)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+#                            DONOT REMOVE THIS FILE
+################################################################################
diff --git a/Coraz7_Test/Coraz7_Test.cache/wt/project.wpc b/Coraz7_Test/Coraz7_Test.cache/wt/project.wpc
new file mode 100644
index 0000000..a27ee4c
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.cache/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+57656254616c6b5472616e736d697373696f6e417474656d70746564:12
+6d6f64655f636f756e7465727c4755494d6f6465:6
+eof:
diff --git a/Coraz7_Test/Coraz7_Test.cache/wt/synthesis.wdf b/Coraz7_Test/Coraz7_Test.cache/wt/synthesis.wdf
new file mode 100644
index 0000000..740a3f2
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.cache/wt/synthesis.wdf
@@ -0,0 +1,44 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303130636c673430302d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:70776d5f74657374:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
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diff --git a/Coraz7_Test/Coraz7_Test.cache/wt/synthesis_details.wdf b/Coraz7_Test/Coraz7_Test.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000..78f8d66
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
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diff --git a/Coraz7_Test/Coraz7_Test.cache/wt/webtalk_pa.xml b/Coraz7_Test/Coraz7_Test.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000..d837656
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Fri Mar 25 10:11:13 2022">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="dccfc252ab414e90be4483ade2e76042" type="ProjectID"/>
+<property name="ProjectIteration" value="22" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/Coraz7_Test/Coraz7_Test.cache/wt/xsim.wdf b/Coraz7_Test/Coraz7_Test.cache/wt/xsim.wdf
new file mode 100644
index 0000000..50afb2c
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
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diff --git a/Coraz7_Test/Coraz7_Test.hw/Coraz7_Test.lpr b/Coraz7_Test/Coraz7_Test.hw/Coraz7_Test.lpr
new file mode 100644
index 0000000..9280233
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.hw/Coraz7_Test.lpr
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0">
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/Coraz7_Test/Coraz7_Test.hw/hw_1/hw.xml b/Coraz7_Test/Coraz7_Test.hw/hw_1/hw.xml
new file mode 100644
index 0000000..64982ec
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.hw/hw_1/hw.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.        -->
+
+<hwsession version="1" minor="2">
+  <device name="xc7z010_1" gui_info=""/>
+  <ObjectList object_type="hw_device" gui_info="">
+    <Object name="xc7z010_1" gui_info="">
+      <Properties Property="FULL_PROBES.FILE" value=""/>
+      <Properties Property="PROBES.FILE" value=""/>
+      <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/pwm_test.bit"/>
+      <Properties Property="SLR.COUNT" value="1"/>
+    </Object>
+  </ObjectList>
+  <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/Coraz7_Test/Coraz7_Test.ip_user_files/README.txt b/Coraz7_Test/Coraz7_Test.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_1.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_10.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_10.xml
new file mode 100644
index 0000000..1ad25b8
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_10.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_11.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_11.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_11.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_12.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_12.xml
new file mode 100644
index 0000000..7d87bda
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_12.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_13.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_13.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_13.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_14.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_14.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_14.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_15.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_15.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_15.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_16.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_16.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_16.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_17.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_17.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_17.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_18.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_18.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_18.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_19.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_19.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_19.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_2.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_20.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_20.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_20.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_21.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_21.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_21.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_22.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_22.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_22.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_23.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_23.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_23.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_24.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_24.xml
new file mode 100644
index 0000000..516336f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_24.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_25.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_25.xml
new file mode 100644
index 0000000..7d87bda
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_25.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_26.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_26.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_26.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_27.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_27.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_27.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_28.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_28.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_28.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_29.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_29.xml
new file mode 100644
index 0000000..e7e8c6f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_29.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_3.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_3.xml
new file mode 100644
index 0000000..822b88f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_30.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_30.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_30.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_31.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_31.xml
new file mode 100644
index 0000000..1ad25b8
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_31.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_4.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_4.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_4.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_5.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_5.xml
new file mode 100644
index 0000000..822b88f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_5.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_6.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_6.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_6.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_7.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_7.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_7.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_8.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_8.xml
new file mode 100644
index 0000000..334a93f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_8.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_9.xml b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_9.xml
new file mode 100644
index 0000000..822b88f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/.jobs/vrs_config_9.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.Vivado_Implementation.queue.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.init_design.begin.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000..5ea62b0
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="10536">
+    </Process>
+</ProcessHandle>
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.init_design.end.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.opt_design.begin.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000..5ea62b0
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="10536">
+    </Process>
+</ProcessHandle>
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.opt_design.end.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.phys_opt_design.begin.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.phys_opt_design.begin.rst
new file mode 100644
index 0000000..5ea62b0
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/.phys_opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="10536">
+    </Process>
+</ProcessHandle>
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.phys_opt_design.end.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.phys_opt_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.place_design.begin.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000..5ea62b0
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="10536">
+    </Process>
+</ProcessHandle>
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.place_design.end.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.route_design.begin.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000..5ea62b0
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="10536">
+    </Process>
+</ProcessHandle>
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.route_design.end.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.vivado.begin.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000..934b7e4
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="13036" HostCore="12" HostMemory="016927088640">
+    </Process>
+</ProcessHandle>
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.vivado.end.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.write_bitstream.begin.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000..5ea62b0
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="10536">
+    </Process>
+</ProcessHandle>
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/.write_bitstream.end.rst b/Coraz7_Test/Coraz7_Test.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/ISEWrap.js b/Coraz7_Test/Coraz7_Test.runs/impl_1/ISEWrap.js
new file mode 100644
index 0000000..db0a510
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/ISEWrap.js
@@ -0,0 +1,269 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\" HostCore=\"" + ISEHOSTCORE +
+			    "\" HostMemory=\"" + ISEMEMTOTAL +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/ISEWrap.sh b/Coraz7_Test/Coraz7_Test.runs/impl_1/ISEWrap.sh
new file mode 100644
index 0000000..c2fbbb6
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,84 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+cmd_exists()
+{
+  command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/gen_run.xml b/Coraz7_Test/Coraz7_Test.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000..b808293
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/gen_run.xml
@@ -0,0 +1,132 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7z010clg400-1" LaunchTime="1648199473">
+  <File Type="OPT-HWDEF" Name="pwm_test.hwdef"/>
+  <File Type="ROUTE-BUS-SKEW" Name="pwm_test_bus_skew_routed.rpt"/>
+  <File Type="PA-DCP" Name="pwm_test.dcp"/>
+  <File Type="ROUTE-PWR" Name="pwm_test_power_routed.rpt"/>
+  <File Type="PA-TCL" Name="pwm_test.tcl"/>
+  <File Type="BITSTR-MMI" Name="pwm_test.mmi"/>
+  <File Type="OPT-METHODOLOGY-DRC" Name="pwm_test_methodology_drc_opted.rpt"/>
+  <File Type="INIT-TIMING" Name="pwm_test_timing_summary_init.rpt"/>
+  <File Type="ROUTE-PWR-SUM" Name="pwm_test_power_summary_routed.pb"/>
+  <File Type="REPORTS-TCL" Name="pwm_test_reports.tcl"/>
+  <File Type="OPT-TIMING" Name="pwm_test_timing_summary_opted.rpt"/>
+  <File Type="OPT-DCP" Name="pwm_test_opt.dcp"/>
+  <File Type="OPT-DRC" Name="pwm_test_drc_opted.rpt"/>
+  <File Type="PWROPT-DCP" Name="pwm_test_pwropt.dcp"/>
+  <File Type="PWROPT-DRC" Name="pwm_test_drc_pwropted.rpt"/>
+  <File Type="PWROPT-TIMING" Name="pwm_test_timing_summary_pwropted.rpt"/>
+  <File Type="PLACE-DCP" Name="pwm_test_placed.dcp"/>
+  <File Type="PLACE-IO" Name="pwm_test_io_placed.rpt"/>
+  <File Type="PLACE-CLK" Name="pwm_test_clock_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL" Name="pwm_test_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL-PB" Name="pwm_test_utilization_placed.pb"/>
+  <File Type="PLACE-CTRL" Name="pwm_test_control_sets_placed.rpt"/>
+  <File Type="PLACE-SIMILARITY" Name="pwm_test_incremental_reuse_placed.rpt"/>
+  <File Type="PLACE-PRE-SIMILARITY" Name="pwm_test_incremental_reuse_pre_placed.rpt"/>
+  <File Type="BG-BIN" Name="pwm_test.bin"/>
+  <File Type="PLACE-TIMING" Name="pwm_test_timing_summary_placed.rpt"/>
+  <File Type="POSTPLACE-PWROPT-DCP" Name="pwm_test_postplace_pwropt.dcp"/>
+  <File Type="BITSTR-MSK" Name="pwm_test.msk"/>
+  <File Type="POSTPLACE-PWROPT-TIMING" Name="pwm_test_timing_summary_postplace_pwropted.rpt"/>
+  <File Type="PHYSOPT-DCP" Name="pwm_test_physopt.dcp"/>
+  <File Type="PHYSOPT-DRC" Name="pwm_test_drc_physopted.rpt"/>
+  <File Type="BITSTR-RBT" Name="pwm_test.rbt"/>
+  <File Type="PHYSOPT-TIMING" Name="pwm_test_timing_summary_physopted.rpt"/>
+  <File Type="ROUTE-ERROR-DCP" Name="pwm_test_routed_error.dcp"/>
+  <File Type="ROUTE-DCP" Name="pwm_test_routed.dcp"/>
+  <File Type="ROUTE-BLACKBOX-DCP" Name="pwm_test_routed_bb.dcp"/>
+  <File Type="ROUTE-DRC" Name="pwm_test_drc_routed.rpt"/>
+  <File Type="ROUTE-DRC-PB" Name="pwm_test_drc_routed.pb"/>
+  <File Type="ROUTE-DRC-RPX" Name="pwm_test_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="pwm_test_methodology_drc_routed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="pwm_test_methodology_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="pwm_test_methodology_drc_routed.pb"/>
+  <File Type="ROUTE-PWR-RPX" Name="pwm_test_power_routed.rpx"/>
+  <File Type="ROUTE-STATUS" Name="pwm_test_route_status.rpt"/>
+  <File Type="ROUTE-STATUS-PB" Name="pwm_test_route_status.pb"/>
+  <File Type="ROUTE-TIMINGSUMMARY" Name="pwm_test_timing_summary_routed.rpt"/>
+  <File Type="ROUTE-TIMING-PB" Name="pwm_test_timing_summary_routed.pb"/>
+  <File Type="ROUTE-TIMING-RPX" Name="pwm_test_timing_summary_routed.rpx"/>
+  <File Type="ROUTE-SIMILARITY" Name="pwm_test_incremental_reuse_routed.rpt"/>
+  <File Type="ROUTE-CLK" Name="pwm_test_clock_utilization_routed.rpt"/>
+  <File Type="ROUTE-BUS-SKEW-PB" Name="pwm_test_bus_skew_routed.pb"/>
+  <File Type="ROUTE-BUS-SKEW-RPX" Name="pwm_test_bus_skew_routed.rpx"/>
+  <File Type="POSTROUTE-PHYSOPT-DCP" Name="pwm_test_postroute_physopt.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="pwm_test_postroute_physopt_bb.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="pwm_test_timing_summary_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="pwm_test_timing_summary_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="pwm_test_timing_summary_postroute_physopted.rpx"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="pwm_test_bus_skew_postroute_physopted.rpt"/>
+  <File Type="BG-BIT" Name="pwm_test.bit"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="pwm_test_bus_skew_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="pwm_test_bus_skew_postroute_physopted.rpx"/>
+  <File Type="BITSTR-NKY" Name="pwm_test.nky"/>
+  <File Type="BITSTR-BMM" Name="pwm_test_bd.bmm"/>
+  <File Type="PDI-FILE" Name="pwm_test.pdi"/>
+  <File Type="RCFI_FILE" Name="pwm_test.rcfi"/>
+  <File Type="CFI_FILE" Name="pwm_test.cfi"/>
+  <File Type="RNPI_FILE" Name="pwm_test.rnpi"/>
+  <File Type="NPI_FILE" Name="pwm_test.npi"/>
+  <File Type="RBD_FILE" Name="pwm_test.rbd"/>
+  <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+  <File Type="BITSTR-LTX" Name="pwm_test.ltx"/>
+  <File Type="BITSTR-SYSDEF" Name="pwm_test.sysdef"/>
+  <File Type="BG-BGN" Name="pwm_test.bgn"/>
+  <File Type="BG-DRC" Name="pwm_test.drc"/>
+  <File Type="RDI-RDI" Name="pwm_test.vdi"/>
+  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/new/pwm_test.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="pwm_test"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc"/>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+    <Filter Type="Utils"/>
+    <File Path="$PSRCDIR/utils_1/imports/synth_1/pwm_test.dcp">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedInSteps" Val="synth_1"/>
+        <Attr Name="AutoDcp" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
+    <Step Id="init_design"/>
+    <Step Id="opt_design"/>
+    <Step Id="power_opt_design"/>
+    <Step Id="place_design"/>
+    <Step Id="post_place_power_opt_design"/>
+    <Step Id="phys_opt_design"/>
+    <Step Id="route_design"/>
+    <Step Id="post_route_phys_opt_design"/>
+    <Step Id="write_bitstream"/>
+  </Strategy>
+</GenRun>
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/htr.txt b/Coraz7_Test/Coraz7_Test.runs/impl_1/htr.txt
new file mode 100644
index 0000000..2e25dfb
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/htr.txt
@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log pwm_test.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/init_design.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/init_design.pb
new file mode 100644
index 0000000..3acd651
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/init_design.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/opt_design.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000..ea724c3
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/opt_design.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/phys_opt_design.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/phys_opt_design.pb
new file mode 100644
index 0000000..4930a64
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/phys_opt_design.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/place_design.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/place_design.pb
new file mode 100644
index 0000000..75d7183
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/place_design.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/project.wdf b/Coraz7_Test/Coraz7_Test.runs/impl_1/project.wdf
new file mode 100644
index 0000000..f9dc52a
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/project.wdf
@@ -0,0 +1,67 @@
+version:1
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp
new file mode 100644
index 0000000..ff44fba
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.tcl b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.tcl
new file mode 100644
index 0000000..54448b7
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.tcl
@@ -0,0 +1,311 @@
+# 
+# Report generation script generated by Vivado
+# 
+
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+namespace eval ::optrace {
+  variable script "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.tcl"
+  variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+proc start_step { step } {
+  set stopFile ".stop.rst"
+  if {[file isfile .stop.rst]} {
+    puts ""
+    puts "*** Halting run - EA reset detected ***"
+    puts ""
+    puts ""
+    return -code error
+  }
+  set beginFile ".$step.begin.rst"
+  set platform "$::tcl_platform(platform)"
+  set user "$::tcl_platform(user)"
+  set pid [pid]
+  set host ""
+  if { [string equal $platform unix] } {
+    if { [info exist ::env(HOSTNAME)] } {
+      set host $::env(HOSTNAME)
+    } elseif { [info exist ::env(HOST)] } {
+      set host $::env(HOST)
+    }
+  } else {
+    if { [info exist ::env(COMPUTERNAME)] } {
+      set host $::env(COMPUTERNAME)
+    }
+  }
+  set ch [open $beginFile w]
+  puts $ch "<?xml version=\"1.0\"?>"
+  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+  puts $ch "    </Process>"
+  puts $ch "</ProcessHandle>"
+  close $ch
+}
+
+proc end_step { step } {
+  set endFile ".$step.end.rst"
+  set ch [open $endFile w]
+  close $ch
+}
+
+proc step_failed { step } {
+  set endFile ".$step.error.rst"
+  set ch [open $endFile w]
+  close $ch
+OPTRACE "impl_1" END { }
+}
+
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+  create_msg_db init_design.pb
+  set_param chipscope.maxJobs 3
+  reset_param project.defaultXPMLibraries 
+  open_checkpoint C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp
+  set_property webtalk.parent_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.cache/wt [current_project]
+  set_property parent.project_path C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr [current_project]
+  set_property ip_output_repo C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.cache/ip [current_project]
+  set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+  close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+  step_failed init_design
+  return -code error $RESULT
+} else {
+  end_step init_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+  create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+  opt_design 
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force pwm_test_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+OPTRACE "opt_design reports" START { REPORT }
+  create_report "impl_1_opt_report_drc_0" "report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx"
+OPTRACE "opt_design reports" END { }
+  close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+  step_failed opt_design
+  return -code error $RESULT
+} else {
+  end_step opt_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+  create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+  if { [llength [get_debug_cores -quiet] ] > 0 }  { 
+OPTRACE "implement_debug_core" START { }
+    implement_debug_core 
+OPTRACE "implement_debug_core" END { }
+  } 
+OPTRACE "place_design" START { }
+  place_design 
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force pwm_test_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+OPTRACE "place_design reports" START { REPORT }
+  create_report "impl_1_place_report_io_0" "report_io -file pwm_test_io_placed.rpt"
+  create_report "impl_1_place_report_utilization_0" "report_utilization -file pwm_test_utilization_placed.rpt -pb pwm_test_utilization_placed.pb"
+  create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file pwm_test_control_sets_placed.rpt"
+OPTRACE "place_design reports" END { }
+  close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+  step_failed place_design
+  return -code error $RESULT
+} else {
+  end_step place_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
+start_step phys_opt_design
+set ACTIVE_STEP phys_opt_design
+set rc [catch {
+  create_msg_db phys_opt_design.pb
+OPTRACE "read constraints: phys_opt_design" START { }
+OPTRACE "read constraints: phys_opt_design" END { }
+OPTRACE "phys_opt_design" START { }
+  phys_opt_design 
+OPTRACE "phys_opt_design" END { }
+OPTRACE "read constraints: phys_opt_design_post" START { }
+OPTRACE "read constraints: phys_opt_design_post" END { }
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force pwm_test_physopt.dcp
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
+OPTRACE "phys_opt_design report" START { REPORT }
+OPTRACE "phys_opt_design report" END { }
+  close_msg_db -file phys_opt_design.pb
+} RESULT]
+if {$rc} {
+  step_failed phys_opt_design
+  return -code error $RESULT
+} else {
+  end_step phys_opt_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Physical Opt Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+  create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+  route_design 
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force pwm_test_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design reports" START { REPORT }
+  create_report "impl_1_route_report_drc_0" "report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx"
+  create_report "impl_1_route_report_methodology_0" "report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx"
+  create_report "impl_1_route_report_power_0" "report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx"
+  create_report "impl_1_route_report_route_status_0" "report_route_status -file pwm_test_route_status.rpt -pb pwm_test_route_status.pb"
+  create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file pwm_test_timing_summary_routed.rpt -pb pwm_test_timing_summary_routed.pb -rpx pwm_test_timing_summary_routed.rpx -warn_on_violation "
+  create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file pwm_test_incremental_reuse_routed.rpt"
+  create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file pwm_test_clock_utilization_routed.rpt"
+  create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file pwm_test_bus_skew_routed.rpt -pb pwm_test_bus_skew_routed.pb -rpx pwm_test_bus_skew_routed.rpx"
+OPTRACE "route_design reports" END { }
+OPTRACE "route_design misc" START { }
+  close_msg_db -file route_design.pb
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+} RESULT]
+if {$rc} {
+  write_checkpoint -force pwm_test_routed_error.dcp
+  step_failed route_design
+  return -code error $RESULT
+} else {
+  end_step route_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+  create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+  catch { write_mem_info -force -no_partial_mmi pwm_test.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+  write_bitstream -force pwm_test.bit 
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+  catch {write_debug_probes -quiet -force pwm_test}
+  catch {file copy -force pwm_test.ltx debug_nets.ltx}
+  close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+  step_failed write_bitstream
+  return -code error $RESULT
+} else {
+  end_step write_bitstream
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.vdi b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.vdi
new file mode 100644
index 0000000..c5ed85a
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.vdi
@@ -0,0 +1,556 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri Mar 25 10:11:21 2022
+# Process ID: 10536
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1
+# Command line: vivado.exe -log pwm_test.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source pwm_test.tcl -notrace
+Command: open_checkpoint C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp
+
+Starting open_checkpoint Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1262.352 ; gain = 1.801
+CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:zybo-z7-10:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
+CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:zybo-z7-10:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1266.320 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Timing 38-478] Restoring timing data from binary archive.
+INFO: [Timing 38-479] Binary timing data restore complete.
+INFO: [Project 1-856] Restoring constraints from binary archive.
+INFO: [Project 1-853] Binary constraint restore complete.
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1357.309 ; gain = 0.000
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1357.309 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1357.309 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Project 1-604] Checkpoint was created with Vivado v2021.2 (64-bit) build 3367213
+open_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1357.309 ; gain = 104.965
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1365.902 ; gain = 8.594
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 1c056137f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1441.777 ; gain = 75.875
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 1c056137f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 1c056137f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 1fbd34c49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 1fbd34c49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 1fbd34c49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 1fbd34c49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1726.871 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: 20c3576ce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1726.871 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 20c3576ce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1726.871 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 20c3576ce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: 20c3576ce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+28 Infos, 0 Warnings, 2 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1726.871 ; gain = 369.562
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
+Command: report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 13ba8a4a3
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bc17a400
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.161 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.164 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.170 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.179 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 2.4 Global Placement Core
+WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
+Phase 2.4 Global Placement Core | Checksum: 12ed945d9
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.657 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 12ed945d9
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.661 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 12ed945d9
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.664 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.677 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.683 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.685 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.720 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.725 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.726 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.727 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+Phase 4.1 Post Commit Optimization | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.745 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.750 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Ending Placer Task | Checksum: deb5d7c7
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1766.074 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+47 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1766.074 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file pwm_test_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1766.074 ; gain = 0.000
+INFO: [runtcl-4] Executing : report_utilization -file pwm_test_utilization_placed.rpt -pb pwm_test_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file pwm_test_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+55 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1766.074 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 584981bf ConstDB: 0 ShapeSum: 866c5608 RouteDB: 0
+Post Restoration Checksum: NetGraph: 32e9d585 NumContArr: cff0ca0e Constraints: 0 Timing: 0
+Phase 1 Build RT Design | Checksum: 102da9f93
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1799.160 ; gain = 26.402
+
+Phase 2 Router Initialization
+INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 102da9f93
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1805.191 ; gain = 32.434
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 102da9f93
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1805.191 ; gain = 32.434
+ Number of Nodes with overlaps = 0
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 48
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 48
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: a88dbed9
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: a88dbed9
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
+Phase 3 Initial Routing | Checksum: 105c3e9d5
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 0
+Phase 4.1 Global Iteration 0 | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+Phase 4 Rip-up And Reroute | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 5 Delay and Skew Optimization
+Phase 5 Delay and Skew Optimization | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+Phase 6.1 Hold Fix Iter | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+Phase 6 Post Hold Fix | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0115428 %
+  Global Horizontal Routing Utilization  = 0.0284926 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Congestion Report
+North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 6.30631%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
+
+------------------------------
+Reporting congestion hotspots
+------------------------------
+Direction: North
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: South
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: East
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: West
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+
+Phase 7 Route finalize | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 8d29afef
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+65 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 44.613
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1820.504 ; gain = 9.816
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
+Command: report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
+Command: report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
+Command: report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
+Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+77 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file pwm_test_route_status.rpt -pb pwm_test_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file pwm_test_timing_summary_routed.rpt -pb pwm_test_timing_summary_routed.pb -rpx pwm_test_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+INFO: [runtcl-4] Executing : report_incremental_reuse -file pwm_test_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file pwm_test_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pwm_test_bus_skew_routed.rpt -pb pwm_test_bus_skew_routed.pb -rpx pwm_test_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+Command: write_bitstream -force pwm_test.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./pwm_test.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
+INFO: [Common 17-83] Releasing license: Implementation
+12 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 2293.621 ; gain = 439.371
+INFO: [Common 17-206] Exiting Vivado at Fri Mar 25 10:12:18 2022...
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.pb
new file mode 100644
index 0000000..3390588
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.rpt
new file mode 100644
index 0000000..d119fc7
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.rpt
@@ -0,0 +1,15 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:12:09 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_bus_skew -warn_on_violation -file pwm_test_bus_skew_routed.rpt -pb pwm_test_bus_skew_routed.pb -rpx pwm_test_bus_skew_routed.rpx
+| Design       : pwm_test
+| Device       : 7z010-clg400
+| Speed File   : -1  PRODUCTION 1.12 2019-11-22
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.rpx b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.rpx
new file mode 100644
index 0000000..a3b84e1
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_bus_skew_routed.rpx differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_clock_utilization_routed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_clock_utilization_routed.rpt
new file mode 100644
index 0000000..9fd77ef
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_clock_utilization_routed.rpt
@@ -0,0 +1,142 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:12:09 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_clock_utilization -file pwm_test_clock_utilization_routed.rpt
+| Design       : pwm_test
+| Device       : 7z010-clg400
+| Speed File   : -1  PRODUCTION 1.12 2019-11-22
+| Design State : Routed
+--------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Device Cell Placement Summary for Global Clock g0
+7. Clock Region Cell Placement per Global Clock: Region X1Y1
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type     | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL |    1 |        32 |   0 |            0 |      0 |
+| BUFH     |    0 |        48 |   0 |            0 |      0 |
+| BUFIO    |    0 |         8 |   0 |            0 |      0 |
+| BUFMR    |    0 |         4 |   0 |            0 |      0 |
+| BUFR     |    0 |         8 |   0 |            0 |      0 |
+| MMCM     |    0 |         2 |   0 |            0 |      0 |
+| PLL      |    0 |         2 |   0 |            0 |      0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site           | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin           | Net           |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
+| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y16 | n/a          |                 1 |          32 |               0 |              |       | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site      | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin      | Net      |
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+| src0      | g0        | IBUF/O          | IOB_X0Y74  | IOB_X0Y74 | X1Y1         |           1 |               0 |                     |              | clk_IBUF_inst/O | clk_IBUF |
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |  1100 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1100 |    0 |   350 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X0Y1              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |  1100 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   32 |  1100 |   32 |   350 |    0 |    40 |    0 |    20 |    0 |    20 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+|    | X0 | X1 |
++----+----+----+
+| Y1 |  0 |  1 |
+| Y0 |  0 |  0 |
++----+----+----+
+
+
+6. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net           |
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+| g0        | BUFG/O          | n/a               |       |             |               |          32 |        0 |              0 |        0 | clk_IBUF_BUFG |
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+-----+-----------------------+
+|    | X0 | X1  | HORIZONTAL PROG DELAY |
++----+----+-----+-----------------------+
+| Y1 |  0 |  32 |                     0 |
+| Y0 |  0 |   0 |                     - |
++----+----+-----+-----------------------+
+
+
+7. Clock Region Cell Placement per Global Clock: Region X1Y1
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net           |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+| g0        | n/a   | BUFG/O          | None       |          32 |               0 | 32 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_IBUF_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives 
+set_property LOC BUFGCTRL_X0Y16 [get_cells clk_IBUF_BUFG_inst]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+set_property LOC IOB_X0Y74 [get_ports clk]
+
+# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16"
+#startgroup
+create_pblock {CLKAG_clk_IBUF_BUFG}
+add_cells_to_pblock [get_pblocks  {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
+#endgroup
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_control_sets_placed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_control_sets_placed.rpt
new file mode 100644
index 0000000..1e36823
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_control_sets_placed.rpt
@@ -0,0 +1,80 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:11:52 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_control_sets -verbose -file pwm_test_control_sets_placed.rpt
+| Design       : pwm_test
+| Device       : xc7z010
+-------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+|                          Status                          | Count |
++----------------------------------------------------------+-------+
+| Total control sets                                       |     2 |
+|    Minimum number of control sets                        |     2 |
+|    Addition due to synthesis replication                 |     0 |
+|    Addition due to physical synthesis replication        |     0 |
+| Unused register locations in slices containing registers |     7 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+|       Fanout       | Count |
++--------------------+-------+
+| Total control sets |     2 |
+| >= 0 to < 4        |     1 |
+| >= 4 to < 6        |     0 |
+| >= 6 to < 8        |     0 |
+| >= 8 to < 10       |     0 |
+| >= 10 to < 12      |     0 |
+| >= 12 to < 14      |     0 |
+| >= 14 to < 16      |     0 |
+| >= 16              |     1 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No           | No                    | No                     |               0 |            0 |
+| No           | No                    | Yes                    |              32 |            8 |
+| No           | Yes                   | No                     |               1 |            1 |
+| Yes          | No                    | No                     |               0 |            0 |
+| Yes          | No                    | Yes                    |               0 |            0 |
+| Yes          | Yes                   | No                     |               0 |            0 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++------------------+---------------+------------------+------------------+----------------+--------------+
+|   Clock Signal   | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++------------------+---------------+------------------+------------------+----------------+--------------+
+|  led_reg_i_1_n_0 |               | led_reg_i_2_n_0  |                1 |              1 |         1.00 |
+|  clk_IBUF_BUFG   |               | led_reg_i_2_n_0  |                8 |             32 |         4.00 |
++------------------+---------------+------------------+------------------+----------------+--------------+
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.pb
new file mode 100644
index 0000000..70698d1
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpt
new file mode 100644
index 0000000..7ec445b
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpt
@@ -0,0 +1,41 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:11:50 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
+| Design       : pwm_test
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: checkpoint_pwm_test
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 1
++--------+----------+--------------------+------------+
+| Rule   | Severity | Description        | Violations |
++--------+----------+--------------------+------------+
+| ZPS7-1 | Warning  | PS7 block required | 1          |
++--------+----------+--------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+ZPS7-1#1 Warning
+PS7 block required  
+The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+Related violations: <none>
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpx b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpx
new file mode 100644
index 0000000..3fef762
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpx differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.pb
new file mode 100644
index 0000000..70698d1
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpt
new file mode 100644
index 0000000..29b7f98
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpt
@@ -0,0 +1,41 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:12:07 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
+| Design       : pwm_test
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Fully Routed
+------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: checkpoint_pwm_test
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 1
++--------+----------+--------------------+------------+
+| Rule   | Severity | Description        | Violations |
++--------+----------+--------------------+------------+
+| ZPS7-1 | Warning  | PS7 block required | 1          |
++--------+----------+--------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+ZPS7-1#1 Warning
+PS7 block required  
+The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+Related violations: <none>
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpx b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpx
new file mode 100644
index 0000000..ba66bab
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpx differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_io_placed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_io_placed.rpt
new file mode 100644
index 0000000..fb38ff1
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_io_placed.rpt
@@ -0,0 +1,442 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------
+| Tool Version              : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date                      : Fri Mar 25 10:11:52 2022
+| Host                      : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command                   : report_io -file pwm_test_io_placed.rpt
+| Design                    : pwm_test
+| Device                    : xc7z010
+| Speed File                : -1
+| Package                   : clg400
+| Package Version           : FINAL 2012-10-23
+| Package Pin Delay Version : VERS. 2.0 2012-10-23
+-------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+|             2 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type  | Pin Name                | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1         |             |            | PS_DDR_DM0_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A2         |             |            | PS_DDR_DQ2_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A3         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| A4         |             |            | PS_DDR_DQ3_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A5         |             |            | PS_MIO6_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A6         |             |            | PS_MIO5_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A7         |             |            | PS_MIO1_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A9         |             |            | PS_MIO43_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A10        |             |            | PS_MIO37_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A11        |             |            | PS_MIO36_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A12        |             |            | PS_MIO34_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A13        |             |            | VCCO_MIO1_501           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| A14        |             |            | PS_MIO32_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A15        |             |            | PS_MIO26_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A16        |             |            | PS_MIO24_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A17        |             |            | PS_MIO20_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A18        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A19        |             |            | PS_MIO16_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A20        |             | High Range | IO_L2N_T0_AD8N_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B1         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B2         |             |            | PS_DDR_DQS_N0_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B3         |             |            | PS_DDR_DQ1_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B4         |             |            | PS_DDR_DRST_B_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B5         |             |            | PS_MIO9_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B6         |             |            | VCCO_MIO0_500           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| B7         |             |            | PS_MIO4_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B8         |             |            | PS_MIO2_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B9         |             |            | PS_MIO51_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B10        |             |            | PS_SRST_B_501           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B12        |             |            | PS_MIO48_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B13        |             |            | PS_MIO50_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B14        |             |            | PS_MIO47_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B15        |             |            | PS_MIO45_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B16        |             |            | VCCO_MIO1_501           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| B17        |             |            | PS_MIO22_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B18        |             |            | PS_MIO18_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B19        |             | High Range | IO_L2P_T0_AD8P_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B20        |             | High Range | IO_L1N_T0_AD0N_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C1         |             |            | PS_DDR_DQ6_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C2         |             |            | PS_DDR_DQS_P0_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C3         |             |            | PS_DDR_DQ0_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C4         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C5         |             |            | PS_MIO14_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C6         |             |            | PS_MIO11_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C7         |             |            | PS_POR_B_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C8         |             |            | PS_MIO15_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C9         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C10        |             |            | PS_MIO52_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C11        |             |            | PS_MIO53_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C12        |             |            | PS_MIO49_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C13        |             |            | PS_MIO29_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C14        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C15        |             |            | PS_MIO30_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C16        |             |            | PS_MIO28_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C17        |             |            | PS_MIO41_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C18        |             |            | PS_MIO39_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C19        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| C20        |             | High Range | IO_L1P_T0_AD0P_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D1         |             |            | PS_DDR_DQ5_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D2         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| D3         |             |            | PS_DDR_DQ4_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D4         |             |            | PS_DDR_A13_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D5         |             |            | PS_MIO8_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D6         |             |            | PS_MIO3_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D7         |             |            | VCCO_MIO0_500           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| D8         |             |            | PS_MIO7_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D9         |             |            | PS_MIO12_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D10        |             |            | PS_MIO19_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D11        |             |            | PS_MIO23_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D12        |             |            | VCCO_MIO1_501           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| D13        |             |            | PS_MIO27_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D14        |             |            | PS_MIO40_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D15        |             |            | PS_MIO33_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D16        |             |            | PS_MIO46_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D17        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D18        |             | High Range | IO_L3N_T0_DQS_AD1N_35   | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D19        |             | High Range | IO_L4P_T0_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D20        |             | High Range | IO_L4N_T0_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E1         |             |            | PS_DDR_DQ7_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E2         |             |            | PS_DDR_DQ8_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E3         |             |            | PS_DDR_DQ9_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E4         |             |            | PS_DDR_A12_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E5         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| E6         |             |            | PS_MIO0_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E7         |             |            | PS_CLK_500              | PSS Clock     |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E8         |             |            | PS_MIO13_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E9         |             |            | PS_MIO10_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E10        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E11        |             |            | PS_MIO_VREF_501         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E12        |             |            | PS_MIO42_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E13        |             |            | PS_MIO38_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E14        |             |            | PS_MIO17_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E15        |             |            | VCCO_MIO1_501           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| E16        |             |            | PS_MIO31_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E17        |             | High Range | IO_L3P_T0_DQS_AD1P_35   | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E18        |             | High Range | IO_L5P_T0_AD9P_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E19        |             | High Range | IO_L5N_T0_AD9N_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E20        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F1         |             |            | PS_DDR_DM1_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F2         |             |            | PS_DDR_DQS_N1_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F3         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F4         |             |            | PS_DDR_A14_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F5         |             |            | PS_DDR_A10_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F6         |             | Dedicated  | TDO_0                   | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F8         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F9         |             | Dedicated  | TCK_0                   | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F10        |             |            | RSVDGND                 | GND           |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F11        |             | Dedicated  | VCCBATT_0               | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F12        |             |            | PS_MIO35_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F13        |             |            | PS_MIO44_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F14        |             |            | PS_MIO21_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F15        |             |            | PS_MIO25_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F16        |             | High Range | IO_L6P_T0_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F17        |             | High Range | IO_L6N_T0_VREF_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F18        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| F19        |             | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F20        |             | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G1         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| G2         |             |            | PS_DDR_DQS_P1_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G3         |             |            | PS_DDR_DQ10_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G4         |             |            | PS_DDR_A11_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G5         |             |            | PS_DDR_VRN_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G6         |             | Dedicated  | TDI_0                   | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G8         |             |            | VCCPLL                  | PSS VCCPLL    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G9         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G10        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G11        |             |            | VCCBRAM                 | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G14        | led         | High Range | IO_0_35                 | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| G15        |             | High Range | IO_L19N_T3_VREF_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G16        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G17        |             | High Range | IO_L16P_T2_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G18        |             | High Range | IO_L16N_T2_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G19        |             | High Range | IO_L18P_T2_AD13P_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G20        |             | High Range | IO_L18N_T2_AD13N_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H1         |             |            | PS_DDR_DQ14_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H2         |             |            | PS_DDR_DQ13_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H3         |             |            | PS_DDR_DQ11_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H4         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| H5         |             |            | PS_DDR_VRP_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H6         |             |            | PS_DDR_VREF0_502        | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H8         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H9         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H10        |             |            | VCCBRAM                 | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H12        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H14        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| H15        |             | High Range | IO_L19P_T3_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H16        | clk         | High Range | IO_L13P_T2_MRCC_35      | INPUT         | LVCMOS33    |      35 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| H17        |             | High Range | IO_L13N_T2_MRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H18        |             | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H19        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H20        |             | High Range | IO_L17N_T2_AD5N_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J1         |             |            | PS_DDR_DQ15_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J2         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J3         |             |            | PS_DDR_DQ12_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J4         |             |            | PS_DDR_A9_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J5         |             |            | PS_DDR_BA2_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J6         |             | Dedicated  | TMS_0                   | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J9         |             | Dedicated  | VCCADC_0                | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J10        |             | Dedicated  | GNDADC_0                | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J11        |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| J12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J14        |             | High Range | IO_L20N_T3_AD6N_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J15        |             | High Range | IO_25_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J16        |             | High Range | IO_L24N_T3_AD15N_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J17        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| J18        |             | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J19        |             | High Range | IO_L10N_T1_AD11N_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J20        |             | High Range | IO_L17P_T2_AD5P_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K1         |             |            | PS_DDR_A8_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K2         |             |            | PS_DDR_A1_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K3         |             |            | PS_DDR_A3_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K4         |             |            | PS_DDR_A7_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K5         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K6         |             | Dedicated  | VCCO_0                  | VCCO          |             |       0 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| K7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K8         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K9         |             | Dedicated  | VP_0                    | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K10        |             | Dedicated  | VREFN_0                 | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K12        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K14        |             | High Range | IO_L20P_T3_AD6P_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K15        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K16        |             | High Range | IO_L24P_T3_AD15P_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K17        |             | High Range | IO_L12P_T1_MRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K18        |             | High Range | IO_L12N_T1_MRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K19        |             | High Range | IO_L10P_T1_AD11P_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K20        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| L1         |             |            | PS_DDR_A5_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L2         |             |            | PS_DDR_CKP_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L3         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| L4         |             |            | PS_DDR_A6_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L5         |             |            | PS_DDR_BA0_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L6         |             | Dedicated  | PROGRAM_B_0             | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L9         |             | Dedicated  | VREFP_0                 | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L10        |             | Dedicated  | VN_0                    | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L11        |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| L12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L14        |             | High Range | IO_L22P_T3_AD7P_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L15        |             | High Range | IO_L22N_T3_AD7N_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L16        |             | High Range | IO_L11P_T1_SRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L17        |             | High Range | IO_L11N_T1_SRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L18        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L19        |             | High Range | IO_L9P_T1_DQS_AD3P_35   | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L20        |             | High Range | IO_L9N_T1_DQS_AD3N_35   | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M1         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M2         |             |            | PS_DDR_CKN_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M3         |             |            | PS_DDR_A2_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M4         |             |            | PS_DDR_A4_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M5         |             |            | PS_DDR_WE_B_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M6         |             | Dedicated  | CFGBVS_0                | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M8         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M9         |             | Dedicated  | DXP_0                   | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M10        |             | Dedicated  | DXN_0                   | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M12        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M14        |             | High Range | IO_L23P_T3_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M15        |             | High Range | IO_L23N_T3_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M16        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| M17        |             | High Range | IO_L8P_T1_AD10P_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M18        |             | High Range | IO_L8N_T1_AD10N_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M19        |             | High Range | IO_L7P_T1_AD2P_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M20        |             | High Range | IO_L7N_T1_AD2N_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N1         |             |            | PS_DDR_CS_B_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N2         |             |            | PS_DDR_A0_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N3         |             |            | PS_DDR_CKE_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N4         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N5         |             |            | PS_DDR_ODT_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N6         |             |            | RSVDVCC3                | Reserved      |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N9         |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| N10        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N11        |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| N12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N14        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N15        |             | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N16        |             | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N17        |             | High Range | IO_L23P_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N18        |             | High Range | IO_L13P_T2_MRCC_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N19        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| N20        |             | High Range | IO_L14P_T2_SRCC_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P1         |             |            | PS_DDR_DQ16_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P2         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| P3         |             |            | PS_DDR_DQ17_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P4         |             |            | PS_DDR_RAS_B_502        | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P5         |             |            | PS_DDR_CAS_B_502        | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P6         |             |            | PS_DDR_VREF1_502        | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P8         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P9         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P10        |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| P11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P12        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P14        |             | High Range | IO_L6P_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P15        |             | High Range | IO_L24P_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P16        |             | High Range | IO_L24N_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P17        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P18        |             | High Range | IO_L23N_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P19        |             | High Range | IO_L13N_T2_MRCC_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P20        |             | High Range | IO_L14N_T2_SRCC_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R1         |             |            | PS_DDR_DQ19_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R2         |             |            | PS_DDR_DQS_P2_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R3         |             |            | PS_DDR_DQ18_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R4         |             |            | PS_DDR_BA1_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R5         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| R6         |             |            | RSVDVCC2                | Reserved      |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| R9         |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| R10        |             | Dedicated  | INIT_B_0                | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R11        |             | Dedicated  | DONE_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| R13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R14        |             | High Range | IO_L6N_T0_VREF_34       | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R15        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| R16        |             | High Range | IO_L19P_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R17        |             | High Range | IO_L19N_T3_VREF_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R18        |             | High Range | IO_L20N_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R19        |             | High Range | IO_0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R20        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T1         |             |            | PS_DDR_DM2_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T2         |             |            | PS_DDR_DQS_N2_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T3         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T4         |             |            | PS_DDR_DQ20_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T5         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T6         |             |            | RSVDVCC1                | Reserved      |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T8         |             | Dedicated  | VCCO_13                 | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| T9         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T10        |             | High Range | IO_L1N_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T11        |             | High Range | IO_L1P_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T12        |             | High Range | IO_L2P_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T14        |             | High Range | IO_L5P_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T15        |             | High Range | IO_L5N_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T16        |             | High Range | IO_L9P_T1_DQS_34        | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T17        |             | High Range | IO_L20P_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T18        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| T19        |             | High Range | IO_25_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T20        |             | High Range | IO_L15P_T2_DQS_34       | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U1         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| U2         |             |            | PS_DDR_DQ22_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U3         |             |            | PS_DDR_DQ23_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U4         |             |            | PS_DDR_DQ21_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U5         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U6         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U7         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U8         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U9         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U10        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U11        |             | Dedicated  | VCCO_13                 | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| U12        |             | High Range | IO_L2N_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U13        |             | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U14        |             | High Range | IO_L11P_T1_SRCC_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U15        |             | High Range | IO_L11N_T1_SRCC_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U16        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U17        |             | High Range | IO_L9N_T1_DQS_34        | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U18        |             | High Range | IO_L12P_T1_MRCC_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U19        |             | High Range | IO_L12N_T1_MRCC_34      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U20        |             | High Range | IO_L15N_T2_DQS_34       | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V1         |             |            | PS_DDR_DQ24_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V2         |             |            | PS_DDR_DQ30_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V3         |             |            | PS_DDR_DQ31_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V4         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| V5         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V6         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V7         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V8         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V9         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V10        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V11        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V12        |             | High Range | IO_L4P_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V13        |             | High Range | IO_L3N_T0_DQS_34        | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V14        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| V15        |             | High Range | IO_L10P_T1_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V16        |             | High Range | IO_L18P_T2_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V17        |             | High Range | IO_L21P_T3_DQS_34       | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V18        |             | High Range | IO_L21N_T3_DQS_34       | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V19        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V20        |             | High Range | IO_L16P_T2_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W1         |             |            | PS_DDR_DQ26_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W2         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W3         |             |            | PS_DDR_DQ29_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W4         |             |            | PS_DDR_DQS_N3_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W5         |             |            | PS_DDR_DQS_P3_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W6         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W7         |             | Dedicated  | VCCO_13                 | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| W8         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W9         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W10        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W11        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W13        |             | High Range | IO_L4N_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W14        |             | High Range | IO_L8P_T1_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W15        |             | High Range | IO_L10N_T1_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W16        |             | High Range | IO_L18N_T2_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W17        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| W18        |             | High Range | IO_L22P_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W19        |             | High Range | IO_L22N_T3_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W20        |             | High Range | IO_L16N_T2_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y1         |             |            | PS_DDR_DM3_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y2         |             |            | PS_DDR_DQ28_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y3         |             |            | PS_DDR_DQ25_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y4         |             |            | PS_DDR_DQ27_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y5         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| Y6         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y7         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y8         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y9         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y10        |             | Dedicated  | VCCO_13                 | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| Y11        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y12        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y13        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y14        |             | High Range | IO_L8N_T1_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y15        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| Y16        |             | High Range | IO_L7P_T1_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y17        |             | High Range | IO_L7N_T1_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y18        |             | High Range | IO_L17P_T2_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y19        |             | High Range | IO_L17N_T2_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y20        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.pb
new file mode 100644
index 0000000..e1e67ee
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpt
new file mode 100644
index 0000000..9c2f229
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpt
@@ -0,0 +1,201 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:12:08 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
+| Design       : pwm_test
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Fully Routed
+--------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: checkpoint_pwm_test
+      Design limits: <entire design considered>
+             Max violations: <unlimited>
+             Violations found: 33
++-----------+------------------+-----------------------------+------------+
+| Rule      | Severity         | Description                 | Violations |
++-----------+------------------+-----------------------------+------------+
+| TIMING-17 | Critical Warning | Non-clocked sequential cell | 32         |
+| TIMING-20 | Warning          | Non-clocked latch           | 1          |
++-----------+------------------+-----------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-17#1 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#2 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[10]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#3 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[11]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#4 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[12]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#5 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[13]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#6 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[14]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#7 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[15]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#8 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[16]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#9 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[17]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#10 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[18]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#11 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[19]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#12 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#13 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[20]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#14 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[21]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#15 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[22]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#16 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[23]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#17 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[24]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#18 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[25]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#19 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[26]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#20 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[27]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#21 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[28]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#22 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[29]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#23 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#24 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[30]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#25 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[31]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#26 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#27 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#28 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#29 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#30 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#31 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[8]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#32 Critical Warning
+Non-clocked sequential cell  
+The clock pin count_reg[9]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#1 Warning
+Non-clocked latch  
+The latch led_reg cannot be properly analyzed as its control pin led_reg/G is not reached by a timing clock
+Related violations: <none>
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpx b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpx
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_opt.dcp b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_opt.dcp
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_physopt.dcp b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_physopt.dcp
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_placed.dcp b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_placed.dcp
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_power_routed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_power_routed.rpt
new file mode 100644
index 0000000..aa9f0fc
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_power_routed.rpt
@@ -0,0 +1,151 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version     : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date             : Fri Mar 25 10:12:09 2022
+| Host             : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command          : report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
+| Design           : pwm_test
+| Device           : xc7z010clg400-1
+| Design State     : routed
+| Grade            : commercial
+| Process          : typical
+| Characterization : Production
+----------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W)  | 0.485        |
+| Design Power Budget (W)  | Unspecified* |
+| Power Budget Margin (W)  | NA           |
+| Dynamic (W)              | 0.391        |
+| Device Static (W)        | 0.094        |
+| Effective TJA (C/W)      | 11.5         |
+| Max Ambient (C)          | 79.4         |
+| Junction Temperature (C) | 30.6         |
+| Confidence Level         | Low          |
+| Setting File             | ---          |
+| Simulation Activity File | ---          |
+| Design Nets Matched      | NA           |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Slice Logic    |     0.201 |      105 |       --- |             --- |
+|   LUT as Logic |     0.157 |       33 |     17600 |            0.19 |
+|   CARRY4       |     0.025 |       16 |      4400 |            0.36 |
+|   Register     |     0.013 |       33 |     35200 |            0.09 |
+|   BUFG         |     0.006 |        1 |        32 |            3.13 |
+|   Others       |     0.000 |        3 |       --- |             --- |
+| Signals        |     0.186 |       50 |       --- |             --- |
+| I/O            |     0.004 |        2 |       100 |            2.00 |
+| Static Power   |     0.094 |          |           |                 |
+| Total          |     0.485 |          |           |                 |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint    |       1.000 |     0.395 |       0.391 |      0.004 |       NA    | Unspecified | NA         |
+| Vccaux    |       1.800 |     0.006 |       0.000 |      0.006 |       NA    | Unspecified | NA         |
+| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccpint   |       1.000 |     0.019 |       0.000 |      0.019 |       NA    | Unspecified | NA         |
+| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |       NA    | Unspecified | NA         |
+| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |       NA    | Unspecified | NA         |
+| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
+| Clock nodes activity        | Low        | User specified less than 75% of clocks                 | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
+| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
+| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
+| Device models               | High       | Device models are Production                           |                                                                                                                    |
+|                             |            |                                                        |                                                                                                                    |
+| Overall confidence level    | Low        |                                                        |                                                                                                                    |
++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+------------------------+
+| Ambient Temp (C)      | 25.0                   |
+| ThetaJA (C/W)         | 11.5                   |
+| Airflow (LFM)         | 250                    |
+| Heat Sink             | none                   |
+| ThetaSA (C/W)         | 0.0                    |
+| Board Selection       | medium (10"x10")       |
+| # of Board Layers     | 8to11 (8 to 11 Layers) |
+| Board Temperature (C) | 25.0                   |
++-----------------------+------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++-------+--------+-----------------+
+| Clock | Domain | Constraint (ns) |
++-------+--------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++----------+-----------+
+| Name     | Power (W) |
++----------+-----------+
+| pwm_test |     0.391 |
++----------+-----------+
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_power_routed.rpx b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_power_routed.rpx
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_power_summary_routed.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_power_summary_routed.pb
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_route_status.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_route_status.pb
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_route_status.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_route_status.rpt
new file mode 100644
index 0000000..da1d598
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+   # of logical nets.......................... :         138 :
+       # of nets not needing routing.......... :          86 :
+           # of internally routed nets........ :          86 :
+       # of routable nets..................... :          52 :
+           # of fully routed nets............. :          52 :
+       # of nets with routing errors.......... :           0 :
+   ------------------------------------------- : ----------- :
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_routed.dcp b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_routed.dcp
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index 0000000..9956031
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diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.pb
new file mode 100644
index 0000000..4526e93
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.pb
@@ -0,0 +1,2 @@
+
+2012.4’)Timing analysis from Implemented netlist.
\ No newline at end of file
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.rpt
new file mode 100644
index 0000000..f9851ea
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.rpt
@@ -0,0 +1,808 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:12:09 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file pwm_test_timing_summary_routed.rpt -pb pwm_test_timing_summary_routed.pb -rpx pwm_test_timing_summary_routed.rpx -warn_on_violation
+| Design       : pwm_test
+| Device       : 7z010-clg400
+| Speed File   : -1  PRODUCTION 1.12 2019-11-22
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+  Enable Multi Corner Analysis               :  Yes
+  Enable Pessimism Removal                   :  Yes
+  Pessimism Removal Resolution               :  Nearest Common Node
+  Enable Input Delay Default Clock           :  No
+  Enable Preset / Clear Arcs                 :  No
+  Disable Flight Delays                      :  No
+  Ignore I/O Paths                           :  No
+  Timing Early Launch at Borrowing Latches   :  No
+  Borrow Time for Max Delay Exceptions       :  Yes
+  Merge Timing Exceptions                    :  Yes
+
+  Corner  Analyze    Analyze    
+  Name    Max Paths  Min Paths  
+  ------  ---------  ---------  
+  Slow    Yes        Yes        
+  Fast    Yes        Yes        
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule       Severity          Description                  Violations  
+---------  ----------------  ---------------------------  ----------  
+TIMING-17  Critical Warning  Non-clocked sequential cell  32          
+TIMING-20  Warning           Non-clocked latch            1           
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (64)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (66)
+5. checking no_input_delay (0)
+6. checking no_output_delay (1)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (64)
+-------------------------
+ There are 32 register/latch pins with no clock driven by root clock pin: clk (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[0]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[10]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[11]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[12]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[13]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[14]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[15]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[16]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[17]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[18]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[19]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[1]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[20]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[21]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[22]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[23]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[24]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[25]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[26]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[27]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[28]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[29]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[2]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[30]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[31]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[3]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[4]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[5]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[6]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[7]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[8]/Q (HIGH)
+
+ There is 1 register/latch pin with no clock driven by root clock pin: count_reg[9]/Q (HIGH)
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (66)
+-------------------------------------------------
+ There are 66 pins that are not constrained for maximum delay. (HIGH)
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (0)
+------------------------------
+ There are 0 input ports with no input delay specified.
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (1)
+-------------------------------
+ There is 1 port with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+        inf        0.000                      0                   67          inf        0.000                      0                   67           NA           NA                      NA                    NA  
+
+
+There are no user specified timing constraints.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| User Ignored Path Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock    
+----------    ----------    --------    
+
+
+------------------------------------------------------------------------------------------------
+| Unconstrained Path Table
+| ------------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock    
+----------    ----------    --------    
+(none)                                    
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  
+  To Clock:  
+
+Max Delay            67 Endpoints
+Min Delay            67 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            led
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.232ns  (logic 5.810ns (62.942%)  route 3.421ns (37.058%))
+  Logic Levels:           8  (CARRY4=4 FDCE=1 LDCE=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 r  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          0.688     3.042    led_reg_i_2_n_0
+    SLICE_X41Y92         LDCE (SetClr_ldce_CLR_Q)     0.791     3.833 f  led_reg/Q
+                         net (fo=1, routed)           1.913     5.746    led_OBUF
+    G14                  OBUF (Prop_obuf_I_O)         3.485     9.232 f  led_OBUF_inst/O
+                         net (fo=0)                   0.000     9.232    led
+    G14                                                               f  led (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[24]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        4.152ns  (logic 1.534ns (36.946%)  route 2.618ns (63.054%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.798     4.152    led_reg_i_2_n_0
+    SLICE_X42Y94         FDCE                                         f  count_reg[24]/CLR
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[25]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        4.152ns  (logic 1.534ns (36.946%)  route 2.618ns (63.054%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.798     4.152    led_reg_i_2_n_0
+    SLICE_X42Y94         FDCE                                         f  count_reg[25]/CLR
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[26]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        4.152ns  (logic 1.534ns (36.946%)  route 2.618ns (63.054%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.798     4.152    led_reg_i_2_n_0
+    SLICE_X42Y94         FDCE                                         f  count_reg[26]/CLR
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[27]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        4.152ns  (logic 1.534ns (36.946%)  route 2.618ns (63.054%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.798     4.152    led_reg_i_2_n_0
+    SLICE_X42Y94         FDCE                                         f  count_reg[27]/CLR
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[20]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.700ns  (logic 1.534ns (41.461%)  route 2.166ns (58.539%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.346     3.700    led_reg_i_2_n_0
+    SLICE_X42Y93         FDCE                                         f  count_reg[20]/CLR
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[21]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.700ns  (logic 1.534ns (41.461%)  route 2.166ns (58.539%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.346     3.700    led_reg_i_2_n_0
+    SLICE_X42Y93         FDCE                                         f  count_reg[21]/CLR
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[22]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.700ns  (logic 1.534ns (41.461%)  route 2.166ns (58.539%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.346     3.700    led_reg_i_2_n_0
+    SLICE_X42Y93         FDCE                                         f  count_reg[22]/CLR
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[23]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.700ns  (logic 1.534ns (41.461%)  route 2.166ns (58.539%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.346     3.700    led_reg_i_2_n_0
+    SLICE_X42Y93         FDCE                                         f  count_reg[23]/CLR
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[3]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[28]/CLR
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.691ns  (logic 1.534ns (41.562%)  route 2.157ns (58.438%))
+  Logic Levels:           6  (CARRY4=4 FDCE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[3]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.518     0.518 f  count_reg[3]/Q
+                         net (fo=5, routed)           0.820     1.338    count_reg[3]
+    SLICE_X43Y89         LUT2 (Prop_lut2_I1_O)        0.124     1.462 r  led_reg_i_58/O
+                         net (fo=1, routed)           0.000     1.462    led_reg_i_58_n_0
+    SLICE_X43Y89         CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     2.012 r  led_reg_i_39/CO[3]
+                         net (fo=1, routed)           0.000     2.012    led_reg_i_39_n_0
+    SLICE_X43Y90         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.126 r  led_reg_i_25/CO[3]
+                         net (fo=1, routed)           0.000     2.126    led_reg_i_25_n_0
+    SLICE_X43Y91         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.240 r  led_reg_i_11/CO[3]
+                         net (fo=1, routed)           0.000     2.240    led_reg_i_11_n_0
+    SLICE_X43Y92         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     2.354 f  led_reg_i_2/CO[3]
+                         net (fo=33, routed)          1.337     3.691    led_reg_i_2_n_0
+    SLICE_X42Y95         FDCE                                         f  count_reg[28]/CLR
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 count_reg[18]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[18]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.401ns  (logic 0.274ns (68.412%)  route 0.127ns (31.588%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y92         FDCE                         0.000     0.000 r  count_reg[18]/C
+    SLICE_X42Y92         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[18]/Q
+                         net (fo=5, routed)           0.127     0.291    count_reg[18]
+    SLICE_X42Y92         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.110     0.401 r  count_reg[16]_i_1/O[2]
+                         net (fo=1, routed)           0.000     0.401    count_reg[16]_i_1_n_5
+    SLICE_X42Y92         FDCE                                         r  count_reg[18]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[26]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[26]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.401ns  (logic 0.274ns (68.401%)  route 0.127ns (31.599%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y94         FDCE                         0.000     0.000 r  count_reg[26]/C
+    SLICE_X42Y94         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[26]/Q
+                         net (fo=4, routed)           0.127     0.291    count_reg[26]
+    SLICE_X42Y94         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.110     0.401 r  count_reg[24]_i_1/O[2]
+                         net (fo=1, routed)           0.000     0.401    count_reg[24]_i_1_n_5
+    SLICE_X42Y94         FDCE                                         r  count_reg[26]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[30]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[30]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.401ns  (logic 0.274ns (68.401%)  route 0.127ns (31.599%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y95         FDCE                         0.000     0.000 r  count_reg[30]/C
+    SLICE_X42Y95         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[30]/Q
+                         net (fo=5, routed)           0.127     0.291    count_reg[30]
+    SLICE_X42Y95         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.110     0.401 r  count_reg[28]_i_1/O[2]
+                         net (fo=1, routed)           0.000     0.401    count_reg[28]_i_1_n_5
+    SLICE_X42Y95         FDCE                                         r  count_reg[30]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[6]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[6]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.412ns  (logic 0.274ns (66.556%)  route 0.138ns (33.444%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y89         FDCE                         0.000     0.000 r  count_reg[6]/C
+    SLICE_X42Y89         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[6]/Q
+                         net (fo=4, routed)           0.138     0.302    count_reg[6]
+    SLICE_X42Y89         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.110     0.412 r  count_reg[4]_i_1/O[2]
+                         net (fo=1, routed)           0.000     0.412    count_reg[4]_i_1_n_5
+    SLICE_X42Y89         FDCE                                         r  count_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[10]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[10]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.412ns  (logic 0.274ns (66.506%)  route 0.138ns (33.494%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y90         FDCE                         0.000     0.000 r  count_reg[10]/C
+    SLICE_X42Y90         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[10]/Q
+                         net (fo=4, routed)           0.138     0.302    count_reg[10]
+    SLICE_X42Y90         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.110     0.412 r  count_reg[8]_i_1/O[2]
+                         net (fo=1, routed)           0.000     0.412    count_reg[8]_i_1_n_5
+    SLICE_X42Y90         FDCE                                         r  count_reg[10]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[14]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[14]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.413ns  (logic 0.274ns (66.390%)  route 0.139ns (33.610%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y91         FDCE                         0.000     0.000 r  count_reg[14]/C
+    SLICE_X42Y91         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[14]/Q
+                         net (fo=4, routed)           0.139     0.303    count_reg[14]
+    SLICE_X42Y91         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.110     0.413 r  count_reg[12]_i_1/O[2]
+                         net (fo=1, routed)           0.000     0.413    count_reg[12]_i_1_n_5
+    SLICE_X42Y91         FDCE                                         r  count_reg[14]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[22]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[22]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.413ns  (logic 0.274ns (66.390%)  route 0.139ns (33.610%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y93         FDCE                         0.000     0.000 r  count_reg[22]/C
+    SLICE_X42Y93         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[22]/Q
+                         net (fo=4, routed)           0.139     0.303    count_reg[22]
+    SLICE_X42Y93         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.110     0.413 r  count_reg[20]_i_1/O[2]
+                         net (fo=1, routed)           0.000     0.413    count_reg[20]_i_1_n_5
+    SLICE_X42Y93         FDCE                                         r  count_reg[22]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[2]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[2]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.413ns  (logic 0.274ns (66.390%)  route 0.139ns (33.610%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y88         FDCE                         0.000     0.000 r  count_reg[2]/C
+    SLICE_X42Y88         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[2]/Q
+                         net (fo=5, routed)           0.139     0.303    count_reg[2]
+    SLICE_X42Y88         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.110     0.413 r  count_reg[0]_i_1/O[2]
+                         net (fo=1, routed)           0.000     0.413    count_reg[0]_i_1_n_5
+    SLICE_X42Y88         FDCE                                         r  count_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[18]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[19]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.437ns  (logic 0.310ns (71.017%)  route 0.127ns (28.983%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y92         FDCE                         0.000     0.000 r  count_reg[18]/C
+    SLICE_X42Y92         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[18]/Q
+                         net (fo=5, routed)           0.127     0.291    count_reg[18]
+    SLICE_X42Y92         CARRY4 (Prop_carry4_S[2]_O[3])
+                                                      0.146     0.437 r  count_reg[16]_i_1/O[3]
+                         net (fo=1, routed)           0.000     0.437    count_reg[16]_i_1_n_4
+    SLICE_X42Y92         FDCE                                         r  count_reg[19]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 count_reg[26]/C
+                            (rising edge-triggered cell FDCE)
+  Destination:            count_reg[27]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.437ns  (logic 0.310ns (71.007%)  route 0.127ns (28.993%))
+  Logic Levels:           2  (CARRY4=1 FDCE=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X42Y94         FDCE                         0.000     0.000 r  count_reg[26]/C
+    SLICE_X42Y94         FDCE (Prop_fdce_C_Q)         0.164     0.164 r  count_reg[26]/Q
+                         net (fo=4, routed)           0.127     0.291    count_reg[26]
+    SLICE_X42Y94         CARRY4 (Prop_carry4_S[2]_O[3])
+                                                      0.146     0.437 r  count_reg[24]_i_1/O[3]
+                         net (fo=1, routed)           0.000     0.437    count_reg[24]_i_1_n_4
+    SLICE_X42Y94         FDCE                                         r  count_reg[27]/D
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.rpx b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.rpx
new file mode 100644
index 0000000..283a243
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_timing_summary_routed.rpx differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_utilization_placed.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_utilization_placed.pb
new file mode 100644
index 0000000..42595b3
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_utilization_placed.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_utilization_placed.rpt b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_utilization_placed.rpt
new file mode 100644
index 0000000..7af5476
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_utilization_placed.rpt
@@ -0,0 +1,202 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:11:52 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_utilization -file pwm_test_utilization_placed.rpt -pb pwm_test_utilization_placed.pb
+| Design       : pwm_test
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Fully Placed
+-------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs              |   33 |     0 |          0 |     17600 |  0.19 |
+|   LUT as Logic          |   33 |     0 |          0 |     17600 |  0.19 |
+|   LUT as Memory         |    0 |     0 |          0 |      6000 |  0.00 |
+| Slice Registers         |   33 |     0 |          0 |     35200 |  0.09 |
+|   Register as Flip Flop |   32 |     0 |          0 |     35200 |  0.09 |
+|   Register as Latch     |    1 |     0 |          0 |     35200 | <0.01 |
+| F7 Muxes                |    0 |     0 |          0 |      8800 |  0.00 |
+| F8 Muxes                |    0 |     0 |          0 |      4400 |  0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 33    |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 0     |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++------------------------------------------+------+-------+------------+-----------+-------+
+|                 Site Type                | Used | Fixed | Prohibited | Available | Util% |
++------------------------------------------+------+-------+------------+-----------+-------+
+| Slice                                    |   16 |     0 |          0 |      4400 |  0.36 |
+|   SLICEL                                 |    8 |     0 |            |           |       |
+|   SLICEM                                 |    8 |     0 |            |           |       |
+| LUT as Logic                             |   33 |     0 |          0 |     17600 |  0.19 |
+|   using O5 output only                   |    0 |       |            |           |       |
+|   using O6 output only                   |   14 |       |            |           |       |
+|   using O5 and O6                        |   19 |       |            |           |       |
+| LUT as Memory                            |    0 |     0 |          0 |      6000 |  0.00 |
+|   LUT as Distributed RAM                 |    0 |     0 |            |           |       |
+|   LUT as Shift Register                  |    0 |     0 |            |           |       |
+| Slice Registers                          |   33 |     0 |          0 |     35200 |  0.09 |
+|   Register driven from within the Slice  |   33 |       |            |           |       |
+|   Register driven from outside the Slice |    0 |       |            |           |       |
+| Unique Control Sets                      |    2 |       |          0 |      4400 |  0.05 |
++------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile |    0 |     0 |          0 |        60 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |          0 |        60 |  0.00 |
+|   RAMB18       |    0 |     0 |          0 |       120 |  0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |        80 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |    2 |     2 |          0 |       100 |  2.00 |
+|   IOB Master Pads           |    1 |       |            |           |       |
+|   IOB Slave Pads            |    0 |       |            |           |       |
+| Bonded IPADs                |    0 |     0 |          0 |         2 |  0.00 |
+| Bonded IOPADs               |    0 |     0 |          0 |       130 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |         2 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |         2 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |         8 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |         8 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |          0 |         2 |  0.00 |
+| IBUFDS                      |    0 |     0 |          0 |        96 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |         8 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |         8 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       100 |  0.00 |
+| ILOGIC                      |    0 |     0 |          0 |       100 |  0.00 |
+| OLOGIC                      |    0 |     0 |          0 |       100 |  0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+|  Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL   |    1 |     0 |          0 |        32 |  3.13 |
+| BUFIO      |    0 |     0 |          0 |         8 |  0.00 |
+| MMCME2_ADV |    0 |     0 |          0 |         2 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |          0 |         2 |  0.00 |
+| BUFMRCE    |    0 |     0 |          0 |         4 |  0.00 |
+| BUFHCE     |    0 |     0 |          0 |        48 |  0.00 |
+| BUFR       |    0 |     0 |          0 |         8 |  0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| LUT2     |   51 |                 LUT |
+| FDCE     |   32 |        Flop & Latch |
+| CARRY4   |   16 |          CarryLogic |
+| OBUF     |    1 |                  IO |
+| LUT1     |    1 |                 LUT |
+| LDCE     |    1 |        Flop & Latch |
+| IBUF     |    1 |                  IO |
+| BUFG     |    1 |               Clock |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/route_design.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/route_design.pb
new file mode 100644
index 0000000..5404fb0
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/route_design.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/rundef.js b/Coraz7_Test/Coraz7_Test.runs/impl_1/rundef.js
new file mode 100644
index 0000000..313a571
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/rundef.js
@@ -0,0 +1,40 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;";
+} else {
+  PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+         "-log pwm_test.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.bat b/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.bat
new file mode 100644
index 0000000..6c4f290
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.bat
@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log b/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
new file mode 100644
index 0000000..55c693d
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
@@ -0,0 +1,553 @@
+
+*** Running vivado
+    with args -log pwm_test.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace
+
+
+
+****** Vivado v2021.2 (64-bit)
+  **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+source pwm_test.tcl -notrace
+Command: open_checkpoint C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1262.352 ; gain = 1.801
+CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:zybo-z7-10:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
+CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:zybo-z7-10:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1266.320 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Timing 38-478] Restoring timing data from binary archive.
+INFO: [Timing 38-479] Binary timing data restore complete.
+INFO: [Project 1-856] Restoring constraints from binary archive.
+INFO: [Project 1-853] Binary constraint restore complete.
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1357.309 ; gain = 0.000
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1357.309 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1357.309 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Project 1-604] Checkpoint was created with Vivado v2021.2 (64-bit) build 3367213
+open_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1357.309 ; gain = 104.965
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1365.902 ; gain = 8.594
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 1c056137f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1441.777 ; gain = 75.875
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 1c056137f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 1c056137f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 1fbd34c49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 1fbd34c49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 1fbd34c49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 1fbd34c49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1726.871 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: 20c3576ce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1726.871 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 20c3576ce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1726.871 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 20c3576ce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: 20c3576ce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+28 Infos, 0 Warnings, 2 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1726.871 ; gain = 369.562
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1726.871 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
+Command: report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 13ba8a4a3
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bc17a400
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.161 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.164 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.170 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 18da1b6ca
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.179 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 2.4 Global Placement Core
+WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
+Phase 2.4 Global Placement Core | Checksum: 12ed945d9
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.657 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 12ed945d9
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.661 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 12ed945d9
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.664 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.677 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.683 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.685 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.720 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.725 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.726 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.727 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+Phase 4.1 Post Commit Optimization | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.745 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.750 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1707a0fa3
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Ending Placer Task | Checksum: deb5d7c7
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1766.074 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+47 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1766.074 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file pwm_test_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1766.074 ; gain = 0.000
+INFO: [runtcl-4] Executing : report_utilization -file pwm_test_utilization_placed.rpt -pb pwm_test_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file pwm_test_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+55 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1766.074 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 584981bf ConstDB: 0 ShapeSum: 866c5608 RouteDB: 0
+Post Restoration Checksum: NetGraph: 32e9d585 NumContArr: cff0ca0e Constraints: 0 Timing: 0
+Phase 1 Build RT Design | Checksum: 102da9f93
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1799.160 ; gain = 26.402
+
+Phase 2 Router Initialization
+INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 102da9f93
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1805.191 ; gain = 32.434
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 102da9f93
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1805.191 ; gain = 32.434
+ Number of Nodes with overlaps = 0
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 48
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 48
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: a88dbed9
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: a88dbed9
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
+Phase 3 Initial Routing | Checksum: 105c3e9d5
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 0
+Phase 4.1 Global Iteration 0 | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+Phase 4 Rip-up And Reroute | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 5 Delay and Skew Optimization
+Phase 5 Delay and Skew Optimization | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+Phase 6.1 Hold Fix Iter | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+Phase 6 Post Hold Fix | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0115428 %
+  Global Horizontal Routing Utilization  = 0.0284926 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Congestion Report
+North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 6.30631%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
+
+------------------------------
+Reporting congestion hotspots
+------------------------------
+Direction: North
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: South
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: East
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: West
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+
+Phase 7 Route finalize | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: ec175c67
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 8d29afef
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+65 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 44.613
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1820.504 ; gain = 9.816
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
+Command: report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
+Command: report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
+Command: report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
+Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+77 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file pwm_test_route_status.rpt -pb pwm_test_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file pwm_test_timing_summary_routed.rpt -pb pwm_test_timing_summary_routed.pb -rpx pwm_test_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+INFO: [runtcl-4] Executing : report_incremental_reuse -file pwm_test_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file pwm_test_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pwm_test_bus_skew_routed.rpt -pb pwm_test_bus_skew_routed.pb -rpx pwm_test_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+Command: write_bitstream -force pwm_test.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./pwm_test.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
+INFO: [Common 17-83] Releasing license: Implementation
+12 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 2293.621 ; gain = 439.371
+INFO: [Common 17-206] Exiting Vivado at Fri Mar 25 10:12:18 2022...
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.sh b/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.sh
new file mode 100644
index 0000000..cd6d86d
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.sh
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin
+else
+  PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log pwm_test.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/vivado.jou b/Coraz7_Test/Coraz7_Test.runs/impl_1/vivado.jou
new file mode 100644
index 0000000..daf9157
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/impl_1/vivado.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri Mar 25 10:11:21 2022
+# Process ID: 10536
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1
+# Command line: vivado.exe -log pwm_test.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source pwm_test.tcl -notrace
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/vivado.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/vivado.pb
new file mode 100644
index 0000000..1f7eef5
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/vivado.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/impl_1/write_bitstream.pb b/Coraz7_Test/Coraz7_Test.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000..df7dd33
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/impl_1/write_bitstream.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/.Vivado_Synthesis.queue.rst b/Coraz7_Test/Coraz7_Test.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/.Xil/pwm_test_propImpl.xdc b/Coraz7_Test/Coraz7_Test.runs/synth_1/.Xil/pwm_test_propImpl.xdc
new file mode 100644
index 0000000..638378c
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/.Xil/pwm_test_propImpl.xdc
@@ -0,0 +1,15 @@
+set_property SRC_FILE_INFO {cfile:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc rfile:../../../../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk #  125 Mhz??
+set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
+set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g
+set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
+set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led }]; #IO_0_35 Sch=led1_b
+set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g
+set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/.vivado.begin.rst b/Coraz7_Test/Coraz7_Test.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000..cfd4aaf
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="1096" HostCore="12" HostMemory="016927088640">
+    </Process>
+</ProcessHandle>
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/.vivado.end.rst b/Coraz7_Test/Coraz7_Test.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/ISEWrap.js b/Coraz7_Test/Coraz7_Test.runs/synth_1/ISEWrap.js
new file mode 100644
index 0000000..db0a510
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/ISEWrap.js
@@ -0,0 +1,269 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\" HostCore=\"" + ISEHOSTCORE +
+			    "\" HostMemory=\"" + ISEMEMTOTAL +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/ISEWrap.sh b/Coraz7_Test/Coraz7_Test.runs/synth_1/ISEWrap.sh
new file mode 100644
index 0000000..c2fbbb6
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,84 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+cmd_exists()
+{
+  command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/__synthesis_is_complete__ b/Coraz7_Test/Coraz7_Test.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/gen_run.xml b/Coraz7_Test/Coraz7_Test.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000..63d0625
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/gen_run.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1648199469" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/pwm_test.dcp">
+  <File Type="PA-TCL" Name="pwm_test.tcl"/>
+  <File Type="RDS-PROPCONSTRS" Name="pwm_test_drc_synth.rpt"/>
+  <File Type="REPORTS-TCL" Name="pwm_test_reports.tcl"/>
+  <File Type="RDS-RDS" Name="pwm_test.vds"/>
+  <File Type="RDS-UTIL" Name="pwm_test_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="pwm_test_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="pwm_test.dcp"/>
+  <File Type="VDS-TIMINGSUMMARY" Name="pwm_test_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="pwm_test_timing_summary_synth.pb"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/new/pwm_test.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="pwm_test"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc"/>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+    <Filter Type="Utils"/>
+    <File Path="$PSRCDIR/utils_1/imports/synth_1/pwm_test.dcp">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedInSteps" Val="synth_1"/>
+        <Attr Name="AutoDcp" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/htr.txt b/Coraz7_Test/Coraz7_Test.runs/synth_1/htr.txt
new file mode 100644
index 0000000..ff6e67d
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/htr.txt
@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log pwm_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pwm_test.tcl
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/project.wdf b/Coraz7_Test/Coraz7_Test.runs/synth_1/project.wdf
new file mode 100644
index 0000000..482b29a
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
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diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
new file mode 100644
index 0000000..bd4c7e0
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.tcl b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.tcl
new file mode 100644
index 0000000..b78e63a
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.tcl
@@ -0,0 +1,125 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+namespace eval ::optrace {
+  variable script "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.tcl"
+  variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7z010clg400-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.cache/wt [current_project]
+set_property parent.project_path C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property board_part_repo_paths {C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/xhub/board_store/xilinx_board_store} [current_project]
+set_property board_part digilentinc.com:zybo-z7-10:part0:1.0 [current_project]
+set_property ip_output_repo c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -library xil_defaultlib C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc
+set_property used_in_implementation false [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+
+read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top pwm_test -part xc7z010clg400-1
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef pwm_test.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file pwm_test_utilization_synth.rpt -pb pwm_test_utilization_synth.pb"
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.vds b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.vds
new file mode 100644
index 0000000..d8888ed
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.vds
@@ -0,0 +1,236 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri Mar 25 10:08:02 2022
+# Process ID: 14164
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+# Command line: vivado.exe -log pwm_test.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source pwm_test.tcl
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.vds
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source pwm_test.tcl -notrace
+create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1254.391 ; gain = 0.000
+Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top pwm_test -part xc7z010clg400-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 9544
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'pwm_test' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
+WARNING: [Synth 8-614] signal 'count' is read in the process but is not in the sensitivity list [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:49]
+INFO: [Synth 8-256] done synthesizing module 'pwm_test' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1254.391 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/pwm_test_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/pwm_test_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.391 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1254.391 ; gain = 0.000
+WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z010clg400-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-327] inferring latch for variable 'led_reg' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:57]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 80 (col length:40)
+BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     1|
+|2     |CARRY4 |    16|
+|3     |LUT1   |     1|
+|4     |LUT2   |    51|
+|5     |FDCE   |    32|
+|6     |LDC    |     1|
+|7     |IBUF   |     1|
+|8     |OBUF   |     1|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1254.391 ; gain = 0.000
+Synthesis Optimization Complete : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1258.488 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 17 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1267.129 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 1 instances were transformed.
+  LDC => LDCE: 1 instance 
+
+Synth Design complete, checksum: 4ecd4cf2
+INFO: [Common 17-83] Releasing license: Synthesis
+21 Infos, 10 Warnings, 5 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 1267.129 ; gain = 12.738
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file pwm_test_utilization_synth.rpt -pb pwm_test_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Fri Mar 25 10:08:57 2022...
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test_utilization_synth.pb b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test_utilization_synth.pb
new file mode 100644
index 0000000..42595b3
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test_utilization_synth.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test_utilization_synth.rpt b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test_utilization_synth.rpt
new file mode 100644
index 0000000..71793bf
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test_utilization_synth.rpt
@@ -0,0 +1,176 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri Mar 25 10:08:57 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_utilization -file pwm_test_utilization_synth.rpt -pb pwm_test_utilization_synth.pb
+| Design       : pwm_test
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Synthesized
+-----------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs*             |   33 |     0 |          0 |     17600 |  0.19 |
+|   LUT as Logic          |   33 |     0 |          0 |     17600 |  0.19 |
+|   LUT as Memory         |    0 |     0 |          0 |      6000 |  0.00 |
+| Slice Registers         |   33 |     0 |          0 |     35200 |  0.09 |
+|   Register as Flip Flop |   32 |     0 |          0 |     35200 |  0.09 |
+|   Register as Latch     |    1 |     0 |          0 |     35200 | <0.01 |
+| F7 Muxes                |    0 |     0 |          0 |      8800 |  0.00 |
+| F8 Muxes                |    0 |     0 |          0 |      4400 |  0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 33    |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 0     |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile |    0 |     0 |          0 |        60 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |          0 |        60 |  0.00 |
+|   RAMB18       |    0 |     0 |          0 |       120 |  0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |        80 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |    2 |     0 |          0 |       100 |  2.00 |
+| Bonded IPADs                |    0 |     0 |          0 |         2 |  0.00 |
+| Bonded IOPADs               |    0 |     0 |          0 |       130 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |         2 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |         2 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |         8 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |         8 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |          0 |         2 |  0.00 |
+| IBUFDS                      |    0 |     0 |          0 |        96 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |         8 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |         8 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       100 |  0.00 |
+| ILOGIC                      |    0 |     0 |          0 |       100 |  0.00 |
+| OLOGIC                      |    0 |     0 |          0 |       100 |  0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+|  Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL   |    1 |     0 |          0 |        32 |  3.13 |
+| BUFIO      |    0 |     0 |          0 |         8 |  0.00 |
+| MMCME2_ADV |    0 |     0 |          0 |         2 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |          0 |         2 |  0.00 |
+| BUFMRCE    |    0 |     0 |          0 |         4 |  0.00 |
+| BUFHCE     |    0 |     0 |          0 |        48 |  0.00 |
+| BUFR       |    0 |     0 |          0 |         8 |  0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| LUT2     |   51 |                 LUT |
+| FDCE     |   32 |        Flop & Latch |
+| CARRY4   |   16 |          CarryLogic |
+| OBUF     |    1 |                  IO |
+| LUT1     |    1 |                 LUT |
+| LDCE     |    1 |        Flop & Latch |
+| IBUF     |    1 |                  IO |
+| BUFG     |    1 |               Clock |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/rundef.js b/Coraz7_Test/Coraz7_Test.runs/synth_1/rundef.js
new file mode 100644
index 0000000..c4671e5
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/rundef.js
@@ -0,0 +1,36 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;";
+} else {
+  PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log pwm_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pwm_test.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.bat b/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.bat
new file mode 100644
index 0000000..6c4f290
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.bat
@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log b/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
new file mode 100644
index 0000000..61f34f9
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
@@ -0,0 +1,235 @@
+
+*** Running vivado
+    with args -log pwm_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pwm_test.tcl
+
+
+
+****** Vivado v2021.2 (64-bit)
+  **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+source pwm_test.tcl -notrace
+create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1254.391 ; gain = 0.000
+Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top pwm_test -part xc7z010clg400-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 9544
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'pwm_test' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
+WARNING: [Synth 8-614] signal 'count' is read in the process but is not in the sensitivity list [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:49]
+INFO: [Synth 8-256] done synthesizing module 'pwm_test' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1254.391 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/pwm_test_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/pwm_test_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.391 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1254.391 ; gain = 0.000
+WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z010clg400-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-327] inferring latch for variable 'led_reg' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:57]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 80 (col length:40)
+BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     1|
+|2     |CARRY4 |    16|
+|3     |LUT1   |     1|
+|4     |LUT2   |    51|
+|5     |FDCE   |    32|
+|6     |LDC    |     1|
+|7     |IBUF   |     1|
+|8     |OBUF   |     1|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1254.391 ; gain = 0.000
+Synthesis Optimization Complete : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.391 ; gain = 0.000
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1258.488 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 17 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1267.129 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 1 instances were transformed.
+  LDC => LDCE: 1 instance 
+
+Synth Design complete, checksum: 4ecd4cf2
+INFO: [Common 17-83] Releasing license: Synthesis
+21 Infos, 10 Warnings, 5 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 1267.129 ; gain = 12.738
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file pwm_test_utilization_synth.rpt -pb pwm_test_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Fri Mar 25 10:08:57 2022...
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.sh b/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.sh
new file mode 100644
index 0000000..e1afd09
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin
+else
+  PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log pwm_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pwm_test.tcl
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/vivado.jou b/Coraz7_Test/Coraz7_Test.runs/synth_1/vivado.jou
new file mode 100644
index 0000000..ea4c926
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.runs/synth_1/vivado.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri Mar 25 10:08:02 2022
+# Process ID: 14164
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+# Command line: vivado.exe -log pwm_test.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source pwm_test.tcl
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.vds
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source pwm_test.tcl -notrace
diff --git a/Coraz7_Test/Coraz7_Test.runs/synth_1/vivado.pb b/Coraz7_Test/Coraz7_Test.runs/synth_1/vivado.pb
new file mode 100644
index 0000000..4686747
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.runs/synth_1/vivado.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
new file mode 100644
index 0000000..131153d
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Mon Mar 21 13:58:53 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+call xvhdl  --incr --relax -prj pwm_test_db_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/compile.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/compile.log
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
new file mode 100644
index 0000000..f21df15
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Mon Mar 21 13:58:54 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+call xelab  --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000..3e29ba8
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,7 @@
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb
new file mode 100644
index 0000000..6fa9743
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl
new file mode 100644
index 0000000..ea95314
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 5 ms
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb
new file mode 100644
index 0000000..d699ee7
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat
new file mode 100644
index 0000000..b0bbd5f
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Mon Mar 21 13:58:56 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch pwm_test_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg -log simulate.log"
+call xsim  pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch pwm_test_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000..3a14ee6
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000..240496d
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg
new file mode 100644
index 0000000..1d8cc0b
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimSettings.ini b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimSettings.ini
new file mode 100644
index 0000000..56ff420
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimcrash.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe
new file mode 100644
index 0000000..bb81b98
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log
new file mode 100644
index 0000000..7bfe923
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/pwm_test_behav/xsimk.exe -simmode gui -wdb pwm_test_behav.wdb -simrunnum 0 -socket 65496
+Design successfully loaded
+Design Loading Memory Usage: 8396 KB (Peak: 8396 KB)
+Design Loading CPU Usage: 15 ms
+Simulation completed
+Simulation Memory Usage: 8892 KB (Peak: 8892 KB)
+Simulation CPU Usage: 78 ms
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt
new file mode 100644
index 0000000..2dfebf2
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "pwm_test_db_behav" "xil_defaultlib.pwm_test_db" -log "elaborate.log" 
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/TempBreakPointFile.txt b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..88991a7
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c
new file mode 100644
index 0000000..73d6575
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c
@@ -0,0 +1,110 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_12(char*, char *);
+IKI_DLLESPEC extern void execute_10(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[5] = {(funcp)execute_11, (funcp)execute_12, (funcp)execute_10, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 5;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc",  (void **)funcTab, 5);
+	iki_vhdl_file_variable_register(dp + 2448);
+	iki_vhdl_file_variable_register(dp + 2504);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc");
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/pwm_test_db_behav/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/pwm_test_db_behav/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/pwm_test_db_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..75fc20c
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg
new file mode 100644
index 0000000..9b603e6
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem
new file mode 100644
index 0000000..656ea6e
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc
new file mode 100644
index 0000000..35bbdbf
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx
new file mode 100644
index 0000000..8d48609
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  13004683983975715120  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , 
+    buildDate : "Oct 19 2021" , 
+    buildTime : "03:16:22" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_behav/xsimk.exe\"   \"xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti
new file mode 100644
index 0000000..5389d0e
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.svtype b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.svtype
new file mode 100644
index 0000000..afe268b
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.svtype differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type
new file mode 100644
index 0000000..e71c3be
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg
new file mode 100644
index 0000000..e0df694
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini
new file mode 100644
index 0000000..f1b6e88
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=156
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=156
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimcrash.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe
new file mode 100644
index 0000000..b585b3d
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
new file mode 100644
index 0000000..41d59c2
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 53560
+Design successfully loaded
+Design Loading Memory Usage: 7816 KB (Peak: 7816 KB)
+Design Loading CPU Usage: 31 ms
+Simulation completed
+Simulation Memory Usage: 16396 KB (Peak: 16396 KB)
+Simulation CPU Usage: 202 ms
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test.vdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test.vdb
new file mode 100644
index 0000000..c21ad38
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test.vdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb
new file mode 100644
index 0000000..ef9aae4
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..42b1486
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,6 @@
+0.7
+2020.2
+Oct 19 2021
+03:16:22
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1647459068,vhdl,,,,pwm_test_db,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1647457989,vhdl,,,,pwm_test,,,,,,,,
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..e8199b2
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000..b155e40
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record

\ No newline at end of file
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/compile.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/compile.bat
new file mode 100644
index 0000000..cfca2da
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/compile.bat
@@ -0,0 +1,30 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Wed Mar 16 20:51:33 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+call xvlog  --incr --relax -prj pwm_test_db_vlog.prj -log xvlog.log
+call type xvlog.log > compile.log
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+call xvhdl  --incr --relax -prj pwm_test_db_vhdl.prj -log xvhdl.log
+call type xvhdl.log >> compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.bat
new file mode 100644
index 0000000..66b4e36
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Wed Mar 16 20:51:37 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+call xelab  --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.log
new file mode 100644
index 0000000..edf13b1
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.log
@@ -0,0 +1,8 @@
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db.tcl b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v
new file mode 100644
index 0000000..aefc624
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v
@@ -0,0 +1,1024 @@
+// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+// Date        : Wed Mar 16 20:26:05 2022
+// Host        : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+// Command     : write_verilog -mode funcsim -nolib -force -file
+//               C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v
+// Design      : pwm_test
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module pwm_test
+   (clk,
+    led);
+  input clk;
+  output led;
+
+  wire clk;
+  wire clk_IBUF;
+  wire clk_IBUF_BUFG;
+  wire \count[0]_i_2_n_0 ;
+  wire [31:0]count_reg;
+  wire \count_reg[0]_i_1_n_0 ;
+  wire \count_reg[0]_i_1_n_1 ;
+  wire \count_reg[0]_i_1_n_2 ;
+  wire \count_reg[0]_i_1_n_3 ;
+  wire \count_reg[0]_i_1_n_4 ;
+  wire \count_reg[0]_i_1_n_5 ;
+  wire \count_reg[0]_i_1_n_6 ;
+  wire \count_reg[0]_i_1_n_7 ;
+  wire \count_reg[12]_i_1_n_0 ;
+  wire \count_reg[12]_i_1_n_1 ;
+  wire \count_reg[12]_i_1_n_2 ;
+  wire \count_reg[12]_i_1_n_3 ;
+  wire \count_reg[12]_i_1_n_4 ;
+  wire \count_reg[12]_i_1_n_5 ;
+  wire \count_reg[12]_i_1_n_6 ;
+  wire \count_reg[12]_i_1_n_7 ;
+  wire \count_reg[16]_i_1_n_0 ;
+  wire \count_reg[16]_i_1_n_1 ;
+  wire \count_reg[16]_i_1_n_2 ;
+  wire \count_reg[16]_i_1_n_3 ;
+  wire \count_reg[16]_i_1_n_4 ;
+  wire \count_reg[16]_i_1_n_5 ;
+  wire \count_reg[16]_i_1_n_6 ;
+  wire \count_reg[16]_i_1_n_7 ;
+  wire \count_reg[20]_i_1_n_0 ;
+  wire \count_reg[20]_i_1_n_1 ;
+  wire \count_reg[20]_i_1_n_2 ;
+  wire \count_reg[20]_i_1_n_3 ;
+  wire \count_reg[20]_i_1_n_4 ;
+  wire \count_reg[20]_i_1_n_5 ;
+  wire \count_reg[20]_i_1_n_6 ;
+  wire \count_reg[20]_i_1_n_7 ;
+  wire \count_reg[24]_i_1_n_0 ;
+  wire \count_reg[24]_i_1_n_1 ;
+  wire \count_reg[24]_i_1_n_2 ;
+  wire \count_reg[24]_i_1_n_3 ;
+  wire \count_reg[24]_i_1_n_4 ;
+  wire \count_reg[24]_i_1_n_5 ;
+  wire \count_reg[24]_i_1_n_6 ;
+  wire \count_reg[24]_i_1_n_7 ;
+  wire \count_reg[28]_i_1_n_1 ;
+  wire \count_reg[28]_i_1_n_2 ;
+  wire \count_reg[28]_i_1_n_3 ;
+  wire \count_reg[28]_i_1_n_4 ;
+  wire \count_reg[28]_i_1_n_5 ;
+  wire \count_reg[28]_i_1_n_6 ;
+  wire \count_reg[28]_i_1_n_7 ;
+  wire \count_reg[4]_i_1_n_0 ;
+  wire \count_reg[4]_i_1_n_1 ;
+  wire \count_reg[4]_i_1_n_2 ;
+  wire \count_reg[4]_i_1_n_3 ;
+  wire \count_reg[4]_i_1_n_4 ;
+  wire \count_reg[4]_i_1_n_5 ;
+  wire \count_reg[4]_i_1_n_6 ;
+  wire \count_reg[4]_i_1_n_7 ;
+  wire \count_reg[8]_i_1_n_0 ;
+  wire \count_reg[8]_i_1_n_1 ;
+  wire \count_reg[8]_i_1_n_2 ;
+  wire \count_reg[8]_i_1_n_3 ;
+  wire \count_reg[8]_i_1_n_4 ;
+  wire \count_reg[8]_i_1_n_5 ;
+  wire \count_reg[8]_i_1_n_6 ;
+  wire \count_reg[8]_i_1_n_7 ;
+  wire led;
+  wire led_OBUF;
+  wire led_reg_i_10_n_0;
+  wire led_reg_i_11_n_0;
+  wire led_reg_i_12_n_0;
+  wire led_reg_i_12_n_1;
+  wire led_reg_i_12_n_2;
+  wire led_reg_i_12_n_3;
+  wire led_reg_i_13_n_0;
+  wire led_reg_i_14_n_0;
+  wire led_reg_i_15_n_0;
+  wire led_reg_i_16_n_0;
+  wire led_reg_i_17_n_0;
+  wire led_reg_i_18_n_0;
+  wire led_reg_i_19_n_0;
+  wire led_reg_i_1_n_0;
+  wire led_reg_i_1_n_1;
+  wire led_reg_i_1_n_2;
+  wire led_reg_i_1_n_3;
+  wire led_reg_i_20_n_0;
+  wire led_reg_i_21_n_0;
+  wire led_reg_i_21_n_1;
+  wire led_reg_i_21_n_2;
+  wire led_reg_i_21_n_3;
+  wire led_reg_i_22_n_0;
+  wire led_reg_i_23_n_0;
+  wire led_reg_i_24_n_0;
+  wire led_reg_i_25_n_0;
+  wire led_reg_i_26_n_0;
+  wire led_reg_i_27_n_0;
+  wire led_reg_i_28_n_0;
+  wire led_reg_i_28_n_1;
+  wire led_reg_i_28_n_2;
+  wire led_reg_i_28_n_3;
+  wire led_reg_i_29_n_0;
+  wire led_reg_i_2_n_0;
+  wire led_reg_i_2_n_1;
+  wire led_reg_i_2_n_2;
+  wire led_reg_i_2_n_3;
+  wire led_reg_i_30_n_0;
+  wire led_reg_i_31_n_0;
+  wire led_reg_i_32_n_0;
+  wire led_reg_i_33_n_0;
+  wire led_reg_i_34_n_0;
+  wire led_reg_i_35_n_0;
+  wire led_reg_i_35_n_1;
+  wire led_reg_i_35_n_2;
+  wire led_reg_i_35_n_3;
+  wire led_reg_i_36_n_0;
+  wire led_reg_i_37_n_0;
+  wire led_reg_i_38_n_0;
+  wire led_reg_i_39_n_0;
+  wire led_reg_i_3_n_0;
+  wire led_reg_i_3_n_1;
+  wire led_reg_i_3_n_2;
+  wire led_reg_i_3_n_3;
+  wire led_reg_i_40_n_0;
+  wire led_reg_i_41_n_0;
+  wire led_reg_i_42_n_0;
+  wire led_reg_i_43_n_0;
+  wire led_reg_i_43_n_1;
+  wire led_reg_i_43_n_2;
+  wire led_reg_i_43_n_3;
+  wire led_reg_i_44_n_0;
+  wire led_reg_i_45_n_0;
+  wire led_reg_i_46_n_0;
+  wire led_reg_i_47_n_0;
+  wire led_reg_i_48_n_0;
+  wire led_reg_i_49_n_0;
+  wire led_reg_i_4_n_0;
+  wire led_reg_i_50_n_0;
+  wire led_reg_i_51_n_0;
+  wire led_reg_i_52_n_0;
+  wire led_reg_i_53_n_0;
+  wire led_reg_i_54_n_0;
+  wire led_reg_i_55_n_0;
+  wire led_reg_i_56_n_0;
+  wire led_reg_i_57_n_0;
+  wire led_reg_i_58_n_0;
+  wire led_reg_i_59_n_0;
+  wire led_reg_i_5_n_0;
+  wire led_reg_i_60_n_0;
+  wire led_reg_i_61_n_0;
+  wire led_reg_i_62_n_0;
+  wire led_reg_i_63_n_0;
+  wire led_reg_i_64_n_0;
+  wire led_reg_i_65_n_0;
+  wire led_reg_i_6_n_0;
+  wire led_reg_i_7_n_0;
+  wire led_reg_i_8_n_0;
+  wire led_reg_i_9_n_0;
+  wire [3:3]\NLW_count_reg[28]_i_1_CO_UNCONNECTED ;
+  wire [3:0]NLW_led_reg_i_1_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_12_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_2_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_21_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_28_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_3_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_35_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_43_O_UNCONNECTED;
+
+  BUFG clk_IBUF_BUFG_inst
+       (.I(clk_IBUF),
+        .O(clk_IBUF_BUFG));
+  IBUF clk_IBUF_inst
+       (.I(clk),
+        .O(clk_IBUF));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \count[0]_i_2 
+       (.I0(count_reg[0]),
+        .O(\count[0]_i_2_n_0 ));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[0] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[0]_i_1_n_7 ),
+        .Q(count_reg[0]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[0]_i_1 
+       (.CI(1'b0),
+        .CO({\count_reg[0]_i_1_n_0 ,\count_reg[0]_i_1_n_1 ,\count_reg[0]_i_1_n_2 ,\count_reg[0]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b1}),
+        .O({\count_reg[0]_i_1_n_4 ,\count_reg[0]_i_1_n_5 ,\count_reg[0]_i_1_n_6 ,\count_reg[0]_i_1_n_7 }),
+        .S({count_reg[3:1],\count[0]_i_2_n_0 }));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[10] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[8]_i_1_n_5 ),
+        .Q(count_reg[10]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[11] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[8]_i_1_n_4 ),
+        .Q(count_reg[11]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[12] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[12]_i_1_n_7 ),
+        .Q(count_reg[12]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[12]_i_1 
+       (.CI(\count_reg[8]_i_1_n_0 ),
+        .CO({\count_reg[12]_i_1_n_0 ,\count_reg[12]_i_1_n_1 ,\count_reg[12]_i_1_n_2 ,\count_reg[12]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[12]_i_1_n_4 ,\count_reg[12]_i_1_n_5 ,\count_reg[12]_i_1_n_6 ,\count_reg[12]_i_1_n_7 }),
+        .S(count_reg[15:12]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[13] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[12]_i_1_n_6 ),
+        .Q(count_reg[13]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[14] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[12]_i_1_n_5 ),
+        .Q(count_reg[14]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[15] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[12]_i_1_n_4 ),
+        .Q(count_reg[15]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[16] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[16]_i_1_n_7 ),
+        .Q(count_reg[16]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[16]_i_1 
+       (.CI(\count_reg[12]_i_1_n_0 ),
+        .CO({\count_reg[16]_i_1_n_0 ,\count_reg[16]_i_1_n_1 ,\count_reg[16]_i_1_n_2 ,\count_reg[16]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[16]_i_1_n_4 ,\count_reg[16]_i_1_n_5 ,\count_reg[16]_i_1_n_6 ,\count_reg[16]_i_1_n_7 }),
+        .S(count_reg[19:16]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[17] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[16]_i_1_n_6 ),
+        .Q(count_reg[17]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[18] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[16]_i_1_n_5 ),
+        .Q(count_reg[18]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[19] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[16]_i_1_n_4 ),
+        .Q(count_reg[19]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[1] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[0]_i_1_n_6 ),
+        .Q(count_reg[1]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[20] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[20]_i_1_n_7 ),
+        .Q(count_reg[20]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[20]_i_1 
+       (.CI(\count_reg[16]_i_1_n_0 ),
+        .CO({\count_reg[20]_i_1_n_0 ,\count_reg[20]_i_1_n_1 ,\count_reg[20]_i_1_n_2 ,\count_reg[20]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[20]_i_1_n_4 ,\count_reg[20]_i_1_n_5 ,\count_reg[20]_i_1_n_6 ,\count_reg[20]_i_1_n_7 }),
+        .S(count_reg[23:20]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[21] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[20]_i_1_n_6 ),
+        .Q(count_reg[21]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[22] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[20]_i_1_n_5 ),
+        .Q(count_reg[22]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[23] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[20]_i_1_n_4 ),
+        .Q(count_reg[23]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[24] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[24]_i_1_n_7 ),
+        .Q(count_reg[24]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[24]_i_1 
+       (.CI(\count_reg[20]_i_1_n_0 ),
+        .CO({\count_reg[24]_i_1_n_0 ,\count_reg[24]_i_1_n_1 ,\count_reg[24]_i_1_n_2 ,\count_reg[24]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[24]_i_1_n_4 ,\count_reg[24]_i_1_n_5 ,\count_reg[24]_i_1_n_6 ,\count_reg[24]_i_1_n_7 }),
+        .S(count_reg[27:24]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[25] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[24]_i_1_n_6 ),
+        .Q(count_reg[25]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[26] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[24]_i_1_n_5 ),
+        .Q(count_reg[26]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[27] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[24]_i_1_n_4 ),
+        .Q(count_reg[27]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[28] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[28]_i_1_n_7 ),
+        .Q(count_reg[28]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[28]_i_1 
+       (.CI(\count_reg[24]_i_1_n_0 ),
+        .CO({\NLW_count_reg[28]_i_1_CO_UNCONNECTED [3],\count_reg[28]_i_1_n_1 ,\count_reg[28]_i_1_n_2 ,\count_reg[28]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[28]_i_1_n_4 ,\count_reg[28]_i_1_n_5 ,\count_reg[28]_i_1_n_6 ,\count_reg[28]_i_1_n_7 }),
+        .S(count_reg[31:28]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[29] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[28]_i_1_n_6 ),
+        .Q(count_reg[29]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[2] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[0]_i_1_n_5 ),
+        .Q(count_reg[2]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[30] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[28]_i_1_n_5 ),
+        .Q(count_reg[30]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[31] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[28]_i_1_n_4 ),
+        .Q(count_reg[31]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[3] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[0]_i_1_n_4 ),
+        .Q(count_reg[3]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[4] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[4]_i_1_n_7 ),
+        .Q(count_reg[4]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[4]_i_1 
+       (.CI(\count_reg[0]_i_1_n_0 ),
+        .CO({\count_reg[4]_i_1_n_0 ,\count_reg[4]_i_1_n_1 ,\count_reg[4]_i_1_n_2 ,\count_reg[4]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[4]_i_1_n_4 ,\count_reg[4]_i_1_n_5 ,\count_reg[4]_i_1_n_6 ,\count_reg[4]_i_1_n_7 }),
+        .S(count_reg[7:4]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[5] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[4]_i_1_n_6 ),
+        .Q(count_reg[5]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[6] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[4]_i_1_n_5 ),
+        .Q(count_reg[6]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[7] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[4]_i_1_n_4 ),
+        .Q(count_reg[7]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[8] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[8]_i_1_n_7 ),
+        .Q(count_reg[8]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[8]_i_1 
+       (.CI(\count_reg[4]_i_1_n_0 ),
+        .CO({\count_reg[8]_i_1_n_0 ,\count_reg[8]_i_1_n_1 ,\count_reg[8]_i_1_n_2 ,\count_reg[8]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[8]_i_1_n_4 ,\count_reg[8]_i_1_n_5 ,\count_reg[8]_i_1_n_6 ,\count_reg[8]_i_1_n_7 }),
+        .S(count_reg[11:8]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[9] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[8]_i_1_n_6 ),
+        .Q(count_reg[9]));
+  OBUF led_OBUF_inst
+       (.I(led_OBUF),
+        .O(led));
+  (* XILINX_LEGACY_PRIM = "LDC" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:GE" *) 
+  LDCE #(
+    .INIT(1'b0)) 
+    led_reg
+       (.CLR(led_reg_i_2_n_0),
+        .D(led_reg_i_1_n_0),
+        .G(led_reg_i_1_n_0),
+        .GE(1'b1),
+        .Q(led_OBUF));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_1
+       (.CI(led_reg_i_3_n_0),
+        .CO({led_reg_i_1_n_0,led_reg_i_1_n_1,led_reg_i_1_n_2,led_reg_i_1_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_4_n_0,led_reg_i_5_n_0,led_reg_i_6_n_0,led_reg_i_7_n_0}),
+        .O(NLW_led_reg_i_1_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_8_n_0,led_reg_i_9_n_0,led_reg_i_10_n_0,led_reg_i_11_n_0}));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_10
+       (.I0(count_reg[26]),
+        .I1(count_reg[27]),
+        .O(led_reg_i_10_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_11
+       (.I0(count_reg[24]),
+        .I1(count_reg[25]),
+        .O(led_reg_i_11_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_12
+       (.CI(led_reg_i_28_n_0),
+        .CO({led_reg_i_12_n_0,led_reg_i_12_n_1,led_reg_i_12_n_2,led_reg_i_12_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_29_n_0,led_reg_i_30_n_0,1'b0,1'b0}),
+        .O(NLW_led_reg_i_12_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_31_n_0,led_reg_i_32_n_0,led_reg_i_33_n_0,led_reg_i_34_n_0}));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_13
+       (.I0(count_reg[30]),
+        .I1(count_reg[31]),
+        .O(led_reg_i_13_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_14
+       (.I0(count_reg[28]),
+        .I1(count_reg[29]),
+        .O(led_reg_i_14_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_15
+       (.I0(count_reg[26]),
+        .I1(count_reg[27]),
+        .O(led_reg_i_15_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_16
+       (.I0(count_reg[24]),
+        .I1(count_reg[25]),
+        .O(led_reg_i_16_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_17
+       (.I0(count_reg[30]),
+        .I1(count_reg[31]),
+        .O(led_reg_i_17_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_18
+       (.I0(count_reg[28]),
+        .I1(count_reg[29]),
+        .O(led_reg_i_18_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_19
+       (.I0(count_reg[26]),
+        .I1(count_reg[27]),
+        .O(led_reg_i_19_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_2
+       (.CI(led_reg_i_12_n_0),
+        .CO({led_reg_i_2_n_0,led_reg_i_2_n_1,led_reg_i_2_n_2,led_reg_i_2_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_13_n_0,led_reg_i_14_n_0,led_reg_i_15_n_0,led_reg_i_16_n_0}),
+        .O(NLW_led_reg_i_2_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_17_n_0,led_reg_i_18_n_0,led_reg_i_19_n_0,led_reg_i_20_n_0}));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_20
+       (.I0(count_reg[24]),
+        .I1(count_reg[25]),
+        .O(led_reg_i_20_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_21
+       (.CI(led_reg_i_35_n_0),
+        .CO({led_reg_i_21_n_0,led_reg_i_21_n_1,led_reg_i_21_n_2,led_reg_i_21_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_36_n_0,led_reg_i_37_n_0,count_reg[11],led_reg_i_38_n_0}),
+        .O(NLW_led_reg_i_21_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_39_n_0,led_reg_i_40_n_0,led_reg_i_41_n_0,led_reg_i_42_n_0}));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_22
+       (.I0(count_reg[22]),
+        .I1(count_reg[23]),
+        .O(led_reg_i_22_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_23
+       (.I0(count_reg[16]),
+        .I1(count_reg[17]),
+        .O(led_reg_i_23_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_24
+       (.I0(count_reg[22]),
+        .I1(count_reg[23]),
+        .O(led_reg_i_24_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_25
+       (.I0(count_reg[20]),
+        .I1(count_reg[21]),
+        .O(led_reg_i_25_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_26
+       (.I0(count_reg[18]),
+        .I1(count_reg[19]),
+        .O(led_reg_i_26_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_27
+       (.I0(count_reg[17]),
+        .I1(count_reg[16]),
+        .O(led_reg_i_27_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_28
+       (.CI(led_reg_i_43_n_0),
+        .CO({led_reg_i_28_n_0,led_reg_i_28_n_1,led_reg_i_28_n_2,led_reg_i_28_n_3}),
+        .CYINIT(1'b0),
+        .DI({count_reg[15],led_reg_i_44_n_0,led_reg_i_45_n_0,led_reg_i_46_n_0}),
+        .O(NLW_led_reg_i_28_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_47_n_0,led_reg_i_48_n_0,led_reg_i_49_n_0,led_reg_i_50_n_0}));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_29
+       (.I0(count_reg[22]),
+        .I1(count_reg[23]),
+        .O(led_reg_i_29_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_3
+       (.CI(led_reg_i_21_n_0),
+        .CO({led_reg_i_3_n_0,led_reg_i_3_n_1,led_reg_i_3_n_2,led_reg_i_3_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_22_n_0,count_reg[21],1'b0,led_reg_i_23_n_0}),
+        .O(NLW_led_reg_i_3_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_24_n_0,led_reg_i_25_n_0,led_reg_i_26_n_0,led_reg_i_27_n_0}));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_30
+       (.I0(count_reg[20]),
+        .I1(count_reg[21]),
+        .O(led_reg_i_30_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_31
+       (.I0(count_reg[22]),
+        .I1(count_reg[23]),
+        .O(led_reg_i_31_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_32
+       (.I0(count_reg[20]),
+        .I1(count_reg[21]),
+        .O(led_reg_i_32_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_33
+       (.I0(count_reg[18]),
+        .I1(count_reg[19]),
+        .O(led_reg_i_33_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_34
+       (.I0(count_reg[16]),
+        .I1(count_reg[17]),
+        .O(led_reg_i_34_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_35
+       (.CI(1'b0),
+        .CO({led_reg_i_35_n_0,led_reg_i_35_n_1,led_reg_i_35_n_2,led_reg_i_35_n_3}),
+        .CYINIT(1'b1),
+        .DI({led_reg_i_51_n_0,led_reg_i_52_n_0,led_reg_i_53_n_0,led_reg_i_54_n_0}),
+        .O(NLW_led_reg_i_35_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_55_n_0,led_reg_i_56_n_0,led_reg_i_57_n_0,led_reg_i_58_n_0}));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_36
+       (.I0(count_reg[14]),
+        .I1(count_reg[15]),
+        .O(led_reg_i_36_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_37
+       (.I0(count_reg[12]),
+        .I1(count_reg[13]),
+        .O(led_reg_i_37_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_38
+       (.I0(count_reg[8]),
+        .I1(count_reg[9]),
+        .O(led_reg_i_38_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_39
+       (.I0(count_reg[15]),
+        .I1(count_reg[14]),
+        .O(led_reg_i_39_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_4
+       (.I0(count_reg[30]),
+        .I1(count_reg[31]),
+        .O(led_reg_i_4_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_40
+       (.I0(count_reg[12]),
+        .I1(count_reg[13]),
+        .O(led_reg_i_40_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_41
+       (.I0(count_reg[10]),
+        .I1(count_reg[11]),
+        .O(led_reg_i_41_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_42
+       (.I0(count_reg[8]),
+        .I1(count_reg[9]),
+        .O(led_reg_i_42_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_43
+       (.CI(1'b0),
+        .CO({led_reg_i_43_n_0,led_reg_i_43_n_1,led_reg_i_43_n_2,led_reg_i_43_n_3}),
+        .CYINIT(1'b1),
+        .DI({count_reg[7],led_reg_i_59_n_0,led_reg_i_60_n_0,led_reg_i_61_n_0}),
+        .O(NLW_led_reg_i_43_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_62_n_0,led_reg_i_63_n_0,led_reg_i_64_n_0,led_reg_i_65_n_0}));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_44
+       (.I0(count_reg[12]),
+        .I1(count_reg[13]),
+        .O(led_reg_i_44_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_45
+       (.I0(count_reg[10]),
+        .I1(count_reg[11]),
+        .O(led_reg_i_45_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_46
+       (.I0(count_reg[8]),
+        .I1(count_reg[9]),
+        .O(led_reg_i_46_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_47
+       (.I0(count_reg[14]),
+        .I1(count_reg[15]),
+        .O(led_reg_i_47_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_48
+       (.I0(count_reg[12]),
+        .I1(count_reg[13]),
+        .O(led_reg_i_48_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_49
+       (.I0(count_reg[10]),
+        .I1(count_reg[11]),
+        .O(led_reg_i_49_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_5
+       (.I0(count_reg[28]),
+        .I1(count_reg[29]),
+        .O(led_reg_i_5_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_50
+       (.I0(count_reg[9]),
+        .I1(count_reg[8]),
+        .O(led_reg_i_50_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_51
+       (.I0(count_reg[6]),
+        .I1(count_reg[7]),
+        .O(led_reg_i_51_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_52
+       (.I0(count_reg[4]),
+        .I1(count_reg[5]),
+        .O(led_reg_i_52_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_53
+       (.I0(count_reg[2]),
+        .I1(count_reg[3]),
+        .O(led_reg_i_53_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_54
+       (.I0(count_reg[0]),
+        .I1(count_reg[1]),
+        .O(led_reg_i_54_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_55
+       (.I0(count_reg[7]),
+        .I1(count_reg[6]),
+        .O(led_reg_i_55_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_56
+       (.I0(count_reg[4]),
+        .I1(count_reg[5]),
+        .O(led_reg_i_56_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_57
+       (.I0(count_reg[2]),
+        .I1(count_reg[3]),
+        .O(led_reg_i_57_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_58
+       (.I0(count_reg[0]),
+        .I1(count_reg[1]),
+        .O(led_reg_i_58_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_59
+       (.I0(count_reg[4]),
+        .I1(count_reg[5]),
+        .O(led_reg_i_59_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_6
+       (.I0(count_reg[26]),
+        .I1(count_reg[27]),
+        .O(led_reg_i_6_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_60
+       (.I0(count_reg[2]),
+        .I1(count_reg[3]),
+        .O(led_reg_i_60_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_61
+       (.I0(count_reg[0]),
+        .I1(count_reg[1]),
+        .O(led_reg_i_61_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_62
+       (.I0(count_reg[6]),
+        .I1(count_reg[7]),
+        .O(led_reg_i_62_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_63
+       (.I0(count_reg[4]),
+        .I1(count_reg[5]),
+        .O(led_reg_i_63_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_64
+       (.I0(count_reg[2]),
+        .I1(count_reg[3]),
+        .O(led_reg_i_64_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_65
+       (.I0(count_reg[0]),
+        .I1(count_reg[1]),
+        .O(led_reg_i_65_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_7
+       (.I0(count_reg[24]),
+        .I1(count_reg[25]),
+        .O(led_reg_i_7_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_8
+       (.I0(count_reg[30]),
+        .I1(count_reg[31]),
+        .O(led_reg_i_8_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_9
+       (.I0(count_reg[28]),
+        .I1(count_reg[29]),
+        .O(led_reg_i_9_n_0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.wdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.wdb
new file mode 100644
index 0000000..d8f570c
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.wdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.bat
new file mode 100644
index 0000000..ba5eaf4
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Wed Mar 16 20:17:55 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim pwm_test_db_func_synth -key {Post-Synthesis:sim_1:Functional:pwm_test_db} -tclbatch pwm_test_db.tcl -log simulate.log"
+call xsim  pwm_test_db_func_synth -key {Post-Synthesis:sim_1:Functional:pwm_test_db} -tclbatch pwm_test_db.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.log
new file mode 100644
index 0000000..3a14ee6
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xelab.pb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xelab.pb
new file mode 100644
index 0000000..f7d526c
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xelab.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/Compile_Options.txt b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/Compile_Options.txt
new file mode 100644
index 0000000..7da51e8
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "pwm_test_db_func_synth" "xil_defaultlib.pwm_test_db" "xil_defaultlib.glbl" -log "elaborate.log" 
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/TempBreakPointFile.txt b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_0.win64.obj b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..1c0621d
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_0.win64.obj differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.c b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.c
new file mode 100644
index 0000000..587a597
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.c
@@ -0,0 +1,376 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_2(char*, char *);
+IKI_DLLESPEC extern void execute_3(char*, char *);
+IKI_DLLESPEC extern void execute_4(char*, char *);
+IKI_DLLESPEC extern void execute_5(char*, char *);
+IKI_DLLESPEC extern void execute_6(char*, char *);
+IKI_DLLESPEC extern void execute_7(char*, char *);
+IKI_DLLESPEC extern void execute_8(char*, char *);
+IKI_DLLESPEC extern void execute_9(char*, char *);
+IKI_DLLESPEC extern void execute_10(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_347(char*, char *);
+IKI_DLLESPEC extern void execute_348(char*, char *);
+IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
+IKI_DLLESPEC extern void execute_933(char*, char *);
+IKI_DLLESPEC extern void execute_938(char*, char *);
+IKI_DLLESPEC extern void execute_944(char*, char *);
+IKI_DLLESPEC extern void execute_951(char*, char *);
+IKI_DLLESPEC extern void execute_957(char*, char *);
+IKI_DLLESPEC extern void execute_963(char*, char *);
+IKI_DLLESPEC extern void execute_971(char*, char *);
+IKI_DLLESPEC extern void execute_977(char*, char *);
+IKI_DLLESPEC extern void execute_982(char*, char *);
+IKI_DLLESPEC extern void execute_987(char*, char *);
+IKI_DLLESPEC extern void execute_351(char*, char *);
+IKI_DLLESPEC extern void execute_21(char*, char *);
+IKI_DLLESPEC extern void execute_352(char*, char *);
+IKI_DLLESPEC extern void execute_24(char*, char *);
+IKI_DLLESPEC extern void execute_354(char*, char *);
+IKI_DLLESPEC extern void execute_355(char*, char *);
+IKI_DLLESPEC extern void execute_353(char*, char *);
+IKI_DLLESPEC extern void execute_26(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_356(char*, char *);
+IKI_DLLESPEC extern void execute_357(char*, char *);
+IKI_DLLESPEC extern void execute_358(char*, char *);
+IKI_DLLESPEC extern void execute_359(char*, char *);
+IKI_DLLESPEC extern void execute_360(char*, char *);
+IKI_DLLESPEC extern void execute_361(char*, char *);
+IKI_DLLESPEC extern void execute_362(char*, char *);
+IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
+IKI_DLLESPEC extern void execute_365(char*, char *);
+IKI_DLLESPEC extern void execute_366(char*, char *);
+IKI_DLLESPEC extern void execute_367(char*, char *);
+IKI_DLLESPEC extern void execute_368(char*, char *);
+IKI_DLLESPEC extern void execute_162(char*, char *);
+IKI_DLLESPEC extern void execute_556(char*, char *);
+IKI_DLLESPEC extern void execute_557(char*, char *);
+IKI_DLLESPEC extern void execute_558(char*, char *);
+IKI_DLLESPEC extern void execute_164(char*, char *);
+IKI_DLLESPEC extern void execute_166(char*, char *);
+IKI_DLLESPEC extern void execute_167(char*, char *);
+IKI_DLLESPEC extern void execute_559(char*, char *);
+IKI_DLLESPEC extern void execute_560(char*, char *);
+IKI_DLLESPEC extern void execute_561(char*, char *);
+IKI_DLLESPEC extern void execute_562(char*, char *);
+IKI_DLLESPEC extern void execute_564(char*, char *);
+IKI_DLLESPEC extern void execute_565(char*, char *);
+IKI_DLLESPEC extern void execute_566(char*, char *);
+IKI_DLLESPEC extern void execute_569(char*, char *);
+IKI_DLLESPEC extern void execute_570(char*, char *);
+IKI_DLLESPEC extern void execute_571(char*, char *);
+IKI_DLLESPEC extern void execute_572(char*, char *);
+IKI_DLLESPEC extern void execute_568(char*, char *);
+IKI_DLLESPEC extern void execute_171(char*, char *);
+IKI_DLLESPEC extern void execute_583(char*, char *);
+IKI_DLLESPEC extern void execute_584(char*, char *);
+IKI_DLLESPEC extern void execute_585(char*, char *);
+IKI_DLLESPEC extern void execute_586(char*, char *);
+IKI_DLLESPEC extern void execute_582(char*, char *);
+IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_47(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_48(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_49(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_50(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_53(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_55(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_56(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_70(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_71(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_73(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_74(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_75(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_76(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_84(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_85(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_86(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_87(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_88(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_89(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_90(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_91(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_92(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_93(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_94(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_95(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_96(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_97(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_98(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_99(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_100(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_101(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_102(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_103(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_104(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_105(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_106(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_107(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_108(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_109(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_110(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_111(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_112(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_113(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_114(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_115(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_116(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_123(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_124(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_125(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_126(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_127(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_130(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_131(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_132(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_133(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_134(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_135(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_136(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_137(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_139(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_140(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_141(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_142(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_144(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_145(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_146(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_147(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_148(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_149(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_150(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_151(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_152(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_153(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_154(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_155(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_156(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_157(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_158(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_159(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_160(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_161(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_162(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_163(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_164(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_166(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_167(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_168(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_169(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_173(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_174(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_175(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_176(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_177(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_178(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_179(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_180(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_181(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_182(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_183(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_184(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_185(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_186(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_187(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_188(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_189(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_190(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_191(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_216(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_334(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_348(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_354(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_366(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_372(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_386(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_392(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_398(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_418(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_424(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_430(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_436(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_450(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_456(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_462(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_468(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_474(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_480(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_494(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_500(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_506(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_512(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_526(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[260] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_347, (funcp)execute_348, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_933, (funcp)execute_938, (funcp)execute_944, (funcp)execute_951, (funcp)execute_957, (funcp)execute_963, (funcp)execute_971, (funcp)execute_977, (funcp)execute_982, (funcp)execute_987, (funcp)execute_351, (funcp)execute_21, (funcp)execute_352, (funcp)execute_24, (funcp)execute_354, (funcp)execute_355, (funcp)execute_353, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_356, (funcp)execute_357, (funcp)execute_358, (funcp)execute_359, (funcp)execute_360, (funcp)execute_361, (funcp)execute_362, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_365, (funcp)execute_366, (funcp)execute_367, (funcp)execute_368, (funcp)execute_162, (funcp)execute_556, (funcp)execute_557, (funcp)execute_558, (funcp)execute_164, (funcp)execute_166, (funcp)execute_167, (funcp)execute_559, (funcp)execute_560, (funcp)execute_561, (funcp)execute_562, (funcp)execute_564, (funcp)execute_565, (funcp)execute_566, (funcp)execute_569, (funcp)execute_570, (funcp)execute_571, (funcp)execute_572, (funcp)execute_568, (funcp)execute_171, (funcp)execute_583, (funcp)execute_584, (funcp)execute_585, (funcp)execute_586, (funcp)execute_582, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)transaction_46, (funcp)transaction_47, (funcp)transaction_48, (funcp)transaction_49, (funcp)transaction_50, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_53, (funcp)transaction_54, (funcp)transaction_55, (funcp)transaction_56, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_70, (funcp)transaction_71, (funcp)transaction_72, (funcp)transaction_73, (funcp)transaction_74, (funcp)transaction_75, (funcp)transaction_76, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_84, (funcp)transaction_85, (funcp)transaction_86, (funcp)transaction_87, (funcp)transaction_88, (funcp)transaction_89, (funcp)transaction_90, (funcp)transaction_91, (funcp)transaction_92, (funcp)transaction_93, (funcp)transaction_94, (funcp)transaction_95, (funcp)transaction_96, (funcp)transaction_97, (funcp)transaction_98, (funcp)transaction_99, (funcp)transaction_100, (funcp)transaction_101, (funcp)transaction_102, (funcp)transaction_103, (funcp)transaction_104, (funcp)transaction_105, (funcp)transaction_106, (funcp)transaction_107, (funcp)transaction_108, (funcp)transaction_109, (funcp)transaction_110, (funcp)transaction_111, (funcp)transaction_112, (funcp)transaction_113, (funcp)transaction_114, (funcp)transaction_115, (funcp)transaction_116, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_123, (funcp)transaction_124, (funcp)transaction_125, (funcp)transaction_126, (funcp)transaction_127, (funcp)transaction_130, (funcp)transaction_131, (funcp)transaction_132, (funcp)transaction_133, (funcp)transaction_134, (funcp)transaction_135, (funcp)transaction_136, (funcp)transaction_137, (funcp)transaction_139, (funcp)transaction_140, (funcp)transaction_141, (funcp)transaction_142, (funcp)transaction_144, (funcp)transaction_145, (funcp)transaction_146, (funcp)transaction_147, (funcp)transaction_148, (funcp)transaction_149, (funcp)transaction_150, (funcp)transaction_151, (funcp)transaction_152, (funcp)transaction_153, (funcp)transaction_154, (funcp)transaction_155, (funcp)transaction_156, (funcp)transaction_157, (funcp)transaction_158, (funcp)transaction_159, (funcp)transaction_160, (funcp)transaction_161, (funcp)transaction_162, (funcp)transaction_163, (funcp)transaction_164, (funcp)transaction_165, (funcp)transaction_166, (funcp)transaction_167, (funcp)transaction_168, (funcp)transaction_169, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_173, (funcp)transaction_174, (funcp)transaction_175, (funcp)transaction_176, (funcp)transaction_177, (funcp)transaction_178, (funcp)transaction_179, (funcp)transaction_180, (funcp)transaction_181, (funcp)transaction_182, (funcp)transaction_183, (funcp)transaction_184, (funcp)transaction_185, (funcp)transaction_186, (funcp)transaction_187, (funcp)transaction_188, (funcp)transaction_189, (funcp)transaction_190, (funcp)transaction_191, (funcp)transaction_192, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_216, (funcp)transaction_275, (funcp)transaction_290, (funcp)transaction_296, (funcp)transaction_302, (funcp)transaction_316, (funcp)transaction_322, (funcp)transaction_328, (funcp)transaction_334, (funcp)transaction_348, (funcp)transaction_354, (funcp)transaction_360, (funcp)transaction_366, (funcp)transaction_372, (funcp)transaction_386, (funcp)transaction_392, (funcp)transaction_398, (funcp)transaction_404, (funcp)transaction_418, (funcp)transaction_424, (funcp)transaction_430, (funcp)transaction_436, (funcp)transaction_450, (funcp)transaction_456, (funcp)transaction_462, (funcp)transaction_468, (funcp)transaction_474, (funcp)transaction_480, (funcp)transaction_494, (funcp)transaction_500, (funcp)transaction_506, (funcp)transaction_512, (funcp)transaction_526};
+const int NumRelocateId= 260;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/pwm_test_db_func_synth/xsim.reloc",  (void **)funcTab, 260);
+	iki_vhdl_file_variable_register(dp + 201296);
+	iki_vhdl_file_variable_register(dp + 201352);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/pwm_test_db_func_synth/xsim.reloc");
+}
+
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+
+void wrapper_func_0(char *dp)
+
+{
+
+	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 206376, dp + 206832, 0, 0, 0, 0, 1, 1);
+
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/pwm_test_db_func_synth/xsim.reloc");
+	wrapper_func_0(dp);
+
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/pwm_test_db_func_synth/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/pwm_test_db_func_synth/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/pwm_test_db_func_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.win64.obj b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..7c5181d
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.win64.obj differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.dbg b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.dbg
new file mode 100644
index 0000000..e242c94
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.dbg differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.mem b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.mem
new file mode 100644
index 0000000..a72c31e
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.mem differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.reloc b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.reloc
new file mode 100644
index 0000000..b7ff7ca
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.reloc differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rlx b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rlx
new file mode 100644
index 0000000..09683a8
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  9113727300305093394  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl" , 
+    buildDate : "Oct 19 2021" , 
+    buildTime : "03:16:22" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_func_synth/xsimk.exe\"   \"xsim.dir/pwm_test_db_func_synth/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_func_synth/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rtti b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rtti
new file mode 100644
index 0000000..265f971
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rtti differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.svtype b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.svtype
new file mode 100644
index 0000000..99e2679
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.svtype differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.type b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.type
new file mode 100644
index 0000000..2eb74e4
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.type differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.xdbg b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.xdbg
new file mode 100644
index 0000000..91656bd
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.xdbg differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimSettings.ini b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimSettings.ini
new file mode 100644
index 0000000..bfb3c44
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=210
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimcrash.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimk.exe b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimk.exe
new file mode 100644
index 0000000..bbe8b79
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimk.exe differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimkernel.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimkernel.log
new file mode 100644
index 0000000..e166472
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/pwm_test_db_func_synth/xsimk.exe -simmode gui -wdb pwm_test_db_func_synth.wdb -simrunnum 0 -socket 49911
+Design successfully loaded
+Design Loading Memory Usage: 8300 KB (Peak: 8300 KB)
+Design Loading CPU Usage: 0 ms
+Simulation completed
+Simulation Memory Usage: 9176 KB (Peak: 9176 KB)
+Simulation CPU Usage: 15 ms
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb
new file mode 100644
index 0000000..663ff15
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb
new file mode 100644
index 0000000..10ea637
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb
new file mode 100644
index 0000000..3ac8021
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..2731f62
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,6 @@
+0.7
+2020.2
+Oct 19 2021
+03:16:22
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v,1647458765,verilog,,,,glbl;pwm_test,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1647459068,vhdl,,,,pwm_test_db,,,,,,,,
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.ini b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.ini
new file mode 100644
index 0000000..e8199b2
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.log
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.pb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.pb
new file mode 100644
index 0000000..b155e40
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record

\ No newline at end of file
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.log
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.pb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.pb
new file mode 100644
index 0000000..b155e40
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record

\ No newline at end of file
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/.usf.tcl_error.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/.usf.tcl_error.log
new file mode 100644
index 0000000..30e81d1
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/.usf.tcl_error.log
@@ -0,0 +1,15 @@
+********************************************************************************
+* Unified simulation Tcl App stack trace dump
+*
+* File: .usf.tcl_error.log (Wed Mar 16 21:02:12 2022)
+*
+* This file is generated by the unified simulation automation and contains the
+* tcl stack trace of error returned by the simulator App for the current run.
+*
+********************************************************************************
+1
+    while executing
+"catch {eval "xsim $cmd_args"} err_msg"
+    (procedure "tclapp::xilinx::xsim::simulate" line 178)
+    invoked from within
+"tclapp::xilinx::xsim::simulate { -simset sim_1 -mode post-synthesis -type timing -run_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/..."
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.bat
new file mode 100644
index 0000000..9642207
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.bat
@@ -0,0 +1,30 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Wed Mar 16 20:54:19 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+call xvlog  --incr --relax -prj pwm_test_db_vlog.prj -log xvlog.log
+call type xvlog.log > compile.log
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+call xvhdl  --incr --relax -prj pwm_test_db_vhdl.prj -log xvhdl.log
+call type xvhdl.log >> compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.log
new file mode 100644
index 0000000..d427ec6
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.log
@@ -0,0 +1,5 @@
+INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module pwm_test
+INFO: [VRFC 10-311] analyzing module glbl
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.bat
new file mode 100644
index 0000000..f6ec502
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Wed Mar 16 20:54:23 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+call xelab  --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.log
new file mode 100644
index 0000000..d3c6e77
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.log
@@ -0,0 +1,31 @@
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut".
+INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut".
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package vl.vl_types
+Compiling module xil_defaultlib.glbl
+Compiling module simprims_ver.BUFG
+Compiling module simprims_ver.IBUF
+Compiling module simprims_ver.x_lut1_mux2
+Compiling module simprims_ver.LUT1(INIT=2'b01)
+Compiling module simprims_ver.FDCE_default
+Compiling module simprims_ver.CARRY4
+Compiling module simprims_ver.OBUF
+Compiling module simprims_ver.latchsre_ldce
+Compiling module simprims_ver.LDCE
+Compiling module simprims_ver.x_lut2_mux4
+Compiling module simprims_ver.LUT2
+Compiling module xil_defaultlib.pwm_test
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_time_synth
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db.tcl b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db.tcl
new file mode 100644
index 0000000..35691cf
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 5000 ms
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf
new file mode 100644
index 0000000..d4abca3
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf
@@ -0,0 +1,2344 @@
+(DELAYFILE 
+(SDFVERSION "3.0" )
+(DESIGN "pwm_test")
+(DATE "Wed Mar 16 20:54:19 2022")
+(VENDOR "XILINX")
+(PROGRAM "Vivado")
+(VERSION "2021.2")
+(DIVIDER /)
+(TIMESCALE 1ps)
+(CELL 
+  (CELLTYPE "BUFG")
+  (INSTANCE clk_IBUF_BUFG_inst)
+  (DELAY 
+    (PATHPULSE (50.0))
+    (ABSOLUTE 
+      (IOPATH I O (91.0:101.0:101.0) (91.0:101.0:101.0))
+    )
+  )
+)
+(CELL 
+  (CELLTYPE "IBUF")
+  (INSTANCE clk_IBUF_inst)
+  (DELAY 
+    (PATHPULSE (50.0))
+    (ABSOLUTE 
+      (IOPATH I O (848.7:982.4:982.4) (848.7:982.4:982.4))
+    )
+  )
+)
+(CELL 
+  (CELLTYPE "LUT1")
+  (INSTANCE count\[0\]_i_2)
+  (DELAY 
+    (PATHPULSE (50.0))
+    (ABSOLUTE 
+      (IOPATH I0 O (100.0:124.0:124.0) (100.0:124.0:124.0))
+    )
+  )
+)
+(CELL 
+  (CELLTYPE "FDCE")
+  (INSTANCE count_reg\[0\])
+  (DELAY 
+    (ABSOLUTE 
+      (IOPATH (posedge CLR) Q (662.0:821.0:821.0))
+      (IOPATH C Q (274.0:340.0:340.0) (274.0:340.0:340.0))
+    )
+  )
+    (TIMINGCHECK
+      (SETUPHOLD (posedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (SETUPHOLD (negedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (RECREM (negedge CLR) (posedge C) (326.0:404.0:404.0) (-248.0:-248.0:-248.0))
+      (SETUPHOLD (posedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
+      (SETUPHOLD (negedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
+    )
+)
+(CELL 
+  (CELLTYPE "CARRY4")
+  (INSTANCE count_reg\[0\]_i_1)
+  (DELAY 
+    (PATHPULSE (50.0))
+    (ABSOLUTE 
+      (IOPATH CYINIT O[0] (385.0:491.0:491.0) (385.0:491.0:491.0))
+      (IOPATH CI O[0] (150.0:235.0:235.0) (150.0:235.0:235.0))
+      (IOPATH S[0] O[0] (170.0:223.0:223.0) (170.0:223.0:223.0))
+      (IOPATH S[1] O[1] (156.0:205.0:205.0) (156.0:205.0:205.0))
+      (IOPATH S[0] O[1] (304.0:400.0:400.0) (304.0:400.0:400.0))
+      (IOPATH CYINIT O[1] (482.0:613.0:613.0) (482.0:613.0:613.0))
+      (IOPATH CI O[1] (269.0:348.0:348.0) (269.0:348.0:348.0))
+      (IOPATH DI[0] O[1] (256.0:420.0:420.0) (256.0:420.0:420.0))
+      (IOPATH S[2] O[2] (171.0:226.0:226.0) (171.0:226.0:226.0))
+      (IOPATH S[1] O[2] (424.0:558.0:558.0) (424.0:558.0:558.0))
+      (IOPATH S[0] O[2] (398.0:523.0:523.0) (398.0:523.0:523.0))
+      (IOPATH DI[1] O[2] (358.0:554.0:554.0) (358.0:554.0:554.0))
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+      (IOPATH C Q (274.0:340.0:340.0) (274.0:340.0:340.0))
+    )
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+      (SETUPHOLD (negedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (RECREM (negedge CLR) (posedge C) (326.0:404.0:404.0) (-248.0:-248.0:-248.0))
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+      (IOPATH C Q (274.0:340.0:340.0) (274.0:340.0:340.0))
+    )
+  )
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+      (SETUPHOLD (posedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (SETUPHOLD (negedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (RECREM (negedge CLR) (posedge C) (326.0:404.0:404.0) (-248.0:-248.0:-248.0))
+      (SETUPHOLD (posedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
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+    )
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+    (ABSOLUTE 
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+      (IOPATH C Q (274.0:340.0:340.0) (274.0:340.0:340.0))
+    )
+  )
+    (TIMINGCHECK
+      (SETUPHOLD (posedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (SETUPHOLD (negedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (RECREM (negedge CLR) (posedge C) (326.0:404.0:404.0) (-248.0:-248.0:-248.0))
+      (SETUPHOLD (posedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
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+    )
+)
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+    )
+  )
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+    (ABSOLUTE 
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+      (IOPATH C Q (274.0:340.0:340.0) (274.0:340.0:340.0))
+    )
+  )
+    (TIMINGCHECK
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+      (SETUPHOLD (negedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (RECREM (negedge CLR) (posedge C) (326.0:404.0:404.0) (-248.0:-248.0:-248.0))
+      (SETUPHOLD (posedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
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+    )
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+  (DELAY 
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+      (IOPATH C Q (274.0:340.0:340.0) (274.0:340.0:340.0))
+    )
+  )
+    (TIMINGCHECK
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+      (SETUPHOLD (negedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (RECREM (negedge CLR) (posedge C) (326.0:404.0:404.0) (-248.0:-248.0:-248.0))
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+    )
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+      (IOPATH C Q (274.0:340.0:340.0) (274.0:340.0:340.0))
+    )
+  )
+    (TIMINGCHECK
+      (SETUPHOLD (posedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (SETUPHOLD (negedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (RECREM (negedge CLR) (posedge C) (326.0:404.0:404.0) (-248.0:-248.0:-248.0))
+      (SETUPHOLD (posedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
+      (SETUPHOLD (negedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
+    )
+)
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+      (IOPATH C Q (274.0:340.0:340.0) (274.0:340.0:340.0))
+    )
+  )
+    (TIMINGCHECK
+      (SETUPHOLD (posedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (SETUPHOLD (negedge CE) (posedge C) (88.0:109.0:109.0) (-9.0:-9.0:-9.0))
+      (RECREM (negedge CLR) (posedge C) (326.0:404.0:404.0) (-248.0:-248.0:-248.0))
+      (SETUPHOLD (posedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
+      (SETUPHOLD (negedge D) (posedge C) (-55.0:-45.0:-45.0) (241.0:241.0:241.0))
+    )
+)
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+    (PATHPULSE (50.0))
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+  )
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+    )
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+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[17\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[18\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
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+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[24\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[25\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[26\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
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+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[31\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[3\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[4\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[5\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[6\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[7\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[8\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[9\]/C (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT clk_IBUF_inst/O clk_IBUF_BUFG_inst/I (759.7:799.7:799.7) (759.7:799.7:799.7))
+      (INTERCONNECT count\[0\]_i_2/O count_reg\[0\]_i_1/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT count_reg\[0\]/Q count\[0\]_i_2/I0 (282.1:297.0:297.0) (282.1:297.0:297.0))
+      (INTERCONNECT count_reg\[0\]/Q led_reg_i_54/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[0\]/Q led_reg_i_58/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[0\]/Q led_reg_i_61/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[0\]/Q led_reg_i_65/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[0\]_i_1/CO[3] count_reg\[4\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT count_reg\[0\]_i_1/O[3] count_reg\[3\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[0\]_i_1/O[2] count_reg\[2\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[0\]_i_1/O[1] count_reg\[1\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[0\]_i_1/O[0] count_reg\[0\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[10\]/Q led_reg_i_41/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[10\]/Q led_reg_i_45/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[10\]/Q led_reg_i_49/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[10\]/Q count_reg\[8\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0))
+      (INTERCONNECT count_reg\[11\]/Q led_reg_i_21/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0))
+      (INTERCONNECT count_reg\[11\]/Q led_reg_i_41/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[11\]/Q led_reg_i_45/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[11\]/Q led_reg_i_49/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[11\]/Q count_reg\[8\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0))
+      (INTERCONNECT count_reg\[12\]/Q led_reg_i_37/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[12\]/Q led_reg_i_40/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[12\]/Q led_reg_i_44/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[12\]/Q led_reg_i_48/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[12\]/Q count_reg\[12\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0))
+      (INTERCONNECT count_reg\[12\]_i_1/CO[3] count_reg\[16\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT count_reg\[12\]_i_1/O[3] count_reg\[15\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[12\]_i_1/O[2] count_reg\[14\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[12\]_i_1/O[1] count_reg\[13\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[12\]_i_1/O[0] count_reg\[12\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[13\]/Q led_reg_i_37/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[13\]/Q led_reg_i_40/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[13\]/Q led_reg_i_44/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[13\]/Q led_reg_i_48/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[13\]/Q count_reg\[12\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0))
+      (INTERCONNECT count_reg\[14\]/Q led_reg_i_36/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[14\]/Q led_reg_i_47/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[14\]/Q led_reg_i_39/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[14\]/Q count_reg\[12\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0))
+      (INTERCONNECT count_reg\[15\]/Q led_reg_i_28/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0))
+      (INTERCONNECT count_reg\[15\]/Q led_reg_i_39/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[15\]/Q led_reg_i_36/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[15\]/Q led_reg_i_47/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[15\]/Q count_reg\[12\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0))
+      (INTERCONNECT count_reg\[16\]/Q led_reg_i_23/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[16\]/Q led_reg_i_34/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[16\]/Q led_reg_i_27/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[16\]/Q count_reg\[16\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0))
+      (INTERCONNECT count_reg\[16\]_i_1/CO[3] count_reg\[20\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT count_reg\[16\]_i_1/O[3] count_reg\[19\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[16\]_i_1/O[2] count_reg\[18\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[16\]_i_1/O[1] count_reg\[17\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[16\]_i_1/O[0] count_reg\[16\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[17\]/Q led_reg_i_27/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[17\]/Q led_reg_i_23/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[17\]/Q led_reg_i_34/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[17\]/Q count_reg\[16\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0))
+      (INTERCONNECT count_reg\[18\]/Q led_reg_i_26/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[18\]/Q led_reg_i_33/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[18\]/Q count_reg\[16\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0))
+      (INTERCONNECT count_reg\[19\]/Q led_reg_i_26/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[19\]/Q led_reg_i_33/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[19\]/Q count_reg\[16\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0))
+      (INTERCONNECT count_reg\[1\]/Q led_reg_i_54/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[1\]/Q led_reg_i_58/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[1\]/Q led_reg_i_61/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[1\]/Q led_reg_i_65/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[1\]/Q count_reg\[0\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0))
+      (INTERCONNECT count_reg\[20\]/Q led_reg_i_25/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[20\]/Q led_reg_i_30/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[20\]/Q led_reg_i_32/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[20\]/Q count_reg\[20\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0))
+      (INTERCONNECT count_reg\[20\]_i_1/CO[3] count_reg\[24\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT count_reg\[20\]_i_1/O[3] count_reg\[23\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[20\]_i_1/O[2] count_reg\[22\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[20\]_i_1/O[1] count_reg\[21\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[20\]_i_1/O[0] count_reg\[20\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[21\]/Q led_reg_i_3/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0))
+      (INTERCONNECT count_reg\[21\]/Q led_reg_i_25/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[21\]/Q led_reg_i_30/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[21\]/Q led_reg_i_32/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[21\]/Q count_reg\[20\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0))
+      (INTERCONNECT count_reg\[22\]/Q led_reg_i_22/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[22\]/Q led_reg_i_24/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[22\]/Q led_reg_i_29/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[22\]/Q led_reg_i_31/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[22\]/Q count_reg\[20\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0))
+      (INTERCONNECT count_reg\[23\]/Q led_reg_i_22/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[23\]/Q led_reg_i_24/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[23\]/Q led_reg_i_29/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[23\]/Q led_reg_i_31/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[23\]/Q count_reg\[20\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0))
+      (INTERCONNECT count_reg\[24\]/Q led_reg_i_11/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[24\]/Q led_reg_i_16/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[24\]/Q led_reg_i_20/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[24\]/Q led_reg_i_7/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[24\]/Q count_reg\[24\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0))
+      (INTERCONNECT count_reg\[24\]_i_1/CO[3] count_reg\[28\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT count_reg\[24\]_i_1/O[3] count_reg\[27\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[24\]_i_1/O[2] count_reg\[26\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[24\]_i_1/O[1] count_reg\[25\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[24\]_i_1/O[0] count_reg\[24\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[25\]/Q led_reg_i_11/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[25\]/Q led_reg_i_16/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[25\]/Q led_reg_i_20/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[25\]/Q led_reg_i_7/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[25\]/Q count_reg\[24\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0))
+      (INTERCONNECT count_reg\[26\]/Q led_reg_i_10/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[26\]/Q led_reg_i_15/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[26\]/Q led_reg_i_19/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[26\]/Q led_reg_i_6/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[26\]/Q count_reg\[24\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0))
+      (INTERCONNECT count_reg\[27\]/Q led_reg_i_10/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[27\]/Q led_reg_i_15/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[27\]/Q led_reg_i_19/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[27\]/Q led_reg_i_6/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[27\]/Q count_reg\[24\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0))
+      (INTERCONNECT count_reg\[28\]/Q led_reg_i_14/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[28\]/Q led_reg_i_18/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[28\]/Q led_reg_i_5/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[28\]/Q led_reg_i_9/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[28\]/Q count_reg\[28\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0))
+      (INTERCONNECT count_reg\[28\]_i_1/O[3] count_reg\[31\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[28\]_i_1/O[2] count_reg\[30\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[28\]_i_1/O[1] count_reg\[29\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[28\]_i_1/O[0] count_reg\[28\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[29\]/Q led_reg_i_14/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[29\]/Q led_reg_i_18/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[29\]/Q led_reg_i_5/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[29\]/Q led_reg_i_9/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[29\]/Q count_reg\[28\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0))
+      (INTERCONNECT count_reg\[2\]/Q led_reg_i_53/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[2\]/Q led_reg_i_57/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[2\]/Q led_reg_i_60/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[2\]/Q led_reg_i_64/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[2\]/Q count_reg\[0\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0))
+      (INTERCONNECT count_reg\[30\]/Q led_reg_i_13/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[30\]/Q led_reg_i_17/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[30\]/Q led_reg_i_4/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[30\]/Q led_reg_i_8/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[30\]/Q count_reg\[28\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0))
+      (INTERCONNECT count_reg\[31\]/Q led_reg_i_13/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[31\]/Q led_reg_i_17/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[31\]/Q led_reg_i_4/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[31\]/Q led_reg_i_8/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[31\]/Q count_reg\[28\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0))
+      (INTERCONNECT count_reg\[3\]/Q led_reg_i_53/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[3\]/Q led_reg_i_57/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[3\]/Q led_reg_i_60/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[3\]/Q led_reg_i_64/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[3\]/Q count_reg\[0\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0))
+      (INTERCONNECT count_reg\[4\]/Q led_reg_i_52/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[4\]/Q led_reg_i_56/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[4\]/Q led_reg_i_59/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[4\]/Q led_reg_i_63/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[4\]/Q count_reg\[4\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0))
+      (INTERCONNECT count_reg\[4\]_i_1/CO[3] count_reg\[8\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT count_reg\[4\]_i_1/O[3] count_reg\[7\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
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+      (INTERCONNECT count_reg\[5\]/Q led_reg_i_52/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[5\]/Q led_reg_i_56/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[5\]/Q led_reg_i_59/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[5\]/Q led_reg_i_63/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[5\]/Q count_reg\[4\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0))
+      (INTERCONNECT count_reg\[6\]/Q led_reg_i_51/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[6\]/Q led_reg_i_62/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[6\]/Q led_reg_i_55/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[6\]/Q count_reg\[4\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0))
+      (INTERCONNECT count_reg\[7\]/Q led_reg_i_43/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0))
+      (INTERCONNECT count_reg\[7\]/Q led_reg_i_55/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[7\]/Q led_reg_i_51/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[7\]/Q led_reg_i_62/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[7\]/Q count_reg\[4\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0))
+      (INTERCONNECT count_reg\[8\]/Q led_reg_i_38/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[8\]/Q led_reg_i_42/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[8\]/Q led_reg_i_46/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[8\]/Q led_reg_i_50/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[8\]/Q count_reg\[8\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0))
+      (INTERCONNECT count_reg\[8\]_i_1/CO[3] count_reg\[12\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT count_reg\[8\]_i_1/O[3] count_reg\[11\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[8\]_i_1/O[2] count_reg\[10\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[8\]_i_1/O[1] count_reg\[9\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[8\]_i_1/O[0] count_reg\[8\]/D (62.0:76.0:76.0) (62.0:76.0:76.0))
+      (INTERCONNECT count_reg\[9\]/Q led_reg_i_50/I0 (584.5:641.0:641.0) (584.5:641.0:641.0))
+      (INTERCONNECT count_reg\[9\]/Q led_reg_i_38/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[9\]/Q led_reg_i_42/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[9\]/Q led_reg_i_46/I1 (433.5:482.0:482.0) (433.5:482.0:482.0))
+      (INTERCONNECT count_reg\[9\]/Q count_reg\[8\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0))
+      (INTERCONNECT led_reg/Q led_OBUF_inst/I (760.7:800.7:800.7) (760.7:800.7:800.7))
+      (INTERCONNECT led_reg_i_1/CO[3] led_reg/D (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT led_reg_i_1/CO[3] led_reg/G (439.0:584.0:584.0) (439.0:584.0:584.0))
+      (INTERCONNECT led_reg_i_10/O led_reg_i_1/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_11/O led_reg_i_1/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT led_reg_i_12/CO[3] led_reg_i_2/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT led_reg_i_13/O led_reg_i_2/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0))
+      (INTERCONNECT led_reg_i_14/O led_reg_i_2/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0))
+      (INTERCONNECT led_reg_i_15/O led_reg_i_2/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_16/O led_reg_i_2/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_17/O led_reg_i_2/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0))
+      (INTERCONNECT led_reg_i_18/O led_reg_i_2/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_19/O led_reg_i_2/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[0\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[10\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[11\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[12\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[13\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[14\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[15\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[16\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[17\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[18\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[19\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[1\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[20\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[21\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[22\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[23\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[24\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[25\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[26\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[27\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[28\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[29\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[2\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[30\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[31\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[3\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[4\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[5\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[6\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[7\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[8\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] count_reg\[9\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_2/CO[3] led_reg/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0))
+      (INTERCONNECT led_reg_i_20/O led_reg_i_2/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT led_reg_i_21/CO[3] led_reg_i_3/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT led_reg_i_22/O led_reg_i_3/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0))
+      (INTERCONNECT led_reg_i_23/O led_reg_i_3/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_24/O led_reg_i_3/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0))
+      (INTERCONNECT led_reg_i_25/O led_reg_i_3/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_26/O led_reg_i_3/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_27/O led_reg_i_3/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT led_reg_i_28/CO[3] led_reg_i_12/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT led_reg_i_29/O led_reg_i_12/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0))
+      (INTERCONNECT led_reg_i_3/CO[3] led_reg_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT led_reg_i_30/O led_reg_i_12/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0))
+      (INTERCONNECT led_reg_i_31/O led_reg_i_12/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0))
+      (INTERCONNECT led_reg_i_32/O led_reg_i_12/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_33/O led_reg_i_12/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_34/O led_reg_i_12/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT led_reg_i_35/CO[3] led_reg_i_21/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT led_reg_i_36/O led_reg_i_21/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0))
+      (INTERCONNECT led_reg_i_37/O led_reg_i_21/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0))
+      (INTERCONNECT led_reg_i_38/O led_reg_i_21/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_39/O led_reg_i_21/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0))
+      (INTERCONNECT led_reg_i_4/O led_reg_i_1/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0))
+      (INTERCONNECT led_reg_i_40/O led_reg_i_21/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_41/O led_reg_i_21/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_42/O led_reg_i_21/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT led_reg_i_43/CO[3] led_reg_i_28/CI (0.0:0.0:0.0) (0.0:0.0:0.0))
+      (INTERCONNECT led_reg_i_44/O led_reg_i_28/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0))
+      (INTERCONNECT led_reg_i_45/O led_reg_i_28/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_46/O led_reg_i_28/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_47/O led_reg_i_28/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0))
+      (INTERCONNECT led_reg_i_48/O led_reg_i_28/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_49/O led_reg_i_28/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_5/O led_reg_i_1/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0))
+      (INTERCONNECT led_reg_i_50/O led_reg_i_28/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT led_reg_i_51/O led_reg_i_35/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0))
+      (INTERCONNECT led_reg_i_52/O led_reg_i_35/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0))
+      (INTERCONNECT led_reg_i_53/O led_reg_i_35/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_54/O led_reg_i_35/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_55/O led_reg_i_35/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0))
+      (INTERCONNECT led_reg_i_56/O led_reg_i_35/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_57/O led_reg_i_35/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_58/O led_reg_i_35/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT led_reg_i_59/O led_reg_i_43/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0))
+      (INTERCONNECT led_reg_i_6/O led_reg_i_1/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_60/O led_reg_i_43/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_61/O led_reg_i_43/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_62/O led_reg_i_43/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0))
+      (INTERCONNECT led_reg_i_63/O led_reg_i_43/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_64/O led_reg_i_43/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      (INTERCONNECT led_reg_i_65/O led_reg_i_43/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0))
+      (INTERCONNECT led_reg_i_7/O led_reg_i_1/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0))
+      (INTERCONNECT led_reg_i_8/O led_reg_i_1/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0))
+      (INTERCONNECT led_reg_i_9/O led_reg_i_1/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0))
+      )
+    )
+)
+)
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v
new file mode 100644
index 0000000..0d4fd63
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v
@@ -0,0 +1,1028 @@
+// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+// Date        : Wed Mar 16 20:54:19 2022
+// Host        : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+// Command     : write_verilog -mode timesim -nolib -sdf_anno true -force -file
+//               C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v
+// Design      : pwm_test
+// Purpose     : This verilog netlist is a timing simulation representation of the design and should not be modified or
+//               synthesized. Please ensure that this netlist is used with the corresponding SDF file.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+`define XIL_TIMING
+
+(* NotValidForBitStream *)
+module pwm_test
+   (clk,
+    led);
+  input clk;
+  output led;
+
+  wire clk;
+  wire clk_IBUF;
+  wire clk_IBUF_BUFG;
+  wire \count[0]_i_2_n_0 ;
+  wire [31:0]count_reg;
+  wire \count_reg[0]_i_1_n_0 ;
+  wire \count_reg[0]_i_1_n_1 ;
+  wire \count_reg[0]_i_1_n_2 ;
+  wire \count_reg[0]_i_1_n_3 ;
+  wire \count_reg[0]_i_1_n_4 ;
+  wire \count_reg[0]_i_1_n_5 ;
+  wire \count_reg[0]_i_1_n_6 ;
+  wire \count_reg[0]_i_1_n_7 ;
+  wire \count_reg[12]_i_1_n_0 ;
+  wire \count_reg[12]_i_1_n_1 ;
+  wire \count_reg[12]_i_1_n_2 ;
+  wire \count_reg[12]_i_1_n_3 ;
+  wire \count_reg[12]_i_1_n_4 ;
+  wire \count_reg[12]_i_1_n_5 ;
+  wire \count_reg[12]_i_1_n_6 ;
+  wire \count_reg[12]_i_1_n_7 ;
+  wire \count_reg[16]_i_1_n_0 ;
+  wire \count_reg[16]_i_1_n_1 ;
+  wire \count_reg[16]_i_1_n_2 ;
+  wire \count_reg[16]_i_1_n_3 ;
+  wire \count_reg[16]_i_1_n_4 ;
+  wire \count_reg[16]_i_1_n_5 ;
+  wire \count_reg[16]_i_1_n_6 ;
+  wire \count_reg[16]_i_1_n_7 ;
+  wire \count_reg[20]_i_1_n_0 ;
+  wire \count_reg[20]_i_1_n_1 ;
+  wire \count_reg[20]_i_1_n_2 ;
+  wire \count_reg[20]_i_1_n_3 ;
+  wire \count_reg[20]_i_1_n_4 ;
+  wire \count_reg[20]_i_1_n_5 ;
+  wire \count_reg[20]_i_1_n_6 ;
+  wire \count_reg[20]_i_1_n_7 ;
+  wire \count_reg[24]_i_1_n_0 ;
+  wire \count_reg[24]_i_1_n_1 ;
+  wire \count_reg[24]_i_1_n_2 ;
+  wire \count_reg[24]_i_1_n_3 ;
+  wire \count_reg[24]_i_1_n_4 ;
+  wire \count_reg[24]_i_1_n_5 ;
+  wire \count_reg[24]_i_1_n_6 ;
+  wire \count_reg[24]_i_1_n_7 ;
+  wire \count_reg[28]_i_1_n_1 ;
+  wire \count_reg[28]_i_1_n_2 ;
+  wire \count_reg[28]_i_1_n_3 ;
+  wire \count_reg[28]_i_1_n_4 ;
+  wire \count_reg[28]_i_1_n_5 ;
+  wire \count_reg[28]_i_1_n_6 ;
+  wire \count_reg[28]_i_1_n_7 ;
+  wire \count_reg[4]_i_1_n_0 ;
+  wire \count_reg[4]_i_1_n_1 ;
+  wire \count_reg[4]_i_1_n_2 ;
+  wire \count_reg[4]_i_1_n_3 ;
+  wire \count_reg[4]_i_1_n_4 ;
+  wire \count_reg[4]_i_1_n_5 ;
+  wire \count_reg[4]_i_1_n_6 ;
+  wire \count_reg[4]_i_1_n_7 ;
+  wire \count_reg[8]_i_1_n_0 ;
+  wire \count_reg[8]_i_1_n_1 ;
+  wire \count_reg[8]_i_1_n_2 ;
+  wire \count_reg[8]_i_1_n_3 ;
+  wire \count_reg[8]_i_1_n_4 ;
+  wire \count_reg[8]_i_1_n_5 ;
+  wire \count_reg[8]_i_1_n_6 ;
+  wire \count_reg[8]_i_1_n_7 ;
+  wire led;
+  wire led_OBUF;
+  wire led_reg_i_10_n_0;
+  wire led_reg_i_11_n_0;
+  wire led_reg_i_12_n_0;
+  wire led_reg_i_12_n_1;
+  wire led_reg_i_12_n_2;
+  wire led_reg_i_12_n_3;
+  wire led_reg_i_13_n_0;
+  wire led_reg_i_14_n_0;
+  wire led_reg_i_15_n_0;
+  wire led_reg_i_16_n_0;
+  wire led_reg_i_17_n_0;
+  wire led_reg_i_18_n_0;
+  wire led_reg_i_19_n_0;
+  wire led_reg_i_1_n_0;
+  wire led_reg_i_1_n_1;
+  wire led_reg_i_1_n_2;
+  wire led_reg_i_1_n_3;
+  wire led_reg_i_20_n_0;
+  wire led_reg_i_21_n_0;
+  wire led_reg_i_21_n_1;
+  wire led_reg_i_21_n_2;
+  wire led_reg_i_21_n_3;
+  wire led_reg_i_22_n_0;
+  wire led_reg_i_23_n_0;
+  wire led_reg_i_24_n_0;
+  wire led_reg_i_25_n_0;
+  wire led_reg_i_26_n_0;
+  wire led_reg_i_27_n_0;
+  wire led_reg_i_28_n_0;
+  wire led_reg_i_28_n_1;
+  wire led_reg_i_28_n_2;
+  wire led_reg_i_28_n_3;
+  wire led_reg_i_29_n_0;
+  wire led_reg_i_2_n_0;
+  wire led_reg_i_2_n_1;
+  wire led_reg_i_2_n_2;
+  wire led_reg_i_2_n_3;
+  wire led_reg_i_30_n_0;
+  wire led_reg_i_31_n_0;
+  wire led_reg_i_32_n_0;
+  wire led_reg_i_33_n_0;
+  wire led_reg_i_34_n_0;
+  wire led_reg_i_35_n_0;
+  wire led_reg_i_35_n_1;
+  wire led_reg_i_35_n_2;
+  wire led_reg_i_35_n_3;
+  wire led_reg_i_36_n_0;
+  wire led_reg_i_37_n_0;
+  wire led_reg_i_38_n_0;
+  wire led_reg_i_39_n_0;
+  wire led_reg_i_3_n_0;
+  wire led_reg_i_3_n_1;
+  wire led_reg_i_3_n_2;
+  wire led_reg_i_3_n_3;
+  wire led_reg_i_40_n_0;
+  wire led_reg_i_41_n_0;
+  wire led_reg_i_42_n_0;
+  wire led_reg_i_43_n_0;
+  wire led_reg_i_43_n_1;
+  wire led_reg_i_43_n_2;
+  wire led_reg_i_43_n_3;
+  wire led_reg_i_44_n_0;
+  wire led_reg_i_45_n_0;
+  wire led_reg_i_46_n_0;
+  wire led_reg_i_47_n_0;
+  wire led_reg_i_48_n_0;
+  wire led_reg_i_49_n_0;
+  wire led_reg_i_4_n_0;
+  wire led_reg_i_50_n_0;
+  wire led_reg_i_51_n_0;
+  wire led_reg_i_52_n_0;
+  wire led_reg_i_53_n_0;
+  wire led_reg_i_54_n_0;
+  wire led_reg_i_55_n_0;
+  wire led_reg_i_56_n_0;
+  wire led_reg_i_57_n_0;
+  wire led_reg_i_58_n_0;
+  wire led_reg_i_59_n_0;
+  wire led_reg_i_5_n_0;
+  wire led_reg_i_60_n_0;
+  wire led_reg_i_61_n_0;
+  wire led_reg_i_62_n_0;
+  wire led_reg_i_63_n_0;
+  wire led_reg_i_64_n_0;
+  wire led_reg_i_65_n_0;
+  wire led_reg_i_6_n_0;
+  wire led_reg_i_7_n_0;
+  wire led_reg_i_8_n_0;
+  wire led_reg_i_9_n_0;
+  wire [3:3]\NLW_count_reg[28]_i_1_CO_UNCONNECTED ;
+  wire [3:0]NLW_led_reg_i_1_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_12_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_2_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_21_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_28_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_3_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_35_O_UNCONNECTED;
+  wire [3:0]NLW_led_reg_i_43_O_UNCONNECTED;
+
+initial begin
+ $sdf_annotate("pwm_test_db_time_synth.sdf",,,,"tool_control");
+end
+  BUFG clk_IBUF_BUFG_inst
+       (.I(clk_IBUF),
+        .O(clk_IBUF_BUFG));
+  IBUF clk_IBUF_inst
+       (.I(clk),
+        .O(clk_IBUF));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \count[0]_i_2 
+       (.I0(count_reg[0]),
+        .O(\count[0]_i_2_n_0 ));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[0] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[0]_i_1_n_7 ),
+        .Q(count_reg[0]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[0]_i_1 
+       (.CI(1'b0),
+        .CO({\count_reg[0]_i_1_n_0 ,\count_reg[0]_i_1_n_1 ,\count_reg[0]_i_1_n_2 ,\count_reg[0]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b1}),
+        .O({\count_reg[0]_i_1_n_4 ,\count_reg[0]_i_1_n_5 ,\count_reg[0]_i_1_n_6 ,\count_reg[0]_i_1_n_7 }),
+        .S({count_reg[3:1],\count[0]_i_2_n_0 }));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[10] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[8]_i_1_n_5 ),
+        .Q(count_reg[10]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[11] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[8]_i_1_n_4 ),
+        .Q(count_reg[11]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[12] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[12]_i_1_n_7 ),
+        .Q(count_reg[12]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[12]_i_1 
+       (.CI(\count_reg[8]_i_1_n_0 ),
+        .CO({\count_reg[12]_i_1_n_0 ,\count_reg[12]_i_1_n_1 ,\count_reg[12]_i_1_n_2 ,\count_reg[12]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[12]_i_1_n_4 ,\count_reg[12]_i_1_n_5 ,\count_reg[12]_i_1_n_6 ,\count_reg[12]_i_1_n_7 }),
+        .S(count_reg[15:12]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[13] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[12]_i_1_n_6 ),
+        .Q(count_reg[13]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[14] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[12]_i_1_n_5 ),
+        .Q(count_reg[14]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[15] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[12]_i_1_n_4 ),
+        .Q(count_reg[15]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[16] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[16]_i_1_n_7 ),
+        .Q(count_reg[16]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[16]_i_1 
+       (.CI(\count_reg[12]_i_1_n_0 ),
+        .CO({\count_reg[16]_i_1_n_0 ,\count_reg[16]_i_1_n_1 ,\count_reg[16]_i_1_n_2 ,\count_reg[16]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[16]_i_1_n_4 ,\count_reg[16]_i_1_n_5 ,\count_reg[16]_i_1_n_6 ,\count_reg[16]_i_1_n_7 }),
+        .S(count_reg[19:16]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[17] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[16]_i_1_n_6 ),
+        .Q(count_reg[17]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[18] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[16]_i_1_n_5 ),
+        .Q(count_reg[18]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[19] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[16]_i_1_n_4 ),
+        .Q(count_reg[19]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[1] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[0]_i_1_n_6 ),
+        .Q(count_reg[1]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[20] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[20]_i_1_n_7 ),
+        .Q(count_reg[20]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[20]_i_1 
+       (.CI(\count_reg[16]_i_1_n_0 ),
+        .CO({\count_reg[20]_i_1_n_0 ,\count_reg[20]_i_1_n_1 ,\count_reg[20]_i_1_n_2 ,\count_reg[20]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[20]_i_1_n_4 ,\count_reg[20]_i_1_n_5 ,\count_reg[20]_i_1_n_6 ,\count_reg[20]_i_1_n_7 }),
+        .S(count_reg[23:20]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[21] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[20]_i_1_n_6 ),
+        .Q(count_reg[21]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[22] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[20]_i_1_n_5 ),
+        .Q(count_reg[22]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[23] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[20]_i_1_n_4 ),
+        .Q(count_reg[23]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[24] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[24]_i_1_n_7 ),
+        .Q(count_reg[24]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[24]_i_1 
+       (.CI(\count_reg[20]_i_1_n_0 ),
+        .CO({\count_reg[24]_i_1_n_0 ,\count_reg[24]_i_1_n_1 ,\count_reg[24]_i_1_n_2 ,\count_reg[24]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[24]_i_1_n_4 ,\count_reg[24]_i_1_n_5 ,\count_reg[24]_i_1_n_6 ,\count_reg[24]_i_1_n_7 }),
+        .S(count_reg[27:24]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[25] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[24]_i_1_n_6 ),
+        .Q(count_reg[25]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[26] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[24]_i_1_n_5 ),
+        .Q(count_reg[26]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[27] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[24]_i_1_n_4 ),
+        .Q(count_reg[27]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[28] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[28]_i_1_n_7 ),
+        .Q(count_reg[28]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[28]_i_1 
+       (.CI(\count_reg[24]_i_1_n_0 ),
+        .CO({\NLW_count_reg[28]_i_1_CO_UNCONNECTED [3],\count_reg[28]_i_1_n_1 ,\count_reg[28]_i_1_n_2 ,\count_reg[28]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[28]_i_1_n_4 ,\count_reg[28]_i_1_n_5 ,\count_reg[28]_i_1_n_6 ,\count_reg[28]_i_1_n_7 }),
+        .S(count_reg[31:28]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[29] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[28]_i_1_n_6 ),
+        .Q(count_reg[29]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[2] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[0]_i_1_n_5 ),
+        .Q(count_reg[2]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[30] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[28]_i_1_n_5 ),
+        .Q(count_reg[30]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[31] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[28]_i_1_n_4 ),
+        .Q(count_reg[31]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[3] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[0]_i_1_n_4 ),
+        .Q(count_reg[3]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[4] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[4]_i_1_n_7 ),
+        .Q(count_reg[4]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[4]_i_1 
+       (.CI(\count_reg[0]_i_1_n_0 ),
+        .CO({\count_reg[4]_i_1_n_0 ,\count_reg[4]_i_1_n_1 ,\count_reg[4]_i_1_n_2 ,\count_reg[4]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[4]_i_1_n_4 ,\count_reg[4]_i_1_n_5 ,\count_reg[4]_i_1_n_6 ,\count_reg[4]_i_1_n_7 }),
+        .S(count_reg[7:4]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[5] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[4]_i_1_n_6 ),
+        .Q(count_reg[5]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[6] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[4]_i_1_n_5 ),
+        .Q(count_reg[6]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[7] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[4]_i_1_n_4 ),
+        .Q(count_reg[7]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[8] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[8]_i_1_n_7 ),
+        .Q(count_reg[8]));
+  (* ADDER_THRESHOLD = "11" *) 
+  CARRY4 \count_reg[8]_i_1 
+       (.CI(\count_reg[4]_i_1_n_0 ),
+        .CO({\count_reg[8]_i_1_n_0 ,\count_reg[8]_i_1_n_1 ,\count_reg[8]_i_1_n_2 ,\count_reg[8]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\count_reg[8]_i_1_n_4 ,\count_reg[8]_i_1_n_5 ,\count_reg[8]_i_1_n_6 ,\count_reg[8]_i_1_n_7 }),
+        .S(count_reg[11:8]));
+  FDCE #(
+    .INIT(1'b0)) 
+    \count_reg[9] 
+       (.C(clk_IBUF_BUFG),
+        .CE(1'b1),
+        .CLR(led_reg_i_2_n_0),
+        .D(\count_reg[8]_i_1_n_6 ),
+        .Q(count_reg[9]));
+  OBUF led_OBUF_inst
+       (.I(led_OBUF),
+        .O(led));
+  (* XILINX_LEGACY_PRIM = "LDC" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:GE" *) 
+  LDCE #(
+    .INIT(1'b0)) 
+    led_reg
+       (.CLR(led_reg_i_2_n_0),
+        .D(led_reg_i_1_n_0),
+        .G(led_reg_i_1_n_0),
+        .GE(1'b1),
+        .Q(led_OBUF));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_1
+       (.CI(led_reg_i_3_n_0),
+        .CO({led_reg_i_1_n_0,led_reg_i_1_n_1,led_reg_i_1_n_2,led_reg_i_1_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_4_n_0,led_reg_i_5_n_0,led_reg_i_6_n_0,led_reg_i_7_n_0}),
+        .O(NLW_led_reg_i_1_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_8_n_0,led_reg_i_9_n_0,led_reg_i_10_n_0,led_reg_i_11_n_0}));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_10
+       (.I0(count_reg[26]),
+        .I1(count_reg[27]),
+        .O(led_reg_i_10_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_11
+       (.I0(count_reg[24]),
+        .I1(count_reg[25]),
+        .O(led_reg_i_11_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_12
+       (.CI(led_reg_i_28_n_0),
+        .CO({led_reg_i_12_n_0,led_reg_i_12_n_1,led_reg_i_12_n_2,led_reg_i_12_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_29_n_0,led_reg_i_30_n_0,1'b0,1'b0}),
+        .O(NLW_led_reg_i_12_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_31_n_0,led_reg_i_32_n_0,led_reg_i_33_n_0,led_reg_i_34_n_0}));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_13
+       (.I0(count_reg[30]),
+        .I1(count_reg[31]),
+        .O(led_reg_i_13_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_14
+       (.I0(count_reg[28]),
+        .I1(count_reg[29]),
+        .O(led_reg_i_14_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_15
+       (.I0(count_reg[26]),
+        .I1(count_reg[27]),
+        .O(led_reg_i_15_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_16
+       (.I0(count_reg[24]),
+        .I1(count_reg[25]),
+        .O(led_reg_i_16_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_17
+       (.I0(count_reg[30]),
+        .I1(count_reg[31]),
+        .O(led_reg_i_17_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_18
+       (.I0(count_reg[28]),
+        .I1(count_reg[29]),
+        .O(led_reg_i_18_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_19
+       (.I0(count_reg[26]),
+        .I1(count_reg[27]),
+        .O(led_reg_i_19_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_2
+       (.CI(led_reg_i_12_n_0),
+        .CO({led_reg_i_2_n_0,led_reg_i_2_n_1,led_reg_i_2_n_2,led_reg_i_2_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_13_n_0,led_reg_i_14_n_0,led_reg_i_15_n_0,led_reg_i_16_n_0}),
+        .O(NLW_led_reg_i_2_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_17_n_0,led_reg_i_18_n_0,led_reg_i_19_n_0,led_reg_i_20_n_0}));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_20
+       (.I0(count_reg[24]),
+        .I1(count_reg[25]),
+        .O(led_reg_i_20_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_21
+       (.CI(led_reg_i_35_n_0),
+        .CO({led_reg_i_21_n_0,led_reg_i_21_n_1,led_reg_i_21_n_2,led_reg_i_21_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_36_n_0,led_reg_i_37_n_0,count_reg[11],led_reg_i_38_n_0}),
+        .O(NLW_led_reg_i_21_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_39_n_0,led_reg_i_40_n_0,led_reg_i_41_n_0,led_reg_i_42_n_0}));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_22
+       (.I0(count_reg[22]),
+        .I1(count_reg[23]),
+        .O(led_reg_i_22_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_23
+       (.I0(count_reg[16]),
+        .I1(count_reg[17]),
+        .O(led_reg_i_23_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_24
+       (.I0(count_reg[22]),
+        .I1(count_reg[23]),
+        .O(led_reg_i_24_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_25
+       (.I0(count_reg[20]),
+        .I1(count_reg[21]),
+        .O(led_reg_i_25_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_26
+       (.I0(count_reg[18]),
+        .I1(count_reg[19]),
+        .O(led_reg_i_26_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_27
+       (.I0(count_reg[17]),
+        .I1(count_reg[16]),
+        .O(led_reg_i_27_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_28
+       (.CI(led_reg_i_43_n_0),
+        .CO({led_reg_i_28_n_0,led_reg_i_28_n_1,led_reg_i_28_n_2,led_reg_i_28_n_3}),
+        .CYINIT(1'b0),
+        .DI({count_reg[15],led_reg_i_44_n_0,led_reg_i_45_n_0,led_reg_i_46_n_0}),
+        .O(NLW_led_reg_i_28_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_47_n_0,led_reg_i_48_n_0,led_reg_i_49_n_0,led_reg_i_50_n_0}));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_29
+       (.I0(count_reg[22]),
+        .I1(count_reg[23]),
+        .O(led_reg_i_29_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_3
+       (.CI(led_reg_i_21_n_0),
+        .CO({led_reg_i_3_n_0,led_reg_i_3_n_1,led_reg_i_3_n_2,led_reg_i_3_n_3}),
+        .CYINIT(1'b0),
+        .DI({led_reg_i_22_n_0,count_reg[21],1'b0,led_reg_i_23_n_0}),
+        .O(NLW_led_reg_i_3_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_24_n_0,led_reg_i_25_n_0,led_reg_i_26_n_0,led_reg_i_27_n_0}));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_30
+       (.I0(count_reg[20]),
+        .I1(count_reg[21]),
+        .O(led_reg_i_30_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_31
+       (.I0(count_reg[22]),
+        .I1(count_reg[23]),
+        .O(led_reg_i_31_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_32
+       (.I0(count_reg[20]),
+        .I1(count_reg[21]),
+        .O(led_reg_i_32_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_33
+       (.I0(count_reg[18]),
+        .I1(count_reg[19]),
+        .O(led_reg_i_33_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_34
+       (.I0(count_reg[16]),
+        .I1(count_reg[17]),
+        .O(led_reg_i_34_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_35
+       (.CI(1'b0),
+        .CO({led_reg_i_35_n_0,led_reg_i_35_n_1,led_reg_i_35_n_2,led_reg_i_35_n_3}),
+        .CYINIT(1'b1),
+        .DI({led_reg_i_51_n_0,led_reg_i_52_n_0,led_reg_i_53_n_0,led_reg_i_54_n_0}),
+        .O(NLW_led_reg_i_35_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_55_n_0,led_reg_i_56_n_0,led_reg_i_57_n_0,led_reg_i_58_n_0}));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_36
+       (.I0(count_reg[14]),
+        .I1(count_reg[15]),
+        .O(led_reg_i_36_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_37
+       (.I0(count_reg[12]),
+        .I1(count_reg[13]),
+        .O(led_reg_i_37_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_38
+       (.I0(count_reg[8]),
+        .I1(count_reg[9]),
+        .O(led_reg_i_38_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_39
+       (.I0(count_reg[15]),
+        .I1(count_reg[14]),
+        .O(led_reg_i_39_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_4
+       (.I0(count_reg[30]),
+        .I1(count_reg[31]),
+        .O(led_reg_i_4_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_40
+       (.I0(count_reg[12]),
+        .I1(count_reg[13]),
+        .O(led_reg_i_40_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_41
+       (.I0(count_reg[10]),
+        .I1(count_reg[11]),
+        .O(led_reg_i_41_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_42
+       (.I0(count_reg[8]),
+        .I1(count_reg[9]),
+        .O(led_reg_i_42_n_0));
+  (* COMPARATOR_THRESHOLD = "11" *) 
+  CARRY4 led_reg_i_43
+       (.CI(1'b0),
+        .CO({led_reg_i_43_n_0,led_reg_i_43_n_1,led_reg_i_43_n_2,led_reg_i_43_n_3}),
+        .CYINIT(1'b1),
+        .DI({count_reg[7],led_reg_i_59_n_0,led_reg_i_60_n_0,led_reg_i_61_n_0}),
+        .O(NLW_led_reg_i_43_O_UNCONNECTED[3:0]),
+        .S({led_reg_i_62_n_0,led_reg_i_63_n_0,led_reg_i_64_n_0,led_reg_i_65_n_0}));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_44
+       (.I0(count_reg[12]),
+        .I1(count_reg[13]),
+        .O(led_reg_i_44_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_45
+       (.I0(count_reg[10]),
+        .I1(count_reg[11]),
+        .O(led_reg_i_45_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_46
+       (.I0(count_reg[8]),
+        .I1(count_reg[9]),
+        .O(led_reg_i_46_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_47
+       (.I0(count_reg[14]),
+        .I1(count_reg[15]),
+        .O(led_reg_i_47_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_48
+       (.I0(count_reg[12]),
+        .I1(count_reg[13]),
+        .O(led_reg_i_48_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_49
+       (.I0(count_reg[10]),
+        .I1(count_reg[11]),
+        .O(led_reg_i_49_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_5
+       (.I0(count_reg[28]),
+        .I1(count_reg[29]),
+        .O(led_reg_i_5_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_50
+       (.I0(count_reg[9]),
+        .I1(count_reg[8]),
+        .O(led_reg_i_50_n_0));
+  LUT2 #(
+    .INIT(4'h8)) 
+    led_reg_i_51
+       (.I0(count_reg[6]),
+        .I1(count_reg[7]),
+        .O(led_reg_i_51_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_52
+       (.I0(count_reg[4]),
+        .I1(count_reg[5]),
+        .O(led_reg_i_52_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_53
+       (.I0(count_reg[2]),
+        .I1(count_reg[3]),
+        .O(led_reg_i_53_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_54
+       (.I0(count_reg[0]),
+        .I1(count_reg[1]),
+        .O(led_reg_i_54_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_55
+       (.I0(count_reg[7]),
+        .I1(count_reg[6]),
+        .O(led_reg_i_55_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_56
+       (.I0(count_reg[4]),
+        .I1(count_reg[5]),
+        .O(led_reg_i_56_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_57
+       (.I0(count_reg[2]),
+        .I1(count_reg[3]),
+        .O(led_reg_i_57_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_58
+       (.I0(count_reg[0]),
+        .I1(count_reg[1]),
+        .O(led_reg_i_58_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_59
+       (.I0(count_reg[4]),
+        .I1(count_reg[5]),
+        .O(led_reg_i_59_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_6
+       (.I0(count_reg[26]),
+        .I1(count_reg[27]),
+        .O(led_reg_i_6_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_60
+       (.I0(count_reg[2]),
+        .I1(count_reg[3]),
+        .O(led_reg_i_60_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_61
+       (.I0(count_reg[0]),
+        .I1(count_reg[1]),
+        .O(led_reg_i_61_n_0));
+  LUT2 #(
+    .INIT(4'h2)) 
+    led_reg_i_62
+       (.I0(count_reg[6]),
+        .I1(count_reg[7]),
+        .O(led_reg_i_62_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_63
+       (.I0(count_reg[4]),
+        .I1(count_reg[5]),
+        .O(led_reg_i_63_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_64
+       (.I0(count_reg[2]),
+        .I1(count_reg[3]),
+        .O(led_reg_i_64_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_65
+       (.I0(count_reg[0]),
+        .I1(count_reg[1]),
+        .O(led_reg_i_65_n_0));
+  LUT2 #(
+    .INIT(4'hE)) 
+    led_reg_i_7
+       (.I0(count_reg[24]),
+        .I1(count_reg[25]),
+        .O(led_reg_i_7_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_8
+       (.I0(count_reg[30]),
+        .I1(count_reg[31]),
+        .O(led_reg_i_8_n_0));
+  LUT2 #(
+    .INIT(4'h1)) 
+    led_reg_i_9
+       (.I0(count_reg[28]),
+        .I1(count_reg[29]),
+        .O(led_reg_i_9_n_0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.wdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.wdb
new file mode 100644
index 0000000..4ddf9ad
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.wdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.bat b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.bat
new file mode 100644
index 0000000..de13086
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Wed Mar 16 20:54:28 +0100 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim pwm_test_db_time_synth -key {Post-Synthesis:sim_1:Timing:pwm_test_db} -tclbatch pwm_test_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg -log simulate.log"
+call xsim  pwm_test_db_time_synth -key {Post-Synthesis:sim_1:Timing:pwm_test_db} -tclbatch pwm_test_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.log
new file mode 100644
index 0000000..8f8d1ed
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.log
@@ -0,0 +1,2 @@
+Time resolution is 1 ps
+INFO: xsimkernel Simulation Memory Usage: 20776 KB (Peak: 20776 KB), Simulation CPU Usage: 461827 ms
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xelab.pb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xelab.pb
new file mode 100644
index 0000000..3da06a8
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xelab.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/Compile_Options.txt b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/Compile_Options.txt
new file mode 100644
index 0000000..f5cc3de
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "2" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "pwm_test_db_time_synth" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.pwm_test_db" "xil_defaultlib.glbl" -log "elaborate.log" 
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/TempBreakPointFile.txt b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_0.win64.obj b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..6ea05cd
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_0.win64.obj differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.c b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.c
new file mode 100644
index 0000000..51840eb
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.c
@@ -0,0 +1,1016 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_2(char*, char *);
+IKI_DLLESPEC extern void execute_3(char*, char *);
+IKI_DLLESPEC extern void execute_4(char*, char *);
+IKI_DLLESPEC extern void execute_5(char*, char *);
+IKI_DLLESPEC extern void execute_6(char*, char *);
+IKI_DLLESPEC extern void execute_7(char*, char *);
+IKI_DLLESPEC extern void execute_8(char*, char *);
+IKI_DLLESPEC extern void execute_9(char*, char *);
+IKI_DLLESPEC extern void execute_10(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_380(char*, char *);
+IKI_DLLESPEC extern void execute_381(char*, char *);
+IKI_DLLESPEC extern void execute_19(char*, char *);
+IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
+IKI_DLLESPEC extern void execute_2296(char*, char *);
+IKI_DLLESPEC extern void execute_2301(char*, char *);
+IKI_DLLESPEC extern void execute_2307(char*, char *);
+IKI_DLLESPEC extern void execute_2314(char*, char *);
+IKI_DLLESPEC extern void execute_2320(char*, char *);
+IKI_DLLESPEC extern void execute_2326(char*, char *);
+IKI_DLLESPEC extern void execute_2334(char*, char *);
+IKI_DLLESPEC extern void execute_2340(char*, char *);
+IKI_DLLESPEC extern void execute_2345(char*, char *);
+IKI_DLLESPEC extern void execute_2350(char*, char *);
+IKI_DLLESPEC extern void execute_2355(char*, char *);
+IKI_DLLESPEC extern void execute_2356(char*, char *);
+IKI_DLLESPEC extern void execute_2357(char*, char *);
+IKI_DLLESPEC extern void execute_2358(char*, char *);
+IKI_DLLESPEC extern void execute_2359(char*, char *);
+IKI_DLLESPEC extern void execute_2360(char*, char *);
+IKI_DLLESPEC extern void execute_2361(char*, char *);
+IKI_DLLESPEC extern void execute_2362(char*, char *);
+IKI_DLLESPEC extern void execute_2363(char*, char *);
+IKI_DLLESPEC extern void execute_2364(char*, char *);
+IKI_DLLESPEC extern void execute_2365(char*, char *);
+IKI_DLLESPEC extern void execute_2366(char*, char *);
+IKI_DLLESPEC extern void execute_2367(char*, char *);
+IKI_DLLESPEC extern void execute_2368(char*, char *);
+IKI_DLLESPEC extern void execute_2369(char*, char *);
+IKI_DLLESPEC extern void execute_2370(char*, char *);
+IKI_DLLESPEC extern void execute_2371(char*, char *);
+IKI_DLLESPEC extern void execute_2372(char*, char *);
+IKI_DLLESPEC extern void execute_2373(char*, char *);
+IKI_DLLESPEC extern void execute_2374(char*, char *);
+IKI_DLLESPEC extern void execute_2375(char*, char *);
+IKI_DLLESPEC extern void execute_2376(char*, char *);
+IKI_DLLESPEC extern void execute_2377(char*, char *);
+IKI_DLLESPEC extern void execute_2378(char*, char *);
+IKI_DLLESPEC extern void execute_2379(char*, char *);
+IKI_DLLESPEC extern void execute_2380(char*, char *);
+IKI_DLLESPEC extern void execute_2381(char*, char *);
+IKI_DLLESPEC extern void execute_2382(char*, char *);
+IKI_DLLESPEC extern void execute_2383(char*, char *);
+IKI_DLLESPEC extern void execute_2384(char*, char *);
+IKI_DLLESPEC extern void execute_2385(char*, char *);
+IKI_DLLESPEC extern void execute_2386(char*, char *);
+IKI_DLLESPEC extern void execute_2387(char*, char *);
+IKI_DLLESPEC extern void execute_2388(char*, char *);
+IKI_DLLESPEC extern void execute_2389(char*, char *);
+IKI_DLLESPEC extern void execute_2390(char*, char *);
+IKI_DLLESPEC extern void execute_2391(char*, char *);
+IKI_DLLESPEC extern void execute_2392(char*, char *);
+IKI_DLLESPEC extern void execute_2393(char*, char *);
+IKI_DLLESPEC extern void execute_2394(char*, char *);
+IKI_DLLESPEC extern void execute_2395(char*, char *);
+IKI_DLLESPEC extern void execute_2396(char*, char *);
+IKI_DLLESPEC extern void execute_2397(char*, char *);
+IKI_DLLESPEC extern void execute_2398(char*, char *);
+IKI_DLLESPEC extern void execute_2399(char*, char *);
+IKI_DLLESPEC extern void execute_2400(char*, char *);
+IKI_DLLESPEC extern void execute_2401(char*, char *);
+IKI_DLLESPEC extern void execute_2402(char*, char *);
+IKI_DLLESPEC extern void execute_2403(char*, char *);
+IKI_DLLESPEC extern void execute_2404(char*, char *);
+IKI_DLLESPEC extern void execute_2405(char*, char *);
+IKI_DLLESPEC extern void execute_2406(char*, char *);
+IKI_DLLESPEC extern void execute_2407(char*, char *);
+IKI_DLLESPEC extern void execute_2408(char*, char *);
+IKI_DLLESPEC extern void execute_2409(char*, char *);
+IKI_DLLESPEC extern void execute_2410(char*, char *);
+IKI_DLLESPEC extern void execute_2411(char*, char *);
+IKI_DLLESPEC extern void execute_2412(char*, char *);
+IKI_DLLESPEC extern void execute_2413(char*, char *);
+IKI_DLLESPEC extern void execute_2414(char*, char *);
+IKI_DLLESPEC extern void execute_2415(char*, char *);
+IKI_DLLESPEC extern void execute_2416(char*, char *);
+IKI_DLLESPEC extern void execute_2417(char*, char *);
+IKI_DLLESPEC extern void execute_2418(char*, char *);
+IKI_DLLESPEC extern void execute_2419(char*, char *);
+IKI_DLLESPEC extern void execute_2420(char*, char *);
+IKI_DLLESPEC extern void execute_2421(char*, char *);
+IKI_DLLESPEC extern void execute_2422(char*, char *);
+IKI_DLLESPEC extern void execute_2423(char*, char *);
+IKI_DLLESPEC extern void execute_2424(char*, char *);
+IKI_DLLESPEC extern void execute_2425(char*, char *);
+IKI_DLLESPEC extern void execute_2426(char*, char *);
+IKI_DLLESPEC extern void execute_2427(char*, char *);
+IKI_DLLESPEC extern void execute_2428(char*, char *);
+IKI_DLLESPEC extern void execute_2429(char*, char *);
+IKI_DLLESPEC extern void execute_2430(char*, char *);
+IKI_DLLESPEC extern void execute_2431(char*, char *);
+IKI_DLLESPEC extern void execute_2432(char*, char *);
+IKI_DLLESPEC extern void execute_2433(char*, char *);
+IKI_DLLESPEC extern void execute_2434(char*, char *);
+IKI_DLLESPEC extern void execute_2435(char*, char *);
+IKI_DLLESPEC extern void execute_2436(char*, char *);
+IKI_DLLESPEC extern void execute_2437(char*, char *);
+IKI_DLLESPEC extern void execute_2438(char*, char *);
+IKI_DLLESPEC extern void execute_2439(char*, char *);
+IKI_DLLESPEC extern void execute_2440(char*, char *);
+IKI_DLLESPEC extern void execute_2441(char*, char *);
+IKI_DLLESPEC extern void execute_2442(char*, char *);
+IKI_DLLESPEC extern void execute_2443(char*, char *);
+IKI_DLLESPEC extern void execute_2444(char*, char *);
+IKI_DLLESPEC extern void execute_2445(char*, char *);
+IKI_DLLESPEC extern void execute_2446(char*, char *);
+IKI_DLLESPEC extern void execute_2447(char*, char *);
+IKI_DLLESPEC extern void execute_2448(char*, char *);
+IKI_DLLESPEC extern void execute_2449(char*, char *);
+IKI_DLLESPEC extern void execute_2450(char*, char *);
+IKI_DLLESPEC extern void execute_2451(char*, char *);
+IKI_DLLESPEC extern void execute_2452(char*, char *);
+IKI_DLLESPEC extern void execute_2453(char*, char *);
+IKI_DLLESPEC extern void execute_2454(char*, char *);
+IKI_DLLESPEC extern void execute_2455(char*, char *);
+IKI_DLLESPEC extern void execute_2456(char*, char *);
+IKI_DLLESPEC extern void execute_2457(char*, char *);
+IKI_DLLESPEC extern void execute_2458(char*, char *);
+IKI_DLLESPEC extern void execute_2459(char*, char *);
+IKI_DLLESPEC extern void execute_2460(char*, char *);
+IKI_DLLESPEC extern void execute_2461(char*, char *);
+IKI_DLLESPEC extern void execute_2462(char*, char *);
+IKI_DLLESPEC extern void execute_2463(char*, char *);
+IKI_DLLESPEC extern void execute_2464(char*, char *);
+IKI_DLLESPEC extern void execute_2465(char*, char *);
+IKI_DLLESPEC extern void execute_2466(char*, char *);
+IKI_DLLESPEC extern void execute_2467(char*, char *);
+IKI_DLLESPEC extern void execute_2468(char*, char *);
+IKI_DLLESPEC extern void execute_2469(char*, char *);
+IKI_DLLESPEC extern void execute_2470(char*, char *);
+IKI_DLLESPEC extern void execute_2471(char*, char *);
+IKI_DLLESPEC extern void execute_2472(char*, char *);
+IKI_DLLESPEC extern void execute_2473(char*, char *);
+IKI_DLLESPEC extern void execute_2474(char*, char *);
+IKI_DLLESPEC extern void execute_2475(char*, char *);
+IKI_DLLESPEC extern void execute_2476(char*, char *);
+IKI_DLLESPEC extern void execute_2477(char*, char *);
+IKI_DLLESPEC extern void execute_2478(char*, char *);
+IKI_DLLESPEC extern void execute_2479(char*, char *);
+IKI_DLLESPEC extern void execute_2480(char*, char *);
+IKI_DLLESPEC extern void execute_2481(char*, char *);
+IKI_DLLESPEC extern void execute_2482(char*, char *);
+IKI_DLLESPEC extern void execute_2483(char*, char *);
+IKI_DLLESPEC extern void execute_2484(char*, char *);
+IKI_DLLESPEC extern void execute_2485(char*, char *);
+IKI_DLLESPEC extern void execute_2486(char*, char *);
+IKI_DLLESPEC extern void execute_2487(char*, char *);
+IKI_DLLESPEC extern void execute_2488(char*, char *);
+IKI_DLLESPEC extern void execute_2489(char*, char *);
+IKI_DLLESPEC extern void execute_2490(char*, char *);
+IKI_DLLESPEC extern void execute_2491(char*, char *);
+IKI_DLLESPEC extern void execute_2492(char*, char *);
+IKI_DLLESPEC extern void execute_2493(char*, char *);
+IKI_DLLESPEC extern void execute_2494(char*, char *);
+IKI_DLLESPEC extern void execute_2495(char*, char *);
+IKI_DLLESPEC extern void execute_2496(char*, char *);
+IKI_DLLESPEC extern void execute_2497(char*, char *);
+IKI_DLLESPEC extern void execute_2498(char*, char *);
+IKI_DLLESPEC extern void execute_2499(char*, char *);
+IKI_DLLESPEC extern void execute_2500(char*, char *);
+IKI_DLLESPEC extern void execute_2501(char*, char *);
+IKI_DLLESPEC extern void execute_2502(char*, char *);
+IKI_DLLESPEC extern void execute_2503(char*, char *);
+IKI_DLLESPEC extern void execute_2504(char*, char *);
+IKI_DLLESPEC extern void execute_2505(char*, char *);
+IKI_DLLESPEC extern void execute_2506(char*, char *);
+IKI_DLLESPEC extern void execute_2507(char*, char *);
+IKI_DLLESPEC extern void execute_2508(char*, char *);
+IKI_DLLESPEC extern void execute_2509(char*, char *);
+IKI_DLLESPEC extern void execute_2510(char*, char *);
+IKI_DLLESPEC extern void execute_2511(char*, char *);
+IKI_DLLESPEC extern void execute_2512(char*, char *);
+IKI_DLLESPEC extern void execute_2513(char*, char *);
+IKI_DLLESPEC extern void execute_2514(char*, char *);
+IKI_DLLESPEC extern void execute_2515(char*, char *);
+IKI_DLLESPEC extern void execute_2516(char*, char *);
+IKI_DLLESPEC extern void execute_2517(char*, char *);
+IKI_DLLESPEC extern void execute_2518(char*, char *);
+IKI_DLLESPEC extern void execute_2519(char*, char *);
+IKI_DLLESPEC extern void execute_2520(char*, char *);
+IKI_DLLESPEC extern void execute_2521(char*, char *);
+IKI_DLLESPEC extern void execute_2522(char*, char *);
+IKI_DLLESPEC extern void execute_2523(char*, char *);
+IKI_DLLESPEC extern void execute_2524(char*, char *);
+IKI_DLLESPEC extern void execute_2525(char*, char *);
+IKI_DLLESPEC extern void execute_2526(char*, char *);
+IKI_DLLESPEC extern void execute_2527(char*, char *);
+IKI_DLLESPEC extern void execute_2528(char*, char *);
+IKI_DLLESPEC extern void execute_2529(char*, char *);
+IKI_DLLESPEC extern void execute_2530(char*, char *);
+IKI_DLLESPEC extern void execute_2531(char*, char *);
+IKI_DLLESPEC extern void execute_2532(char*, char *);
+IKI_DLLESPEC extern void execute_2533(char*, char *);
+IKI_DLLESPEC extern void execute_2534(char*, char *);
+IKI_DLLESPEC extern void execute_2535(char*, char *);
+IKI_DLLESPEC extern void execute_2536(char*, char *);
+IKI_DLLESPEC extern void execute_2537(char*, char *);
+IKI_DLLESPEC extern void execute_2538(char*, char *);
+IKI_DLLESPEC extern void execute_2539(char*, char *);
+IKI_DLLESPEC extern void execute_2540(char*, char *);
+IKI_DLLESPEC extern void execute_2541(char*, char *);
+IKI_DLLESPEC extern void execute_2542(char*, char *);
+IKI_DLLESPEC extern void execute_2543(char*, char *);
+IKI_DLLESPEC extern void execute_2544(char*, char *);
+IKI_DLLESPEC extern void execute_2545(char*, char *);
+IKI_DLLESPEC extern void execute_2546(char*, char *);
+IKI_DLLESPEC extern void execute_2547(char*, char *);
+IKI_DLLESPEC extern void execute_2548(char*, char *);
+IKI_DLLESPEC extern void execute_2549(char*, char *);
+IKI_DLLESPEC extern void execute_2550(char*, char *);
+IKI_DLLESPEC extern void execute_2551(char*, char *);
+IKI_DLLESPEC extern void execute_2552(char*, char *);
+IKI_DLLESPEC extern void execute_2553(char*, char *);
+IKI_DLLESPEC extern void execute_2554(char*, char *);
+IKI_DLLESPEC extern void execute_2555(char*, char *);
+IKI_DLLESPEC extern void execute_2556(char*, char *);
+IKI_DLLESPEC extern void execute_2557(char*, char *);
+IKI_DLLESPEC extern void execute_2558(char*, char *);
+IKI_DLLESPEC extern void execute_2559(char*, char *);
+IKI_DLLESPEC extern void execute_2560(char*, char *);
+IKI_DLLESPEC extern void execute_2561(char*, char *);
+IKI_DLLESPEC extern void execute_2562(char*, char *);
+IKI_DLLESPEC extern void execute_2563(char*, char *);
+IKI_DLLESPEC extern void execute_2564(char*, char *);
+IKI_DLLESPEC extern void execute_2565(char*, char *);
+IKI_DLLESPEC extern void execute_2566(char*, char *);
+IKI_DLLESPEC extern void execute_2567(char*, char *);
+IKI_DLLESPEC extern void execute_2568(char*, char *);
+IKI_DLLESPEC extern void execute_2569(char*, char *);
+IKI_DLLESPEC extern void execute_2570(char*, char *);
+IKI_DLLESPEC extern void execute_2571(char*, char *);
+IKI_DLLESPEC extern void execute_2572(char*, char *);
+IKI_DLLESPEC extern void execute_2573(char*, char *);
+IKI_DLLESPEC extern void execute_2574(char*, char *);
+IKI_DLLESPEC extern void execute_2575(char*, char *);
+IKI_DLLESPEC extern void execute_2576(char*, char *);
+IKI_DLLESPEC extern void execute_2577(char*, char *);
+IKI_DLLESPEC extern void execute_2578(char*, char *);
+IKI_DLLESPEC extern void execute_2579(char*, char *);
+IKI_DLLESPEC extern void execute_2580(char*, char *);
+IKI_DLLESPEC extern void execute_2581(char*, char *);
+IKI_DLLESPEC extern void execute_2582(char*, char *);
+IKI_DLLESPEC extern void execute_2583(char*, char *);
+IKI_DLLESPEC extern void execute_384(char*, char *);
+IKI_DLLESPEC extern void vlog_timingcheck_execute_0(char*, char*, char*);
+IKI_DLLESPEC extern void execute_22(char*, char *);
+IKI_DLLESPEC extern void execute_387(char*, char *);
+IKI_DLLESPEC extern void execute_25(char*, char *);
+IKI_DLLESPEC extern void execute_389(char*, char *);
+IKI_DLLESPEC extern void execute_390(char*, char *);
+IKI_DLLESPEC extern void execute_388(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_29(char*, char *);
+IKI_DLLESPEC extern void execute_30(char*, char *);
+IKI_DLLESPEC extern void execute_391(char*, char *);
+IKI_DLLESPEC extern void execute_392(char*, char *);
+IKI_DLLESPEC extern void execute_393(char*, char *);
+IKI_DLLESPEC extern void execute_394(char*, char *);
+IKI_DLLESPEC extern void execute_395(char*, char *);
+IKI_DLLESPEC extern void execute_396(char*, char *);
+IKI_DLLESPEC extern void execute_397(char*, char *);
+IKI_DLLESPEC extern void execute_398(char*, char *);
+IKI_DLLESPEC extern void execute_399(char*, char *);
+IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
+IKI_DLLESPEC extern void execute_401(char*, char *);
+IKI_DLLESPEC extern void execute_402(char*, char *);
+IKI_DLLESPEC extern void execute_403(char*, char *);
+IKI_DLLESPEC extern void execute_404(char*, char *);
+IKI_DLLESPEC extern void execute_405(char*, char *);
+IKI_DLLESPEC extern void execute_406(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_1(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_2(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_751(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_752(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_753(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_754(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_755(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_756(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_757(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_758(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_759(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_760(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_761(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_762(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_763(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_764(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_765(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_766(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_767(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_768(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_769(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_770(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_771(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_772(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_773(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_774(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_27(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_28(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_29(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_30(char*, char *);
+IKI_DLLESPEC extern void execute_425(char*, char *);
+IKI_DLLESPEC extern void execute_431(char*, char *);
+IKI_DLLESPEC extern void execute_432(char*, char *);
+IKI_DLLESPEC extern void execute_433(char*, char *);
+IKI_DLLESPEC extern void execute_434(char*, char *);
+IKI_DLLESPEC extern void execute_435(char*, char *);
+IKI_DLLESPEC extern void execute_436(char*, char *);
+IKI_DLLESPEC extern void execute_437(char*, char *);
+IKI_DLLESPEC extern void execute_440(char*, char *);
+IKI_DLLESPEC extern void execute_441(char*, char *);
+IKI_DLLESPEC extern void execute_442(char*, char *);
+IKI_DLLESPEC extern void execute_443(char*, char *);
+IKI_DLLESPEC extern void execute_195(char*, char *);
+IKI_DLLESPEC extern void execute_1871(char*, char *);
+IKI_DLLESPEC extern void execute_1872(char*, char *);
+IKI_DLLESPEC extern void execute_1873(char*, char *);
+IKI_DLLESPEC extern void execute_197(char*, char *);
+IKI_DLLESPEC extern void execute_199(char*, char *);
+IKI_DLLESPEC extern void execute_200(char*, char *);
+IKI_DLLESPEC extern void execute_1874(char*, char *);
+IKI_DLLESPEC extern void execute_1875(char*, char *);
+IKI_DLLESPEC extern void execute_1876(char*, char *);
+IKI_DLLESPEC extern void execute_1877(char*, char *);
+IKI_DLLESPEC extern void execute_1879(char*, char *);
+IKI_DLLESPEC extern void execute_1880(char*, char *);
+IKI_DLLESPEC extern void execute_1881(char*, char *);
+IKI_DLLESPEC extern void execute_1882(char*, char *);
+IKI_DLLESPEC extern void execute_1883(char*, char *);
+IKI_DLLESPEC extern void execute_1884(char*, char *);
+IKI_DLLESPEC extern void execute_1885(char*, char *);
+IKI_DLLESPEC extern void execute_1886(char*, char *);
+IKI_DLLESPEC extern void execute_1887(char*, char *);
+IKI_DLLESPEC extern void execute_1888(char*, char *);
+IKI_DLLESPEC extern void execute_1890(char*, char *);
+IKI_DLLESPEC extern void execute_1891(char*, char *);
+IKI_DLLESPEC extern void execute_1892(char*, char *);
+IKI_DLLESPEC extern void execute_1893(char*, char *);
+IKI_DLLESPEC extern void execute_1895(char*, char *);
+IKI_DLLESPEC extern void execute_1896(char*, char *);
+IKI_DLLESPEC extern void execute_1897(char*, char *);
+IKI_DLLESPEC extern void execute_1898(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_775(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_776(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_777(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_778(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_779(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_780(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_781(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_782(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_783(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_784(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_785(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_786(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_787(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_788(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_789(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_790(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_791(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_792(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_793(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_794(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_795(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_796(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_797(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_798(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_799(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_800(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_801(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_802(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_803(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_804(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_805(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_806(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_807(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_808(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_809(char*, char *);
+IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_810(char*, char *);
+IKI_DLLESPEC extern void execute_1925(char*, char *);
+IKI_DLLESPEC extern void execute_1933(char*, char *);
+IKI_DLLESPEC extern void execute_1934(char*, char *);
+IKI_DLLESPEC extern void execute_1935(char*, char *);
+IKI_DLLESPEC extern void execute_1899(char*, char *);
+IKI_DLLESPEC extern void execute_204(char*, char *);
+IKI_DLLESPEC extern void execute_1946(char*, char *);
+IKI_DLLESPEC extern void execute_1947(char*, char *);
+IKI_DLLESPEC extern void execute_1948(char*, char *);
+IKI_DLLESPEC extern void execute_1949(char*, char *);
+IKI_DLLESPEC extern void execute_1945(char*, char *);
+IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_39(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_47(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_48(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_49(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_50(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_53(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_55(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_56(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_70(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_71(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_73(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_74(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_75(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_76(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_84(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_85(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_86(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_87(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_88(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_89(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_90(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_91(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_92(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_93(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_94(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_95(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_96(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_97(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_98(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_99(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_100(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_101(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_102(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_103(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_104(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_105(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_106(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_107(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_108(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_109(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_110(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_111(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_112(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_113(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_114(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_115(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_116(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_123(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_124(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_125(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_126(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_127(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_128(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_129(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_130(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_131(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_132(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_133(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_134(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_135(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_136(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_137(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_138(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_139(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_140(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_141(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_142(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_143(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_144(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_145(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_146(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_147(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_148(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_149(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_150(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_151(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_152(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_153(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_154(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_155(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_156(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_157(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_158(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_159(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_160(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_161(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_162(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_163(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_164(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_166(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_167(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_168(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_169(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_173(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_174(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_175(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_176(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_177(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_178(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_179(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_180(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_181(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_182(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_183(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_184(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_185(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_186(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_187(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_188(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_189(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_190(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_191(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_196(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_198(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_199(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_200(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_202(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_203(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_204(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_205(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_206(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_207(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_208(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_209(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_210(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_211(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_212(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_213(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_214(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_215(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_216(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_217(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_218(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_219(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_220(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_221(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_222(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_223(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_224(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_225(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_226(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_227(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_228(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_229(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_230(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_231(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_233(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_234(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_235(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_236(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_237(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_238(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_239(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_240(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_241(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_242(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_243(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_244(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_245(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_246(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_247(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_248(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_249(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_250(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_251(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_252(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_253(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_254(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_255(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_256(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_257(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_258(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_259(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_260(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_261(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_262(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_263(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_264(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_265(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_266(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_267(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_268(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_269(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_270(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_271(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_272(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_324(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_325(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_326(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_327(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_329(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_330(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_331(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_332(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_333(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_334(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_335(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_336(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_337(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_338(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_339(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_340(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_341(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_342(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_343(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_344(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_345(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_346(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_347(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_348(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_349(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_350(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_351(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_352(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_353(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_354(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_355(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_356(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_357(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_359(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_361(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_362(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_363(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_364(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_365(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_366(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_367(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_368(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_369(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_370(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_371(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_372(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_373(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_374(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_375(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_376(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_377(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_378(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_379(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_380(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_381(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_382(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_383(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_384(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_385(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_386(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_387(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_388(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_389(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_390(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_391(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_392(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_393(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_394(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_395(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_396(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_397(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_398(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_399(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_400(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_401(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_402(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_403(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_405(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_406(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_407(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_408(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_409(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_410(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_411(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_412(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_413(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_414(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_415(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_416(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_417(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_418(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_419(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_420(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_421(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_422(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_423(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_424(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_425(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_426(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_427(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_428(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_429(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_430(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_431(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_432(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_433(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_434(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_435(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_436(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_437(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_438(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_439(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_440(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_441(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_442(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_443(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_444(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_445(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_447(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_448(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_453(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_454(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_461(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_462(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_467(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_468(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_473(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_474(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_480(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_481(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_486(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_487(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_491(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_492(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_493(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_529(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_530(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_531(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_625(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_626(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_749(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_750(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_902(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_903(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1026(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1027(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1150(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1151(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1332(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1333(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1456(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1457(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1530(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1531(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1532(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1551(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1552(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1601(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1602(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1603(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1616(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1617(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1618(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1661(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1662(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1663(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1676(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1677(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1714(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1715(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1716(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1771(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1772(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1773(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_509(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_547(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_576(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_605(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_642(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_671(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_700(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_729(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_766(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_795(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_824(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_853(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_882(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_919(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_948(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_977(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1006(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1043(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1072(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1101(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1130(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1167(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1196(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1225(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1254(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1283(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1312(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1349(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1378(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1407(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1436(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1473(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[900] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_380, (funcp)execute_381, (funcp)execute_19, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_2296, (funcp)execute_2301, (funcp)execute_2307, (funcp)execute_2314, (funcp)execute_2320, (funcp)execute_2326, (funcp)execute_2334, (funcp)execute_2340, (funcp)execute_2345, (funcp)execute_2350, (funcp)execute_2355, (funcp)execute_2356, (funcp)execute_2357, (funcp)execute_2358, (funcp)execute_2359, (funcp)execute_2360, (funcp)execute_2361, (funcp)execute_2362, (funcp)execute_2363, (funcp)execute_2364, (funcp)execute_2365, (funcp)execute_2366, (funcp)execute_2367, (funcp)execute_2368, (funcp)execute_2369, (funcp)execute_2370, (funcp)execute_2371, (funcp)execute_2372, (funcp)execute_2373, (funcp)execute_2374, (funcp)execute_2375, (funcp)execute_2376, (funcp)execute_2377, (funcp)execute_2378, (funcp)execute_2379, (funcp)execute_2380, (funcp)execute_2381, (funcp)execute_2382, (funcp)execute_2383, (funcp)execute_2384, (funcp)execute_2385, (funcp)execute_2386, (funcp)execute_2387, (funcp)execute_2388, (funcp)execute_2389, (funcp)execute_2390, (funcp)execute_2391, (funcp)execute_2392, (funcp)execute_2393, (funcp)execute_2394, (funcp)execute_2395, (funcp)execute_2396, (funcp)execute_2397, (funcp)execute_2398, (funcp)execute_2399, (funcp)execute_2400, (funcp)execute_2401, (funcp)execute_2402, (funcp)execute_2403, (funcp)execute_2404, (funcp)execute_2405, (funcp)execute_2406, (funcp)execute_2407, (funcp)execute_2408, (funcp)execute_2409, (funcp)execute_2410, (funcp)execute_2411, (funcp)execute_2412, (funcp)execute_2413, (funcp)execute_2414, (funcp)execute_2415, (funcp)execute_2416, (funcp)execute_2417, (funcp)execute_2418, (funcp)execute_2419, (funcp)execute_2420, (funcp)execute_2421, (funcp)execute_2422, (funcp)execute_2423, (funcp)execute_2424, (funcp)execute_2425, (funcp)execute_2426, (funcp)execute_2427, (funcp)execute_2428, (funcp)execute_2429, (funcp)execute_2430, (funcp)execute_2431, (funcp)execute_2432, (funcp)execute_2433, (funcp)execute_2434, (funcp)execute_2435, (funcp)execute_2436, (funcp)execute_2437, (funcp)execute_2438, (funcp)execute_2439, (funcp)execute_2440, (funcp)execute_2441, (funcp)execute_2442, (funcp)execute_2443, (funcp)execute_2444, (funcp)execute_2445, (funcp)execute_2446, (funcp)execute_2447, (funcp)execute_2448, (funcp)execute_2449, (funcp)execute_2450, (funcp)execute_2451, (funcp)execute_2452, (funcp)execute_2453, (funcp)execute_2454, (funcp)execute_2455, (funcp)execute_2456, (funcp)execute_2457, (funcp)execute_2458, (funcp)execute_2459, (funcp)execute_2460, (funcp)execute_2461, (funcp)execute_2462, (funcp)execute_2463, (funcp)execute_2464, (funcp)execute_2465, (funcp)execute_2466, (funcp)execute_2467, (funcp)execute_2468, (funcp)execute_2469, (funcp)execute_2470, (funcp)execute_2471, (funcp)execute_2472, (funcp)execute_2473, (funcp)execute_2474, (funcp)execute_2475, (funcp)execute_2476, (funcp)execute_2477, (funcp)execute_2478, (funcp)execute_2479, (funcp)execute_2480, (funcp)execute_2481, (funcp)execute_2482, (funcp)execute_2483, (funcp)execute_2484, (funcp)execute_2485, (funcp)execute_2486, (funcp)execute_2487, (funcp)execute_2488, (funcp)execute_2489, (funcp)execute_2490, (funcp)execute_2491, (funcp)execute_2492, (funcp)execute_2493, (funcp)execute_2494, (funcp)execute_2495, (funcp)execute_2496, (funcp)execute_2497, (funcp)execute_2498, (funcp)execute_2499, (funcp)execute_2500, (funcp)execute_2501, (funcp)execute_2502, (funcp)execute_2503, (funcp)execute_2504, (funcp)execute_2505, (funcp)execute_2506, (funcp)execute_2507, (funcp)execute_2508, (funcp)execute_2509, (funcp)execute_2510, (funcp)execute_2511, (funcp)execute_2512, (funcp)execute_2513, (funcp)execute_2514, (funcp)execute_2515, (funcp)execute_2516, (funcp)execute_2517, (funcp)execute_2518, (funcp)execute_2519, (funcp)execute_2520, (funcp)execute_2521, (funcp)execute_2522, (funcp)execute_2523, (funcp)execute_2524, (funcp)execute_2525, (funcp)execute_2526, (funcp)execute_2527, (funcp)execute_2528, (funcp)execute_2529, (funcp)execute_2530, (funcp)execute_2531, (funcp)execute_2532, (funcp)execute_2533, (funcp)execute_2534, (funcp)execute_2535, (funcp)execute_2536, (funcp)execute_2537, (funcp)execute_2538, (funcp)execute_2539, (funcp)execute_2540, (funcp)execute_2541, (funcp)execute_2542, (funcp)execute_2543, (funcp)execute_2544, (funcp)execute_2545, (funcp)execute_2546, (funcp)execute_2547, (funcp)execute_2548, (funcp)execute_2549, (funcp)execute_2550, (funcp)execute_2551, (funcp)execute_2552, (funcp)execute_2553, (funcp)execute_2554, (funcp)execute_2555, (funcp)execute_2556, (funcp)execute_2557, (funcp)execute_2558, (funcp)execute_2559, (funcp)execute_2560, (funcp)execute_2561, (funcp)execute_2562, (funcp)execute_2563, (funcp)execute_2564, (funcp)execute_2565, (funcp)execute_2566, (funcp)execute_2567, (funcp)execute_2568, (funcp)execute_2569, (funcp)execute_2570, (funcp)execute_2571, (funcp)execute_2572, (funcp)execute_2573, (funcp)execute_2574, (funcp)execute_2575, (funcp)execute_2576, (funcp)execute_2577, (funcp)execute_2578, (funcp)execute_2579, (funcp)execute_2580, (funcp)execute_2581, (funcp)execute_2582, (funcp)execute_2583, (funcp)execute_384, (funcp)vlog_timingcheck_execute_0, (funcp)execute_22, (funcp)execute_387, (funcp)execute_25, (funcp)execute_389, (funcp)execute_390, (funcp)execute_388, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_391, (funcp)execute_392, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_397, (funcp)execute_398, (funcp)execute_399, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_401, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)execute_406, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_1, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_2, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_751, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_752, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_753, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_754, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_755, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_756, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_757, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_758, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_759, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_760, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_761, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_762, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_763, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_764, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_765, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_766, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_767, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_768, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_769, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_770, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_771, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_772, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_773, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_774, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_27, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_28, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_29, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_30, (funcp)execute_425, (funcp)execute_431, (funcp)execute_432, (funcp)execute_433, (funcp)execute_434, (funcp)execute_435, (funcp)execute_436, (funcp)execute_437, (funcp)execute_440, (funcp)execute_441, (funcp)execute_442, (funcp)execute_443, (funcp)execute_195, (funcp)execute_1871, (funcp)execute_1872, (funcp)execute_1873, (funcp)execute_197, (funcp)execute_199, (funcp)execute_200, (funcp)execute_1874, (funcp)execute_1875, (funcp)execute_1876, (funcp)execute_1877, (funcp)execute_1879, (funcp)execute_1880, (funcp)execute_1881, (funcp)execute_1882, (funcp)execute_1883, (funcp)execute_1884, (funcp)execute_1885, (funcp)execute_1886, (funcp)execute_1887, (funcp)execute_1888, (funcp)execute_1890, (funcp)execute_1891, (funcp)execute_1892, (funcp)execute_1893, (funcp)execute_1895, (funcp)execute_1896, (funcp)execute_1897, (funcp)execute_1898, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_775, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_776, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_777, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_778, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_779, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_780, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_781, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_782, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_783, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_784, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_785, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_786, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_787, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_788, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_789, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_790, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_791, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_792, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_793, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_794, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_795, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_796, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_797, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_798, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_799, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_800, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_801, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_802, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_803, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_804, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_805, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_806, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_807, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_808, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_809, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_810, (funcp)execute_1925, (funcp)execute_1933, (funcp)execute_1934, (funcp)execute_1935, (funcp)execute_1899, (funcp)execute_204, (funcp)execute_1946, (funcp)execute_1947, (funcp)execute_1948, (funcp)execute_1949, (funcp)execute_1945, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)transaction_46, (funcp)transaction_47, (funcp)transaction_48, (funcp)transaction_49, (funcp)transaction_50, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_53, (funcp)transaction_54, (funcp)transaction_55, (funcp)transaction_56, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_70, (funcp)transaction_71, (funcp)transaction_72, (funcp)transaction_73, (funcp)transaction_74, (funcp)transaction_75, (funcp)transaction_76, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_84, (funcp)transaction_85, (funcp)transaction_86, (funcp)transaction_87, (funcp)transaction_88, (funcp)transaction_89, (funcp)transaction_90, (funcp)transaction_91, (funcp)transaction_92, (funcp)transaction_93, (funcp)transaction_94, (funcp)transaction_95, (funcp)transaction_96, (funcp)transaction_97, (funcp)transaction_98, (funcp)transaction_99, (funcp)transaction_100, (funcp)transaction_101, (funcp)transaction_102, (funcp)transaction_103, (funcp)transaction_104, (funcp)transaction_105, (funcp)transaction_106, (funcp)transaction_107, (funcp)transaction_108, (funcp)transaction_109, (funcp)transaction_110, (funcp)transaction_111, (funcp)transaction_112, (funcp)transaction_113, (funcp)transaction_114, (funcp)transaction_115, (funcp)transaction_116, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_123, (funcp)transaction_124, (funcp)transaction_125, (funcp)transaction_126, (funcp)transaction_127, (funcp)transaction_128, (funcp)transaction_129, (funcp)transaction_130, (funcp)transaction_131, (funcp)transaction_132, (funcp)transaction_133, (funcp)transaction_134, (funcp)transaction_135, (funcp)transaction_136, (funcp)transaction_137, (funcp)transaction_138, (funcp)transaction_139, (funcp)transaction_140, (funcp)transaction_141, (funcp)transaction_142, (funcp)transaction_143, (funcp)transaction_144, (funcp)transaction_145, (funcp)transaction_146, (funcp)transaction_147, (funcp)transaction_148, (funcp)transaction_149, (funcp)transaction_150, (funcp)transaction_151, (funcp)transaction_152, (funcp)transaction_153, (funcp)transaction_154, (funcp)transaction_155, (funcp)transaction_156, (funcp)transaction_157, (funcp)transaction_158, (funcp)transaction_159, (funcp)transaction_160, (funcp)transaction_161, (funcp)transaction_162, (funcp)transaction_163, (funcp)transaction_164, (funcp)transaction_165, (funcp)transaction_166, (funcp)transaction_167, (funcp)transaction_168, (funcp)transaction_169, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_173, (funcp)transaction_174, (funcp)transaction_175, (funcp)transaction_176, (funcp)transaction_177, (funcp)transaction_178, (funcp)transaction_179, (funcp)transaction_180, (funcp)transaction_181, (funcp)transaction_182, (funcp)transaction_183, (funcp)transaction_184, (funcp)transaction_185, (funcp)transaction_186, (funcp)transaction_187, (funcp)transaction_188, (funcp)transaction_189, (funcp)transaction_190, (funcp)transaction_191, (funcp)transaction_192, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_196, (funcp)transaction_197, (funcp)transaction_198, (funcp)transaction_199, (funcp)transaction_200, (funcp)transaction_201, (funcp)transaction_202, (funcp)transaction_203, (funcp)transaction_204, (funcp)transaction_205, (funcp)transaction_206, (funcp)transaction_207, (funcp)transaction_208, (funcp)transaction_209, (funcp)transaction_210, (funcp)transaction_211, (funcp)transaction_212, (funcp)transaction_213, (funcp)transaction_214, (funcp)transaction_215, (funcp)transaction_216, (funcp)transaction_217, (funcp)transaction_218, (funcp)transaction_219, (funcp)transaction_220, (funcp)transaction_221, (funcp)transaction_222, (funcp)transaction_223, (funcp)transaction_224, (funcp)transaction_225, (funcp)transaction_226, (funcp)transaction_227, (funcp)transaction_228, (funcp)transaction_229, (funcp)transaction_230, (funcp)transaction_231, (funcp)transaction_232, (funcp)transaction_233, (funcp)transaction_234, (funcp)transaction_235, (funcp)transaction_236, (funcp)transaction_237, (funcp)transaction_238, (funcp)transaction_239, (funcp)transaction_240, (funcp)transaction_241, (funcp)transaction_242, (funcp)transaction_243, (funcp)transaction_244, (funcp)transaction_245, (funcp)transaction_246, (funcp)transaction_247, (funcp)transaction_248, (funcp)transaction_249, (funcp)transaction_250, (funcp)transaction_251, (funcp)transaction_252, (funcp)transaction_253, (funcp)transaction_254, (funcp)transaction_255, (funcp)transaction_256, (funcp)transaction_257, (funcp)transaction_258, (funcp)transaction_259, (funcp)transaction_260, (funcp)transaction_261, (funcp)transaction_262, (funcp)transaction_263, (funcp)transaction_264, (funcp)transaction_265, (funcp)transaction_266, (funcp)transaction_267, (funcp)transaction_268, (funcp)transaction_269, (funcp)transaction_270, (funcp)transaction_271, (funcp)transaction_272, (funcp)transaction_273, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_324, (funcp)transaction_325, (funcp)transaction_326, (funcp)transaction_327, (funcp)transaction_328, (funcp)transaction_329, (funcp)transaction_330, (funcp)transaction_331, (funcp)transaction_332, (funcp)transaction_333, (funcp)transaction_334, (funcp)transaction_335, (funcp)transaction_336, (funcp)transaction_337, (funcp)transaction_338, (funcp)transaction_339, (funcp)transaction_340, (funcp)transaction_341, (funcp)transaction_342, (funcp)transaction_343, (funcp)transaction_344, (funcp)transaction_345, (funcp)transaction_346, (funcp)transaction_347, (funcp)transaction_348, (funcp)transaction_349, (funcp)transaction_350, (funcp)transaction_351, (funcp)transaction_352, (funcp)transaction_353, (funcp)transaction_354, (funcp)transaction_355, (funcp)transaction_356, (funcp)transaction_357, (funcp)transaction_358, (funcp)transaction_359, (funcp)transaction_360, (funcp)transaction_361, (funcp)transaction_362, (funcp)transaction_363, (funcp)transaction_364, (funcp)transaction_365, (funcp)transaction_366, (funcp)transaction_367, (funcp)transaction_368, (funcp)transaction_369, (funcp)transaction_370, (funcp)transaction_371, (funcp)transaction_372, (funcp)transaction_373, (funcp)transaction_374, (funcp)transaction_375, (funcp)transaction_376, (funcp)transaction_377, (funcp)transaction_378, (funcp)transaction_379, (funcp)transaction_380, (funcp)transaction_381, (funcp)transaction_382, (funcp)transaction_383, (funcp)transaction_384, (funcp)transaction_385, (funcp)transaction_386, (funcp)transaction_387, (funcp)transaction_388, (funcp)transaction_389, (funcp)transaction_390, (funcp)transaction_391, (funcp)transaction_392, (funcp)transaction_393, (funcp)transaction_394, (funcp)transaction_395, (funcp)transaction_396, (funcp)transaction_397, (funcp)transaction_398, (funcp)transaction_399, (funcp)transaction_400, (funcp)transaction_401, (funcp)transaction_402, (funcp)transaction_403, (funcp)transaction_404, (funcp)transaction_405, (funcp)transaction_406, (funcp)transaction_407, (funcp)transaction_408, (funcp)transaction_409, (funcp)transaction_410, (funcp)transaction_411, (funcp)transaction_412, (funcp)transaction_413, (funcp)transaction_414, (funcp)transaction_415, (funcp)transaction_416, (funcp)transaction_417, (funcp)transaction_418, (funcp)transaction_419, (funcp)transaction_420, (funcp)transaction_421, (funcp)transaction_422, (funcp)transaction_423, (funcp)transaction_424, (funcp)transaction_425, (funcp)transaction_426, (funcp)transaction_427, (funcp)transaction_428, (funcp)transaction_429, (funcp)transaction_430, (funcp)transaction_431, (funcp)transaction_432, (funcp)transaction_433, (funcp)transaction_434, (funcp)transaction_435, (funcp)transaction_436, (funcp)transaction_437, (funcp)transaction_438, (funcp)transaction_439, (funcp)transaction_440, (funcp)transaction_441, (funcp)transaction_442, (funcp)transaction_443, (funcp)transaction_444, (funcp)transaction_445, (funcp)transaction_447, (funcp)transaction_448, (funcp)transaction_453, (funcp)transaction_454, (funcp)transaction_461, (funcp)transaction_462, (funcp)transaction_467, (funcp)transaction_468, (funcp)transaction_473, (funcp)transaction_474, (funcp)transaction_480, (funcp)transaction_481, (funcp)transaction_486, (funcp)transaction_487, (funcp)transaction_491, (funcp)transaction_492, (funcp)transaction_493, (funcp)transaction_529, (funcp)transaction_530, (funcp)transaction_531, (funcp)transaction_625, (funcp)transaction_626, (funcp)transaction_749, (funcp)transaction_750, (funcp)transaction_902, (funcp)transaction_903, (funcp)transaction_1026, (funcp)transaction_1027, (funcp)transaction_1150, (funcp)transaction_1151, (funcp)transaction_1332, (funcp)transaction_1333, (funcp)transaction_1456, (funcp)transaction_1457, (funcp)transaction_1530, (funcp)transaction_1531, (funcp)transaction_1532, (funcp)transaction_1551, (funcp)transaction_1552, (funcp)transaction_1601, (funcp)transaction_1602, (funcp)transaction_1603, (funcp)transaction_1616, (funcp)transaction_1617, (funcp)transaction_1618, (funcp)transaction_1661, (funcp)transaction_1662, (funcp)transaction_1663, (funcp)transaction_1676, (funcp)transaction_1677, (funcp)transaction_1714, (funcp)transaction_1715, (funcp)transaction_1716, (funcp)transaction_1771, (funcp)transaction_1772, (funcp)transaction_1773, (funcp)transaction_509, (funcp)transaction_547, (funcp)transaction_576, (funcp)transaction_605, (funcp)transaction_642, (funcp)transaction_671, (funcp)transaction_700, (funcp)transaction_729, (funcp)transaction_766, (funcp)transaction_795, (funcp)transaction_824, (funcp)transaction_853, (funcp)transaction_882, (funcp)transaction_919, (funcp)transaction_948, (funcp)transaction_977, (funcp)transaction_1006, (funcp)transaction_1043, (funcp)transaction_1072, (funcp)transaction_1101, (funcp)transaction_1130, (funcp)transaction_1167, (funcp)transaction_1196, (funcp)transaction_1225, (funcp)transaction_1254, (funcp)transaction_1283, (funcp)transaction_1312, (funcp)transaction_1349, (funcp)transaction_1378, (funcp)transaction_1407, (funcp)transaction_1436, (funcp)transaction_1473};
+const int NumRelocateId= 900;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/pwm_test_db_time_synth/xsim.reloc",  (void **)funcTab, 900);
+	iki_vhdl_file_variable_register(dp + 1321952);
+	iki_vhdl_file_variable_register(dp + 1322008);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/pwm_test_db_time_synth/xsim.reloc");
+}
+
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+
+void wrapper_func_0(char *dp)
+
+{
+
+	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1327032, dp + 1327488, 0, 0, 0, 0, 1, 1);
+
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/pwm_test_db_time_synth/xsim.reloc");
+	wrapper_func_0(dp);
+
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/pwm_test_db_time_synth/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/pwm_test_db_time_synth/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/pwm_test_db_time_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.win64.obj b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..4ab6d50
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.win64.obj differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.dbg b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.dbg
new file mode 100644
index 0000000..b4a8dfc
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.dbg differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.mem b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.mem
new file mode 100644
index 0000000..99f00d2
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.mem differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.reloc b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.reloc
new file mode 100644
index 0000000..66264ce
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.reloc differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rlx b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rlx
new file mode 100644
index 0000000..6795fbb
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  4084566433590232689  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl" , 
+    buildDate : "Oct 19 2021" , 
+    buildTime : "03:16:22" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_time_synth/xsimk.exe\"   \"xsim.dir/pwm_test_db_time_synth/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_time_synth/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rtti b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rtti
new file mode 100644
index 0000000..4168c98
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diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.svtype b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.svtype
new file mode 100644
index 0000000..5315270
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.svtype differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.type b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.type
new file mode 100644
index 0000000..4185d6e
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diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.xdbg b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.xdbg
new file mode 100644
index 0000000..1ecabf7
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.xdbg differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimSettings.ini b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimSettings.ini
new file mode 100644
index 0000000..fabf023
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=210
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=210
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimcrash.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimk.exe b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimk.exe
new file mode 100644
index 0000000..dde0172
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimk.exe differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimkernel.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimkernel.log
new file mode 100644
index 0000000..104868a
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/pwm_test_db_time_synth/xsimk.exe -simmode gui -wdb pwm_test_db_time_synth.wdb -simrunnum 0 -socket 49950
+Design successfully loaded
+Design Loading Memory Usage: 10480 KB (Peak: 10480 KB)
+Design Loading CPU Usage: 31 ms
+Simulation completed
+Simulation Memory Usage: 20776 KB (Peak: 20776 KB)
+Simulation CPU Usage: 461827 ms
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb
new file mode 100644
index 0000000..755c375
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb
new file mode 100644
index 0000000..c12c6f1
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb
new file mode 100644
index 0000000..7f2244b
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..302f1e1
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,6 @@
+0.7
+2020.2
+Oct 19 2021
+03:16:22
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v,1647460459,verilog,,,,glbl;pwm_test,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1647459068,vhdl,,,,pwm_test_db,,,,,,,,
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.ini b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.ini
new file mode 100644
index 0000000..e8199b2
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.log
new file mode 100644
index 0000000..a0e1ca7
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.log
@@ -0,0 +1,2 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.pb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.pb
new file mode 100644
index 0000000..f4c8b8e
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.log b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.log
new file mode 100644
index 0000000..086a5ad
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.log
@@ -0,0 +1,3 @@
+INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module pwm_test
+INFO: [VRFC 10-311] analyzing module glbl
diff --git a/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.pb b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.pb
new file mode 100644
index 0000000..465ffe8
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.pb differ
diff --git a/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd b/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
new file mode 100644
index 0000000..3f2acc0
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
@@ -0,0 +1,67 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 16.03.2022 20:07:22
+-- Design Name: 
+-- Module Name: pwm_test_db - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity pwm_test_db is
+--  Port ( );
+end pwm_test_db;
+
+architecture Behavioral of pwm_test_db is
+
+component pwm_test is
+    Port ( clk : in STD_LOGIC;
+           led : out STD_LOGIC);
+end component;
+
+signal clk, led : std_logic := '0';
+
+begin
+
+uut: pwm_test PORT MAP (
+    clk => clk,
+    led => led
+);
+
+--generate clock
+clk <= not clk after 10 ns;
+
+
+process 
+begin
+
+
+    wait;
+
+end process;
+
+
+end Behavioral;
diff --git a/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd b/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd
new file mode 100644
index 0000000..bbc5a75
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd
@@ -0,0 +1,13 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0x0",
+      "gen_directory": "../../../../Coraz7_Test.gen/sources_1/bd/IO_Test",
+      "name": "IO_Test",
+      "rev_ctrl_bd_flag": "RevCtrlBdOff",
+      "synth_flow_mode": "Hierarchical",
+      "tool_version": "2021.2"
+    },
+    "design_tree": {}
+  }
+}
\ No newline at end of file
diff --git a/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/ui/bd_316ac62b.ui b/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/ui/bd_316ac62b.ui
new file mode 100644
index 0000000..b6d7bc6
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/ui/bd_316ac62b.ui
@@ -0,0 +1,12 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-600,-236",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0r6  2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
+#  -string -flagsOSRD
+levelinfo -pg 1 0 10
+pagesize -pg 1 -db -bbox -sgen 0 0 10 10
+"
+}
+
diff --git a/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v b/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
new file mode 100644
index 0000000..402d187
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
@@ -0,0 +1,27 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 16.03.2022 18:50:02
+// Design Name: 
+// Module Name: IO_Test
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module IO_Test(
+    input clk,
+    output led
+    );
+endmodule
diff --git a/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd b/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
new file mode 100644
index 0000000..08fff25
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 16.03.2022 19:12:30
+-- Design Name: 
+-- Module Name: pwm_test - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity pwm_test is
+    Port ( clk : in STD_LOGIC;
+           led : out STD_LOGIC);
+end pwm_test;
+
+architecture Behavioral of pwm_test is
+
+constant pwm_duty : integer := 50;  --Duty 
+constant counter_max : integer := 125000000; --100000000 geht, 125000000 geht nicht ?!
+
+
+signal count : integer := 0;
+
+begin
+
+process(clk)
+    begin
+        if rising_edge(clk) then
+            count <= count +1;
+        end if;
+        
+        if(count >= counter_max)then
+                count <= 0;
+                led <= '0';
+        elsif (count >= counter_max/100*pwm_duty) then
+                led <= '1';
+        end if;
+   
+end process;
+
+--test
+    
+end Behavioral;
diff --git a/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp b/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp
new file mode 100644
index 0000000..d879b17
Binary files /dev/null and b/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp differ
diff --git a/Coraz7_Test/Coraz7_Test.xpr b/Coraz7_Test/Coraz7_Test.xpr
new file mode 100644
index 0000000..7d773c2
--- /dev/null
+++ b/Coraz7_Test/Coraz7_Test.xpr
@@ -0,0 +1,240 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="56" Path="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="0548ab2430ec43b198e1ef48542e139d"/>
+    <Option Name="Part" Val="xc7z010clg400-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2021.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2020.4"/>
+    <Option Name="SimulatorVersionQuesta" Val="2020.4"/>
+    <Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
+    <Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
+    <Option Name="SimulatorVersionRiviera" Val="2020.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
+    <Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
+    <Option Name="BoardPart" Val="digilentinc.com:zybo-z7-10:part0:1.0"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../../AppData/Roaming/Xilinx/Vivado/2021.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="zybo-z7-10"/>
+    <Option Name="WTXSimLaunchSim" Val="44"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/pwm_test.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="pwm_test"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/new/pwm_test_db.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/pwm_test_db_func_synth.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="pwm_test_db"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/pwm_test_db_func_synth.wcfg"/>
+        <Option Name="xsim.simulate.runtime" Val="5 ms"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/pwm_test.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="15">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/pwm_test.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/Coraz7_Test/pwm_test_db_func_synth.wcfg b/Coraz7_Test/pwm_test_db_func_synth.wcfg
new file mode 100644
index 0000000..3801930
--- /dev/null
+++ b/Coraz7_Test/pwm_test_db_func_synth.wcfg
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="pwm_test_db_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="pwm_test_db" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="103,350.000 ns"></ZoomStartTime>
+      <ZoomEndTime time="103,761.001 ns"></ZoomEndTime>
+      <Cursor1Time time="4,999,989.266 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="147"></NameColumnWidth>
+      <ValueColumnWidth column_width="62"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="3" />
+   <wvobject fp_name="/pwm_test_db/clk" type="logic">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pwm_test_db/led" type="logic">
+      <obj_property name="ElementShortName">led</obj_property>
+      <obj_property name="ObjectShortName">led</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pwm_test_db/uut/count" type="other">
+      <obj_property name="ElementShortName">count</obj_property>
+      <obj_property name="ObjectShortName">count</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/Coraz7_Test/vivado.jou b/Coraz7_Test/vivado.jou
new file mode 100644
index 0000000..9cf7de6
--- /dev/null
+++ b/Coraz7_Test/vivado.jou
@@ -0,0 +1,26 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri Mar 25 10:05:22 2022
+# Process ID: 12568
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6576 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
+update_compile_order -fileset sources_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+open_run synth_1 -name synth_1
+set_property IOSTANDARD {} [get_ports [list clk]]
+set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]
+save_constraints
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+close_design
+open_run impl_1
diff --git a/Coraz7_Test/vivado.log b/Coraz7_Test/vivado.log
new file mode 100644
index 0000000..a3dc2dc
--- /dev/null
+++ b/Coraz7_Test/vivado.log
@@ -0,0 +1,144 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri Mar 25 10:05:22 2022
+# Process ID: 12568
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6576 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'.
+Scanning sources...
+Finished scanning sources
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+open_project: Time (s): cpu = 00:00:39 ; elapsed = 00:00:18 . Memory (MB): peak = 1253.125 ; gain = 0.000
+update_compile_order -fileset sources_1
+exit
+INFO: [Common 17-206] Exiting Vivado at Fri Mar 25 10:18:08 2022...
+eDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Fri Mar 25 10:07:58 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+open_run synth_1 -name synth_1
+Design is defaulting to impl run constrset: constrs_1
+Design is defaulting to synth run part: xc7z010clg400-1
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1573.328 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1579.062 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+open_run: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 1699.648 ; gain = 126.320
+set_property IOSTANDARD {} [get_ports [list clk]]
+set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]
+save_constraints
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 2351.969 ; gain = 0.000
+[Fri Mar 25 10:11:13 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+close_design
+open_run impl_1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2351.969 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Timing 38-478] Restoring timing data from binary archive.
+INFO: [Timing 38-479] Binary timing data restore complete.
+INFO: [Project 1-856] Restoring constraints from binary archive.
+INFO: [Project 1-853] Binary constraint restore complete.
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 2351.969 ; gain = 0.000
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 2351.969 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.969 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+exit
+INFO: [Common 17-206] Exiting Vivado at Fri Mar 25 11:12:40 2022...
diff --git a/Coraz7_Test/vivado_1824.backup.jou b/Coraz7_Test/vivado_1824.backup.jou
new file mode 100644
index 0000000..662668d
--- /dev/null
+++ b/Coraz7_Test/vivado_1824.backup.jou
@@ -0,0 +1,115 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Wed Mar 16 18:29:30 2022
+# Process ID: 1824
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21192 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
+create_bd_design "IO_Test"
+update_compile_order -fileset sources_1
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new
+close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v w ]
+add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
+update_compile_order -fileset sources_1
+close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd w ]
+add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
+update_compile_order -fileset sources_1
+export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v] -no_script -reset -force -quiet
+remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_simulation
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_simulation
+source pwm_test.tcl
+launch_runs impl_1 -jobs 6
+wait_on_run impl_1
+open_run impl_1
+export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd] -no_script -reset -force -quiet
+remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd
+file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd w ]
+add_files -fileset sim_1 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
+update_compile_order -fileset sim_1
+update_compile_order -fileset sim_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_runs impl_1 -jobs 6
+wait_on_run impl_1
+refresh_design
+launch_simulation
+launch_simulation
+launch_simulation
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_simulation
+launch_simulation -mode post-synthesis -type functional
+source pwm_test_db.tcl
+relaunch_sim
+relaunch_sim
+current_wave_config {Untitled 2}
+add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 
+relaunch_sim
+current_wave_config {Untitled 2}
+add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 
+launch_simulation
+relaunch_sim
+relaunch_sim
+current_wave_config {Untitled 2}
+add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_2 }} 
+relaunch_sim
+current_wave_config {Untitled 2}
+add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_1 }} 
+current_wave_config {Untitled 2}
+add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_3 }} 
+relaunch_sim
+current_wave_config {Untitled 2}
+add_wave {{/pwm_test_db/uut}} 
+relaunch_sim
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+add_files -fileset sim_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+set_property xsim.view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg [get_filesets sim_1]
+set_property -name {xsim.simulate.runtime} -value {5000 ms} -objects [get_filesets sim_1]
+relaunch_sim
+relaunch_sim
+launch_simulation
+relaunch_sim
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+relaunch_sim
+relaunch_sim
+reset_simulation -simset sim_1 -mode behavioral
+relaunch_sim
+reset_simulation -simset sim_1 -mode post-synthesis -type timing
+close_design
+launch_simulation -mode post-synthesis -type timing
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+close_sim
+current_sim simulation_2
+close_sim
+close_sim
diff --git a/Coraz7_Test/vivado_1824.backup.log b/Coraz7_Test/vivado_1824.backup.log
new file mode 100644
index 0000000..fe58ccd
--- /dev/null
+++ b/Coraz7_Test/vivado_1824.backup.log
@@ -0,0 +1,996 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Wed Mar 16 18:29:30 2022
+# Process ID: 1824
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21192 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'.
+Scanning sources...
+Finished scanning sources
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 1252.246 ; gain = 0.000
+create_bd_design "IO_Test"
+Wrote  : <C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.srcs\sources_1\bd\IO_Test\IO_Test.bd> 
+INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1/bd/IO_Test for IO_Test cannot be found.
+create_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1252.246 ; gain = 0.000
+update_compile_order -fileset sources_1
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
+file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new
+close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v w ]
+add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
+update_compile_order -fileset sources_1
+close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd w ]
+add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
+update_compile_order -fileset sources_1
+export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v] -no_script -reset -force -quiet
+remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+launch_runs synth_1 -jobs 6
+WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
+[Wed Mar 16 19:55:26 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test'
+ERROR: [VRFC 10-3031] 'led' with mode 'out' cannot be read [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]
+ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
+INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd' ignored due to errors
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log'
+ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
+[Wed Mar 16 19:57:51 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_behav xil_defaultlib.pwm_test -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_behav xil_defaultlib.pwm_test -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test
+Built simulation snapshot pwm_test_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_behav -key {Behavioral:sim_1:Functional:pwm_test} -tclbatch {pwm_test.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source pwm_test.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1349.082 ; gain = 26.551
+launch_runs impl_1 -jobs 6
+[Wed Mar 16 19:58:36 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+open_run impl_1
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1688.973 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1764.523 ; gain = 0.172
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1764.523 ; gain = 0.172
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2169.715 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+open_run: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2238.512 ; gain = 881.695
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd] -no_script -reset -force -quiet
+remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd
+Wrote  : <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/ui/bd_316ac62b.ui> 
+file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd w ]
+add_files -fileset sim_1 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
+update_compile_order -fileset sim_1
+update_compile_order -fileset sim_1
+reset_run synth_1
+INFO: [Project 1-1160] Copying file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp to C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1 and adding it to utils fileset
+launch_runs synth_1 -jobs 6
+[Wed Mar 16 20:13:13 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 6
+[Wed Mar 16 20:13:57 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+refresh_design
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2357.781 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 2357.781 ; gain = 0.000
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 2357.781 ; gain = 0.000
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+launch_runs synth_1 -jobs 6
+[Wed Mar 16 20:16:57 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"
+launch_simulation -mode post-synthesis -type functional
+Command: launch_simulation  -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+Design is defaulting to impl run constrset: constrs_1
+Design is defaulting to synth run part: xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2379.422 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2431.441 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'...
+INFO: [SIM-utils-25] write_verilog -mode funcsim -nolib -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v"
+INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module pwm_test
+INFO: [VRFC 10-311] analyzing module glbl
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package vl.vl_types
+Compiling module xil_defaultlib.glbl
+Compiling module unisims_ver.BUFG
+Compiling module unisims_ver.IBUF
+Compiling module unisims_ver.x_lut1_mux2
+Compiling module unisims_ver.LUT1(INIT=2'b01)
+Compiling module unisims_ver.FDCE_default
+Compiling module unisims_ver.CARRY4
+Compiling module unisims_ver.OBUF
+Compiling module unisims_ver.latchsre_ldce
+Compiling module unisims_ver.LDCE
+Compiling module unisims_ver.x_lut2_mux4
+Compiling module unisims_ver.LUT2
+Compiling module xil_defaultlib.pwm_test
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_func_synth
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_func_synth -key {Post-Synthesis:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_func_synth' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 2560.469 ; gain = 181.691
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'...
+INFO: [SIM-utils-25] write_verilog -mode funcsim -nolib -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v"
+INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module pwm_test
+INFO: [VRFC 10-311] analyzing module glbl
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package vl.vl_types
+Compiling module xil_defaultlib.glbl
+Compiling module unisims_ver.BUFG
+Compiling module unisims_ver.IBUF
+Compiling module unisims_ver.x_lut1_mux2
+Compiling module unisims_ver.LUT1(INIT=2'b01)
+Compiling module unisims_ver.FDCE_default
+Compiling module unisims_ver.CARRY4
+Compiling module unisims_ver.OBUF
+Compiling module unisims_ver.latchsre_ldce
+Compiling module unisims_ver.LDCE
+Compiling module unisims_ver.x_lut2_mux4
+Compiling module unisims_ver.LUT2
+Compiling module xil_defaultlib.pwm_test
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_func_synth
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 2565.645 ; gain = 0.000
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package vl.vl_types
+Compiling module xil_defaultlib.glbl
+Compiling module unisims_ver.BUFG
+Compiling module unisims_ver.IBUF
+Compiling module unisims_ver.x_lut1_mux2
+Compiling module unisims_ver.LUT1(INIT=2'b01)
+Compiling module unisims_ver.FDCE_default
+Compiling module unisims_ver.CARRY4
+Compiling module unisims_ver.OBUF
+Compiling module unisims_ver.latchsre_ldce
+Compiling module unisims_ver.LDCE
+Compiling module unisims_ver.x_lut2_mux4
+Compiling module unisims_ver.LUT2
+Compiling module xil_defaultlib.pwm_test
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_func_synth
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 2569.133 ; gain = 3.281
+current_wave_config {Untitled 2}
+Untitled 2
+add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 2569.211 ; gain = 0.000
+current_wave_config {Untitled 2}
+Untitled 2
+add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 2635.207 ; gain = 0.000
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package vl.vl_types
+Compiling module xil_defaultlib.glbl
+Compiling module unisims_ver.BUFG
+Compiling module unisims_ver.IBUF
+Compiling module unisims_ver.x_lut1_mux2
+Compiling module unisims_ver.LUT1(INIT=2'b01)
+Compiling module unisims_ver.FDCE_default
+Compiling module unisims_ver.CARRY4
+Compiling module unisims_ver.OBUF
+Compiling module unisims_ver.latchsre_ldce
+Compiling module unisims_ver.LDCE
+Compiling module unisims_ver.x_lut2_mux4
+Compiling module unisims_ver.LUT2
+Compiling module xil_defaultlib.pwm_test
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_func_synth
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 2847.305 ; gain = 0.000
+current_wave_config {Untitled 2}
+Untitled 2
+add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_2 }} 
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3078.270 ; gain = 0.000
+current_wave_config {Untitled 2}
+Untitled 2
+add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_1 }} 
+current_wave_config {Untitled 2}
+Untitled 2
+add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_3 }} 
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000
+current_wave_config {Untitled 2}
+Untitled 2
+add_wave {{/pwm_test_db/uut}} 
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+add_files -fileset sim_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+set_property xsim.view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg [get_filesets sim_1]
+set_property -name {xsim.simulate.runtime} -value {5000 ms} -objects [get_filesets sim_1]
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 3895.711 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed Mar 16 20:50:10 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000
+reset_simulation -simset sim_1 -mode behavioral
+INFO: [Vivado 12-2266] Removing simulation data...
+WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb
+WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log
+WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb
+WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg
+WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimcrash.log
+WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe
+WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log
+WARNING: [Vivado 12-4421] Failed to remove directory:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav
+WARNING: [Vivado 12-4421] Failed to remove directory:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir
+INFO: [Vivado 12-2267] Reset complete
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000
+reset_simulation -simset sim_1 -mode post-synthesis -type timing
+close_design
+launch_simulation -mode post-synthesis -type timing
+Command: launch_simulation  -mode post-synthesis -type timing
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching post-synthesis timing simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+Design is defaulting to impl run constrset: constrs_1
+Design is defaulting to synth run part: xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3895.711 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3895.711 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'...
+INFO: [SIM-utils-25] write_verilog -mode timesim -nolib -sdf_anno true -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v"
+INFO: [SIM-utils-27] Writing SDF file...
+INFO: [SIM-utils-28] write_sdf -mode timesim -process_corner slow -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf"
+INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v
+INFO: [SIM-utils-37] SDF generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim'
+"xvlog --incr --relax -prj pwm_test_db_vlog.prj"
+INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module pwm_test
+INFO: [VRFC 10-311] analyzing module glbl
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim'
+"xelab --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut".
+INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut".
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package vl.vl_types
+Compiling module xil_defaultlib.glbl
+Compiling module simprims_ver.BUFG
+Compiling module simprims_ver.IBUF
+Compiling module simprims_ver.x_lut1_mux2
+Compiling module simprims_ver.LUT1(INIT=2'b01)
+Compiling module simprims_ver.FDCE_default
+Compiling module simprims_ver.CARRY4
+Compiling module simprims_ver.OBUF
+Compiling module simprims_ver.latchsre_ldce
+Compiling module simprims_ver.LDCE
+Compiling module simprims_ver.x_lut2_mux4
+Compiling module simprims_ver.LUT2
+Compiling module xil_defaultlib.pwm_test
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_time_synth
+run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 3895.711 ; gain = 0.000
+INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_time_synth -key {Post-Synthesis:sim_1:Timing:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5000 ms
+INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+run: Time (s): cpu = 00:00:27 ; elapsed = 00:07:42 . Memory (MB): peak = 3895.711 ; gain = 0.000
+INFO: [Common 17-344] 'run' was cancelled
+INFO: [Common 17-344] 'source' was cancelled
+xsim: Time (s): cpu = 00:00:28 ; elapsed = 00:07:44 . Memory (MB): peak = 3895.711 ; gain = 0.000
+INFO: [Common 17-344] 'xsim' was cancelled
+INFO: [Vivado 12-5357] 'simulate' step aborted
+launch_simulation: Time (s): cpu = 00:00:35 ; elapsed = 00:07:56 . Memory (MB): peak = 3895.711 ; gain = 0.000
+INFO: [Common 17-344] 'launch_simulation' was cancelled
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+close_sim
+INFO: xsimkernel Simulation Memory Usage: 20776 KB (Peak: 20776 KB), Simulation CPU Usage: 461827 ms
+INFO: [Simtcl 6-16] Simulation closed
+current_sim simulation_2
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+exit
+INFO: [Common 17-206] Exiting Vivado at Wed Mar 16 21:11:02 2022...
diff --git a/Coraz7_Test/vivado_20284.backup.jou b/Coraz7_Test/vivado_20284.backup.jou
new file mode 100644
index 0000000..5603cd9
--- /dev/null
+++ b/Coraz7_Test/vivado_20284.backup.jou
@@ -0,0 +1,55 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Mon Mar 21 13:28:28 2022
+# Process ID: 20284
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22908 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
+update_compile_order -fileset sources_1
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+current_wave_config {pwm_test_db_func_synth.wcfg}
+add_wave {{/pwm_test_db/uut/count}} 
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+set_property -name {xsim.simulate.runtime} -value {5 ms} -objects [get_filesets sim_1]
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+current_wave_config {pwm_test_db_func_synth.wcfg}
+add_wave {{/pwm_test_db/uut/count}} 
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+current_wave_config {pwm_test_db_func_synth.wcfg}
+add_wave {{/pwm_test_db/uut/count}} 
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+open_hw_manager
+add_files -fileset constrs_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc
+reset_run synth_1
+launch_runs synth_1
+wait_on_run synth_1
+close_sim
diff --git a/Coraz7_Test/vivado_20284.backup.log b/Coraz7_Test/vivado_20284.backup.log
new file mode 100644
index 0000000..10eb6f1
--- /dev/null
+++ b/Coraz7_Test/vivado_20284.backup.log
@@ -0,0 +1,417 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Mon Mar 21 13:28:28 2022
+# Process ID: 20284
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22908 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'.
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
+Scanning sources...
+Finished scanning sources
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 1254.008 ; gain = 0.000
+update_compile_order -fileset sources_1
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test [pwm_test_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+WARNING: Simulation object /pwm_test_db/uut/count_reg was not found in the design.
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5000 ms
+INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+run: Time (s): cpu = 00:01:38 ; elapsed = 00:01:33 . Memory (MB): peak = 1254.008 ; gain = 0.000
+INFO: [Common 17-344] 'run' was cancelled
+INFO: [Common 17-344] 'source' was cancelled
+xsim: Time (s): cpu = 00:01:42 ; elapsed = 00:01:35 . Memory (MB): peak = 1254.008 ; gain = 0.000
+INFO: [Common 17-344] 'xsim' was cancelled
+INFO: [Vivado 12-5357] 'simulate' step aborted
+launch_simulation: Time (s): cpu = 00:01:45 ; elapsed = 00:01:40 . Memory (MB): peak = 1254.008 ; gain = 0.000
+INFO: [Common 17-344] 'launch_simulation' was cancelled
+current_wave_config {pwm_test_db_func_synth.wcfg}
+pwm_test_db_func_synth.wcfg
+add_wave {{/pwm_test_db/uut/count}} 
+close_sim
+INFO: xsimkernel Simulation Memory Usage: 16964 KB (Peak: 16964 KB), Simulation CPU Usage: 47390 ms
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+WARNING: Simulation object /pwm_test_db/uut/count_reg was not found in the design.
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5000 ms
+INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+run: Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1720.883 ; gain = 0.000
+INFO: [Common 17-344] 'run' was cancelled
+INFO: [Common 17-344] 'source' was cancelled
+xsim: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1720.883 ; gain = 0.000
+INFO: [Common 17-344] 'xsim' was cancelled
+INFO: [Vivado 12-5357] 'simulate' step aborted
+launch_simulation: Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1720.883 ; gain = 0.000
+INFO: [Common 17-344] 'launch_simulation' was cancelled
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+WARNING: Simulation object /pwm_test_db/uut/count_reg was not found in the design.
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5000 ms
+INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+run: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1720.883 ; gain = 0.000
+INFO: [Common 17-344] 'run' was cancelled
+INFO: [Common 17-344] 'source' was cancelled
+xsim: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1720.883 ; gain = 0.000
+INFO: [Common 17-344] 'xsim' was cancelled
+INFO: [Vivado 12-5357] 'simulate' step aborted
+launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1720.883 ; gain = 0.000
+INFO: [Common 17-344] 'launch_simulation' was cancelled
+set_property -name {xsim.simulate.runtime} -value {5 ms} -objects [get_filesets sim_1]
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+WARNING: Simulation object /pwm_test_db/uut/count_reg was not found in the design.
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 ms
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 ms
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1720.883 ; gain = 0.000
+current_wave_config {pwm_test_db_func_synth.wcfg}
+pwm_test_db_func_synth.wcfg
+add_wave {{/pwm_test_db/uut/count}} 
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+WARNING: Simulation object /pwm_test_db/uut/count_reg was not found in the design.
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 ms
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 ms
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1720.883 ; gain = 0.000
+current_wave_config {pwm_test_db_func_synth.wcfg}
+pwm_test_db_func_synth.wcfg
+add_wave {{/pwm_test_db/uut/count}} 
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 ms
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 ms
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1720.883 ; gain = 0.000
+open_hw_manager
+add_files -fileset constrs_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1
+[Mon Mar 21 14:05:30 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+exit
+INFO: [Common 17-206] Exiting Vivado at Mon Mar 21 14:32:11 2022...
diff --git a/Coraz7_Test/vivado_2148.backup.jou b/Coraz7_Test/vivado_2148.backup.jou
new file mode 100644
index 0000000..bb7df03
--- /dev/null
+++ b/Coraz7_Test/vivado_2148.backup.jou
@@ -0,0 +1,165 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Thu Mar 24 14:37:08 2022
+# Process ID: 2148
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent12260 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
+update_compile_order -fileset sources_1
+synth_design -rtl -rtl_skip_mlo -name rtl_1
+open_run synth_1 -name synth_1
+set_property target_constrs_file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc [current_fileset -constrset]
+launch_runs impl_1 -jobs 6
+wait_on_run impl_1
+close_design
+open_run impl_1
+set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]
+set_property IOSTANDARD LVCMOS33 [get_ports [list led]]
+place_ports led G14
+set_property DRIVE 12 [get_ports [list led]]
+set_property IOSTANDARD LVCMOS33 [get_ports [list led]]
+set_property OFFCHIP_TERM NONE [get_ports [list clk]]
+set_property PULLTYPE NONE [get_ports [list clk]]
+set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]
+place_ports clk H16
+save_constraints
+reset_run impl_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+current_hw_device [get_hw_devices xc7z010_1]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+disconnect_hw_server localhost:3121
+connect_hw_server -allow_non_jtag
+disconnect_hw_server localhost:3121
+connect_hw_server -allow_non_jtag
+open_hw_target
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+current_hw_device [get_hw_devices xc7z010_1]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+reset_run impl_1 -prev_step 
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs impl_1 -jobs 6
+wait_on_run impl_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
diff --git a/Coraz7_Test/vivado_2148.backup.log b/Coraz7_Test/vivado_2148.backup.log
new file mode 100644
index 0000000..ceb7ee3
--- /dev/null
+++ b/Coraz7_Test/vivado_2148.backup.log
@@ -0,0 +1,509 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Thu Mar 24 14:37:08 2022
+# Process ID: 2148
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent12260 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'.
+Scanning sources...
+Finished scanning sources
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:12 . Memory (MB): peak = 1250.879 ; gain = 0.000
+update_compile_order -fileset sources_1
+synth_design -rtl -rtl_skip_mlo -name rtl_1
+Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
+Starting synth_design
+Using part: xc7z010clg400-1
+Top: pwm_test
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1814.371 ; gain = 346.223
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'pwm_test' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
+WARNING: [Synth 8-614] signal 'count' is read in the process but is not in the sensitivity list [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]
+INFO: [Synth 8-256] done synthesizing module 'pwm_test' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1866.227 ; gain = 398.078
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1866.227 ; gain = 398.078
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1866.227 ; gain = 398.078
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1866.227 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1926.578 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+RTL Elaboration Complete:  : Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2005.672 ; gain = 537.523
+5 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2005.672 ; gain = 754.793
+open_run synth_1 -name synth_1
+Design is defaulting to impl run constrset: constrs_1
+Design is defaulting to synth run part: xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2029.652 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2076.340 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+set_property target_constrs_file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc [current_fileset -constrset]
+launch_runs impl_1 -jobs 6
+INFO: [Timing 38-480] Writing timing data to binary archive.
+[Thu Mar 24 14:43:23 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+close_design
+open_run impl_1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2656.508 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Timing 38-478] Restoring timing data from binary archive.
+INFO: [Timing 38-479] Binary timing data restore complete.
+INFO: [Project 1-856] Restoring constraints from binary archive.
+INFO: [Project 1-853] Binary constraint restore complete.
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 2723.512 ; gain = 0.000
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 2723.512 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2723.512 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]
+set_property IOSTANDARD LVCMOS33 [get_ports [list led]]
+place_ports led G14
+set_property DRIVE 12 [get_ports [list led]]
+set_property IOSTANDARD LVCMOS33 [get_ports [list led]]
+set_property OFFCHIP_TERM NONE [get_ports [list clk]]
+set_property PULLTYPE NONE [get_ports [list clk]]
+set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]
+place_ports clk H16
+save_constraints
+reset_run impl_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:24:32 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+open_hw_manager
+connect_hw_server -allow_non_jtag
+INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
+INFO: [Labtools 27-2222] Launching hw_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+****** Xilinx hw_server v2021.2
+  **** Build date : Oct 19 2021 at 03:13:30
+    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+
+INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
+INFO: [Labtools 27-3417] Launching cs_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+
+******** Xilinx cs_server v2021.2.0
+  ****** Build date   : Sep 27 2021-23:44:20
+    **** Build number : 2021.2.1632779060
+      ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
+
+
+
+connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2769.398 ; gain = 1.105
+open_hw_target
+INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210370A9326CA
+open_hw_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:20 . Memory (MB): peak = 4542.070 ; gain = 1772.672
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+current_hw_device [get_hw_devices xc7z010_1]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1435] Device xc7z010 (JTAG device index = 1) is not programmed (DONE status = 0).
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4567.656 ; gain = 1.344
+ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210370A9326CA
+disconnect_hw_server localhost:3121
+connect_hw_server -allow_non_jtag
+INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
+INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
+INFO: [Labtools 27-3414] Connected to existing cs_server.
+ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
+ Targets(s) ", jsn-Cora Z7 - 7007S-210370A9326CA" may be locked by another hw_server.
+disconnect_hw_server localhost:3121
+connect_hw_server -allow_non_jtag
+INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
+INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
+INFO: [Labtools 27-3414] Connected to existing cs_server.
+open_hw_target
+INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210370A9326CA
+open_hw_target: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4573.051 ; gain = 5.395
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+current_hw_device [get_hw_devices xc7z010_1]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1435] Device xc7z010 (JTAG device index = 1) is not programmed (DONE status = 0).
+refresh_hw_device: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4573.098 ; gain = 0.047
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4573.469 ; gain = 0.371
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:33:29 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 15:33:29 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+reset_run impl_1 -prev_step 
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:35:31 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:37:14 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 15:37:14 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:42:50 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 15:42:50 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:46:07 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 15:46:07 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:48:19 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 15:48:19 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+program_hw_devices: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4620.117 ; gain = 0.000
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:52:13 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 15:52:13 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+reset_run synth_1
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 15:52:57 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 15:52:57 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 16:01:12 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 16:01:12 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+program_hw_devices: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 4678.754 ; gain = 0.000
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 16:04:44 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 16:04:44 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+program_hw_devices: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
+ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210370A9326CA
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 16:09:21 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 16:09:21 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210370A9326CA
+open_hw_target: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
+WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
+INFO: [Labtools 27-1435] Device xc7z010 (JTAG device index = 1) is not programmed (DONE status = 0).
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
+WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Thu Mar 24 16:12:11 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Thu Mar 24 16:13:15 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -jobs 6
+[Thu Mar 24 16:15:07 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 16:15:07 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 16:17:27 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+program_hw_devices: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 4678.754 ; gain = 0.000
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 16:19:45 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 16:19:45 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4684.273 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 16:24:27 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 16:24:27 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4684.273 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 16:27:46 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 16:27:46 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4684.273 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1
+
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+[Thu Mar 24 16:30:07 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
+[Thu Mar 24 16:30:07 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
+set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
+refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4684.273 ; gain = 0.000
+exit
+INFO: [Common 17-206] Exiting Vivado at Thu Mar 24 16:34:16 2022...