#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Wed Mar 16 18:29:30 2022
# Process ID: 1824
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21192 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
#-----------------------------------------------------------
start_gui
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
create_bd_design "IO_Test"
update_compile_order -fileset sources_1
open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new
close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v w ]
add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
update_compile_order -fileset sources_1
close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd w ]
add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
update_compile_order -fileset sources_1
export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v] -no_script -reset -force -quiet
remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
launch_runs synth_1 -jobs 6
wait_on_run synth_1
launch_simulation
reset_run synth_1
launch_runs synth_1 -jobs 6
wait_on_run synth_1
launch_simulation
source pwm_test.tcl
launch_runs impl_1 -jobs 6
wait_on_run impl_1
open_run impl_1
export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd] -no_script -reset -force -quiet
remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd
file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd w ]
add_files -fileset sim_1 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
reset_run synth_1
launch_runs synth_1 -jobs 6
wait_on_run synth_1
launch_runs impl_1 -jobs 6
wait_on_run impl_1
refresh_design
launch_simulation
launch_simulation
launch_simulation
reset_run synth_1
launch_runs synth_1 -jobs 6
wait_on_run synth_1
launch_simulation
launch_simulation -mode post-synthesis -type functional
source pwm_test_db.tcl
relaunch_sim
relaunch_sim
current_wave_config {Untitled 2}
add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 
relaunch_sim
current_wave_config {Untitled 2}
add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 
launch_simulation
relaunch_sim
relaunch_sim
current_wave_config {Untitled 2}
add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_2 }} 
relaunch_sim
current_wave_config {Untitled 2}
add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_1 }} 
current_wave_config {Untitled 2}
add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_3 }} 
relaunch_sim
current_wave_config {Untitled 2}
add_wave {{/pwm_test_db/uut}} 
relaunch_sim
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
add_files -fileset sim_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
set_property xsim.view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg [get_filesets sim_1]
set_property -name {xsim.simulate.runtime} -value {5000 ms} -objects [get_filesets sim_1]
relaunch_sim
relaunch_sim
launch_simulation
relaunch_sim
reset_run synth_1
launch_runs synth_1 -jobs 6
wait_on_run synth_1
relaunch_sim
relaunch_sim
reset_simulation -simset sim_1 -mode behavioral
relaunch_sim
reset_simulation -simset sim_1 -mode post-synthesis -type timing
close_design
launch_simulation -mode post-synthesis -type timing
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
source pwm_test_db.tcl
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
close_sim
current_sim simulation_2
close_sim
close_sim