#----------------------------------------------------------- # Vivado v2021.2 (64-bit) # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 # Start of session at: Wed Mar 16 18:29:30 2022 # Process ID: 1824 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21192 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB #----------------------------------------------------------- start_gui open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'. Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 1252.246 ; gain = 0.000 create_bd_design "IO_Test" Wrote : INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1/bd/IO_Test for IO_Test cannot be found. create_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1252.246 ; gain = 0.000 update_compile_order -fileset sources_1 open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd} open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd} open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd} open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd} open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd} open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd} file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v w ] add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v update_compile_order -fileset sources_1 close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd w ] add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd update_compile_order -fileset sources_1 export_ip_user_files -of_objects [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v] -no_script -reset -force -quiet remove_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 launch_runs synth_1 -jobs 6 WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. [Wed Mar 16 19:55:26 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log launch_simulation Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'pwm_test' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' "xvhdl --incr --relax -prj pwm_test_vhdl.prj" INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test' ERROR: [VRFC 10-3031] 'led' with mode 'out' cannot be read [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48] ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39] INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd' ignored due to errors INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. reset_run synth_1 launch_runs synth_1 -jobs 6 WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. [Wed Mar 16 19:57:51 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log launch_simulation Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'pwm_test' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' "xvhdl --incr --relax -prj pwm_test_vhdl.prj" INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test' INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_behav xil_defaultlib.pwm_test -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_behav xil_defaultlib.pwm_test -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling architecture behavioral of entity xil_defaultlib.pwm_test Built simulation snapshot pwm_test_behav INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "pwm_test_behav -key {Behavioral:sim_1:Functional:pwm_test} -tclbatch {pwm_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Time resolution is 1 ps source pwm_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1349.082 ; gain = 26.551 launch_runs impl_1 -jobs 6 [Wed Mar 16 19:58:36 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log open_run impl_1 INFO: [Device 21-403] Loading part xc7z010clg400-1 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1688.973 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2021.2 INFO: [Project 1-570] Preparing netlist for logic optimization Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1764.523 ; gain = 0.172 Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1764.523 ; gain = 0.172 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2169.715 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. open_run: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2238.512 ; gain = 881.695 WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. export_ip_user_files -of_objects [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd] -no_script -reset -force -quiet remove_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd Wrote : file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new set_property SOURCE_SET sources_1 [get_filesets sim_1] close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd w ] add_files -fileset sim_1 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd update_compile_order -fileset sim_1 update_compile_order -fileset sim_1 reset_run synth_1 INFO: [Project 1-1160] Copying file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp to C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1 and adding it to utils fileset launch_runs synth_1 -jobs 6 [Wed Mar 16 20:13:13 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log launch_runs impl_1 -jobs 6 [Wed Mar 16 20:13:57 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log refresh_design Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2357.781 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2021.2 INFO: [Project 1-570] Preparing netlist for logic optimization Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 2357.781 ; gain = 0.000 Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 2357.781 ; gain = 0.000 WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. launch_simulation Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log" launch_simulation Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log" launch_simulation Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log" reset_run synth_1 INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp launch_runs synth_1 -jobs 6 [Wed Mar 16 20:16:57 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log launch_simulation Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log" launch_simulation -mode post-synthesis -type functional Command: launch_simulation -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7z010clg400-1 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2379.422 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2021.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2431.441 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'... INFO: [SIM-utils-25] write_verilog -mode funcsim -nolib -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v" INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module pwm_test INFO: [VRFC 10-311] analyzing module glbl "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' INFO: [USF-XSim-69] 'compile' step finished in '4' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package vl.vl_types Compiling module xil_defaultlib.glbl Compiling module unisims_ver.BUFG Compiling module unisims_ver.IBUF Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1(INIT=2'b01) Compiling module unisims_ver.FDCE_default Compiling module unisims_ver.CARRY4 Compiling module unisims_ver.OBUF Compiling module unisims_ver.latchsre_ldce Compiling module unisims_ver.LDCE Compiling module unisims_ver.x_lut2_mux4 Compiling module unisims_ver.LUT2 Compiling module xil_defaultlib.pwm_test Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db Built simulation snapshot pwm_test_db_func_synth INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [USF-XSim-98] *** Running xsim with args "pwm_test_db_func_synth -key {Post-Synthesis:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Time resolution is 1 ps source pwm_test_db.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_func_synth' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 2560.469 ; gain = 181.691 relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'... INFO: [SIM-utils-25] write_verilog -mode funcsim -nolib -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v" INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module pwm_test INFO: [VRFC 10-311] analyzing module glbl "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package vl.vl_types Compiling module xil_defaultlib.glbl Compiling module unisims_ver.BUFG Compiling module unisims_ver.IBUF Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1(INIT=2'b01) Compiling module unisims_ver.FDCE_default Compiling module unisims_ver.CARRY4 Compiling module unisims_ver.OBUF Compiling module unisims_ver.latchsre_ldce Compiling module unisims_ver.LDCE Compiling module unisims_ver.x_lut2_mux4 Compiling module unisims_ver.LUT2 Compiling module xil_defaultlib.pwm_test Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db Built simulation snapshot pwm_test_db_func_synth INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 2565.645 ; gain = 0.000 relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package vl.vl_types Compiling module xil_defaultlib.glbl Compiling module unisims_ver.BUFG Compiling module unisims_ver.IBUF Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1(INIT=2'b01) Compiling module unisims_ver.FDCE_default Compiling module unisims_ver.CARRY4 Compiling module unisims_ver.OBUF Compiling module unisims_ver.latchsre_ldce Compiling module unisims_ver.LDCE Compiling module unisims_ver.x_lut2_mux4 Compiling module unisims_ver.LUT2 Compiling module xil_defaultlib.pwm_test Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db Built simulation snapshot pwm_test_db_func_synth INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 2569.133 ; gain = 3.281 current_wave_config {Untitled 2} Untitled 2 add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 2569.211 ; gain = 0.000 current_wave_config {Untitled 2} Untitled 2 add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} launch_simulation Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log" relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 2635.207 ; gain = 0.000 relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package vl.vl_types Compiling module xil_defaultlib.glbl Compiling module unisims_ver.BUFG Compiling module unisims_ver.IBUF Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1(INIT=2'b01) Compiling module unisims_ver.FDCE_default Compiling module unisims_ver.CARRY4 Compiling module unisims_ver.OBUF Compiling module unisims_ver.latchsre_ldce Compiling module unisims_ver.LDCE Compiling module unisims_ver.x_lut2_mux4 Compiling module unisims_ver.LUT2 Compiling module xil_defaultlib.pwm_test Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db Built simulation snapshot pwm_test_db_func_synth INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 2847.305 ; gain = 0.000 current_wave_config {Untitled 2} Untitled 2 add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_2 }} relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '2' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3078.270 ; gain = 0.000 current_wave_config {Untitled 2} Untitled 2 add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_1 }} current_wave_config {Untitled 2} Untitled 2 add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_3 }} relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000 current_wave_config {Untitled 2} Untitled 2 add_wave {{/pwm_test_db/uut}} relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000 save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} add_files -fileset sim_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg set_property xsim.view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg [get_filesets sim_1] set_property -name {xsim.simulate.runtime} -value {5000 ms} -objects [get_filesets sim_1] relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000 relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000 launch_simulation Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log" relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 3895.711 ; gain = 0.000 reset_run synth_1 INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp WARNING: [Vivado 12-1017] Problems encountered: 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1 launch_runs synth_1 -jobs 6 [Wed Mar 16 20:50:10 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000 relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '3' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000 reset_simulation -simset sim_1 -mode behavioral INFO: [Vivado 12-2266] Removing simulation data... WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimcrash.log WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log WARNING: [Vivado 12-4421] Failed to remove directory:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav WARNING: [Vivado 12-4421] Failed to remove directory:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir INFO: [Vivado 12-2267] Reset complete relaunch_sim Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [USF-XSim-69] 'compile' step finished in '4' seconds Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim' "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000 reset_simulation -simset sim_1 -mode post-synthesis -type timing close_design launch_simulation -mode post-synthesis -type timing Command: launch_simulation -mode post-synthesis -type timing INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' WARNING: [Vivado 12-12986] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching post-synthesis timing simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7z010clg400-1 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3895.711 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2021.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3895.711 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'... INFO: [SIM-utils-25] write_verilog -mode timesim -nolib -sdf_anno true -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v" INFO: [SIM-utils-27] Writing SDF file... INFO: [SIM-utils-28] write_sdf -mode timesim -process_corner slow -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf" INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v INFO: [SIM-utils-37] SDF generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim' "xvlog --incr --relax -prj pwm_test_db_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module pwm_test INFO: [VRFC 10-311] analyzing module glbl "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim' "xelab --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut". INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut". Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package vl.vl_types Compiling module xil_defaultlib.glbl Compiling module simprims_ver.BUFG Compiling module simprims_ver.IBUF Compiling module simprims_ver.x_lut1_mux2 Compiling module simprims_ver.LUT1(INIT=2'b01) Compiling module simprims_ver.FDCE_default Compiling module simprims_ver.CARRY4 Compiling module simprims_ver.OBUF Compiling module simprims_ver.latchsre_ldce Compiling module simprims_ver.LDCE Compiling module simprims_ver.x_lut2_mux4 Compiling module simprims_ver.LUT2 Compiling module xil_defaultlib.pwm_test Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db Built simulation snapshot pwm_test_db_time_synth run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 3895.711 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim' INFO: [USF-XSim-98] *** Running xsim with args "pwm_test_db_time_synth -key {Post-Synthesis:sim_1:Timing:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Time resolution is 1 ps open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg source pwm_test_db.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 5000 ms INFO: [Common 17-41] Interrupt caught. Command should exit soon. run: Time (s): cpu = 00:00:27 ; elapsed = 00:07:42 . Memory (MB): peak = 3895.711 ; gain = 0.000 INFO: [Common 17-344] 'run' was cancelled INFO: [Common 17-344] 'source' was cancelled xsim: Time (s): cpu = 00:00:28 ; elapsed = 00:07:44 . Memory (MB): peak = 3895.711 ; gain = 0.000 INFO: [Common 17-344] 'xsim' was cancelled INFO: [Vivado 12-5357] 'simulate' step aborted launch_simulation: Time (s): cpu = 00:00:35 ; elapsed = 00:07:56 . Memory (MB): peak = 3895.711 ; gain = 0.000 INFO: [Common 17-344] 'launch_simulation' was cancelled save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} close_sim INFO: xsimkernel Simulation Memory Usage: 20776 KB (Peak: 20776 KB), Simulation CPU Usage: 461827 ms INFO: [Simtcl 6-16] Simulation closed current_sim simulation_2 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim INFO: [Simtcl 6-16] Simulation closed exit INFO: [Common 17-206] Exiting Vivado at Wed Mar 16 21:11:02 2022...