FPGA_Projekt/Coraz7_Test/vivado_2148.backup.log

#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Thu Mar 24 14:37:08 2022
# Process ID: 2148
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent12260 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
#-----------------------------------------------------------
start_gui
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:12 . Memory (MB): peak = 1250.879 ; gain = 0.000
update_compile_order -fileset sources_1
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7z010clg400-1
Top: pwm_test
INFO: [Device 21-403] Loading part xc7z010clg400-1
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1814.371 ; gain = 346.223
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'pwm_test' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
WARNING: [Synth 8-614] signal 'count' is read in the process but is not in the sensitivity list [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'pwm_test' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1866.227 ; gain = 398.078
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1866.227 ; gain = 398.078
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1866.227 ; gain = 398.078
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1866.227 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1926.578 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

RTL Elaboration Complete:  : Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2005.672 ; gain = 537.523
5 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2005.672 ; gain = 754.793
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7z010clg400-1
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2029.652 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2021.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2076.340 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

set_property target_constrs_file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc [current_fileset -constrset]
launch_runs impl_1 -jobs 6
INFO: [Timing 38-480] Writing timing data to binary archive.
[Thu Mar 24 14:43:23 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
close_design
open_run impl_1
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2656.508 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2021.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 2723.512 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 2723.512 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2723.512 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]
set_property IOSTANDARD LVCMOS33 [get_ports [list led]]
place_ports led G14
set_property DRIVE 12 [get_ports [list led]]
set_property IOSTANDARD LVCMOS33 [get_ports [list led]]
set_property OFFCHIP_TERM NONE [get_ports [list clk]]
set_property PULLTYPE NONE [get_ports [list clk]]
set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]
place_ports clk H16
save_constraints
reset_run impl_1
launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:24:32 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
open_hw_manager
connect_hw_server -allow_non_jtag
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2021.2
  **** Build date : Oct 19 2021 at 03:13:30
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.


INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3417] Launching cs_server...
INFO: [Labtools 27-2221] Launch Output:


******** Xilinx cs_server v2021.2.0
  ****** Build date   : Sep 27 2021-23:44:20
    **** Build number : 2021.2.1632779060
      ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.



connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2769.398 ; gain = 1.105
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210370A9326CA
open_hw_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:20 . Memory (MB): peak = 4542.070 ; gain = 1772.672
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
current_hw_device [get_hw_devices xc7z010_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1435] Device xc7z010 (JTAG device index = 1) is not programmed (DONE status = 0).
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4567.656 ; gain = 1.344
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210370A9326CA
disconnect_hw_server localhost:3121
connect_hw_server -allow_non_jtag
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3414] Connected to existing cs_server.
ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
 Targets(s) ", jsn-Cora Z7 - 7007S-210370A9326CA" may be locked by another hw_server.
disconnect_hw_server localhost:3121
connect_hw_server -allow_non_jtag
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3414] Connected to existing cs_server.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210370A9326CA
open_hw_target: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4573.051 ; gain = 5.395
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
current_hw_device [get_hw_devices xc7z010_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1435] Device xc7z010 (JTAG device index = 1) is not programmed (DONE status = 0).
refresh_hw_device: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4573.098 ; gain = 0.047
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4573.469 ; gain = 0.371
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:33:29 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 15:33:29 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
reset_run impl_1 -prev_step 
launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:35:31 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:37:14 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 15:37:14 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:42:50 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 15:42:50 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:46:07 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 15:46:07 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:48:19 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 15:48:19 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4620.117 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:52:13 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 15:52:13 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 15:52:57 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 15:52:57 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 16:01:12 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 16:01:12 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 4678.754 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 16:04:44 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 16:04:44 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210370A9326CA
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 16:09:21 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 16:09:21 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210370A9326CA
open_hw_target: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
INFO: [Labtools 27-1435] Device xc7z010 (JTAG device index = 1) is not programmed (DONE status = 0).
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs synth_1 -jobs 6
[Thu Mar 24 16:12:11 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs synth_1 -jobs 6
[Thu Mar 24 16:13:15 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -jobs 6
[Thu Mar 24 16:15:07 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 16:15:07 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 16:17:27 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 4678.754 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4678.754 ; gain = 0.000
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 16:19:45 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 16:19:45 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4684.273 ; gain = 0.000
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 16:24:27 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 16:24:27 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4684.273 ; gain = 0.000
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 16:27:46 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 16:27:46 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4684.273 ; gain = 0.000
reset_run synth_1
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

launch_runs impl_1 -to_step write_bitstream -jobs 6
[Thu Mar 24 16:30:07 2022] Launched synth_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log
[Thu Mar 24 16:30:07 2022] Launched impl_1...
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
refresh_hw_device: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 4684.273 ; gain = 0.000
exit
INFO: [Common 17-206] Exiting Vivado at Thu Mar 24 16:34:16 2022...