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FPGA_Projekt/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-a7-100/E.0/1.0/board.xml

board.xml 58KB
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  1. <?xml version="1.0" encoding="UTF-8" standalone="no"?> 

  2. <!--

  3. MIT License

  4. 

  5. Copyright (c) 2021 Digilent, Inc.

  6. 

  7. Permission is hereby granted, free of charge, to any person obtaining a copy

  8. of this software and associated documentation files (the "Software"), to deal

  9. in the Software without restriction, including without limitation the rights

  10. to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

  11. copies of the Software, and to permit persons to whom the Software is

  12. furnished to do so, subject to the following conditions:

  13. 

  14. The above copyright notice and this permission notice shall be included in all

  15. copies or substantial portions of the Software.

  16. 

  17. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

  18. IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

  19. FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

  20. AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

  21. LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

  22. OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  23. SOFTWARE.

  24. -->

  25. <board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-100" display_name="Arty A7-100" url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >

  26. <compatible_board_revisions>

  27.   <revision id="0">E.0</revision>

  28. </compatible_board_revisions>

  29. <file_version>1.0</file_version>

  30. <description>Arty A7-100</description>

  31. <components>

  32.   <component name="part0" display_name="Arty A7-100" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start">

  33.     <interfaces>

  34.       <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 

  35. 		<description>DDR3 board interface, it can use MIG IP for connection.</description>

  36. 		<preferred_ips>

  37. 			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>

  38. 	  </preferred_ips>

  39. 	  </interface>

  40.       <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">

  41.         <description>4-position user DIP Switches</description>

  42. 		<preferred_ips>

  43. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  44. 		</preferred_ips>

  45. 		<port_maps>

  46.           <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0"> 

  47.             <pin_maps>

  48.               <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/> 

  49.               <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/> 

  50.               <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/> 

  51.               <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/> 

  52.             </pin_maps>

  53.           </port_map>

  54.         </port_maps>

  55.       </interface>

  56.       <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">

  57. 	  <description>Secondary interface to communicate with ethernet phy. </description>

  58.         <port_maps>

  59.           <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">

  60.             <pin_maps>

  61.               <pin_map port_index="0" component_pin="eth_mdio_i"/> 

  62.             </pin_maps>

  63.           </port_map>

  64.           <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">

  65.             <pin_maps>

  66.               <pin_map port_index="0" component_pin="eth_mdio_i"/> 

  67.             </pin_maps>

  68.           </port_map>

  69.           <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">

  70.             <pin_maps>

  71.               <pin_map port_index="0" component_pin="eth_mdio_i"/> 

  72.             </pin_maps>

  73.           </port_map>

  74.           <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">

  75.             <pin_maps>

  76.               <pin_map port_index="0" component_pin="eth_mdc"/> 

  77.             </pin_maps>

  78.           </port_map>

  79.         </port_maps>

  80.       </interface>

  81.       <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">

  82.         <description>Primary interface to communicate with ethernet phy in MII mode. </description>

  83.           <preferred_ips>

  84.             <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>

  85.           </preferred_ips>

  86. 		<port_maps>

  87.           <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0"> 

  88.             <pin_maps>

  89.               <pin_map port_index="0" component_pin="eth_txd_0"/> 

  90.               <pin_map port_index="1" component_pin="eth_txd_1"/> 

  91.               <pin_map port_index="2" component_pin="eth_txd_2"/> 

  92.               <pin_map port_index="3" component_pin="eth_txd_3"/> 

  93.             </pin_maps>

  94.           </port_map>

  95.           <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">

  96.             <pin_maps>

  97.               <pin_map port_index="0" component_pin="eth_tx_en"/> 

  98.             </pin_maps>

  99.           </port_map>

  100.           <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0"> 

  101.             <pin_maps>

  102.               <pin_map port_index="0" component_pin="eth_rxd_0"/> 

  103.               <pin_map port_index="1" component_pin="eth_rxd_1"/> 

  104.               <pin_map port_index="2" component_pin="eth_rxd_2"/> 

  105.               <pin_map port_index="3" component_pin="eth_rxd_3"/> 

  106.             </pin_maps>

  107.           </port_map>

  108.           <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">

  109.             <pin_maps>

  110.               <pin_map port_index="0" component_pin="eth_rx_dv"/> 

  111.             </pin_maps>

  112.           </port_map>

  113.           <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">

  114.             <pin_maps>

  115.               <pin_map port_index="0" component_pin="eth_rx_er"/> 

  116.             </pin_maps>

  117.           </port_map>

  118.           <port_map logical_port="CRS" physical_port="eth_crs" dir="in">

  119.             <pin_maps>

  120.               <pin_map port_index="0" component_pin="eth_crs"/> 

  121.             </pin_maps>

  122.           </port_map>

  123.           <port_map logical_port="COL" physical_port="eth_col" dir="in">

  124.             <pin_maps>

  125.               <pin_map port_index="0" component_pin="eth_col"/> 

  126.             </pin_maps>

  127.           </port_map>

  128.           <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">

  129.             <pin_maps>

  130.               <pin_map port_index="0" component_pin="eth_tx_clk"/> 

  131.             </pin_maps>

  132.           </port_map>

  133.           <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">

  134.             <pin_maps>

  135.               <pin_map port_index="0" component_pin="eth_rx_clk"/> 

  136.             </pin_maps>

  137.           </port_map>

  138.           <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">

  139.             <pin_maps>

  140.               <pin_map port_index="0" component_pin="eth_rstn"/> 

  141.             </pin_maps>

  142.           </port_map>

  143.         </port_maps>

  144.       </interface>

  145.       <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">

  146.         <description>Shield I2C</description>

  147. 		<preferred_ips>

  148.             <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>

  149.         </preferred_ips>

  150. 		<port_maps>

  151.           <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">

  152.             <pin_maps>

  153.               <pin_map port_index="0" component_pin="i2c_sda_i"/> 

  154.             </pin_maps>

  155.           </port_map>

  156.           <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">

  157.             <pin_maps>

  158.               <pin_map port_index="0" component_pin="i2c_sda_i"/> 

  159.             </pin_maps>

  160.           </port_map>

  161.           <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">

  162.             <pin_maps>

  163.               <pin_map port_index="0" component_pin="i2c_sda_i"/> 

  164.             </pin_maps>

  165.           </port_map>

  166.           <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">

  167.             <pin_maps>

  168.               <pin_map port_index="0" component_pin="i2c_scl_i"/> 

  169.             </pin_maps>

  170.           </port_map>

  171.           <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">

  172.             <pin_maps>

  173.               <pin_map port_index="0" component_pin="i2c_scl_i"/> 

  174.             </pin_maps>

  175.           </port_map>

  176.           <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">

  177.             <pin_maps>

  178.               <pin_map port_index="0" component_pin="i2c_scl_i"/> 

  179.             </pin_maps>

  180.           </port_map>

  181.         </port_maps>

  182.       </interface>

  183.       <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">

  184.         <description>I2C Pullups to enable shield I2C</description>

  185. 		<preferred_ips>

  186. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  187. 		</preferred_ips>

  188. 		<port_maps>

  189.           <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0"> 

  190.             <pin_maps>

  191.               <pin_map port_index="0" component_pin="i2c_pullup_0"/> 

  192.               <pin_map port_index="1" component_pin="i2c_pullup_1"/> 

  193.             </pin_maps>

  194.           </port_map>

  195.         </port_maps>

  196.       </interface>

  197.       <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">

  198.         <description>4 LEDs</description>

  199. 		<preferred_ips>

  200. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  201. 		</preferred_ips>

  202. 		<port_maps>

  203.           <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 

  204.             <pin_maps>

  205.               <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 

  206.               <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 

  207.               <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 

  208.               <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 

  209.             </pin_maps>

  210.           </port_map>

  211.         </port_maps>

  212.       </interface>

  213.       <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">

  214.         <description>4 Push Buttons</description>

  215. 		<preferred_ips>

  216. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  217. 		</preferred_ips>

  218. 		<port_maps>

  219.           <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0"> 

  220.             <pin_maps>

  221.               <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/> 

  222.               <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/> 

  223.               <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/> 

  224.               <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/> 

  225.             </pin_maps>

  226.           </port_map>

  227.         </port_maps>

  228.       </interface>

  229.       <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">

  230.         <description>Quad SPI Flash</description>

  231. 		<preferred_ips>

  232. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>

  233. 		</preferred_ips>

  234. 		<port_maps>

  235.           <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">

  236.             <pin_maps>

  237.               <pin_map port_index="0" component_pin="qspi_db0_i"/> 

  238.             </pin_maps>

  239.           </port_map>

  240.           <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">

  241.             <pin_maps>

  242.               <pin_map port_index="0" component_pin="qspi_db0_i"/> 

  243.             </pin_maps>

  244.           </port_map>

  245.           <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">

  246.             <pin_maps>

  247.               <pin_map port_index="0" component_pin="qspi_db0_i"/> 

  248.             </pin_maps>

  249.           </port_map>

  250.           <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">

  251.             <pin_maps>

  252.               <pin_map port_index="0" component_pin="qspi_db1_i"/> 

  253.             </pin_maps>

  254.           </port_map>

  255.           <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">

  256.             <pin_maps>

  257.               <pin_map port_index="0" component_pin="qspi_db1_i"/> 

  258.             </pin_maps>

  259.           </port_map>

  260.           <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">

  261.             <pin_maps>

  262.               <pin_map port_index="0" component_pin="qspi_db1_i"/> 

  263.             </pin_maps>

  264.           </port_map>

  265.           <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">

  266.             <pin_maps>

  267.               <pin_map port_index="0" component_pin="qspi_db2_i"/> 

  268.             </pin_maps>

  269.           </port_map>

  270.           <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">

  271.             <pin_maps>

  272.               <pin_map port_index="0" component_pin="qspi_db2_i"/> 

  273.             </pin_maps>

  274.           </port_map>

  275.           <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">

  276.             <pin_maps>

  277.               <pin_map port_index="0" component_pin="qspi_db2_i"/> 

  278.             </pin_maps>

  279.           </port_map>

  280.           <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">

  281.             <pin_maps>

  282.               <pin_map port_index="0" component_pin="qspi_db3_i"/> 

  283.             </pin_maps>

  284.           </port_map>

  285.           <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">

  286.             <pin_maps>

  287.               <pin_map port_index="0" component_pin="qspi_db3_i"/> 

  288.             </pin_maps>

  289.           </port_map>

  290.           <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">

  291.             <pin_maps>

  292.               <pin_map port_index="0" component_pin="qspi_db3_i"/> 

  293.             </pin_maps>

  294.           </port_map>

  295.           <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">

  296.             <pin_maps>

  297.               <pin_map port_index="0" component_pin="qspi_csn_i"/> 

  298.             </pin_maps>

  299.           </port_map>

  300.           <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">

  301.             <pin_maps>

  302.               <pin_map port_index="0" component_pin="qspi_csn_i"/> 

  303.             </pin_maps>

  304.           </port_map>

  305.           <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">

  306.             <pin_maps>

  307.               <pin_map port_index="0" component_pin="qspi_csn_i"/> 

  308.             </pin_maps>

  309.           </port_map>

  310. 		  <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">

  311.             <pin_maps>

  312.               <pin_map port_index="0" component_pin="qspi_sclk_i"/> 

  313.             </pin_maps>

  314.           </port_map>

  315.           <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">

  316.             <pin_maps>

  317.               <pin_map port_index="0" component_pin="qspi_sclk_i"/> 

  318.             </pin_maps>

  319.           </port_map>

  320.           <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">

  321.             <pin_maps>

  322.               <pin_map port_index="0" component_pin="qspi_sclk_i"/> 

  323.             </pin_maps>

  324.           </port_map>

  325.         </port_maps>

  326.       </interface>

  327.       <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">

  328.         <description>Onboard Reset Button</description>

  329. 		<parameters>

  330.             <parameter name="rst_polarity" value="0"/>

  331.           </parameters>

  332.           <preferred_ips>

  333.             <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>

  334.           </preferred_ips>

  335. 		<port_maps>

  336.           <port_map logical_port="RST" physical_port="reset" dir="in">

  337.             <pin_maps>

  338.               <pin_map port_index="0" component_pin="reset"/> 

  339.             </pin_maps>

  340.           </port_map>

  341.         </port_maps>

  342.       </interface>

  343.       <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">

  344.         <description>4 RGB LEDs</description>

  345. 		<preferred_ips>

  346. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  347. 		</preferred_ips>

  348. 		<port_maps>

  349.           <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0"> 

  350.             <pin_maps>

  351.               <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 

  352.               <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 

  353.               <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 

  354.               <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 

  355.               <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 

  356.               <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 

  357.               <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/> 

  358.               <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/> 

  359.               <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/> 

  360.               <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/> 

  361.               <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/> 

  362.               <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/> 

  363.             </pin_maps>

  364.           </port_map>

  365.         </port_maps>

  366.       </interface>

  367.       <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">

  368. 		<preferred_ips>

  369. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  370. 		</preferred_ips>

  371.         <port_maps>

  372.           <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0"> 

  373.             <pin_maps>

  374.               <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 

  375.               <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 

  376.               <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 

  377.               <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 

  378.               <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 

  379.               <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 

  380.               <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 

  381.               <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 

  382.               <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 

  383.               <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 

  384.               <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 

  385.               <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 

  386.               <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 

  387.               <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 

  388.               <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 

  389.               <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 

  390.               <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 

  391.               <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 

  392.               <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 

  393.               <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 

  394.             </pin_maps>

  395.           </port_map>

  396.           <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0"> 

  397.             <pin_maps>

  398.               <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 

  399.               <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 

  400.               <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 

  401.               <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 

  402.               <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 

  403.               <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 

  404.               <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 

  405.               <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 

  406.               <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 

  407.               <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 

  408.               <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 

  409.               <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 

  410.               <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 

  411.               <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 

  412.               <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 

  413.               <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 

  414.               <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 

  415.               <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 

  416.               <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 

  417.               <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 

  418.             </pin_maps>

  419.           </port_map>

  420.           <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0"> 

  421.             <pin_maps>

  422.               <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/> 

  423.               <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/> 

  424.               <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/> 

  425.               <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/> 

  426.               <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/> 

  427.               <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/> 

  428.               <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/> 

  429.               <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/> 

  430.               <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/> 

  431.               <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/> 

  432.               <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/> 

  433.               <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/> 

  434.               <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/> 

  435.               <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/> 

  436.               <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/> 

  437.               <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/> 

  438.               <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/> 

  439.               <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/> 

  440.               <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/> 

  441.               <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/> 

  442.             </pin_maps>

  443.           </port_map>

  444.         </port_maps>

  445.       </interface>

  446.       <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">

  447. 		<preferred_ips>

  448. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  449. 		</preferred_ips>

  450.         <port_maps>

  451.           <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 

  452.             <pin_maps>

  453.               <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 

  454.               <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 

  455.               <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 

  456.               <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 

  457.               <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 

  458.               <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 

  459.               <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 

  460.               <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 

  461.               <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 

  462.               <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 

  463.               <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 

  464.               <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 

  465.               <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 

  466.               <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 

  467.               <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 

  468.               <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 

  469.             </pin_maps>

  470.           </port_map>

  471.           <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 

  472.             <pin_maps>

  473.               <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 

  474.               <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 

  475.               <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 

  476.               <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 

  477.               <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 

  478.               <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 

  479.               <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 

  480.               <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 

  481.               <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 

  482.               <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 

  483.               <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 

  484.               <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 

  485.               <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 

  486.               <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 

  487.               <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 

  488.               <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 

  489.             </pin_maps>

  490.           </port_map>

  491.           <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 

  492.             <pin_maps>

  493.               <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 

  494.               <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 

  495.               <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 

  496.               <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 

  497.               <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 

  498.               <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 

  499.               <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 

  500.               <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 

  501.               <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 

  502.               <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 

  503.               <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 

  504.               <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 

  505.               <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 

  506.               <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 

  507.               <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 

  508.               <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 

  509.             </pin_maps>

  510.           </port_map>

  511.         </port_maps>

  512.       </interface>

  513.       <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">

  514.         <preferred_ips>

  515. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>

  516. 		</preferred_ips>

  517. 		<port_maps>

  518.           <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">

  519.             <pin_maps>

  520.               <pin_map port_index="0" component_pin="spi_mosi_i"/> 

  521.             </pin_maps>

  522.           </port_map>

  523.           <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">

  524.             <pin_maps>

  525.               <pin_map port_index="0" component_pin="spi_mosi_i"/> 

  526.             </pin_maps>

  527.           </port_map>

  528.           <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">

  529.             <pin_maps>

  530.               <pin_map port_index="0" component_pin="spi_mosi_i"/> 

  531.             </pin_maps>

  532.           </port_map>

  533.           <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">

  534.             <pin_maps>

  535.               <pin_map port_index="0" component_pin="spi_miso_i"/> 

  536.             </pin_maps>

  537.           </port_map>

  538.           <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">

  539.             <pin_maps>

  540.               <pin_map port_index="0" component_pin="spi_miso_i"/> 

  541.             </pin_maps>

  542.           </port_map>

  543.           <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">

  544.             <pin_maps>

  545.               <pin_map port_index="0" component_pin="spi_miso_i"/> 

  546.             </pin_maps>

  547.           </port_map>

  548.           <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">

  549.             <pin_maps>

  550.               <pin_map port_index="0" component_pin="spi_sclk_i"/> 

  551.             </pin_maps>

  552.           </port_map>

  553.           <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">

  554.             <pin_maps>

  555.               <pin_map port_index="0" component_pin="spi_sclk_i"/> 

  556.             </pin_maps>

  557.           </port_map>

  558.           <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">

  559.             <pin_maps>

  560.               <pin_map port_index="0" component_pin="spi_sclk_i"/> 

  561.             </pin_maps>

  562.           </port_map>

  563.           <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">

  564.             <pin_maps>

  565.               <pin_map port_index="0" component_pin="spi_ss_i"/> 

  566.             </pin_maps>

  567.           </port_map>

  568.           <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">

  569.             <pin_maps>

  570.               <pin_map port_index="0" component_pin="spi_ss_i"/> 

  571.             </pin_maps>

  572.           </port_map>

  573.           <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">

  574.             <pin_maps>

  575.               <pin_map port_index="0" component_pin="spi_ss_i"/> 

  576.             </pin_maps>

  577.           </port_map>

  578.         </port_maps>

  579.       </interface>

  580.       <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">

  581.         <parameters>

  582.           <parameter name="frequency" value="100000000"/>

  583.         </parameters>

  584.         <preferred_ips>

  585.           <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>

  586.         </preferred_ips>

  587. 		<port_maps>

  588.           <port_map logical_port="clk" physical_port="clk" dir="in">

  589.             <pin_maps>

  590.               <pin_map port_index="0" component_pin="clk"/> 

  591.             </pin_maps>

  592.           </port_map>

  593.         </port_maps>

  594.         <parameters>

  595.           <parameter name="frequency" value="100000000" />

  596.        </parameters>

  597.       </interface>

  598.       <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">

  599.         <preferred_ips>

  600.           <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>

  601.         </preferred_ips>

  602. 		<port_maps>

  603.           <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">

  604.             <pin_maps>

  605.               <pin_map port_index="0" component_pin="usb_uart_txd"/> 

  606.             </pin_maps>

  607.           </port_map>

  608.           <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">

  609.             <pin_maps>

  610.               <pin_map port_index="0" component_pin="usb_uart_rxd"/> 

  611.             </pin_maps>

  612.           </port_map>

  613.         </port_maps>

  614.       </interface>

  615. 	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">

  616.         <port_maps>

  617.           <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 

  618.             <pin_maps>

  619.               <pin_map port_index="0" component_pin="JA1"/> 

  620. 			</pin_maps>

  621. 		  </port_map>

  622. 		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 

  623.             <pin_maps>

  624.               <pin_map port_index="0" component_pin="JA1"/> 

  625. 			</pin_maps>

  626. 		  </port_map>

  627. 		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 

  628.             <pin_maps>

  629.               <pin_map port_index="0" component_pin="JA1"/> 

  630. 			</pin_maps>

  631. 		  </port_map>

  632. 		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 

  633.             <pin_maps>

  634.               <pin_map port_index="0" component_pin="JA2"/> 

  635. 			</pin_maps>

  636. 		  </port_map>

  637. 		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 

  638.             <pin_maps>

  639.               <pin_map port_index="0" component_pin="JA2"/> 

  640. 			</pin_maps>

  641. 		  </port_map>

  642. 		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 

  643.             <pin_maps>

  644.               <pin_map port_index="0" component_pin="JA2"/> 

  645. 			</pin_maps>

  646. 		  </port_map>

  647. 		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 

  648.             <pin_maps>

  649.               <pin_map port_index="0" component_pin="JA3"/> 

  650. 			</pin_maps>

  651. 		  </port_map>

  652. 		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 

  653.             <pin_maps>

  654.               <pin_map port_index="0" component_pin="JA3"/> 

  655. 			</pin_maps>

  656. 		  </port_map>

  657. 		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 

  658.             <pin_maps>

  659.               <pin_map port_index="0" component_pin="JA3"/> 

  660. 			</pin_maps>

  661. 		  </port_map>

  662. 		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 

  663.             <pin_maps>

  664.               <pin_map port_index="0" component_pin="JA4"/> 

  665. 			</pin_maps>

  666. 		  </port_map>

  667. 		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 

  668.             <pin_maps>

  669.               <pin_map port_index="0" component_pin="JA4"/> 

  670. 			</pin_maps>

  671. 		  </port_map>

  672. 		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 

  673.             <pin_maps>

  674.               <pin_map port_index="0" component_pin="JA4"/> 

  675. 			</pin_maps>

  676. 		  </port_map>

  677. 		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 

  678.             <pin_maps>

  679.               <pin_map port_index="0" component_pin="JA7"/> 

  680. 			</pin_maps>

  681. 		  </port_map>

  682. 		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 

  683.             <pin_maps>

  684.               <pin_map port_index="0" component_pin="JA7"/> 

  685. 			</pin_maps>

  686. 		  </port_map>

  687. 		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 

  688.             <pin_maps>

  689.               <pin_map port_index="0" component_pin="JA7"/> 

  690. 			</pin_maps>

  691. 		  </port_map>

  692. 		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 

  693.             <pin_maps>

  694.               <pin_map port_index="0" component_pin="JA8"/> 

  695. 			</pin_maps>

  696. 		  </port_map>

  697. 		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 

  698.             <pin_maps>

  699.               <pin_map port_index="0" component_pin="JA8"/> 

  700. 			</pin_maps>

  701. 		  </port_map>

  702. 		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 

  703.             <pin_maps>

  704.               <pin_map port_index="0" component_pin="JA8"/> 

  705. 			</pin_maps>

  706. 		  </port_map>

  707. 		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 

  708.             <pin_maps>

  709.               <pin_map port_index="0" component_pin="JA9"/> 

  710. 			</pin_maps>

  711. 		  </port_map>

  712. 		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 

  713.             <pin_maps>

  714.               <pin_map port_index="0" component_pin="JA9"/> 

  715. 			</pin_maps>

  716. 		  </port_map>

  717. 		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 

  718.             <pin_maps>

  719.               <pin_map port_index="0" component_pin="JA9"/> 

  720. 			</pin_maps>

  721. 		  </port_map>

  722. 		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 

  723.             <pin_maps>

  724.               <pin_map port_index="0" component_pin="JA10"/> 

  725. 			</pin_maps>

  726. 		  </port_map>

  727. 		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 

  728.             <pin_maps>

  729.               <pin_map port_index="0" component_pin="JA10"/> 

  730. 			</pin_maps>

  731. 		  </port_map>

  732. 		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 

  733.             <pin_maps>

  734.               <pin_map port_index="0" component_pin="JA10"/> 

  735. 			</pin_maps>

  736. 		  </port_map>

  737.         </port_maps>

  738.       </interface>

  739. 	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">

  740.         <port_maps>

  741.           <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 

  742.             <pin_maps>

  743.               <pin_map port_index="0" component_pin="JB1"/> 

  744. 			</pin_maps>

  745. 		  </port_map>

  746. 		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 

  747.             <pin_maps>

  748.               <pin_map port_index="0" component_pin="JB1"/> 

  749. 			</pin_maps>

  750. 		  </port_map>

  751. 		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 

  752.             <pin_maps>

  753.               <pin_map port_index="0" component_pin="JB1"/> 

  754. 			</pin_maps>

  755. 		  </port_map>

  756. 		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 

  757.             <pin_maps>

  758.               <pin_map port_index="0" component_pin="JB2"/> 

  759. 			</pin_maps>

  760. 		  </port_map>

  761. 		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 

  762.             <pin_maps>

  763.               <pin_map port_index="0" component_pin="JB2"/> 

  764. 			</pin_maps>

  765. 		  </port_map>

  766. 		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 

  767.             <pin_maps>

  768.               <pin_map port_index="0" component_pin="JB2"/> 

  769. 			</pin_maps>

  770. 		  </port_map>

  771. 		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 

  772.             <pin_maps>

  773.               <pin_map port_index="0" component_pin="JB3"/> 

  774. 			</pin_maps>

  775. 		  </port_map>

  776. 		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 

  777.             <pin_maps>

  778.               <pin_map port_index="0" component_pin="JB3"/> 

  779. 			</pin_maps>

  780. 		  </port_map>

  781. 		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 

  782.             <pin_maps>

  783.               <pin_map port_index="0" component_pin="JB3"/> 

  784. 			</pin_maps>

  785. 		  </port_map>

  786. 		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 

  787.             <pin_maps>

  788.               <pin_map port_index="0" component_pin="JB4"/> 

  789. 			</pin_maps>

  790. 		  </port_map>

  791. 		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 

  792.             <pin_maps>

  793.               <pin_map port_index="0" component_pin="JB4"/> 

  794. 			</pin_maps>

  795. 		  </port_map>

  796. 		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 

  797.             <pin_maps>

  798.               <pin_map port_index="0" component_pin="JB4"/> 

  799. 			</pin_maps>

  800. 		  </port_map>

  801. 		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 

  802.             <pin_maps>

  803.               <pin_map port_index="0" component_pin="JB7"/> 

  804. 			</pin_maps>

  805. 		  </port_map>

  806. 		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 

  807.             <pin_maps>

  808.               <pin_map port_index="0" component_pin="JB7"/> 

  809. 			</pin_maps>

  810. 		  </port_map>

  811. 		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 

  812.             <pin_maps>

  813.               <pin_map port_index="0" component_pin="JB7"/> 

  814. 			</pin_maps>

  815. 		  </port_map>

  816. 		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 

  817.             <pin_maps>

  818.               <pin_map port_index="0" component_pin="JB8"/> 

  819. 			</pin_maps>

  820. 		  </port_map>

  821. 		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 

  822.             <pin_maps>

  823.               <pin_map port_index="0" component_pin="JB8"/> 

  824. 			</pin_maps>

  825. 		  </port_map>

  826. 		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 

  827.             <pin_maps>

  828.               <pin_map port_index="0" component_pin="JB8"/> 

  829. 			</pin_maps>

  830. 		  </port_map>

  831. 		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 

  832.             <pin_maps>

  833.               <pin_map port_index="0" component_pin="JB9"/> 

  834. 			</pin_maps>

  835. 		  </port_map>

  836. 		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 

  837.             <pin_maps>

  838.               <pin_map port_index="0" component_pin="JB9"/> 

  839. 			</pin_maps>

  840. 		  </port_map>

  841. 		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 

  842.             <pin_maps>

  843.               <pin_map port_index="0" component_pin="JB9"/> 

  844. 			</pin_maps>

  845. 		  </port_map>

  846. 		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 

  847.             <pin_maps>

  848.               <pin_map port_index="0" component_pin="JB10"/> 

  849. 			</pin_maps>

  850. 		  </port_map>

  851. 		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 

  852.             <pin_maps>

  853.               <pin_map port_index="0" component_pin="JB10"/> 

  854. 			</pin_maps>

  855. 		  </port_map>

  856. 		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 

  857.             <pin_maps>

  858.               <pin_map port_index="0" component_pin="JB10"/> 

  859. 			</pin_maps>

  860. 		  </port_map>

  861.         </port_maps>

  862.       </interface>

  863. 	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">

  864.         <port_maps>

  865.           <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 

  866.             <pin_maps>

  867.               <pin_map port_index="0" component_pin="JC1"/> 

  868. 			</pin_maps>

  869. 		  </port_map>

  870. 		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 

  871.             <pin_maps>

  872.               <pin_map port_index="0" component_pin="JC1"/> 

  873. 			</pin_maps>

  874. 		  </port_map>

  875. 		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 

  876.             <pin_maps>

  877.               <pin_map port_index="0" component_pin="JC1"/> 

  878. 			</pin_maps>

  879. 		  </port_map>

  880. 		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 

  881.             <pin_maps>

  882.               <pin_map port_index="0" component_pin="JC2"/> 

  883. 			</pin_maps>

  884. 		  </port_map>

  885. 		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 

  886.             <pin_maps>

  887.               <pin_map port_index="0" component_pin="JC2"/> 

  888. 			</pin_maps>

  889. 		  </port_map>

  890. 		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 

  891.             <pin_maps>

  892.               <pin_map port_index="0" component_pin="JC2"/> 

  893. 			</pin_maps>

  894. 		  </port_map>

  895. 		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 

  896.             <pin_maps>

  897.               <pin_map port_index="0" component_pin="JC3"/> 

  898. 			</pin_maps>

  899. 		  </port_map>

  900. 		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 

  901.             <pin_maps>

  902.               <pin_map port_index="0" component_pin="JC3"/> 

  903. 			</pin_maps>

  904. 		  </port_map>

  905. 		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 

  906.             <pin_maps>

  907.               <pin_map port_index="0" component_pin="JC3"/> 

  908. 			</pin_maps>

  909. 		  </port_map>

  910. 		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 

  911.             <pin_maps>

  912.               <pin_map port_index="0" component_pin="JC4"/> 

  913. 			</pin_maps>

  914. 		  </port_map>

  915. 		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 

  916.             <pin_maps>

  917.               <pin_map port_index="0" component_pin="JC4"/> 

  918. 			</pin_maps>

  919. 		  </port_map>

  920. 		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 

  921.             <pin_maps>

  922.               <pin_map port_index="0" component_pin="JC4"/> 

  923. 			</pin_maps>

  924. 		  </port_map>

  925. 		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 

  926.             <pin_maps>

  927.               <pin_map port_index="0" component_pin="JC7"/> 

  928. 			</pin_maps>

  929. 		  </port_map>

  930. 		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 

  931.             <pin_maps>

  932.               <pin_map port_index="0" component_pin="JC7"/> 

  933. 			</pin_maps>

  934. 		  </port_map>

  935. 		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 

  936.             <pin_maps>

  937.               <pin_map port_index="0" component_pin="JC7"/> 

  938. 			</pin_maps>

  939. 		  </port_map>

  940. 		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 

  941.             <pin_maps>

  942.               <pin_map port_index="0" component_pin="JC8"/> 

  943. 			</pin_maps>

  944. 		  </port_map>

  945. 		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 

  946.             <pin_maps>

  947.               <pin_map port_index="0" component_pin="JC8"/> 

  948. 			</pin_maps>

  949. 		  </port_map>

  950. 		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 

  951.             <pin_maps>

  952.               <pin_map port_index="0" component_pin="JC8"/> 

  953. 			</pin_maps>

  954. 		  </port_map>

  955. 		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 

  956.             <pin_maps>

  957.               <pin_map port_index="0" component_pin="JC9"/> 

  958. 			</pin_maps>

  959. 		  </port_map>

  960. 		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 

  961.             <pin_maps>

  962.               <pin_map port_index="0" component_pin="JC9"/> 

  963. 			</pin_maps>

  964. 		  </port_map>

  965. 		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 

  966.             <pin_maps>

  967.               <pin_map port_index="0" component_pin="JC9"/> 

  968. 			</pin_maps>

  969. 		  </port_map>

  970. 		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 

  971.             <pin_maps>

  972.               <pin_map port_index="0" component_pin="JC10"/> 

  973. 			</pin_maps>

  974. 		  </port_map>

  975. 		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 

  976.             <pin_maps>

  977.               <pin_map port_index="0" component_pin="JC10"/> 

  978. 			</pin_maps>

  979. 		  </port_map>

  980. 		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 

  981.             <pin_maps>

  982.               <pin_map port_index="0" component_pin="JC10"/> 

  983. 			</pin_maps>

  984. 		  </port_map>

  985.         </port_maps>

  986.       </interface>

  987. 	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">

  988.         <port_maps>

  989.           <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 

  990.             <pin_maps>

  991.               <pin_map port_index="0" component_pin="JD1"/> 

  992. 			</pin_maps>

  993. 		  </port_map>

  994. 		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 

  995.             <pin_maps>

  996.               <pin_map port_index="0" component_pin="JD1"/> 

  997. 			</pin_maps>

  998. 		  </port_map>

  999. 		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 

  1000.             <pin_maps>

  1001.               <pin_map port_index="0" component_pin="JD1"/> 

  1002. 			</pin_maps>

  1003. 		  </port_map>

  1004. 		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 

  1005.             <pin_maps>

  1006.               <pin_map port_index="0" component_pin="JD2"/> 

  1007. 			</pin_maps>

  1008. 		  </port_map>

  1009. 		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 

  1010.             <pin_maps>

  1011.               <pin_map port_index="0" component_pin="JD2"/> 

  1012. 			</pin_maps>

  1013. 		  </port_map>

  1014. 		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 

  1015.             <pin_maps>

  1016.               <pin_map port_index="0" component_pin="JD2"/> 

  1017. 			</pin_maps>

  1018. 		  </port_map>

  1019. 		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 

  1020.             <pin_maps>

  1021.               <pin_map port_index="0" component_pin="JD3"/> 

  1022. 			</pin_maps>

  1023. 		  </port_map>

  1024. 		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 

  1025.             <pin_maps>

  1026.               <pin_map port_index="0" component_pin="JD3"/> 

  1027. 			</pin_maps>

  1028. 		  </port_map>

  1029. 		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 

  1030.             <pin_maps>

  1031.               <pin_map port_index="0" component_pin="JD3"/> 

  1032. 			</pin_maps>

  1033. 		  </port_map>

  1034. 		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 

  1035.             <pin_maps>

  1036.               <pin_map port_index="0" component_pin="JD4"/> 

  1037. 			</pin_maps>

  1038. 		  </port_map>

  1039. 		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 

  1040.             <pin_maps>

  1041.               <pin_map port_index="0" component_pin="JD4"/> 

  1042. 			</pin_maps>

  1043. 		  </port_map>

  1044. 		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 

  1045.             <pin_maps>

  1046.               <pin_map port_index="0" component_pin="JD4"/> 

  1047. 			</pin_maps>

  1048. 		  </port_map>

  1049. 		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 

  1050.             <pin_maps>

  1051.               <pin_map port_index="0" component_pin="JD7"/> 

  1052. 			</pin_maps>

  1053. 		  </port_map>

  1054. 		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 

  1055.             <pin_maps>

  1056.               <pin_map port_index="0" component_pin="JD7"/> 

  1057. 			</pin_maps>

  1058. 		  </port_map>

  1059. 		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 

  1060.             <pin_maps>

  1061.               <pin_map port_index="0" component_pin="JD7"/> 

  1062. 			</pin_maps>

  1063. 		  </port_map>

  1064. 		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 

  1065.             <pin_maps>

  1066.               <pin_map port_index="0" component_pin="JD8"/> 

  1067. 			</pin_maps>

  1068. 		  </port_map>

  1069. 		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 

  1070.             <pin_maps>

  1071.               <pin_map port_index="0" component_pin="JD8"/> 

  1072. 			</pin_maps>

  1073. 		  </port_map>

  1074. 		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 

  1075.             <pin_maps>

  1076.               <pin_map port_index="0" component_pin="JD8"/> 

  1077. 			</pin_maps>

  1078. 		  </port_map>

  1079. 		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 

  1080.             <pin_maps>

  1081.               <pin_map port_index="0" component_pin="JD9"/> 

  1082. 			</pin_maps>

  1083. 		  </port_map>

  1084. 		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 

  1085.             <pin_maps>

  1086.               <pin_map port_index="0" component_pin="JD9"/> 

  1087. 			</pin_maps>

  1088. 		  </port_map>

  1089. 		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 

  1090.             <pin_maps>

  1091.               <pin_map port_index="0" component_pin="JD9"/> 

  1092. 			</pin_maps>

  1093. 		  </port_map>

  1094. 		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 

  1095.             <pin_maps>

  1096.               <pin_map port_index="0" component_pin="JD10"/> 

  1097. 			</pin_maps>

  1098. 		  </port_map>

  1099. 		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 

  1100.             <pin_maps>

  1101.               <pin_map port_index="0" component_pin="JD10"/> 

  1102. 			</pin_maps>

  1103. 		  </port_map>

  1104. 		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 

  1105.             <pin_maps>

  1106.               <pin_map port_index="0" component_pin="JD10"/> 

  1107. 			</pin_maps>

  1108. 		  </port_map>

  1109.         </port_maps>

  1110.       </interface>

  1111.     </interfaces>

  1112.   </component>

  1113.   

  1114.   <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">

  1115. 	<description>256 MB DDR3L memory SODIMM </description>

  1116. 	<parameters>

  1117.         <parameter name="ddr_type" value="ddr3"/>

  1118.         <parameter name="size" value="256MB"/>

  1119. 	</parameters>

  1120.   </component>

  1121.   <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">

  1122. 	<description>DIP Switches 3 to 0</description>

  1123.   </component>

  1124.   <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">

  1125. 	<description>PHY Ethernet on the board</description>

  1126. 	 <component_modes>

  1127.         <component_mode name="mii" display_name="MII mode">

  1128. 		  <interfaces>

  1129.             <interface name="eth_mii" order="0"/>

  1130.             <interface name="eth_mdio_mdc" order="1" optional="true"/>

  1131.           </interfaces>

  1132. 		</component_mode>

  1133. 	 </component_modes>

  1134.   </component>

  1135.   <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">

  1136.   <description>Shield i2c</description>

  1137.   </component>

  1138.   <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">

  1139.   <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>

  1140.   </component>

  1141.   <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">

  1142. 	<description>LEDs 3 to 0</description>

  1143.   </component>

  1144.   <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">

  1145.   	<description>Push buttons 3 to 0</description>

  1146.   </component>

  1147.   <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">

  1148.   	<description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>

  1149.   </component>

  1150.   <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">

  1151.   	<description>CPU Reset Push Button, active low</description>

  1152.   </component>

  1153.   <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">

  1154.   	<description>RGB leds 12 to 0 (3 per LED)</description>

  1155.   </component>

  1156.   <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">

  1157.   	<description>Shield pins 0 through 19</description>

  1158.   </component>

  1159.   <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">

  1160.   	<description>Shield pins 26 through 41</description>

  1161.   </component>

  1162.   <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">

  1163.   	<description>Shield SPI</description>

  1164.   </component>

  1165.   <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">

  1166.   	<description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>

  1167.   </component>

  1168.   <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">

  1169.   	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>

  1170.   </component>

  1171.    <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">

  1172. 	<description>Pmod Connector JA</description>

  1173.   </component>

  1174.   <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">

  1175. 	<description>Pmod Connector JB</description>

  1176.   </component>

  1177.   <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">

  1178. 	<description>Pmod Connector JC</description>

  1179.   </component>

  1180.   <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">

  1181. 	<description>Pmod Connector JD</description>

  1182.   </component>

  1183. </components>

  1184. 

  1185. <jtag_chains>

  1186.   <jtag_chain name="chain1">

  1187.     <position name="0" component="part0"/>

  1188.   </jtag_chain>

  1189. </jtag_chains>

  1190. <connections>

  1191.   <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">

  1192.     <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>

  1193.   </connection>

  1194.   <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">

  1195.     <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>

  1196. 	<connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>

  1197.   </connection>

  1198.   <connection name="part0_i2c" component1="part0" component2="i2c">

  1199.     <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>

  1200. 	</connection>

  1201.   <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">

  1202.     <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>

  1203.   </connection>

  1204.   <connection name="part0_led_4bits" component1="part0" component2="led_4bits">

  1205.     <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>

  1206.   </connection>

  1207.   <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">

  1208.     <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>

  1209.   </connection>

  1210.   <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">

  1211.     <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>

  1212.   </connection>

  1213.   <connection name="part0_reset" component1="part0" component2="reset">

  1214.     <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>

  1215.   </connection>

  1216.   <connection name="part0_rgb_led" component1="part0" component2="rgb_led">

  1217.     <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>

  1218.   </connection>

  1219.   <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">

  1220.     <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>

  1221.   </connection>

  1222.   <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">

  1223.     <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>

  1224.   </connection>

  1225.   <connection name="part0_spi" component1="part0" component2="spi">

  1226.     <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>

  1227.   </connection>

  1228.   <connection name="part0_sys_clock" component1="part0" component2="sys_clock">

  1229.     <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>

  1230.   </connection>

  1231.   <connection name="part0_usb_uart" component1="part0" component2="usb_uart">

  1232.     <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>

  1233.   </connection>

  1234.    <connection name="part0_ja" component1="part0" component2="ja">

  1235.     <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>

  1236.   </connection>

  1237.   <connection name="part0_jb" component1="part0" component2="jb">

  1238.     <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>

  1239.   </connection>

  1240.   <connection name="part0_jc" component1="part0" component2="jc">

  1241.     <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>

  1242.   </connection>

  1243.   <connection name="part0_jd" component1="part0" component2="jd">

  1244.     <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>

  1245.   </connection>

  1246. </connections>

  1247. </board>