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FPGA_Projekt/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/arty-z7-20/A.0/board.xml

board.xml 32KB
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  1. <?xml version="1.0" encoding="UTF-8" standalone="no"?> 

  2. <!--

  3. MIT License

  4. 

  5. Copyright (c) 2021 Digilent, Inc.

  6. 

  7. Permission is hereby granted, free of charge, to any person obtaining a copy

  8. of this software and associated documentation files (the "Software"), to deal

  9. in the Software without restriction, including without limitation the rights

  10. to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

  11. copies of the Software, and to permit persons to whom the Software is

  12. furnished to do so, subject to the following conditions:

  13. 

  14. The above copyright notice and this permission notice shall be included in all

  15. copies or substantial portions of the Software.

  16. 

  17. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

  18. IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

  19. FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

  20. AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

  21. LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

  22. OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  23. SOFTWARE.

  24. -->

  25. <board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-20" display_name="Arty Z7-20" url="https://digilent.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >

  26. <compatible_board_revisions>

  27.   <revision id="0">A.0</revision>

  28. </compatible_board_revisions>

  29. <file_version>1.1</file_version>

  30. <description>Arty Z7-20 </description>

  31. <components>

  32.   <component name="part0" display_name="Arty Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/arty-z7/start">

  33.     <interfaces>

  34.       <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">

  35.         <port_maps>

  36.           <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0"> 

  37.             <pin_maps>

  38.               <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/> 

  39.               <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/> 

  40.               <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/> 

  41.               <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/> 

  42.             </pin_maps>

  43.           </port_map>

  44.         </port_maps>

  45.       </interface>

  46.       <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">

  47.         <port_maps>

  48.           <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0"> 

  49.             <pin_maps>

  50.               <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/> 

  51.               <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/> 

  52.               <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/> 

  53.               <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/> 

  54.             </pin_maps>

  55.           </port_map>

  56.         </port_maps>

  57.       </interface>

  58.       <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 

  59.       </interface>

  60.       <interface mode="master" name="sws_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_2bits" preset_proc="dip_switches_2bits_preset">

  61. 		<port_maps>

  62.           <port_map logical_port="TRI_I" physical_port="sws_2bits_tri_i" dir="in" left="1" right="0"> 

  63.             <pin_maps>

  64.               <pin_map port_index="0" component_pin="sws_2bits_tri_i_0"/> 

  65.               <pin_map port_index="1" component_pin="sws_2bits_tri_i_1"/> 

  66.             </pin_maps>

  67.           </port_map>

  68.         </port_maps>

  69.       </interface>

  70.       <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">

  71.         <port_maps>

  72.           <port_map logical_port="CLK" physical_port="sys_clk" dir="in">

  73.             <pin_maps>

  74.               <pin_map port_index="0" component_pin="sys_clk"/> 

  75.             </pin_maps>

  76.           </port_map>

  77.         </port_maps>

  78.         <parameters>

  79.           <parameter name="frequency" value="125000000" />

  80.        </parameters>

  81.       </interface>

  82. 	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">

  83.         <port_maps>

  84.           <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 

  85.             <pin_maps>

  86.               <pin_map port_index="0" component_pin="JA1"/> 

  87. 			</pin_maps>

  88. 		  </port_map>

  89. 		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 

  90.             <pin_maps>

  91.               <pin_map port_index="0" component_pin="JA1"/> 

  92. 			</pin_maps>

  93. 		  </port_map>

  94. 		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 

  95.             <pin_maps>

  96.               <pin_map port_index="0" component_pin="JA1"/> 

  97. 			</pin_maps>

  98. 		  </port_map>

  99. 		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 

  100.             <pin_maps>

  101.               <pin_map port_index="0" component_pin="JA2"/> 

  102. 			</pin_maps>

  103. 		  </port_map>

  104. 		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 

  105.             <pin_maps>

  106.               <pin_map port_index="0" component_pin="JA2"/> 

  107. 			</pin_maps>

  108. 		  </port_map>

  109. 		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 

  110.             <pin_maps>

  111.               <pin_map port_index="0" component_pin="JA2"/> 

  112. 			</pin_maps>

  113. 		  </port_map>

  114. 		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 

  115.             <pin_maps>

  116.               <pin_map port_index="0" component_pin="JA3"/> 

  117. 			</pin_maps>

  118. 		  </port_map>

  119. 		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 

  120.             <pin_maps>

  121.               <pin_map port_index="0" component_pin="JA3"/> 

  122. 			</pin_maps>

  123. 		  </port_map>

  124. 		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 

  125.             <pin_maps>

  126.               <pin_map port_index="0" component_pin="JA3"/> 

  127. 			</pin_maps>

  128. 		  </port_map>

  129. 		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 

  130.             <pin_maps>

  131.               <pin_map port_index="0" component_pin="JA4"/> 

  132. 			</pin_maps>

  133. 		  </port_map>

  134. 		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 

  135.             <pin_maps>

  136.               <pin_map port_index="0" component_pin="JA4"/> 

  137. 			</pin_maps>

  138. 		  </port_map>

  139. 		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 

  140.             <pin_maps>

  141.               <pin_map port_index="0" component_pin="JA4"/> 

  142. 			</pin_maps>

  143. 		  </port_map>

  144. 		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 

  145.             <pin_maps>

  146.               <pin_map port_index="0" component_pin="JA7"/> 

  147. 			</pin_maps>

  148. 		  </port_map>

  149. 		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 

  150.             <pin_maps>

  151.               <pin_map port_index="0" component_pin="JA7"/> 

  152. 			</pin_maps>

  153. 		  </port_map>

  154. 		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 

  155.             <pin_maps>

  156.               <pin_map port_index="0" component_pin="JA7"/> 

  157. 			</pin_maps>

  158. 		  </port_map>

  159. 		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 

  160.             <pin_maps>

  161.               <pin_map port_index="0" component_pin="JA8"/> 

  162. 			</pin_maps>

  163. 		  </port_map>

  164. 		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 

  165.             <pin_maps>

  166.               <pin_map port_index="0" component_pin="JA8"/> 

  167. 			</pin_maps>

  168. 		  </port_map>

  169. 		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 

  170.             <pin_maps>

  171.               <pin_map port_index="0" component_pin="JA8"/> 

  172. 			</pin_maps>

  173. 		  </port_map>

  174. 		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 

  175.             <pin_maps>

  176.               <pin_map port_index="0" component_pin="JA9"/> 

  177. 			</pin_maps>

  178. 		  </port_map>

  179. 		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 

  180.             <pin_maps>

  181.               <pin_map port_index="0" component_pin="JA9"/> 

  182. 			</pin_maps>

  183. 		  </port_map>

  184. 		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 

  185.             <pin_maps>

  186.               <pin_map port_index="0" component_pin="JA9"/> 

  187. 			</pin_maps>

  188. 		  </port_map>

  189. 		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 

  190.             <pin_maps>

  191.               <pin_map port_index="0" component_pin="JA10"/> 

  192. 			</pin_maps>

  193. 		  </port_map>

  194. 		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 

  195.             <pin_maps>

  196.               <pin_map port_index="0" component_pin="JA10"/> 

  197. 			</pin_maps>

  198. 		  </port_map>

  199. 		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 

  200.             <pin_maps>

  201.               <pin_map port_index="0" component_pin="JA10"/> 

  202. 			</pin_maps>

  203. 		  </port_map>

  204.         </port_maps>

  205.       </interface>

  206. 	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">

  207.         <port_maps>

  208.           <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 

  209.             <pin_maps>

  210.               <pin_map port_index="0" component_pin="JB1"/> 

  211. 			</pin_maps>

  212. 		  </port_map>

  213. 		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 

  214.             <pin_maps>

  215.               <pin_map port_index="0" component_pin="JB1"/> 

  216. 			</pin_maps>

  217. 		  </port_map>

  218. 		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 

  219.             <pin_maps>

  220.               <pin_map port_index="0" component_pin="JB1"/> 

  221. 			</pin_maps>

  222. 		  </port_map>

  223. 		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 

  224.             <pin_maps>

  225.               <pin_map port_index="0" component_pin="JB2"/> 

  226. 			</pin_maps>

  227. 		  </port_map>

  228. 		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 

  229.             <pin_maps>

  230.               <pin_map port_index="0" component_pin="JB2"/> 

  231. 			</pin_maps>

  232. 		  </port_map>

  233. 		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 

  234.             <pin_maps>

  235.               <pin_map port_index="0" component_pin="JB2"/> 

  236. 			</pin_maps>

  237. 		  </port_map>

  238. 		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 

  239.             <pin_maps>

  240.               <pin_map port_index="0" component_pin="JB3"/> 

  241. 			</pin_maps>

  242. 		  </port_map>

  243. 		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 

  244.             <pin_maps>

  245.               <pin_map port_index="0" component_pin="JB3"/> 

  246. 			</pin_maps>

  247. 		  </port_map>

  248. 		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 

  249.             <pin_maps>

  250.               <pin_map port_index="0" component_pin="JB3"/> 

  251. 			</pin_maps>

  252. 		  </port_map>

  253. 		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 

  254.             <pin_maps>

  255.               <pin_map port_index="0" component_pin="JB4"/> 

  256. 			</pin_maps>

  257. 		  </port_map>

  258. 		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 

  259.             <pin_maps>

  260.               <pin_map port_index="0" component_pin="JB4"/> 

  261. 			</pin_maps>

  262. 		  </port_map>

  263. 		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 

  264.             <pin_maps>

  265.               <pin_map port_index="0" component_pin="JB4"/> 

  266. 			</pin_maps>

  267. 		  </port_map>

  268. 		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 

  269.             <pin_maps>

  270.               <pin_map port_index="0" component_pin="JB7"/> 

  271. 			</pin_maps>

  272. 		  </port_map>

  273. 		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 

  274.             <pin_maps>

  275.               <pin_map port_index="0" component_pin="JB7"/> 

  276. 			</pin_maps>

  277. 		  </port_map>

  278. 		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 

  279.             <pin_maps>

  280.               <pin_map port_index="0" component_pin="JB7"/> 

  281. 			</pin_maps>

  282. 		  </port_map>

  283. 		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 

  284.             <pin_maps>

  285.               <pin_map port_index="0" component_pin="JB8"/> 

  286. 			</pin_maps>

  287. 		  </port_map>

  288. 		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 

  289.             <pin_maps>

  290.               <pin_map port_index="0" component_pin="JB8"/> 

  291. 			</pin_maps>

  292. 		  </port_map>

  293. 		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 

  294.             <pin_maps>

  295.               <pin_map port_index="0" component_pin="JB8"/> 

  296. 			</pin_maps>

  297. 		  </port_map>

  298. 		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 

  299.             <pin_maps>

  300.               <pin_map port_index="0" component_pin="JB9"/> 

  301. 			</pin_maps>

  302. 		  </port_map>

  303. 		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 

  304.             <pin_maps>

  305.               <pin_map port_index="0" component_pin="JB9"/> 

  306. 			</pin_maps>

  307. 		  </port_map>

  308. 		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 

  309.             <pin_maps>

  310.               <pin_map port_index="0" component_pin="JB9"/> 

  311. 			</pin_maps>

  312. 		  </port_map>

  313. 		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 

  314.             <pin_maps>

  315.               <pin_map port_index="0" component_pin="JB10"/> 

  316. 			</pin_maps>

  317. 		  </port_map>

  318. 		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 

  319.             <pin_maps>

  320.               <pin_map port_index="0" component_pin="JB10"/> 

  321. 			</pin_maps>

  322. 		  </port_map>

  323. 		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 

  324.             <pin_maps>

  325.               <pin_map port_index="0" component_pin="JB10"/> 

  326. 			</pin_maps>

  327. 		  </port_map>

  328.         </port_maps>

  329.       </interface>

  330.       <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">

  331.         <description>Shield I2C</description>

  332. 		<preferred_ips>

  333.             <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>

  334.         </preferred_ips>

  335. 		<port_maps>

  336.           <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">

  337.             <pin_maps>

  338.               <pin_map port_index="0" component_pin="i2c_sda_i"/> 

  339.             </pin_maps>

  340.           </port_map>

  341.           <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">

  342.             <pin_maps>

  343.               <pin_map port_index="0" component_pin="i2c_sda_i"/> 

  344.             </pin_maps>

  345.           </port_map>

  346.           <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">

  347.             <pin_maps>

  348.               <pin_map port_index="0" component_pin="i2c_sda_i"/> 

  349.             </pin_maps>

  350.           </port_map>

  351.           <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">

  352.             <pin_maps>

  353.               <pin_map port_index="0" component_pin="i2c_scl_i"/> 

  354.             </pin_maps>

  355.           </port_map>

  356.           <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">

  357.             <pin_maps>

  358.               <pin_map port_index="0" component_pin="i2c_scl_i"/> 

  359.             </pin_maps>

  360.           </port_map>

  361.           <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">

  362.             <pin_maps>

  363.               <pin_map port_index="0" component_pin="i2c_scl_i"/> 

  364.             </pin_maps>

  365.           </port_map>

  366.         </port_maps>

  367.       </interface>

  368.       <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">

  369.         <description>2 RGB LEDs</description>

  370. 		<preferred_ips>

  371. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  372. 		</preferred_ips>

  373. 		<port_maps>

  374.           <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 

  375.             <pin_maps>

  376.               <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 

  377.               <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 

  378.               <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 

  379.               <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 

  380.               <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 

  381.               <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 

  382.             </pin_maps>

  383.           </port_map>

  384.         </port_maps>

  385.       </interface>

  386.       <interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">

  387. 		<preferred_ips>

  388. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  389. 		</preferred_ips>

  390.         <port_maps>

  391.           <port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0"> 

  392.             <pin_maps>

  393.               <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 

  394.               <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 

  395.               <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 

  396.               <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 

  397.               <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 

  398.               <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 

  399.               <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 

  400.               <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 

  401.               <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 

  402.               <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 

  403.               <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 

  404.               <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 

  405.               <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 

  406.               <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 

  407.             </pin_maps>

  408.           </port_map>

  409.           <port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0"> 

  410.             <pin_maps>

  411.               <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 

  412.               <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 

  413.               <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 

  414.               <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 

  415.               <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 

  416.               <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 

  417.               <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 

  418.               <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 

  419.               <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 

  420.               <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 

  421.               <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 

  422.               <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 

  423.               <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 

  424.               <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 

  425.             </pin_maps>

  426.           </port_map>

  427.           <port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0"> 

  428.             <pin_maps>

  429.               <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/> 

  430.               <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/> 

  431.               <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/> 

  432.               <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/> 

  433.               <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/> 

  434.               <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/> 

  435.               <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/> 

  436.               <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/> 

  437.               <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/> 

  438.               <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/> 

  439.               <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/> 

  440.               <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/> 

  441.               <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/> 

  442.               <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/> 

  443.             </pin_maps>

  444.           </port_map>

  445.         </port_maps>

  446.       </interface>

  447.       <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">

  448. 		<preferred_ips>

  449. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  450. 		</preferred_ips>

  451.         <port_maps>

  452.           <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0"> 

  453.             <pin_maps>

  454.               <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 

  455.               <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 

  456.               <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 

  457.               <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 

  458.               <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 

  459.               <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 

  460.               <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 

  461.               <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 

  462.               <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 

  463.               <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 

  464.               <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 

  465.               <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 

  466.               <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 

  467.               <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 

  468.               <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 

  469.               <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 

  470.             </pin_maps>

  471.           </port_map>

  472.           <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0"> 

  473.             <pin_maps>

  474.               <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 

  475.               <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 

  476.               <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 

  477.               <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 

  478.               <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 

  479.               <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 

  480.               <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 

  481.               <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 

  482.               <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 

  483.               <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 

  484.               <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 

  485.               <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 

  486.               <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 

  487.               <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 

  488.               <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 

  489.               <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 

  490.             </pin_maps>

  491.           </port_map>

  492.           <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0"> 

  493.             <pin_maps>

  494.               <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/> 

  495.               <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/> 

  496.               <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/> 

  497.               <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/> 

  498.               <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/> 

  499.               <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/> 

  500.               <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/> 

  501.               <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/> 

  502.               <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/> 

  503.               <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/> 

  504.               <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/> 

  505.               <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/> 

  506.               <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/> 

  507.               <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/> 

  508.               <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/> 

  509.               <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/> 

  510.             </pin_maps>

  511.           </port_map>

  512.         </port_maps>

  513.       </interface>

  514.       <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">

  515.         <preferred_ips>

  516. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>

  517. 		</preferred_ips>

  518. 		<port_maps>

  519.           <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">

  520.             <pin_maps>

  521.               <pin_map port_index="0" component_pin="spi_mosi_i"/> 

  522.             </pin_maps>

  523.           </port_map>

  524.           <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">

  525.             <pin_maps>

  526.               <pin_map port_index="0" component_pin="spi_mosi_i"/> 

  527.             </pin_maps>

  528.           </port_map>

  529.           <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">

  530.             <pin_maps>

  531.               <pin_map port_index="0" component_pin="spi_mosi_i"/> 

  532.             </pin_maps>

  533.           </port_map>

  534.           <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">

  535.             <pin_maps>

  536.               <pin_map port_index="0" component_pin="spi_miso_i"/> 

  537.             </pin_maps>

  538.           </port_map>

  539.           <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">

  540.             <pin_maps>

  541.               <pin_map port_index="0" component_pin="spi_miso_i"/> 

  542.             </pin_maps>

  543.           </port_map>

  544.           <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">

  545.             <pin_maps>

  546.               <pin_map port_index="0" component_pin="spi_miso_i"/> 

  547.             </pin_maps>

  548.           </port_map>

  549.           <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">

  550.             <pin_maps>

  551.               <pin_map port_index="0" component_pin="spi_sclk_i"/> 

  552.             </pin_maps>

  553.           </port_map>

  554.           <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">

  555.             <pin_maps>

  556.               <pin_map port_index="0" component_pin="spi_sclk_i"/> 

  557.             </pin_maps>

  558.           </port_map>

  559.           <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">

  560.             <pin_maps>

  561.               <pin_map port_index="0" component_pin="spi_sclk_i"/> 

  562.             </pin_maps>

  563.           </port_map>

  564.           <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">

  565.             <pin_maps>

  566.               <pin_map port_index="0" component_pin="spi_ss_i"/> 

  567.             </pin_maps>

  568.           </port_map>

  569.           <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">

  570.             <pin_maps>

  571.               <pin_map port_index="0" component_pin="spi_ss_i"/> 

  572.             </pin_maps>

  573.           </port_map>

  574.           <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">

  575.             <pin_maps>

  576.               <pin_map port_index="0" component_pin="spi_ss_i"/> 

  577.             </pin_maps>

  578.           </port_map>

  579.         </port_maps>

  580.       </interface>	  

  581.     </interfaces>

  582.   </component>

  583.   

  584.   <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">

  585. 	<description>Buttons 3 to 0</description>

  586.   </component>

  587.   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">

  588. 	<description>Pmod Connector JA</description>

  589.   </component>

  590.   <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">

  591. 	<description>Pmod Connector JB</description>

  592.   </component>

  593.   <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">

  594. 	<description>LEDs 3 to 0</description>

  595.   </component>

  596.   <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>

  597.   <component name="sws_2bits" display_name="2 Switches" type="chip" sub_type="switch" major_group="GPIO">

  598. 	<description>DIP Switches 1 to 0</description>

  599.   </component>

  600.   <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">

  601.   <description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>

  602.   </component>

  603. 

  604.   <component name="i2c" display_name="I2C on J2" type="chip" sub_type="mux" major_group="I2C">

  605.   <description>Shield i2c</description>

  606.   </component>

  607.   <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">

  608.   	<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>

  609.   </component>

  610.   <component name="shield_dp0_dp13" display_name="Shield Pins 0 through 13" type="chip" sub_type="led" major_group="GPIO">

  611.   	<description>Digital Shield pins DP0 through DP13</description>

  612.   </component>

  613.   <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">

  614.   	<description>Digital Shield pins DP26 through DP41</description>

  615.   </component>

  616.   <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">

  617.   	<description>Shield SPI</description>

  618.   </component>

  619. 

  620. </components>

  621. <jtag_chains>

  622.   <jtag_chain name="chain1">

  623.     <position name="0" component="part0"/>

  624.   </jtag_chain>

  625. </jtag_chains>

  626. <connections>

  627.   <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">

  628.     <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>

  629.   </connection>

  630.   <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">

  631.     <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>

  632.   </connection>

  633.   <connection name="part0_sws_2bits" component1="part0" component2="sws_2bits">

  634.     <connection_map name="part0_sws_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>

  635.   </connection>

  636.   <connection name="part0_sys_clock" component1="part0" component2="sys_clock">

  637.     <connection_map name="part0_sys_clock_1" c1_st_index="10" c1_end_index="10" c2_st_index="0" c2_end_index="0"/>

  638.   </connection>

  639.   <connection name="part0_ja" component1="part0" component2="ja">

  640.     <connection_map name="part0_ja_1" c1_st_index="11" c1_end_index="18" c2_st_index="0" c2_end_index="7"/>

  641.   </connection>

  642.   <connection name="part0_jb" component1="part0" component2="jb">

  643.     <connection_map name="part0_jb_1" c1_st_index="19" c1_end_index="26" c2_st_index="0" c2_end_index="7"/>

  644.   </connection>

  645.   <connection name="part0_i2c" component1="part0" component2="i2c">

  646.     <connection_map name="part0_i2c_1" c1_st_index="27" c1_end_index="28" c2_st_index="0" c2_end_index="1"/>

  647.   </connection>

  648.   <connection name="part0_rgb_led" component1="part0" component2="rgb_led">

  649.     <connection_map name="part0_rgb_led_1" c1_st_index="29" c1_end_index="34" c2_st_index="0" c2_end_index="5"/>

  650.   </connection>

  651.   <connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">

  652.     <connection_map name="part0_shield_dp0_dp13_1" c1_st_index="35" c1_end_index="48" c2_st_index="0" c2_end_index="13"/>

  653.   </connection>

  654.   <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">

  655.     <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="49" c1_end_index="64" c2_st_index="0" c2_end_index="15"/>

  656.   </connection>

  657.   <connection name="part0_spi" component1="part0" component2="spi">

  658.     <connection_map name="part0_spi_1" c1_st_index="65" c1_end_index="68" c2_st_index="0" c2_end_index="3"/>

  659.   </connection>

  660. </connections>

  661. </board>