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- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
- <!--
- MIT License
-
- Copyright (c) 2021 Digilent, Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining a copy
- of this software and associated documentation files (the "Software"), to deal
- in the Software without restriction, including without limitation the rights
- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- copies of the Software, and to permit persons to whom the Software is
- furnished to do so, subject to the following conditions:
-
- The above copyright notice and this permission notice shall be included in all
- copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
- -->
- <board schema_version="2.0" vendor="digilentinc.com" name="cmod-s7-25" display_name="Cmod S7-25" url="https://digilent.com/reference/programmable-logic/cmod-s7/start" preset_file="preset.xml">
- <compatible_board_revisions>
- <revision id="0">B.0</revision>
- </compatible_board_revisions>
- <file_version>1.0</file_version>
- <description>Cmod S7-25</description>
- <components>
- <component name="part0" display_name="Cmod S7-25" type="fpga" part_name="xc7s25csga225-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-s7/start">
- <interfaces>
- <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
- <description>12 MHz Single-Ended System Clock</description>
- <port_maps>
- <port_map logical_port="CLK" physical_port="clk" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="clk"/>
- </pin_maps>
- </port_map>
- </port_maps>
- <parameters>
- <parameter name="frequency" value="12000000"/>
- </parameters>
- </interface>
- <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
- <description>BTN0 used as Active High System Reset</description>
- <port_maps>
- <port_map logical_port="RST" physical_port="reset_btn0" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
- </pin_maps>
- </port_map>
- </port_maps>
- <parameters>
- <parameter name="rst_polarity" value="1"/>
- </parameters>
- </interface>
- <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="output_4bits_preset">
- <description>4 LEDs</description>
- <port_maps>
- <port_map logical_port="TRI_O" physical_port="led_4bits_tri_io" dir="out" left="3" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="led_4bits_tri_io_0"/>
- <pin_map port_index="1" component_pin="led_4bits_tri_io_1"/>
- <pin_map port_index="2" component_pin="led_4bits_tri_io_2"/>
- <pin_map port_index="3" component_pin="led_4bits_tri_io_3"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="rgb_led_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led_3bits" preset_proc="rgb_led_3bits_preset">
- <description>RGB LED</description>
- <port_maps>
- <port_map logical_port="TRI_O" physical_port="rgb_led_3bits_tri_io" dir="out" left="2" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="rgb_led_3bits_tri_io_0"/>
- <pin_map port_index="1" component_pin="rgb_led_3bits_tri_io_1"/>
- <pin_map port_index="2" component_pin="rgb_led_3bits_tri_io_2"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="input_2bits_preset">
- <description>2 Push Buttons</description>
- <port_maps>
- <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
- <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="input_1bit_preset">
- <description>Only BTN1</description>
- <port_maps>
- <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in">
- <pin_maps>
- <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <!-- Add "pio_32bits" ? -->
- <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="usb_uart_preset">
- <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
- <port_maps>
- <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="usb_uart_txd"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="usb_uart_rxd"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_flash_preset">
- <description>Quad SPI Flash</description>
- <preferred_ips>
- <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
- </preferred_ips>
- <port_maps>
- <port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db0"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db0"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db0"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_db3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_csn"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_csn"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_csn"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="SCK_I" physical_port="qspi_sck" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_sck"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="SCK_O" physical_port="qspi_sck" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_sck"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="SCK_T" physical_port="qspi_sck" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="qspi_sck"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
- <description>Pmod Connector JA</description>
- <port_maps>
- <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA10"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- </interfaces>
- </component>
- <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
- <description>12 MHz System Clock</description>
- </component>
- <component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
- <description>Configure BTN0 as System Reset button, active high</description>
- </component>
- <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
- <description>LEDs 3 to 0</description>
- </component>
- <component name="rgb_led_3bits" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
- <description>RGB LED 2 downto 0 (ordered RGB)</description>
- </component>
-
- <component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
- <description>Push Buttons 1 to 0</description>
- <component_modes>
- <component_mode name="2_btns" display_name="2 Buttons (No Reset)">
- <interfaces>
- <interface name="push_buttons_2bits" order="0"/>
- </interfaces>
- </component_mode>
- <component_mode name="1_btn" display_name="Only BTN1">
- <interfaces>
- <interface name="push_buttons_1bit" order="0"/>
- </interfaces>
- </component_mode>
- </component_modes>
- </component>
- <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
- <description>USB UART</description>
- </component>
- <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
- <description>QSPI Flash</description>
- </component>
- <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
- <description>Pmod Connector JA</description>
- </component>
- </components>
- <jtag_chains>
- <jtag_chain name="chain1">
- <position name="0" component="part0"/>
- </jtag_chain>
- </jtag_chains>
- <connections>
- <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
- <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
- </connection>
- <connection name="part0_reset" component1="part0" component2="reset">
- <connection_map name="part0_reset_1" c1_st_index="8" c1_end_index="8" c2_st_index="0" c2_end_index="0"/>
- </connection>
- <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
- <connection_map name="part0_led_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
- </connection>
- <connection name="part0_rgb_led_3bits" component1="part0" component2="rgb_led_3bits">
- <connection_map name="part0_rgb_led_3bits_1" c1_st_index="5" c1_end_index="7" c2_st_index="0" c2_end_index="2"/>
- </connection>
- <connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
- <connection_map name="part0_push_buttons_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
- </connection>
- <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
- <connection_map name="part0_usb_uart_1" c1_st_index="10" c1_end_index="11" c2_st_index="0" c2_end_index="1"/>
- </connection>
- <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
- <connection_map name="part0_qspi_flash_1" c1_st_index="12" c1_end_index="17" c2_st_index="0" c2_end_index="5"/>
- </connection>
- <connection name="part0_ja" component1="part0" component2="ja">
- <connection_map name="part0_ja_1" c1_st_index="18" c1_end_index="25" c2_st_index="0" c2_end_index="7"/>
- </connection>
- </connections>
- </board>
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