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FPGA_Projekt/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/board.xml

board.xml 22KB
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  1. <?xml version="1.0" encoding="UTF-8" standalone="no"?> 

  2. <!--

  3. MIT License

  4. 

  5. Copyright (c) 2021 Digilent, Inc.

  6. 

  7. Permission is hereby granted, free of charge, to any person obtaining a copy

  8. of this software and associated documentation files (the "Software"), to deal

  9. in the Software without restriction, including without limitation the rights

  10. to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

  11. copies of the Software, and to permit persons to whom the Software is

  12. furnished to do so, subject to the following conditions:

  13. 

  14. The above copyright notice and this permission notice shall be included in all

  15. copies or substantial portions of the Software.

  16. 

  17. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

  18. IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

  19. FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

  20. AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

  21. LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

  22. OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  23. SOFTWARE.

  24. -->

  25. <board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-15t" display_name="Cmod A7-15t" url="https://digilent.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">

  26. <compatible_board_revisions>

  27.   <revision id="0">B.0</revision>

  28. </compatible_board_revisions>

  29. <file_version>1.2</file_version>

  30. <description>Cmod A7-15t</description>

  31. <components>

  32.   <component name="part0" display_name="Cmod A7-15t" type="fpga" part_name="xc7a15tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-a7/start">

  33.     <interfaces>

  34. 	<interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">

  35.         <description>512KB SRAM</description>

  36. 		<port_maps>

  37.           <port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="18" right="0"> 

  38.             <pin_maps>

  39.               <pin_map port_index="0" component_pin="cellular_ram_addr_0"/> 

  40.               <pin_map port_index="1" component_pin="cellular_ram_addr_1"/> 

  41.               <pin_map port_index="2" component_pin="cellular_ram_addr_2"/> 

  42.               <pin_map port_index="3" component_pin="cellular_ram_addr_3"/> 

  43.               <pin_map port_index="4" component_pin="cellular_ram_addr_4"/> 

  44.               <pin_map port_index="5" component_pin="cellular_ram_addr_5"/> 

  45.               <pin_map port_index="6" component_pin="cellular_ram_addr_6"/> 

  46.               <pin_map port_index="7" component_pin="cellular_ram_addr_7"/> 

  47.               <pin_map port_index="8" component_pin="cellular_ram_addr_8"/> 

  48.               <pin_map port_index="9" component_pin="cellular_ram_addr_9"/> 

  49.               <pin_map port_index="10" component_pin="cellular_ram_addr_10"/> 

  50.               <pin_map port_index="11" component_pin="cellular_ram_addr_11"/> 

  51.               <pin_map port_index="12" component_pin="cellular_ram_addr_12"/> 

  52.               <pin_map port_index="13" component_pin="cellular_ram_addr_13"/> 

  53.               <pin_map port_index="14" component_pin="cellular_ram_addr_14"/> 

  54.               <pin_map port_index="15" component_pin="cellular_ram_addr_15"/> 

  55.               <pin_map port_index="16" component_pin="cellular_ram_addr_16"/> 

  56.               <pin_map port_index="17" component_pin="cellular_ram_addr_17"/> 

  57.               <pin_map port_index="18" component_pin="cellular_ram_addr_18"/>

  58.             </pin_maps>

  59.           </port_map>

  60.           <port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="7" right="0"> 

  61.             <pin_maps>

  62.               <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 

  63.               <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 

  64.               <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 

  65.               <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 

  66.               <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 

  67.               <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 

  68.               <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 

  69.               <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 

  70.             </pin_maps>

  71.           </port_map>

  72.           <port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="7" right="0"> 

  73.             <pin_maps>

  74.               <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 

  75.               <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 

  76.               <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 

  77.               <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 

  78.               <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 

  79.               <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 

  80.               <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 

  81.               <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 

  82.             </pin_maps>

  83.           </port_map>

  84.           <port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="7" right="0"> 

  85.             <pin_maps>

  86.               <pin_map port_index="0" component_pin="cellular_ram_dq_0"/> 

  87.               <pin_map port_index="1" component_pin="cellular_ram_dq_1"/> 

  88.               <pin_map port_index="2" component_pin="cellular_ram_dq_2"/> 

  89.               <pin_map port_index="3" component_pin="cellular_ram_dq_3"/> 

  90.               <pin_map port_index="4" component_pin="cellular_ram_dq_4"/> 

  91.               <pin_map port_index="5" component_pin="cellular_ram_dq_5"/> 

  92.               <pin_map port_index="6" component_pin="cellular_ram_dq_6"/> 

  93.               <pin_map port_index="7" component_pin="cellular_ram_dq_7"/> 

  94.             </pin_maps>

  95.           </port_map>

  96.           <port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">

  97.             <pin_maps>

  98.               <pin_map port_index="0" component_pin="cellular_ram_oen"/> 

  99.             </pin_maps>

  100.           </port_map>

  101.           <port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">

  102.             <pin_maps>

  103.               <pin_map port_index="0" component_pin="cellular_ram_wen"/> 

  104.             </pin_maps>

  105.           </port_map>

  106.           <port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">

  107.             <pin_maps>

  108.               <pin_map port_index="0" component_pin="cellular_ram_ce_n"/> 

  109.             </pin_maps>

  110.           </port_map>

  111.         </port_maps>

  112.       </interface>

  113.       <interface mode="master" name="led_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_2bits" preset_proc="led_2bits_preset">

  114.         <port_maps>

  115.           <port_map logical_port="TRI_O" physical_port="led_2bits_tri_o" dir="out" left="1" right="0"> 

  116.             <pin_maps>

  117.               <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/> 

  118.               <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>

  119.             </pin_maps>

  120.           </port_map>

  121.         </port_maps>

  122.       </interface>

  123. 	  <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_3bits_preset">

  124.         <description>RGB LED</description>

  125. 		<port_maps>

  126.           <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0"> 

  127.             <pin_maps>

  128.               <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 

  129.               <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>

  130. 			  <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>

  131.             </pin_maps>

  132.           </port_map>

  133.         </port_maps>

  134.       </interface>

  135.       <interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_2bits_preset">

  136.         <port_maps>

  137.           <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0"> 

  138.             <pin_maps>

  139.               <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/> 

  140.               <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/> 

  141.             </pin_maps>

  142.           </port_map>

  143.         </port_maps>

  144.       </interface>

  145. 	  <interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_1bit_preset">

  146.         <port_maps>

  147.           <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in"> 

  148.             <pin_maps>

  149.               <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_1"/> 

  150.             </pin_maps>

  151.           </port_map>

  152.         </port_maps>

  153.       </interface>

  154.       <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">

  155.         <description>Quad SPI Flash</description>

  156. 		<preferred_ips>

  157. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>

  158. 		</preferred_ips>

  159. 		<port_maps>

  160.           <port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">

  161.             <pin_maps>

  162.               <pin_map port_index="0" component_pin="qspi_db0"/> 

  163.             </pin_maps>

  164.           </port_map>

  165.           <port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">

  166.             <pin_maps>

  167.               <pin_map port_index="0" component_pin="qspi_db0"/> 

  168.             </pin_maps>

  169.           </port_map>

  170.           <port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">

  171.             <pin_maps>

  172.               <pin_map port_index="0" component_pin="qspi_db0"/> 

  173.             </pin_maps>

  174.           </port_map>

  175.           <port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">

  176.             <pin_maps>

  177.               <pin_map port_index="0" component_pin="qspi_db1"/> 

  178.             </pin_maps>

  179.           </port_map>

  180.           <port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">

  181.             <pin_maps>

  182.               <pin_map port_index="0" component_pin="qspi_db1"/> 

  183.             </pin_maps>

  184.           </port_map>

  185.           <port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">

  186.             <pin_maps>

  187.               <pin_map port_index="0" component_pin="qspi_db1"/> 

  188.             </pin_maps>

  189.           </port_map>

  190.           <port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">

  191.             <pin_maps>

  192.               <pin_map port_index="0" component_pin="qspi_db2"/> 

  193.             </pin_maps>

  194.           </port_map>

  195.           <port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">

  196.             <pin_maps>

  197.               <pin_map port_index="0" component_pin="qspi_db2"/> 

  198.             </pin_maps>

  199.           </port_map>

  200.           <port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">

  201.             <pin_maps>

  202.               <pin_map port_index="0" component_pin="qspi_db2"/> 

  203.             </pin_maps>

  204.           </port_map>

  205.           <port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">

  206.             <pin_maps>

  207.               <pin_map port_index="0" component_pin="qspi_db3"/> 

  208.             </pin_maps>

  209.           </port_map>

  210.           <port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">

  211.             <pin_maps>

  212.               <pin_map port_index="0" component_pin="qspi_db3"/> 

  213.             </pin_maps>

  214.           </port_map>

  215.           <port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">

  216.             <pin_maps>

  217.               <pin_map port_index="0" component_pin="qspi_db3"/> 

  218.             </pin_maps>

  219.           </port_map>

  220.           <port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">

  221.             <pin_maps>

  222.               <pin_map port_index="0" component_pin="qspi_csn"/> 

  223.             </pin_maps>

  224.           </port_map>

  225.           <port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">

  226.             <pin_maps>

  227.               <pin_map port_index="0" component_pin="qspi_csn"/> 

  228.             </pin_maps>

  229.           </port_map>

  230.           <port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">

  231.             <pin_maps>

  232.               <pin_map port_index="0" component_pin="qspi_csn"/> 

  233.             </pin_maps>

  234.           </port_map>

  235.         </port_maps>

  236.       </interface>

  237.       <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">

  238.         <description>Use BTN0 as System Reset, active high</description>

  239. 		<port_maps>

  240.           <port_map logical_port="RST" physical_port="reset_btn0" dir="in">

  241.             <pin_maps>

  242.               <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/> 

  243.             </pin_maps>

  244.           </port_map>

  245.         </port_maps>

  246.         <parameters>

  247.           <parameter name="rst_polarity" value="1" />

  248.        </parameters>

  249.       </interface>

  250.       <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">

  251.         <description>12 MHz Single-Ended System Clock</description>

  252. 		<port_maps>

  253.           <port_map logical_port="CLK" physical_port="clk" dir="in">

  254.             <pin_maps>

  255.               <pin_map port_index="0" component_pin="clk"/> 

  256.             </pin_maps>

  257.           </port_map>

  258.         </port_maps>

  259.         <parameters>

  260.           <parameter name="frequency" value="12000000" />

  261.        </parameters>

  262.       </interface>

  263.       <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">

  264.         <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>

  265. 		<port_maps>

  266.           <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">

  267.             <pin_maps>

  268.               <pin_map port_index="0" component_pin="usb_uart_txd"/> 

  269.             </pin_maps>

  270.           </port_map>

  271.           <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">

  272.             <pin_maps>

  273.               <pin_map port_index="0" component_pin="usb_uart_rxd"/> 

  274.             </pin_maps>

  275.           </port_map>

  276.         </port_maps>

  277.       </interface>

  278.       <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">

  279.         <port_maps>

  280.           <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 

  281.             <pin_maps>

  282.               <pin_map port_index="0" component_pin="JA1"/> 

  283. 			</pin_maps>

  284. 		  </port_map>

  285. 		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 

  286.             <pin_maps>

  287.               <pin_map port_index="0" component_pin="JA1"/> 

  288. 			</pin_maps>

  289. 		  </port_map>

  290. 		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 

  291.             <pin_maps>

  292.               <pin_map port_index="0" component_pin="JA1"/> 

  293. 			</pin_maps>

  294. 		  </port_map>

  295. 		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 

  296.             <pin_maps>

  297.               <pin_map port_index="0" component_pin="JA2"/> 

  298. 			</pin_maps>

  299. 		  </port_map>

  300. 		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 

  301.             <pin_maps>

  302.               <pin_map port_index="0" component_pin="JA2"/> 

  303. 			</pin_maps>

  304. 		  </port_map>

  305. 		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 

  306.             <pin_maps>

  307.               <pin_map port_index="0" component_pin="JA2"/> 

  308. 			</pin_maps>

  309. 		  </port_map>

  310. 		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 

  311.             <pin_maps>

  312.               <pin_map port_index="0" component_pin="JA3"/> 

  313. 			</pin_maps>

  314. 		  </port_map>

  315. 		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 

  316.             <pin_maps>

  317.               <pin_map port_index="0" component_pin="JA3"/> 

  318. 			</pin_maps>

  319. 		  </port_map>

  320. 		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 

  321.             <pin_maps>

  322.               <pin_map port_index="0" component_pin="JA3"/> 

  323. 			</pin_maps>

  324. 		  </port_map>

  325. 		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 

  326.             <pin_maps>

  327.               <pin_map port_index="0" component_pin="JA4"/> 

  328. 			</pin_maps>

  329. 		  </port_map>

  330. 		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 

  331.             <pin_maps>

  332.               <pin_map port_index="0" component_pin="JA4"/> 

  333. 			</pin_maps>

  334. 		  </port_map>

  335. 		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 

  336.             <pin_maps>

  337.               <pin_map port_index="0" component_pin="JA4"/> 

  338. 			</pin_maps>

  339. 		  </port_map>

  340. 		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 

  341.             <pin_maps>

  342.               <pin_map port_index="0" component_pin="JA7"/> 

  343. 			</pin_maps>

  344. 		  </port_map>

  345. 		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 

  346.             <pin_maps>

  347.               <pin_map port_index="0" component_pin="JA7"/> 

  348. 			</pin_maps>

  349. 		  </port_map>

  350. 		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 

  351.             <pin_maps>

  352.               <pin_map port_index="0" component_pin="JA7"/> 

  353. 			</pin_maps>

  354. 		  </port_map>

  355. 		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 

  356.             <pin_maps>

  357.               <pin_map port_index="0" component_pin="JA8"/> 

  358. 			</pin_maps>

  359. 		  </port_map>

  360. 		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 

  361.             <pin_maps>

  362.               <pin_map port_index="0" component_pin="JA8"/> 

  363. 			</pin_maps>

  364. 		  </port_map>

  365. 		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 

  366.             <pin_maps>

  367.               <pin_map port_index="0" component_pin="JA8"/> 

  368. 			</pin_maps>

  369. 		  </port_map>

  370. 		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 

  371.             <pin_maps>

  372.               <pin_map port_index="0" component_pin="JA9"/> 

  373. 			</pin_maps>

  374. 		  </port_map>

  375. 		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 

  376.             <pin_maps>

  377.               <pin_map port_index="0" component_pin="JA9"/> 

  378. 			</pin_maps>

  379. 		  </port_map>

  380. 		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 

  381.             <pin_maps>

  382.               <pin_map port_index="0" component_pin="JA9"/> 

  383. 			</pin_maps>

  384. 		  </port_map>

  385. 		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 

  386.             <pin_maps>

  387.               <pin_map port_index="0" component_pin="JA10"/> 

  388. 			</pin_maps>

  389. 		  </port_map>

  390. 		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 

  391.             <pin_maps>

  392.               <pin_map port_index="0" component_pin="JA10"/> 

  393. 			</pin_maps>

  394. 		  </port_map>

  395. 		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 

  396.             <pin_maps>

  397.               <pin_map port_index="0" component_pin="JA10"/> 

  398. 			</pin_maps>

  399. 		  </port_map>

  400.         </port_maps>

  401.       </interface>

  402. 	</interfaces>

  403.   </component>

  404.   <component name="cellular_ram" display_name="Cell RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">

  405. 	<description>512KB SRAM</description>

  406.   </component>

  407.   <component name="led_2bits" display_name="2 LEDs" type="chip" sub_type="led" major_group="GPIO">

  408. 	<description>LEDs 1 to 0</description>

  409.   </component>

  410.   <component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">

  411. 	<description>RGB led 2 downto 0 [R G B]</description>

  412.   </component>

  413.   <component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">

  414. 	<description>Push buttons 1 to 0</description>

  415. 	<component_modes>

  416.         <component_mode name="2_btns" display_name="2 Buttons (No Reset)">

  417. 		  <interfaces>

  418.             <interface name="push_buttons_2bits" order="0"/>

  419.           </interfaces>

  420. 		</component_mode>

  421. 		<component_mode name="1_btn" display_name="Just use BTN1">

  422. 		  <interfaces>

  423.             <interface name="push_buttons_1bit" order="0"/>

  424.           </interfaces>

  425. 		</component_mode>

  426. 	 </component_modes>

  427.   </component>

  428.   <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">

  429. 	<description>QSPI Flash</description>

  430.   </component>

  431.   <component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">

  432. 	<description>Configure BTN0 as System Reset button, active high</description>

  433.   </component>

  434.   <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">

  435. 	<description>12 MHz System Clock</description>

  436.   </component>

  437.   <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">

  438. 	<description>USB UART</description>

  439.   </component>

  440.   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">

  441. 	<description>Pmod Connector JA</description>

  442.   </component>

  443. </components>

  444. <jtag_chains>

  445.   <jtag_chain name="chain1">

  446.     <position name="0" component="part0"/>

  447.   </jtag_chain>

  448. </jtag_chains>

  449. <connections>

  450.   <connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">

  451.     <connection_map name="part0_cellular_ram_1" c1_st_index="1" c1_end_index="30" c2_st_index="0" c2_end_index="29"/>

  452.   </connection>

  453.   <connection name="part0_led_2bits" component1="part0" component2="led_2bits">

  454.     <connection_map name="part0_led_16bits_1" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>

  455.   </connection>

  456.   <connection name="part0_rgb_led" component1="part0" component2="rgb_led">

  457.     <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="35" c2_st_index="0" c2_end_index="2"/>

  458.   </connection>

  459.   <connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">

  460.     <connection_map name="part0_push_buttons_2bits_1" c1_st_index="41" c1_end_index="42" c2_st_index="0" c2_end_index="1"/>

  461.   </connection>

  462.   <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">

  463.     <connection_map name="part0_qspi_flash_1" c1_st_index="36" c1_end_index="40" c2_st_index="0" c2_end_index="4"/>

  464.   </connection>

  465.   <connection name="part0_reset" component1="part0" component2="reset">

  466.     <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>

  467.   </connection>

  468.   <connection name="part0_sys_clock" component1="part0" component2="sys_clock">

  469.     <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>

  470.   </connection>

  471.   <connection name="part0_usb_uart" component1="part0" component2="usb_uart">

  472.     <connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>

  473.   </connection>

  474.   <connection name="part0_ja" component1="part0" component2="ja">

  475.     <connection_map name="part0_ja_1" c1_st_index="45" c1_end_index="52" c2_st_index="0" c2_end_index="7"/>

  476.   </connection>

  477. </connections>

  478. </board>