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- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
- <!--
- MIT License
-
- Copyright (c) 2021 Digilent, Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining a copy
- of this software and associated documentation files (the "Software"), to deal
- in the Software without restriction, including without limitation the rights
- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- copies of the Software, and to permit persons to whom the Software is
- furnished to do so, subject to the following conditions:
-
- The above copyright notice and this permission notice shall be included in all
- copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
- -->
- <part_info part_name="xc7a35tcpg236-1">
- <pins>
- <pin index="0" name ="clk" iostandard="LVCMOS33" loc="L17"/>
- <pin index="1" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="M18"/>
- <pin index="2" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="M19"/>
- <pin index="3" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="K17"/>
- <pin index="4" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="N17"/>
- <pin index="5" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="P17"/>
- <pin index="6" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="P18"/>
- <pin index="7" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="R18"/>
- <pin index="8" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="W19"/>
- <pin index="9" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="U19"/>
- <pin index="10" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="V19"/>
- <pin index="11" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="W18"/>
- <pin index="12" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="T17"/>
- <pin index="13" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="T18"/>
- <pin index="14" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U17"/>
- <pin index="15" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="U18"/>
- <pin index="16" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="V16"/>
- <pin index="17" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="W16"/>
- <pin index="18" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="W17"/>
- <pin index="19" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V15"/>
- <pin index="20" name ="cellular_ram_dq_0" iostandard="LVCMOS33" loc="W15"/>
- <pin index="21" name ="cellular_ram_dq_1" iostandard="LVCMOS33" loc="W13"/>
- <pin index="22" name ="cellular_ram_dq_2" iostandard="LVCMOS33" loc="W14"/>
- <pin index="23" name ="cellular_ram_dq_3" iostandard="LVCMOS33" loc="U15"/>
- <pin index="24" name ="cellular_ram_dq_4" iostandard="LVCMOS33" loc="U16"/>
- <pin index="25" name ="cellular_ram_dq_5" iostandard="LVCMOS33" loc="V13"/>
- <pin index="26" name ="cellular_ram_dq_6" iostandard="LVCMOS33" loc="V14"/>
- <pin index="27" name ="cellular_ram_dq_7" iostandard="LVCMOS33" loc="U14"/>
- <pin index="28" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="P19"/>
- <pin index="29" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R19"/>
- <pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="N19"/>
- <pin index="31" name ="led_2bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/>
- <pin index="32" name ="led_2bits_tri_o_1" iostandard="LVCMOS33" loc="C16"/>
- <pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="B17"/>
- <pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="B16"/>
- <pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="C17"/>
- <pin index="36" name ="qspi_csn" iostandard="LVCMOS33" loc="K19"/>
- <pin index="37" name ="qspi_db0" iostandard="LVCMOS33" loc="D18"/>
- <pin index="38" name ="qspi_db1" iostandard="LVCMOS33" loc="D19"/>
- <pin index="39" name ="qspi_db2" iostandard="LVCMOS33" loc="G18"/>
- <pin index="40" name ="qspi_db3" iostandard="LVCMOS33" loc="F18"/>
- <pin index="41" name ="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="A18"/>
- <pin index="42" name ="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="B18"/>
- <pin index="43" name ="usb_uart_txd" iostandard="LVCMOS33" loc="J18"/>
- <pin index="44" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="J17"/>
- <pin index="45" name ="JA1" iostandard="LVCMOS33" loc="G17"/>
- <pin index="46" name ="JA2" iostandard="LVCMOS33" loc="G19"/>
- <pin index="47" name ="JA3" iostandard="LVCMOS33" loc="N18"/>
- <pin index="48" name ="JA4" iostandard="LVCMOS33" loc="L18"/>
- <pin index="49" name ="JA7" iostandard="LVCMOS33" loc="H17"/>
- <pin index="50" name ="JA8" iostandard="LVCMOS33" loc="H19"/>
- <pin index="51" name ="JA9" iostandard="LVCMOS33" loc="J19"/>
- <pin index="52" name ="JA10" iostandard="LVCMOS33" loc="K18"/>
- </pins>
- </part_info>
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