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- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
- <!--
- MIT License
-
- Copyright (c) 2021 Digilent, Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining a copy
- of this software and associated documentation files (the "Software"), to deal
- in the Software without restriction, including without limitation the rights
- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- copies of the Software, and to permit persons to whom the Software is
- furnished to do so, subject to the following conditions:
-
- The above copyright notice and this permission notice shall be included in all
- copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
- -->
- <board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://www.digilentinc.com" preset_file="preset.xml">
- <compatible_board_revisions>
- <revision id="0">A.0</revision>
- </compatible_board_revisions>
- <file_version>1.0</file_version>
- <description>Eclypse Z7</description>
-
- <components>
- <!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
- <component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com">
- <interfaces>
- <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
- <port_maps>
- <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="sys_clk"/>
- </pin_maps>
- </port_map>
- </port_maps>
- <parameters>
- <parameter name="frequency" value="125000000"/>
- </parameters>
- </interface>
- <interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
- <description>Buttons</description>
- <preferred_ips>
- <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
- </preferred_ips>
- <port_maps>
- <port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="1" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/>
- <pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="rgbled_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_6bits" preset_proc="rgbled_6bits_preset">
- <description>8 LEDs</description>
- <preferred_ips>
- <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
- </preferred_ips>
- <port_maps>
- <port_map logical_port="TRI_O" physical_port="rgbled_6bits_tri_o" dir="out" left="5" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="rgbled_6bits_tri_o_0"/>
- <pin_map port_index="1" component_pin="rgbled_6bits_tri_o_1"/>
- <pin_map port_index="2" component_pin="rgbled_6bits_tri_o_2"/>
- <pin_map port_index="3" component_pin="rgbled_6bits_tri_o_3"/>
- <pin_map port_index="4" component_pin="rgbled_6bits_tri_o_4"/>
- <pin_map port_index="5" component_pin="rgbled_6bits_tri_o_5"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="pmod_ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_ja">
- <port_maps>
- <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JA10"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
- <port_maps>
- <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB10"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
- </interface>
- </interfaces>
- </component>
-
- <!-- Descriptions of components that will appear in the IPI Board tab -->
- <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
- <description>3.3V Single-Ended 125 MHz clock from Ethernet PHY</description>
- </component>
- <component name="btn_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
- <description>Buttons 1 to 0</description>
- </component>
- <component name="rgbled_6bits" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
- <description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
- </component>
- <component name="pmod_ja" display_name="Pmod Connector JA" type="chip" sub_type="chip" major_group="Pmod">
- <description>Pmod Connector JA</description>
- </component>
- <component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
- <description>Pmod Connector JB</description>
- </component>
- <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
- </components>
-
- <jtag_chains>
- <jtag_chain name="chain1">
- <position name="0" component="part0"/>
- </jtag_chain>
- </jtag_chains>
-
- <connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
- <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
- <connection_map name="part0_sys_clock_map" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
- </connection>
- <connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
- <connection_map name="part0_btn_2bits_map" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
- </connection>
- <connection name="part0_rgbled_6bits" component1="part0" component2="rgbled_6bits">
- <connection_map name="part0_rgbled_6bits_map" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
- </connection>
- <connection name="part0_pmod_ja" component1="part0" component2="pmod_ja">
- <connection_map name="part0_pmod_ja_map" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
- </connection>
- <connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
- <connection_map name="part0_pmod_jb_map" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
- </connection>
- </connections>
-
- </board>
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