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- <?xml version="1.0" encoding="UTF-8" standalone="no"?>
- <!--
- MIT License
-
- Copyright (c) 2022 Digilent, Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining a copy
- of this software and associated documentation files (the "Software"), to deal
- in the Software without restriction, including without limitation the rights
- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- copies of the Software, and to permit persons to whom the Software is
- furnished to do so, subject to the following conditions:
-
- The above copyright notice and this permission notice shall be included in all
- copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
- -->
- <board schema_version="2.1" vendor="digilentinc.com" name="gzu_3eg" display_name="Genesys ZU-3EG" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">
- <compatible_board_revisions>
- <revision id="0">D.0</revision>
- </compatible_board_revisions>
- <file_version>1.1</file_version>
- <description>Genesys ZU-3EG</description>
-
- <components>
- <!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
- <component name="part0" display_name="Genesys ZU-3EG" type="fpga" part_name="xczu3eg-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">
- <interfaces>
- <interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset">
- <preferred_ips>
- <preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
- </preferred_ips>
- </interface>
- <interface mode="master" name="btn_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_5bits" preset_proc="btn_5bits_preset">
- <description>5 PL Buttons (Ordered "UCDLR")</description>
- <preferred_ips>
- <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
- </preferred_ips>
- <port_maps>
- <port_map logical_port="TRI_I" physical_port="btn_5bits_tri_i" dir="in" left="4" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="btn_5bits_tri_i_0"/>
- <pin_map port_index="1" component_pin="btn_5bits_tri_i_1"/>
- <pin_map port_index="2" component_pin="btn_5bits_tri_i_2"/>
- <pin_map port_index="3" component_pin="btn_5bits_tri_i_3"/>
- <pin_map port_index="4" component_pin="btn_5bits_tri_i_4"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="switch_4bits" preset_proc="switch_4bits_preset">
- <description>4 PL Switches</description>
- <preferred_ips>
- <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
- </preferred_ips>
- <port_maps>
- <port_map logical_port="TRI_I" physical_port="switch_4bits_tri_i" dir="in" left="3" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="switch_4bits_tri_i_0"/>
- <pin_map port_index="1" component_pin="switch_4bits_tri_i_1"/>
- <pin_map port_index="2" component_pin="switch_4bits_tri_i_2"/>
- <pin_map port_index="3" component_pin="switch_4bits_tri_i_3"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="rgbled_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_3bits" preset_proc="rgbled_3bits_preset">
- <description>PL RGB LED (ordered RGB)</description>
- <preferred_ips>
- <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
- </preferred_ips>
- <port_maps>
- <port_map logical_port="TRI_O" physical_port="rgbled_3bits_tri_o" dir="out" left="2" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="rgbled_3bits_tri_o_0"/>
- <pin_map port_index="1" component_pin="rgbled_3bits_tri_o_1"/>
- <pin_map port_index="2" component_pin="rgbled_3bits_tri_o_2"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
- <description>4 LEDs</description>
- <preferred_ips>
- <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
- </preferred_ips>
- <port_maps>
- <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
- <pin_maps>
- <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
- <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
- <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
- <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
- <port_maps>
- <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JB10"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="pmod_jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jc">
- <port_maps>
- <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JC10"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- <interface mode="master" name="pmod_jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jd">
- <port_maps>
- <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD1"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD2"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD3"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD4"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD7"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD8"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD9"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD10"/>
- </pin_maps>
- </port_map>
- <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
- <pin_maps>
- <pin_map port_index="0" component_pin="JD10"/>
- </pin_maps>
- </port_map>
- </port_maps>
- </interface>
- </interfaces>
- </component>
-
- <!-- Descriptions of components that will appear in the IPI Board tab -->
- <component name="ps8_fixedio" display_name="PS8 Fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
- <component name="btn_5bits" display_name="5 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
- <description>5 Buttons (Ordered "UCDLR")</description>
- </component>
- <component name="switch_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
- <description>4 Switches</description>
- </component>
- <component name="rgbled_3bits" display_name="1 RGB LED" type="chip" sub_type="led" major_group="GPIO">
- <description>1 RGB LED (Ordered "RGB")</description>
- </component>
- <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
- <description>4 LEDs</description>
- </component>
- <component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
- <description>Pmod Connector JB</description>
- </component>
- <component name="pmod_jc" display_name="Pmod Connector JC" type="chip" sub_type="chip" major_group="Pmod">
- <description>Pmod Connector JC</description>
- </component>
- <component name="pmod_jd" display_name="Pmod Connector JD" type="chip" sub_type="chip" major_group="Pmod">
- <description>Pmod Connector JD</description>
- </component>
- </components>
-
- <jtag_chains>
- <jtag_chain name="chain1">
- <position name="0" component="part0"/>
- </jtag_chain>
- </jtag_chains>
-
- <connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
- <connection name="part0_btn_5bits" component1="part0" component2="btn_5bits">
- <connection_map name="part0_btn_5bits_map" c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
- </connection>
- <connection name="part0_switch_4bits" component1="part0" component2="switch_4bits">
- <connection_map name="part0_switch_4bits_map" c1_st_index="5" c1_end_index="8" c2_st_index="0" c2_end_index="3"/>
- </connection>
- <connection name="rgbled_3bits" component1="part0" component2="rgbled_3bits">
- <connection_map name="part0_rgbled_3bits_map" c1_st_index="9" c1_end_index="11" c2_st_index="0" c2_end_index="2"/>
- </connection>
- <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
- <connection_map name="part0_led_4bits_map" c1_st_index="12" c1_end_index="15" c2_st_index="0" c2_end_index="3"/>
- </connection>
- <connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
- <connection_map name="part0_pmod_jb_map" c1_st_index="16" c1_end_index="23" c2_st_index="0" c2_end_index="7"/>
- </connection>
- <connection name="part0_pmod_jc" component1="part0" component2="pmod_jc">
- <connection_map name="part0_pmod_jc_map" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
- </connection>
- <connection name="part0_pmod_jd" component1="part0" component2="pmod_jd">
- <connection_map name="part0_pmod_jd_map" c1_st_index="32" c1_end_index="39" c2_st_index="0" c2_end_index="7"/>
- </connection>
- </connections>
-
- </board>
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