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FPGA_Projekt/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/board.xml

board.xml 21KB
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  1. <?xml version="1.0" encoding="UTF-8" standalone="no"?> 

  2. <!--

  3. MIT License

  4. 

  5. Copyright (c) 2022 Digilent, Inc.

  6. 

  7. Permission is hereby granted, free of charge, to any person obtaining a copy

  8. of this software and associated documentation files (the "Software"), to deal

  9. in the Software without restriction, including without limitation the rights

  10. to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

  11. copies of the Software, and to permit persons to whom the Software is

  12. furnished to do so, subject to the following conditions:

  13. 

  14. The above copyright notice and this permission notice shall be included in all

  15. copies or substantial portions of the Software.

  16. 

  17. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

  18. IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

  19. FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

  20. AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

  21. LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

  22. OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  23. SOFTWARE.

  24. -->

  25. <board schema_version="2.1" vendor="digilentinc.com" name="gzu_5ev" display_name="Genesys ZU-5EV" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">

  26. <compatible_board_revisions>

  27. 	<revision id="0">C.0</revision>

  28. </compatible_board_revisions>

  29. <file_version>1.1</file_version>

  30. <description>Genesys ZU-5EV</description>

  31. 

  32. <components>

  33. 	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->

  34. 	<component name="part0" display_name="Genesys ZU-5EV" type="fpga" part_name="xczu5ev-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">

  35. 		<interfaces>

  36. 			<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset"> 

  37. 				<preferred_ips>

  38. 					<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>

  39. 				</preferred_ips>

  40. 			</interface>

  41. 			<interface mode="master" name="btn_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_5bits" preset_proc="btn_5bits_preset">

  42. 				<description>5 PL Buttons (Ordered "UCDLR")</description>

  43. 				<preferred_ips>

  44. 					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  45. 				</preferred_ips>

  46. 				<port_maps>

  47. 					<port_map logical_port="TRI_I" physical_port="btn_5bits_tri_i" dir="in" left="4" right="0"> 

  48. 						<pin_maps>

  49. 							<pin_map port_index="0" component_pin="btn_5bits_tri_i_0"/> 

  50. 							<pin_map port_index="1" component_pin="btn_5bits_tri_i_1"/> 

  51. 							<pin_map port_index="2" component_pin="btn_5bits_tri_i_2"/> 

  52. 							<pin_map port_index="3" component_pin="btn_5bits_tri_i_3"/> 

  53. 							<pin_map port_index="4" component_pin="btn_5bits_tri_i_4"/> 

  54. 						</pin_maps>

  55. 					</port_map>

  56. 				</port_maps>

  57. 			</interface>

  58. 			<interface mode="master" name="switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="switch_4bits" preset_proc="switch_4bits_preset">

  59. 				<description>4 PL Switches</description>

  60. 				<preferred_ips>

  61. 					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  62. 				</preferred_ips>

  63. 				<port_maps>

  64. 					<port_map logical_port="TRI_I" physical_port="switch_4bits_tri_i" dir="in" left="3" right="0"> 

  65. 						<pin_maps>

  66. 							<pin_map port_index="0" component_pin="switch_4bits_tri_i_0"/> 

  67. 							<pin_map port_index="1" component_pin="switch_4bits_tri_i_1"/> 

  68. 							<pin_map port_index="2" component_pin="switch_4bits_tri_i_2"/> 

  69. 							<pin_map port_index="3" component_pin="switch_4bits_tri_i_3"/> 

  70. 						</pin_maps>

  71. 					</port_map>

  72. 				</port_maps>

  73. 			</interface>

  74. 			<interface mode="master" name="rgbled_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_3bits" preset_proc="rgbled_3bits_preset">

  75. 				<description>PL RGB LED (ordered RGB)</description>

  76. 				<preferred_ips>

  77. 					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  78. 				</preferred_ips>

  79. 				<port_maps>

  80. 					<port_map logical_port="TRI_O" physical_port="rgbled_3bits_tri_o" dir="out" left="2" right="0"> 

  81. 						<pin_maps>

  82. 							<pin_map port_index="0" component_pin="rgbled_3bits_tri_o_0"/> 

  83. 							<pin_map port_index="1" component_pin="rgbled_3bits_tri_o_1"/> 

  84. 							<pin_map port_index="2" component_pin="rgbled_3bits_tri_o_2"/> 

  85. 						</pin_maps>

  86. 					</port_map>

  87. 				</port_maps>

  88. 			</interface>

  89. 			<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">

  90. 				<description>4 LEDs</description>

  91. 				<preferred_ips>

  92. 					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  93. 				</preferred_ips>

  94. 				<port_maps>

  95. 					<port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0"> 

  96. 						<pin_maps>

  97. 							<pin_map port_index="0" component_pin="led_4bits_tri_o_0"/> 

  98. 							<pin_map port_index="1" component_pin="led_4bits_tri_o_1"/> 

  99. 							<pin_map port_index="2" component_pin="led_4bits_tri_o_2"/> 

  100. 							<pin_map port_index="3" component_pin="led_4bits_tri_o_3"/> 

  101. 						</pin_maps>

  102. 					</port_map>

  103. 				</port_maps>

  104. 			</interface>

  105. 			<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">

  106. 				<port_maps>

  107. 					<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 

  108. 						<pin_maps>

  109. 							<pin_map port_index="0" component_pin="JB1"/> 

  110. 						</pin_maps>

  111. 					</port_map>

  112. 					<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 

  113. 						<pin_maps>

  114. 							<pin_map port_index="0" component_pin="JB1"/> 

  115. 						</pin_maps>

  116. 					</port_map>

  117. 					<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 

  118. 						<pin_maps>

  119. 							<pin_map port_index="0" component_pin="JB1"/> 

  120. 						</pin_maps>

  121. 					</port_map>

  122. 					<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 

  123. 						<pin_maps>

  124. 							<pin_map port_index="0" component_pin="JB2"/> 

  125. 						</pin_maps>

  126. 					</port_map>

  127. 					<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 

  128. 						<pin_maps>

  129. 							<pin_map port_index="0" component_pin="JB2"/> 

  130. 						</pin_maps>

  131. 					</port_map>

  132. 					<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 

  133. 						<pin_maps>

  134. 							<pin_map port_index="0" component_pin="JB2"/> 

  135. 						</pin_maps>

  136. 					</port_map>

  137. 					<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 

  138. 						<pin_maps>

  139. 							<pin_map port_index="0" component_pin="JB3"/> 

  140. 						</pin_maps>

  141. 					</port_map>

  142. 					<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 

  143. 						<pin_maps>

  144. 							<pin_map port_index="0" component_pin="JB3"/> 

  145. 						</pin_maps>

  146. 					</port_map>

  147. 					<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 

  148. 						<pin_maps>

  149. 							<pin_map port_index="0" component_pin="JB3"/> 

  150. 						</pin_maps>

  151. 					</port_map>

  152. 					<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 

  153. 						<pin_maps>

  154. 							<pin_map port_index="0" component_pin="JB4"/> 

  155. 						</pin_maps>

  156. 					</port_map>

  157. 					<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 

  158. 						<pin_maps>

  159. 							<pin_map port_index="0" component_pin="JB4"/> 

  160. 						</pin_maps>

  161. 					</port_map>

  162. 					<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 

  163. 						<pin_maps>

  164. 							<pin_map port_index="0" component_pin="JB4"/> 

  165. 						</pin_maps>

  166. 					</port_map>

  167. 					<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 

  168. 						<pin_maps>

  169. 							<pin_map port_index="0" component_pin="JB7"/> 

  170. 						</pin_maps>

  171. 					</port_map>

  172. 					<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 

  173. 						<pin_maps>

  174. 							<pin_map port_index="0" component_pin="JB7"/> 

  175. 						</pin_maps>

  176. 					</port_map>

  177. 					<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 

  178. 						<pin_maps>

  179. 							<pin_map port_index="0" component_pin="JB7"/> 

  180. 						</pin_maps>

  181. 					</port_map>

  182. 					<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 

  183. 						<pin_maps>

  184. 							<pin_map port_index="0" component_pin="JB8"/> 

  185. 						</pin_maps>

  186. 					</port_map>

  187. 					<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 

  188. 						<pin_maps>

  189. 							<pin_map port_index="0" component_pin="JB8"/> 

  190. 						</pin_maps>

  191. 					</port_map>

  192. 					<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 

  193. 						<pin_maps>

  194. 							<pin_map port_index="0" component_pin="JB8"/> 

  195. 						</pin_maps>

  196. 					</port_map>

  197. 					<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 

  198. 						<pin_maps>

  199. 							<pin_map port_index="0" component_pin="JB9"/> 

  200. 						</pin_maps>

  201. 					</port_map>

  202. 					<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 

  203. 						<pin_maps>

  204. 							<pin_map port_index="0" component_pin="JB9"/> 

  205. 						</pin_maps>

  206. 					</port_map>

  207. 					<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 

  208. 						<pin_maps>

  209. 							<pin_map port_index="0" component_pin="JB9"/> 

  210. 						</pin_maps>

  211. 					</port_map>

  212. 					<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 

  213. 						<pin_maps>

  214. 							<pin_map port_index="0" component_pin="JB10"/> 

  215. 						</pin_maps>

  216. 					</port_map>

  217. 					<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 

  218. 						<pin_maps>

  219. 							<pin_map port_index="0" component_pin="JB10"/> 

  220. 						</pin_maps>

  221. 					</port_map>

  222. 					<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 

  223. 						<pin_maps>

  224. 							<pin_map port_index="0" component_pin="JB10"/> 

  225. 						</pin_maps>

  226. 					</port_map>

  227. 				</port_maps>

  228. 			</interface>

  229. 			<interface mode="master" name="pmod_jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jc">

  230. 				<port_maps>

  231. 					<port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 

  232. 						<pin_maps>

  233. 							<pin_map port_index="0" component_pin="JC1"/> 

  234. 						</pin_maps>

  235. 					</port_map>

  236. 					<port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 

  237. 						<pin_maps>

  238. 							<pin_map port_index="0" component_pin="JC1"/> 

  239. 						</pin_maps>

  240. 					</port_map>

  241. 					<port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 

  242. 						<pin_maps>

  243. 							<pin_map port_index="0" component_pin="JC1"/> 

  244. 						</pin_maps>

  245. 					</port_map>

  246. 					<port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 

  247. 						<pin_maps>

  248. 							<pin_map port_index="0" component_pin="JC2"/> 

  249. 						</pin_maps>

  250. 					</port_map>

  251. 					<port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 

  252. 						<pin_maps>

  253. 							<pin_map port_index="0" component_pin="JC2"/> 

  254. 						</pin_maps>

  255. 					</port_map>

  256. 					<port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 

  257. 						<pin_maps>

  258. 							<pin_map port_index="0" component_pin="JC2"/> 

  259. 						</pin_maps>

  260. 					</port_map>

  261. 					<port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 

  262. 						<pin_maps>

  263. 							<pin_map port_index="0" component_pin="JC3"/> 

  264. 						</pin_maps>

  265. 					</port_map>

  266. 					<port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 

  267. 						<pin_maps>

  268. 							<pin_map port_index="0" component_pin="JC3"/> 

  269. 						</pin_maps>

  270. 					</port_map>

  271. 					<port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 

  272. 						<pin_maps>

  273. 							<pin_map port_index="0" component_pin="JC3"/> 

  274. 						</pin_maps>

  275. 					</port_map>

  276. 					<port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 

  277. 						<pin_maps>

  278. 							<pin_map port_index="0" component_pin="JC4"/> 

  279. 						</pin_maps>

  280. 					</port_map>

  281. 					<port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 

  282. 						<pin_maps>

  283. 							<pin_map port_index="0" component_pin="JC4"/> 

  284. 						</pin_maps>

  285. 					</port_map>

  286. 					<port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 

  287. 						<pin_maps>

  288. 							<pin_map port_index="0" component_pin="JC4"/> 

  289. 						</pin_maps>

  290. 					</port_map>

  291. 					<port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 

  292. 						<pin_maps>

  293. 							<pin_map port_index="0" component_pin="JC7"/> 

  294. 						</pin_maps>

  295. 					</port_map>

  296. 					<port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 

  297. 						<pin_maps>

  298. 							<pin_map port_index="0" component_pin="JC7"/> 

  299. 						</pin_maps>

  300. 					</port_map>

  301. 					<port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 

  302. 						<pin_maps>

  303. 							<pin_map port_index="0" component_pin="JC7"/> 

  304. 						</pin_maps>

  305. 					</port_map>

  306. 					<port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 

  307. 						<pin_maps>

  308. 							<pin_map port_index="0" component_pin="JC8"/> 

  309. 						</pin_maps>

  310. 					</port_map>

  311. 					<port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 

  312. 						<pin_maps>

  313. 							<pin_map port_index="0" component_pin="JC8"/> 

  314. 						</pin_maps>

  315. 					</port_map>

  316. 					<port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 

  317. 						<pin_maps>

  318. 							<pin_map port_index="0" component_pin="JC8"/> 

  319. 						</pin_maps>

  320. 					</port_map>

  321. 					<port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 

  322. 						<pin_maps>

  323. 							<pin_map port_index="0" component_pin="JC9"/> 

  324. 						</pin_maps>

  325. 					</port_map>

  326. 					<port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 

  327. 						<pin_maps>

  328. 							<pin_map port_index="0" component_pin="JC9"/> 

  329. 						</pin_maps>

  330. 					</port_map>

  331. 					<port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 

  332. 						<pin_maps>

  333. 							<pin_map port_index="0" component_pin="JC9"/> 

  334. 						</pin_maps>

  335. 					</port_map>

  336. 					<port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 

  337. 						<pin_maps>

  338. 							<pin_map port_index="0" component_pin="JC10"/> 

  339. 						</pin_maps>

  340. 					</port_map>

  341. 					<port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 

  342. 						<pin_maps>

  343. 							<pin_map port_index="0" component_pin="JC10"/> 

  344. 						</pin_maps>

  345. 					</port_map>

  346. 					<port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 

  347. 						<pin_maps>

  348. 							<pin_map port_index="0" component_pin="JC10"/> 

  349. 						</pin_maps>

  350. 					</port_map>

  351. 				</port_maps>

  352. 			</interface>

  353. 			<interface mode="master" name="pmod_jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jd">

  354. 				<port_maps>

  355. 					<port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 

  356. 						<pin_maps>

  357. 							<pin_map port_index="0" component_pin="JD1"/> 

  358. 						</pin_maps>

  359. 					</port_map>

  360. 					<port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 

  361. 						<pin_maps>

  362. 							<pin_map port_index="0" component_pin="JD1"/> 

  363. 						</pin_maps>

  364. 					</port_map>

  365. 					<port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 

  366. 						<pin_maps>

  367. 							<pin_map port_index="0" component_pin="JD1"/> 

  368. 						</pin_maps>

  369. 					</port_map>

  370. 					<port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 

  371. 						<pin_maps>

  372. 							<pin_map port_index="0" component_pin="JD2"/> 

  373. 						</pin_maps>

  374. 					</port_map>

  375. 					<port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 

  376. 						<pin_maps>

  377. 							<pin_map port_index="0" component_pin="JD2"/> 

  378. 						</pin_maps>

  379. 					</port_map>

  380. 					<port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 

  381. 						<pin_maps>

  382. 							<pin_map port_index="0" component_pin="JD2"/> 

  383. 						</pin_maps>

  384. 					</port_map>

  385. 					<port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 

  386. 						<pin_maps>

  387. 							<pin_map port_index="0" component_pin="JD3"/> 

  388. 						</pin_maps>

  389. 					</port_map>

  390. 					<port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 

  391. 						<pin_maps>

  392. 							<pin_map port_index="0" component_pin="JD3"/> 

  393. 						</pin_maps>

  394. 					</port_map>

  395. 					<port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 

  396. 						<pin_maps>

  397. 							<pin_map port_index="0" component_pin="JD3"/> 

  398. 						</pin_maps>

  399. 					</port_map>

  400. 					<port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 

  401. 						<pin_maps>

  402. 							<pin_map port_index="0" component_pin="JD4"/> 

  403. 						</pin_maps>

  404. 					</port_map>

  405. 					<port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 

  406. 						<pin_maps>

  407. 							<pin_map port_index="0" component_pin="JD4"/> 

  408. 						</pin_maps>

  409. 					</port_map>

  410. 					<port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 

  411. 						<pin_maps>

  412. 							<pin_map port_index="0" component_pin="JD4"/> 

  413. 						</pin_maps>

  414. 					</port_map>

  415. 					<port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 

  416. 						<pin_maps>

  417. 							<pin_map port_index="0" component_pin="JD7"/> 

  418. 						</pin_maps>

  419. 					</port_map>

  420. 					<port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 

  421. 						<pin_maps>

  422. 							<pin_map port_index="0" component_pin="JD7"/> 

  423. 						</pin_maps>

  424. 					</port_map>

  425. 					<port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 

  426. 						<pin_maps>

  427. 							<pin_map port_index="0" component_pin="JD7"/> 

  428. 						</pin_maps>

  429. 					</port_map>

  430. 					<port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 

  431. 						<pin_maps>

  432. 							<pin_map port_index="0" component_pin="JD8"/> 

  433. 						</pin_maps>

  434. 					</port_map>

  435. 					<port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 

  436. 						<pin_maps>

  437. 							<pin_map port_index="0" component_pin="JD8"/> 

  438. 						</pin_maps>

  439. 					</port_map>

  440. 					<port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 

  441. 						<pin_maps>

  442. 							<pin_map port_index="0" component_pin="JD8"/> 

  443. 						</pin_maps>

  444. 					</port_map>

  445. 					<port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 

  446. 						<pin_maps>

  447. 							<pin_map port_index="0" component_pin="JD9"/> 

  448. 						</pin_maps>

  449. 					</port_map>

  450. 					<port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 

  451. 						<pin_maps>

  452. 							<pin_map port_index="0" component_pin="JD9"/> 

  453. 						</pin_maps>

  454. 					</port_map>

  455. 					<port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 

  456. 						<pin_maps>

  457. 							<pin_map port_index="0" component_pin="JD9"/> 

  458. 						</pin_maps>

  459. 					</port_map>

  460. 					<port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 

  461. 						<pin_maps>

  462. 							<pin_map port_index="0" component_pin="JD10"/> 

  463. 						</pin_maps>

  464. 					</port_map>

  465. 					<port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 

  466. 						<pin_maps>

  467. 							<pin_map port_index="0" component_pin="JD10"/> 

  468. 						</pin_maps>

  469. 					</port_map>

  470. 					<port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 

  471. 						<pin_maps>

  472. 							<pin_map port_index="0" component_pin="JD10"/> 

  473. 						</pin_maps>

  474. 					</port_map>

  475. 				</port_maps>

  476. 			</interface>

  477. 		</interfaces>

  478. 	</component>

  479. 	

  480. 	<!-- Descriptions of components that will appear in the IPI Board tab -->

  481. 	<component name="ps8_fixedio" display_name="PS8 Fixed IO" type="chip" sub_type="fixed_io" major_group=""/>

  482. 	<component name="btn_5bits" display_name="5 Buttons" type="chip" sub_type="push_button" major_group="GPIO">

  483. 		<description>5 Buttons (Ordered "UCDLR")</description>

  484. 	</component>

  485. 	<component name="switch_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">

  486. 		<description>4 Switches</description>

  487. 	</component>

  488. 	<component name="rgbled_3bits" display_name="1 RGB LED" type="chip" sub_type="led" major_group="GPIO">

  489. 		<description>1 RGB LED (Ordered "RGB")</description>

  490. 	</component>

  491. 	<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">

  492. 		<description>4 LEDs</description>

  493. 	</component>

  494. 	<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">

  495. 		<description>Pmod Connector JB</description>

  496. 	</component>

  497. 	<component name="pmod_jc" display_name="Pmod Connector JC" type="chip" sub_type="chip" major_group="Pmod">

  498. 		<description>Pmod Connector JC</description>

  499. 	</component>

  500. 	<component name="pmod_jd" display_name="Pmod Connector JD" type="chip" sub_type="chip" major_group="Pmod">

  501. 		<description>Pmod Connector JD</description>

  502. 	</component>

  503. </components>

  504. 

  505. <jtag_chains>

  506. 	<jtag_chain name="chain1">

  507. 		<position name="0" component="part0"/>

  508. 	</jtag_chain>

  509. </jtag_chains>

  510. 

  511. <connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->

  512. 	<connection name="part0_btn_5bits" component1="part0" component2="btn_5bits">

  513. 		<connection_map name="part0_btn_5bits_map"    c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>

  514. 	</connection>

  515. 	<connection name="part0_switch_4bits" component1="part0" component2="switch_4bits">

  516. 		<connection_map name="part0_switch_4bits_map" c1_st_index="5" c1_end_index="8" c2_st_index="0" c2_end_index="3"/>

  517. 	</connection>

  518. 	<connection name="rgbled_3bits" component1="part0" component2="rgbled_3bits">

  519. 		<connection_map name="part0_rgbled_3bits_map"    c1_st_index="9" c1_end_index="11" c2_st_index="0" c2_end_index="2"/>

  520. 	</connection>

  521. 	<connection name="part0_led_4bits" component1="part0" component2="led_4bits">

  522. 		<connection_map name="part0_led_4bits_map" c1_st_index="12" c1_end_index="15" c2_st_index="0" c2_end_index="3"/>

  523. 	</connection>

  524. 	<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">

  525. 		<connection_map name="part0_pmod_jb_map" c1_st_index="16" c1_end_index="23" c2_st_index="0" c2_end_index="7"/>

  526. 	</connection>

  527. 	<connection name="part0_pmod_jc" component1="part0" component2="pmod_jc">

  528. 		<connection_map name="part0_pmod_jc_map" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>

  529. 	</connection>

  530. 	<connection name="part0_pmod_jd" component1="part0" component2="pmod_jd">

  531. 		<connection_map name="part0_pmod_jd_map" c1_st_index="32" c1_end_index="39" c2_st_index="0" c2_end_index="7"/>

  532. 	</connection>

  533. </connections>

  534. 

  535. </board>