stammfe87185
/
FPGA_Projekt
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
FPGA Projektarbeit
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
2 Commits
1 Branch
Tree: d46f525db8
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'd46f525db8'
${ noResults }
FPGA_Projekt/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys-zu-5ev/C.0/changelog.txt

changelog.txt 199B
Raw Blame History

12 
  1. 1.1 Fixed PSU__DDRC__DDR4_ADDR_MAPPING appearing twice and with conflicting values that was causing a silent FSBL failure in the boot process.

  2. 1.0. Genesys ZU-ZU5EV initial board support for rev C.