FPGA_Projekt/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/genesys2/H/board.xml

<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
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<board schema_version="2.0" vendor="digilentinc.com" name="genesys2" display_name="Genesys2" url="https://reference.digilentinc.com/reference/programmable-logic/genesys-2/start" preset_file="preset.xml" >
<compatible_board_revisions>
  <revision id="0">H</revision>
</compatible_board_revisions>
<file_version>1.1</file_version>
<description>Genesys2</description>
<components>
  <component name="part0" display_name="Genesys2" type="fpga" part_name="xc7k325tffg900-2" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/genesys-2/start">
    <interfaces>
      <interface mode="master" name="audio_codec_iic" type="xilinx.com:interface:iic_rtl:1.0" of_component="audio_codec_iic">
        <description>I2C bus to communicate with the Audio Codec</description>
		<preferred_ips>
            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
        </preferred_ips>
		<port_maps>
          <port_map logical_port="SDA_I" physical_port="aud_sda_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="aud_sda_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SDA_O" physical_port="aud_sda_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="aud_sda_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SDA_T" physical_port="aud_sda_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="aud_sda_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_I" physical_port="aud_scl_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="aud_scl_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_O" physical_port="aud_scl_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="aud_scl_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_T" physical_port="aud_scl_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="aud_scl_i"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
      <description>DDR3 board interface, it can use MIG IP for connection.</description>
	  <preferred_ips>
			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
	  </preferred_ips>
	  </interface>
      <interface mode="master" name="dip_switches_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_8bits" preset_proc="dip_switches_8bits_preset">
        <description>8 DIP Switches</description>
		<preferred_ips>
			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
		</preferred_ips>
		<port_maps>
          <port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="7" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="dip_switches_8bits_tri_i_0"/> 
              <pin_map port_index="1" component_pin="dip_switches_8bits_tri_i_1"/> 
              <pin_map port_index="2" component_pin="dip_switches_8bits_tri_i_2"/> 
              <pin_map port_index="3" component_pin="dip_switches_8bits_tri_i_3"/> 
              <pin_map port_index="4" component_pin="dip_switches_8bits_tri_i_4"/> 
              <pin_map port_index="5" component_pin="dip_switches_8bits_tri_i_5"/> 
              <pin_map port_index="6" component_pin="dip_switches_8bits_tri_i_6"/> 
              <pin_map port_index="7" component_pin="dip_switches_8bits_tri_i_7"/> 
            </pin_maps>
          </port_map>
		  
        </port_maps>
      </interface>
      <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
        <preferred_ips>
			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
		</preferred_ips>
		<port_maps>
          <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
            <pin_maps>
              <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/> 
			  <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/> 
			  <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
            <pin_maps>
              <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/> 
			  <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/> 
			  <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
	   <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
        <description>HDMI DDC</description>
		<preferred_ips>
			<preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
		</preferred_ips>
		<port_maps>
          <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
        <port_maps>
          <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
            </pin_maps>
          </port_map>
		  <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
            </pin_maps>
          </port_map>
		  <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_rx_hpd"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
        <description>HDMI Out</description>
		<preferred_ips>
			<preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
		</preferred_ips>
		<port_maps>
          <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
            <pin_maps>
              <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/> 
			  <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/> 
			  <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
            <pin_maps>
              <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/> 
			  <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/> 
			  <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
        <port_maps>
          <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
            </pin_maps>
          </port_map>
		  <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
            </pin_maps>
          </port_map>
		  <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="hdmi_tx_hpd"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
        <description>Secondary interface to communicate with ethernet phy. </description>
		<port_maps>
          <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_mdio_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_mdc"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
        <description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
		<port_maps>
          <port_map logical_port="TD" physical_port="eth_rgmii_td" dir="out" left="3" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_rgmii_td_0"/> 
              <pin_map port_index="1" component_pin="eth_rgmii_td_1"/> 
              <pin_map port_index="2" component_pin="eth_rgmii_td_2"/> 
              <pin_map port_index="3" component_pin="eth_rgmii_td_3"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="RD" physical_port="eth_rgmii_rd" dir="in" left="3" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_rgmii_rd_0"/> 
              <pin_map port_index="1" component_pin="eth_rgmii_rd_1"/> 
              <pin_map port_index="2" component_pin="eth_rgmii_rd_2"/> 
              <pin_map port_index="3" component_pin="eth_rgmii_rd_3"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="RX_CTL" physical_port="eth_rgmii_rx_ctl" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_rgmii_rx_ctl"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="TX_CTL" physical_port="eth_rgmii_tx_ctl" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_rgmii_tx_ctl"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="TXC" physical_port="eth_rgmii_txc" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_rgmii_txc"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="RXC" physical_port="eth_rgmii_rxc" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="eth_rgmii_rxc"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
	  <interface mode="master" name="phy_reset_out" type="xilinx.com:signal:reset_rtl:1.0" of_component="phy_onboard">
          <description>Onboard Reset Button</description>
		  <preferred_ips>
            <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernet" order="0"/>
          </preferred_ips>
          <port_maps>
            <port_map logical_port="RESET" physical_port="phy_reset_n" dir="out">
              <pin_maps>
                <pin_map port_index="0" component_pin="phy_reset_n"/>
              </pin_maps>
            </port_map>
          </port_maps>
        </interface>
      <interface mode="master" name="iic_bus" type="xilinx.com:interface:iic_rtl:1.0" of_component="iic_bus">
        <description>System I2C</description>
		<port_maps>
          <port_map logical_port="SDA_I" physical_port="sda_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="sda_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SDA_O" physical_port="sda_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sda_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SDA_T" physical_port="sda_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sda_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_I" physical_port="scl_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="scl_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_O" physical_port="scl_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="scl_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCL_T" physical_port="scl_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="scl_i"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="led_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_8bits" preset_proc="led_8bits_preset">
        <description>8 LEDs</description>
		<preferred_ips>
			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
		</preferred_ips>
		<port_maps>
          <port_map logical_port="TRI_O" physical_port="led_8bits_tri_o" dir="out" left="7" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/> 
              <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/> 
              <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/> 
              <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/> 
              <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/> 
              <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/> 
              <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/> 
              <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
        <description>5 Push Buttons</description>
		<preferred_ips>
			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
		</preferred_ips>
		<port_maps>
          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
        <description>Quad SPI Flash</description>
		<preferred_ips>
			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
		</preferred_ips>
		<port_maps>
          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
        <description>Onboard Reset Button</description>
		<preferred_ips>
            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
          </preferred_ips>
		<port_maps>
          <port_map logical_port="RESET" physical_port="reset" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="reset"/> 
            </pin_maps>
          </port_map>
        </port_maps>
        <parameters>
          <parameter name="rst_polarity" value="0" />
       </parameters>
      </interface>
      <interface mode="master" name="sd_spi_mode" type="xilinx.com:interface:spi_rtl:1.0" of_component="sd_spi_mode" preset_proc="spi_preset">
        <description>SD Card reader in SPI Mode</description>
		<preferred_ips>
			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
		</preferred_ips>
		<port_maps>
          <port_map logical_port="IO0_I" physical_port="sd_miso_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_miso_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO0_O" physical_port="sd_miso_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_miso_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO0_T" physical_port="sd_miso_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_miso_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO1_I" physical_port="sd_mosi_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_mosi_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO1_O" physical_port="sd_mosi_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_mosi_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="IO1_T" physical_port="sd_mosi_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_mosi_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCK_I" physical_port="sd_sclk_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_sclk_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCK_O" physical_port="sd_sclk_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_sclk_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SCK_T" physical_port="sd_sclk_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_sclk_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SS_I" physical_port="sd_ss_i" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_ss_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SS_O" physical_port="sd_ss_o" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_ss_i"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="SS_T" physical_port="sd_ss_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="sd_ss_i"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
      <!--<interface mode="master" name="usb_otg_master" type="xilinx.com:interface:ulpi_rtl:1.0" of_component="usb_otg_master">
        <port_maps>
          <port_map logical_port="CLK" physical_port="otg_clk_m" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="otg_clk_m"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="RST" physical_port="otg_rst_m" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="otg_rst_m"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="DIR" physical_port="otg_dir_m" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="otg_dir_m"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="NEXT" physical_port="otg_next_m" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="otg_next_m"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="STOP" physical_port="otg_stop_m" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="otg_stop_m"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="DATA_I" physical_port="otg_data_i" dir="in" left="7" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="otg_data_i_0"/> 
              <pin_map port_index="1" component_pin="otg_data_i_1"/> 
              <pin_map port_index="2" component_pin="otg_data_i_2"/> 
              <pin_map port_index="3" component_pin="otg_data_i_3"/> 
              <pin_map port_index="4" component_pin="otg_data_i_4"/> 
              <pin_map port_index="5" component_pin="otg_data_i_5"/> 
              <pin_map port_index="6" component_pin="otg_data_i_6"/> 
              <pin_map port_index="7" component_pin="otg_data_i_7"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="DATA_O" physical_port="otg_data_o" dir="out" left="7" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="otg_data_i_0"/> 
              <pin_map port_index="1" component_pin="otg_data_i_1"/> 
              <pin_map port_index="2" component_pin="otg_data_i_2"/> 
              <pin_map port_index="3" component_pin="otg_data_i_3"/> 
              <pin_map port_index="4" component_pin="otg_data_i_4"/> 
              <pin_map port_index="5" component_pin="otg_data_i_5"/> 
              <pin_map port_index="6" component_pin="otg_data_i_6"/> 
              <pin_map port_index="7" component_pin="otg_data_i_7"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="DATA_T" physical_port="otg_data_t" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="otg_data_i_0"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>-->
	  
	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
        <port_maps>
          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JC10"/> 
			</pin_maps>
		  </port_map>
        </port_maps>
      </interface>
	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
        <port_maps>
          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JD10"/> 
			</pin_maps>
		  </port_map>
        </port_maps>
      </interface>
	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
        <port_maps>
          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JB10"/> 
			</pin_maps>
		  </port_map>
        </port_maps>
      </interface>
	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
        <port_maps>
          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="JA10"/> 
			</pin_maps>
		  </port_map>
        </port_maps>
      </interface>
	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
	  <preferred_ips>
			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
		</preferred_ips>
        <port_maps>
          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD1"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD3"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="SD9"/> 
			</pin_maps>
		  </port_map>
        </port_maps>
      </interface>	  
	   <interface mode="master" name="oled" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="oled" preset_proc="oled_preset">
       <preferred_ips>
			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
		</preferred_ips>
		<port_maps>
		  <port_map logical_port="PIN2_I" physical_port="OLED2" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_O" physical_port="OLED2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN2_T" physical_port="OLED2" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED2"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_I" physical_port="OLED4" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_O" physical_port="OLED4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN4_T" physical_port="OLED4" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED4"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_I" physical_port="OLED7" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_O" physical_port="OLED7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN7_T" physical_port="OLED7" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED7"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_I" physical_port="OLED8" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_O" physical_port="OLED8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN8_T" physical_port="OLED8" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED8"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_I" physical_port="OLED9" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_O" physical_port="OLED9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN9_T" physical_port="OLED9" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED9"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_I" physical_port="OLED10" dir="in"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_O" physical_port="OLED10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED10"/> 
			</pin_maps>
		  </port_map>
		  <port_map logical_port="PIN10_T" physical_port="OLED10" dir="out"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="OLED10"/> 
			</pin_maps>
		  </port_map>
        </port_maps>
      </interface>
	  
      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
        <port_maps>
          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
            <pin_maps>
              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
            </pin_maps>
          </port_map>
          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
            </pin_maps>
          </port_map>
        </port_maps>
      </interface>
	  <interface mode="slave" name="sys_diff_clock" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sys_diff_clock" preset_proc="sys_diff_clock_preset">
          <parameters>
            <parameter name="frequency" value="200000000"/>
          </parameters>
          <preferred_ips>
            <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
          </preferred_ips>
          <port_maps>
            <port_map logical_port="CLK_P" physical_port="clk_p" dir="in">
              <pin_maps>
                <pin_map port_index="0" component_pin="clk_p"/>
              </pin_maps>
            </port_map>
            <port_map logical_port="CLK_N" physical_port="clk_n" dir="in">
              <pin_maps>
                <pin_map port_index="0" component_pin="clk_n"/>
              </pin_maps>
            </port_map>
          </port_maps>
        </interface>
    </interfaces>
  </component>
  <component name="audio_codec_iic" display_name="Audio Codec I2C" type="chip" sub_type="mux" major_group="Audio">
	<description>I2C bus to communicate with the Audio Codec</description>
  </component>
  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
	<description>1 GB 1800Mt/s on-board DDR3 </description>
	<parameters>
        <parameter name="ddr_type" value="ddr3"/>
        <parameter name="size" value="1GB"/>
	</parameters>
  </component>
  <component name="dip_switches_8bits" display_name="8 Switches" type="chip" sub_type="switch" major_group="GPIO">
	<description>DIP Switches 7 to 0</description>
  </component>
  <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
	<description>HDMI input (Requires Digilent's TMDS interface)</description>
	<component_modes>
        <component_mode name="HDMI_IN" display_name="HDMI In">
		  <interfaces>
            <interface name="hdmi_in" order="0"/>
            <interface name="hdmi_in_ddc" order="1"/>
          </interfaces>
		</component_mode>
	 </component_modes>
  </component>
  <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
	<description>HDMI in HPD (Connected to LD8)</description>
  </component>
  <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
	<description>HDMI Out (Requires Digilent's TMDS interface)</description>
  </component>
  <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
	<description>HDMI out HPD</description>
  </component>
  <component name="phy_onboard" display_name="Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
	<description>PHY Ethernet on the board</description>
	 <component_modes>
        <component_mode name="rgmii" display_name="RGMII mode">
		  <interfaces>
            <interface name="eth_rgmii" order="0"/>
            <interface name="eth_mdio_mdc" order="1"/>
			<interface name="phy_reset_out" order="2" optional="true"/>
          </interfaces>
		</component_mode>
	 </component_modes>
  </component>
  <component name="iic_bus" display_name="I2C" type="chip" sub_type="mux" major_group="I2C">
	<description>I2C bus</description>
  </component>
  <component name="led_8bits" display_name="8 LEDs" type="chip" sub_type="led" major_group="GPIO">
	<description>LEDs 7 to 0</description>
  </component>
  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
  </component>
  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
	<description>QSPI Flash</description>
  </component>
  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
	<description>System Reset Button</description>
  </component>
  <component name="sd_spi_mode" display_name="SD Card (SPI)" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
	<description>SD Card in SPI Mode</description>
  </component>
  <!--<component name="usb_otg_master" display_name="USB OTG" type="chip" sub_type="uart" major_group="UART">
	<description>USB OTG (Needs work)</description>
	<preferred_ips>
		<preferred_ip vendor="xilinx.com" library="ip" name="axi_usb2_device" order="0"/>
	</preferred_ips>
  </component>-->
  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
	<description>Pmod Connector JA</description>
  </component>
  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
	<description>Pmod Connector JB</description>
  </component>
  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
	<description>Pmod Connector JC</description>
  </component>
  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
	<description>Pmod Connector JD</description>
  </component>
  <component name="sd" display_name="Micro SD Card" type="chip" sub_type="chip" major_group="External Memory">
	<description>Micro SD Card Reader</description>
	<component_modes>
	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
	  <interfaces>
		<interface name="sd"/>
	  </interfaces>
	  <preferred_ips>
			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
	  </preferred_ips>
	</component_mode>
	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
	  <interfaces>
		<interface name="sd"/>
	  </interfaces>
	  <preferred_ips>
		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
	  </preferred_ips>
	</component_mode>
  </component_modes>
  </component>
  <component name="oled" display_name="Onboard OLED" type="chip" sub_type="chip" major_group="GPIO">
  <component_modes>
	<component_mode name="apmodoled" display_name="Digilent PmodOLED IP">
	  <interfaces>
		<interface name="oled"/>
	  </interfaces>
	  <preferred_ips>
			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
	  </preferred_ips>
	</component_mode>
	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
	  <interfaces>
		<interface name="oled"/>
	  </interfaces>
	  <preferred_ips>
		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
	  </preferred_ips>
	</component_mode>
  </component_modes>
  
	<description>Onboard OLED (DISP1)</description>
  </component>
  
  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
  </component>
  <component name="sys_diff_clock" display_name="System differential clock" type="chip" sub_type="system_clock" major_group="Clock Sources" >
      <description>3.3V LVDS differential 200 MHz oscillator used as system differential clock on the board</description>
      <parameters>
        <parameter name="frequency" value="200000000"/>
      </parameters>
    </component>
</components>
<jtag_chains>
  <jtag_chain name="chain1">
    <position name="0" component="part0"/>
  </jtag_chain>
</jtag_chains>
<connections>
  <connection name="part0_audio_codec_iic" component1="part0" component2="audio_codec_iic">
    <connection_map name="part0_audio_codec_iic_1" c1_st_index="0" c1_end_index="1" c2_st_index="0" c2_end_index="1"/>
  </connection>
  <connection name="part0_dip_switches_8bits" component1="part0" component2="dip_switches_8bits">
    <connection_map name="part0_dip_switches_8bits_1" c1_st_index="4" c1_end_index="11" c2_st_index="0" c2_end_index="7"/>
  </connection>
  <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
    <connection_map name="part0_hdmi_in_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
	<connection_map name="part0_hdmi_in_ddc" c1_st_index="89" c1_end_index="90" c2_st_index="0" c2_end_index="1"/>
  </connection>
  <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
    <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
  </connection>
  <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
    <connection_map name="part0_hdmi_out_1" c1_st_index="81" c1_end_index="88" c2_st_index="0" c2_end_index="7"/>
  </connection>
  <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
    <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="21" c1_end_index="21" c2_st_index="0" c2_end_index="0"/>
  </connection>
  <connection name="part0_dspi" component1="part0" component2="dspi">
    <connection_map name="part0_dspi_1" c1_st_index="44" c1_end_index="77" c2_st_index="0" c2_end_index="33"/>
  </connection>
  <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
	<connection_map name="part0_eth_rgmii_1" c1_st_index="24" c1_end_index="35" c2_st_index="0" c2_end_index="11"/>
    <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="22" c1_end_index="23" c2_st_index="0" c2_end_index="1"/>
	<connection_map name="part0_eth_phy_reset_n" c1_st_index="80" c1_end_index="80" c2_st_index="0" c2_end_index="0"/>
  </connection>
  <connection name="part0_iic_bus" component1="part0" component2="iic_bus">
    <connection_map name="part0_iic_bus_1" c1_st_index="71" c1_end_index="72" c2_st_index="0" c2_end_index="1"/>
  </connection>
  <connection name="part0_led_8bits" component1="part0" component2="led_8bits">
    <connection_map name="part0_led_8bits_1" c1_st_index="36" c1_end_index="43" c2_st_index="0" c2_end_index="7"/>
  </connection>
  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
  </connection>
  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
    <connection_map name="part0_qspi_flash_1" c1_st_index="64" c1_end_index="68" c2_st_index="0" c2_end_index="4"/>
  </connection>
  <connection name="part0_reset" component1="part0" component2="reset">
    <connection_map name="part0_reset_1" c1_st_index="69" c1_end_index="69" c2_st_index="0" c2_end_index="0"/>
  </connection>
  <connection name="part0_sd_spi_mode" component1="part0" component2="sd_spi_mode">
    <connection_map name="part0_sd_spi_mode_1" c1_st_index="73" c1_end_index="76" c2_st_index="0" c2_end_index="3"/>
  </connection>
  <!--<connection name="part0_usb_otg_master" component1="part0" component2="usb_otg_master">
    <connection_map name="part0_usb_otg_master_1" c1_st_index="46" c1_end_index="58" c2_st_index="0" c2_end_index="12"/>
  </connection>-->
  
  <connection name="part0_jc" component1="part0" component2="jc">
    <connection_map name="part0_jc_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
  </connection>
  <connection name="part0_jd" component1="part0" component2="jd">
    <connection_map name="part0_jd_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
  </connection>
  <connection name="part0_jb" component1="part0" component2="jb">
    <connection_map name="part0_jb_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
  </connection>
  <connection name="part0_ja" component1="part0" component2="ja">
    <connection_map name="part0_ja_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
  </connection>
  <connection name="part0_sd" component1="part0" component2="sd">
    <connection_map name="part0_ja_1" c1_st_index="129" c1_end_index="135" c2_st_index="0" c2_end_index="6"/>
  </connection>
  <connection name="part0_oled" component1="part0" component2="oled">
    <connection_map name="part0_oled_1" c1_st_index="123" c1_end_index="128" c2_st_index="0" c2_end_index="5"/>
  </connection>
  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
    <connection_map name="part0_usb_uart_1" c1_st_index="78" c1_end_index="79" c2_st_index="0" c2_end_index="1"/>
  </connection>
  <connection name="part0_sysclk" component1="part0" component2="sys_diff_clock">
    <connection_map name="part0_sys_clk_1" c1_st_index="2" c1_end_index="3" c2_st_index="0" c2_end_index="1"/>
  </connection>
</connections>
</board>