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FPGA_Projekt/Bibliotheken/vivado-boards-master/vivado-boards-master/new/board_files/nexys-a7-100t/D.0/1.2/board.xml

board.xml 55KB
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  1. <?xml version="1.0" encoding="UTF-8" standalone="no"?> 

  2. <!--

  3. MIT License

  4. 

  5. Copyright (c) 2021 Digilent, Inc.

  6. 

  7. Permission is hereby granted, free of charge, to any person obtaining a copy

  8. of this software and associated documentation files (the "Software"), to deal

  9. in the Software without restriction, including without limitation the rights

  10. to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

  11. copies of the Software, and to permit persons to whom the Software is

  12. furnished to do so, subject to the following conditions:

  13. 

  14. The above copyright notice and this permission notice shall be included in all

  15. copies or substantial portions of the Software.

  16. 

  17. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

  18. IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

  19. FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

  20. AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

  21. LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

  22. OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  23. SOFTWARE.

  24. -->

  25. <board schema_version="2.0" vendor="digilentinc.com" name="nexys-a7-100t" display_name="Nexys A7-100T" url="https://digilent.com/reference/programmable-logic/nexys-a7/start" preset_file="preset.xml" >

  26. <compatible_board_revisions>

  27.   <revision id="0">D.0</revision>

  28. </compatible_board_revisions>

  29. <file_version>1.2</file_version>

  30. <description>Nexys A7-100T</description>

  31. <components>

  32.   <component name="part0" display_name="Nexys A7-100T" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/nexys-a7/start">

  33.     <interfaces>

  34.       <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">

  35.         <description>Accelerometer control through SPI</description>

  36. 		<preferred_ips>

  37. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>

  38. 		</preferred_ips>

  39. 		<port_maps>

  40.           <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">

  41.             <pin_maps>

  42.               <pin_map port_index="0" component_pin="acl_miso_i"/> 

  43.             </pin_maps>

  44.           </port_map>

  45.           <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">

  46.             <pin_maps>

  47.               <pin_map port_index="0" component_pin="acl_miso_i"/> 

  48.             </pin_maps>

  49.           </port_map>

  50.           <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">

  51.             <pin_maps>

  52.               <pin_map port_index="0" component_pin="acl_miso_i"/> 

  53.             </pin_maps>

  54.           </port_map>

  55.           <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">

  56.             <pin_maps>

  57.               <pin_map port_index="0" component_pin="acl_mosi_i"/> 

  58.             </pin_maps>

  59.           </port_map>

  60.           <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">

  61.             <pin_maps>

  62.               <pin_map port_index="0" component_pin="acl_mosi_i"/> 

  63.             </pin_maps>

  64.           </port_map>

  65.           <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">

  66.             <pin_maps>

  67.               <pin_map port_index="0" component_pin="acl_mosi_i"/> 

  68.             </pin_maps>

  69.           </port_map>

  70.           <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">

  71.             <pin_maps>

  72.               <pin_map port_index="0" component_pin="acl_sclk_i"/> 

  73.             </pin_maps>

  74.           </port_map>

  75.           <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">

  76.             <pin_maps>

  77.               <pin_map port_index="0" component_pin="acl_sclk_i"/> 

  78.             </pin_maps>

  79.           </port_map>

  80.           <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">

  81.             <pin_maps>

  82.               <pin_map port_index="0" component_pin="acl_sclk_i"/> 

  83.             </pin_maps>

  84.           </port_map>

  85.           <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">

  86.             <pin_maps>

  87.               <pin_map port_index="0" component_pin="acl_ss_i"/> 

  88.             </pin_maps>

  89.           </port_map>

  90.           <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">

  91.             <pin_maps>

  92.               <pin_map port_index="0" component_pin="acl_ss_i"/> 

  93.             </pin_maps>

  94.           </port_map>

  95.           <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">

  96.             <pin_maps>

  97.               <pin_map port_index="0" component_pin="acl_ss_i"/> 

  98.             </pin_maps>

  99.           </port_map>

  100.         </port_maps>

  101.       </interface>

  102.       <interface mode="master" name="ddr2_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr2_sdram" preset_proc="ddr2_sdram_preset"> 

  103.       <description>DDR2 board interface, it can use MIG IP for connection.</description>

  104. 	  <preferred_ips>

  105. 			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>

  106. 	  </preferred_ips>

  107. 	  </interface>

  108.       <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">

  109.         <description>16 DIP Switches</description>

  110. 		<preferred_ips>

  111. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  112. 		</preferred_ips>

  113. 		<port_maps>

  114.           <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 

  115.             <pin_maps>

  116.               <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 

  117.               <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 

  118.               <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 

  119.               <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 

  120.               <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 

  121.               <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 

  122.               <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 

  123.               <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 

  124.               <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 

  125.               <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 

  126.               <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 

  127.               <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 

  128.               <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 

  129.               <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 

  130.               <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 

  131.               <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 

  132.             </pin_maps>

  133.           </port_map>

  134.         </port_maps>

  135.       </interface>

  136.       <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">

  137.         <description>Dual 7 Seg LED Segments</description>

  138. 		<preferred_ips>

  139. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  140. 		</preferred_ips>

  141. 		<port_maps>

  142.           <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 

  143.             <pin_maps>

  144.               <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/> 

  145.               <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/> 

  146.               <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/> 

  147.               <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/> 

  148.               <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/> 

  149.               <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/> 

  150.               <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/> 

  151.               <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/> 

  152.             </pin_maps>

  153.           </port_map>

  154.         </port_maps>

  155.       </interface>

  156.       <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">

  157.         <description>16 LEDs</description>

  158. 		<preferred_ips>

  159. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  160. 		</preferred_ips>

  161. 		<port_maps>

  162.           <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 

  163.             <pin_maps>

  164.               <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 

  165.               <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 

  166.               <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 

  167.               <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 

  168.               <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 

  169.               <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 

  170.               <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 

  171.               <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 

  172.               <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 

  173.               <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 

  174.               <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 

  175.               <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 

  176.               <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 

  177.               <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 

  178.               <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 

  179.               <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 

  180.             </pin_maps>

  181.           </port_map>

  182.         </port_maps>

  183.       </interface>

  184.       <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">

  185.         <description>5 Push Buttons</description>

  186. 		<preferred_ips>

  187. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  188. 		</preferred_ips>

  189. 		<port_maps>

  190.           <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 

  191.             <pin_maps>

  192.               <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 

  193.               <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 

  194.               <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 

  195.               <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 

  196.               <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 

  197.             </pin_maps>

  198.           </port_map>

  199.         </port_maps>

  200.       </interface>

  201.       <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">

  202.         <description>Quad SPI Flash</description>

  203. 		<preferred_ips>

  204. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>

  205. 		</preferred_ips>

  206. 		<port_maps>

  207.           <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">

  208.             <pin_maps>

  209.               <pin_map port_index="0" component_pin="qspi_db0_i"/> 

  210.             </pin_maps>

  211.           </port_map>

  212.           <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">

  213.             <pin_maps>

  214.               <pin_map port_index="0" component_pin="qspi_db0_i"/> 

  215.             </pin_maps>

  216.           </port_map>

  217.           <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">

  218.             <pin_maps>

  219.               <pin_map port_index="0" component_pin="qspi_db0_i"/> 

  220.             </pin_maps>

  221.           </port_map>

  222.           <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">

  223.             <pin_maps>

  224.               <pin_map port_index="0" component_pin="qspi_db1_i"/> 

  225.             </pin_maps>

  226.           </port_map>

  227.           <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">

  228.             <pin_maps>

  229.               <pin_map port_index="0" component_pin="qspi_db1_i"/> 

  230.             </pin_maps>

  231.           </port_map>

  232.           <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">

  233.             <pin_maps>

  234.               <pin_map port_index="0" component_pin="qspi_db1_i"/> 

  235.             </pin_maps>

  236.           </port_map>

  237.           <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">

  238.             <pin_maps>

  239.               <pin_map port_index="0" component_pin="qspi_db2_i"/> 

  240.             </pin_maps>

  241.           </port_map>

  242.           <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">

  243.             <pin_maps>

  244.               <pin_map port_index="0" component_pin="qspi_db2_i"/> 

  245.             </pin_maps>

  246.           </port_map>

  247.           <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">

  248.             <pin_maps>

  249.               <pin_map port_index="0" component_pin="qspi_db2_i"/> 

  250.             </pin_maps>

  251.           </port_map>

  252.           <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">

  253.             <pin_maps>

  254.               <pin_map port_index="0" component_pin="qspi_db3_i"/> 

  255.             </pin_maps>

  256.           </port_map>

  257.           <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">

  258.             <pin_maps>

  259.               <pin_map port_index="0" component_pin="qspi_db3_i"/> 

  260.             </pin_maps>

  261.           </port_map>

  262.           <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">

  263.             <pin_maps>

  264.               <pin_map port_index="0" component_pin="qspi_db3_i"/> 

  265.             </pin_maps>

  266.           </port_map>

  267.           <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">

  268.             <pin_maps>

  269.               <pin_map port_index="0" component_pin="qspi_csn_i"/> 

  270.             </pin_maps>

  271.           </port_map>

  272.           <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">

  273.             <pin_maps>

  274.               <pin_map port_index="0" component_pin="qspi_csn_i"/> 

  275.             </pin_maps>

  276.           </port_map>

  277.           <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">

  278.             <pin_maps>

  279.               <pin_map port_index="0" component_pin="qspi_csn_i"/> 

  280.             </pin_maps>

  281.           </port_map>

  282.         </port_maps>

  283.       </interface>

  284.       <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">

  285.         <port_maps>

  286.           <port_map logical_port="RST" physical_port="reset" dir="in">

  287.             <pin_maps>

  288.               <pin_map port_index="0" component_pin="reset"/> 

  289.             </pin_maps>

  290.           </port_map>

  291.         </port_maps>

  292.         <parameters>

  293.           <parameter name="rst_polarity" value="0" />

  294.        </parameters>

  295.       </interface>

  296.       <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">

  297.         <description>2 RGB LEDs</description>

  298. 		<preferred_ips>

  299. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  300. 		</preferred_ips>

  301. 		<port_maps>

  302.           <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 

  303.             <pin_maps>

  304.               <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 

  305.               <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 

  306.               <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 

  307.               <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 

  308.               <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 

  309.               <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 

  310.             </pin_maps>

  311.           </port_map>

  312.         </port_maps>

  313.       </interface>

  314.       <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">

  315.         <description>7 Segment Display Anodes</description>

  316. 		<preferred_ips>

  317. 			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>

  318. 		</preferred_ips>

  319. 		<port_maps>

  320.           <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0"> 

  321.             <pin_maps>

  322.               <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 

  323.               <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 

  324.               <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 

  325.               <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 

  326.               <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/> 

  327.               <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/> 

  328.               <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/> 

  329.               <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/> 

  330.             </pin_maps>

  331.           </port_map>

  332.         </port_maps>

  333.       </interface>

  334.       <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">

  335.         <port_maps>

  336.           <port_map logical_port="CLK" physical_port="clk" dir="in">

  337.             <pin_maps>

  338.               <pin_map port_index="0" component_pin="clk"/> 

  339.             </pin_maps>

  340.           </port_map>

  341.         </port_maps>

  342.         <parameters>

  343.           <parameter name="frequency" value="100000000" />

  344.        </parameters>

  345.       </interface>

  346.       <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">

  347.         <description>Temperature Sensor connected to I2C</description>

  348. 		<port_maps>

  349.           <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">

  350.             <pin_maps>

  351.               <pin_map port_index="0" component_pin="temp_sda_i"/> 

  352.             </pin_maps>

  353.           </port_map>

  354.           <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">

  355.             <pin_maps>

  356.               <pin_map port_index="0" component_pin="temp_sda_i"/> 

  357.             </pin_maps>

  358.           </port_map>

  359.           <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">

  360.             <pin_maps>

  361.               <pin_map port_index="0" component_pin="temp_sda_i"/> 

  362.             </pin_maps>

  363.           </port_map>

  364.           <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">

  365.             <pin_maps>

  366.               <pin_map port_index="0" component_pin="temp_scl_i"/> 

  367.             </pin_maps>

  368.           </port_map>

  369.           <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">

  370.             <pin_maps>

  371.               <pin_map port_index="0" component_pin="temp_scl_i"/> 

  372.             </pin_maps>

  373.           </port_map>

  374.           <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">

  375.             <pin_maps>

  376.               <pin_map port_index="0" component_pin="temp_scl_i"/> 

  377.             </pin_maps>

  378.           </port_map>

  379.         </port_maps>

  380.       </interface>

  381.       <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">

  382.         <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>

  383. 		<port_maps>

  384.           <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">

  385.             <pin_maps>

  386.               <pin_map port_index="0" component_pin="usb_uart_txd"/> 

  387.             </pin_maps>

  388.           </port_map>

  389.           <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">

  390.             <pin_maps>

  391.               <pin_map port_index="0" component_pin="usb_uart_rxd"/> 

  392.             </pin_maps>

  393.           </port_map>

  394. 		  <port_map logical_port="RTSn" physical_port="usb_uart_rts" dir="out">

  395.             <pin_maps>

  396.               <pin_map port_index="0" component_pin="usb_uart_rts"/> 

  397.             </pin_maps>

  398.           </port_map>

  399. 		  <port_map logical_port="CTSn" physical_port="usb_uart_cts" dir="in">

  400.             <pin_maps>

  401.               <pin_map port_index="0" component_pin="usb_uart_cts"/> 

  402.             </pin_maps>

  403.           </port_map>

  404.         </port_maps>

  405.       </interface>

  406. 	  

  407. 	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">

  408.         <port_maps>

  409.           <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 

  410.             <pin_maps>

  411.               <pin_map port_index="0" component_pin="JA1"/> 

  412. 			</pin_maps>

  413. 		  </port_map>

  414. 		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 

  415.             <pin_maps>

  416.               <pin_map port_index="0" component_pin="JA1"/> 

  417. 			</pin_maps>

  418. 		  </port_map>

  419. 		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 

  420.             <pin_maps>

  421.               <pin_map port_index="0" component_pin="JA1"/> 

  422. 			</pin_maps>

  423. 		  </port_map>

  424. 		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 

  425.             <pin_maps>

  426.               <pin_map port_index="0" component_pin="JA2"/> 

  427. 			</pin_maps>

  428. 		  </port_map>

  429. 		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 

  430.             <pin_maps>

  431.               <pin_map port_index="0" component_pin="JA2"/> 

  432. 			</pin_maps>

  433. 		  </port_map>

  434. 		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 

  435.             <pin_maps>

  436.               <pin_map port_index="0" component_pin="JA2"/> 

  437. 			</pin_maps>

  438. 		  </port_map>

  439. 		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 

  440.             <pin_maps>

  441.               <pin_map port_index="0" component_pin="JA3"/> 

  442. 			</pin_maps>

  443. 		  </port_map>

  444. 		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 

  445.             <pin_maps>

  446.               <pin_map port_index="0" component_pin="JA3"/> 

  447. 			</pin_maps>

  448. 		  </port_map>

  449. 		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 

  450.             <pin_maps>

  451.               <pin_map port_index="0" component_pin="JA3"/> 

  452. 			</pin_maps>

  453. 		  </port_map>

  454. 		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 

  455.             <pin_maps>

  456.               <pin_map port_index="0" component_pin="JA4"/> 

  457. 			</pin_maps>

  458. 		  </port_map>

  459. 		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 

  460.             <pin_maps>

  461.               <pin_map port_index="0" component_pin="JA4"/> 

  462. 			</pin_maps>

  463. 		  </port_map>

  464. 		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 

  465.             <pin_maps>

  466.               <pin_map port_index="0" component_pin="JA4"/> 

  467. 			</pin_maps>

  468. 		  </port_map>

  469. 		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 

  470.             <pin_maps>

  471.               <pin_map port_index="0" component_pin="JA7"/> 

  472. 			</pin_maps>

  473. 		  </port_map>

  474. 		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 

  475.             <pin_maps>

  476.               <pin_map port_index="0" component_pin="JA7"/> 

  477. 			</pin_maps>

  478. 		  </port_map>

  479. 		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 

  480.             <pin_maps>

  481.               <pin_map port_index="0" component_pin="JA7"/> 

  482. 			</pin_maps>

  483. 		  </port_map>

  484. 		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 

  485.             <pin_maps>

  486.               <pin_map port_index="0" component_pin="JA8"/> 

  487. 			</pin_maps>

  488. 		  </port_map>

  489. 		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 

  490.             <pin_maps>

  491.               <pin_map port_index="0" component_pin="JA8"/> 

  492. 			</pin_maps>

  493. 		  </port_map>

  494. 		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 

  495.             <pin_maps>

  496.               <pin_map port_index="0" component_pin="JA8"/> 

  497. 			</pin_maps>

  498. 		  </port_map>

  499. 		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 

  500.             <pin_maps>

  501.               <pin_map port_index="0" component_pin="JA9"/> 

  502. 			</pin_maps>

  503. 		  </port_map>

  504. 		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 

  505.             <pin_maps>

  506.               <pin_map port_index="0" component_pin="JA9"/> 

  507. 			</pin_maps>

  508. 		  </port_map>

  509. 		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 

  510.             <pin_maps>

  511.               <pin_map port_index="0" component_pin="JA9"/> 

  512. 			</pin_maps>

  513. 		  </port_map>

  514. 		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 

  515.             <pin_maps>

  516.               <pin_map port_index="0" component_pin="JA10"/> 

  517. 			</pin_maps>

  518. 		  </port_map>

  519. 		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 

  520.             <pin_maps>

  521.               <pin_map port_index="0" component_pin="JA10"/> 

  522. 			</pin_maps>

  523. 		  </port_map>

  524. 		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 

  525.             <pin_maps>

  526.               <pin_map port_index="0" component_pin="JA10"/> 

  527. 			</pin_maps>

  528. 		  </port_map>

  529.         </port_maps>

  530.       </interface>

  531. 	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">

  532.         <port_maps>

  533.           <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 

  534.             <pin_maps>

  535.               <pin_map port_index="0" component_pin="JB1"/> 

  536. 			</pin_maps>

  537. 		  </port_map>

  538. 		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 

  539.             <pin_maps>

  540.               <pin_map port_index="0" component_pin="JB1"/> 

  541. 			</pin_maps>

  542. 		  </port_map>

  543. 		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 

  544.             <pin_maps>

  545.               <pin_map port_index="0" component_pin="JB1"/> 

  546. 			</pin_maps>

  547. 		  </port_map>

  548. 		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 

  549.             <pin_maps>

  550.               <pin_map port_index="0" component_pin="JB2"/> 

  551. 			</pin_maps>

  552. 		  </port_map>

  553. 		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 

  554.             <pin_maps>

  555.               <pin_map port_index="0" component_pin="JB2"/> 

  556. 			</pin_maps>

  557. 		  </port_map>

  558. 		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 

  559.             <pin_maps>

  560.               <pin_map port_index="0" component_pin="JB2"/> 

  561. 			</pin_maps>

  562. 		  </port_map>

  563. 		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 

  564.             <pin_maps>

  565.               <pin_map port_index="0" component_pin="JB3"/> 

  566. 			</pin_maps>

  567. 		  </port_map>

  568. 		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 

  569.             <pin_maps>

  570.               <pin_map port_index="0" component_pin="JB3"/> 

  571. 			</pin_maps>

  572. 		  </port_map>

  573. 		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 

  574.             <pin_maps>

  575.               <pin_map port_index="0" component_pin="JB3"/> 

  576. 			</pin_maps>

  577. 		  </port_map>

  578. 		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 

  579.             <pin_maps>

  580.               <pin_map port_index="0" component_pin="JB4"/> 

  581. 			</pin_maps>

  582. 		  </port_map>

  583. 		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 

  584.             <pin_maps>

  585.               <pin_map port_index="0" component_pin="JB4"/> 

  586. 			</pin_maps>

  587. 		  </port_map>

  588. 		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 

  589.             <pin_maps>

  590.               <pin_map port_index="0" component_pin="JB4"/> 

  591. 			</pin_maps>

  592. 		  </port_map>

  593. 		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 

  594.             <pin_maps>

  595.               <pin_map port_index="0" component_pin="JB7"/> 

  596. 			</pin_maps>

  597. 		  </port_map>

  598. 		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 

  599.             <pin_maps>

  600.               <pin_map port_index="0" component_pin="JB7"/> 

  601. 			</pin_maps>

  602. 		  </port_map>

  603. 		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 

  604.             <pin_maps>

  605.               <pin_map port_index="0" component_pin="JB7"/> 

  606. 			</pin_maps>

  607. 		  </port_map>

  608. 		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 

  609.             <pin_maps>

  610.               <pin_map port_index="0" component_pin="JB8"/> 

  611. 			</pin_maps>

  612. 		  </port_map>

  613. 		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 

  614.             <pin_maps>

  615.               <pin_map port_index="0" component_pin="JB8"/> 

  616. 			</pin_maps>

  617. 		  </port_map>

  618. 		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 

  619.             <pin_maps>

  620.               <pin_map port_index="0" component_pin="JB8"/> 

  621. 			</pin_maps>

  622. 		  </port_map>

  623. 		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 

  624.             <pin_maps>

  625.               <pin_map port_index="0" component_pin="JB9"/> 

  626. 			</pin_maps>

  627. 		  </port_map>

  628. 		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 

  629.             <pin_maps>

  630.               <pin_map port_index="0" component_pin="JB9"/> 

  631. 			</pin_maps>

  632. 		  </port_map>

  633. 		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 

  634.             <pin_maps>

  635.               <pin_map port_index="0" component_pin="JB9"/> 

  636. 			</pin_maps>

  637. 		  </port_map>

  638. 		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 

  639.             <pin_maps>

  640.               <pin_map port_index="0" component_pin="JB10"/> 

  641. 			</pin_maps>

  642. 		  </port_map>

  643. 		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 

  644.             <pin_maps>

  645.               <pin_map port_index="0" component_pin="JB10"/> 

  646. 			</pin_maps>

  647. 		  </port_map>

  648. 		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 

  649.             <pin_maps>

  650.               <pin_map port_index="0" component_pin="JB10"/> 

  651. 			</pin_maps>

  652. 		  </port_map>

  653.         </port_maps>

  654.       </interface>

  655. 	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">

  656.         <port_maps>

  657.           <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 

  658.             <pin_maps>

  659.               <pin_map port_index="0" component_pin="JC1"/> 

  660. 			</pin_maps>

  661. 		  </port_map>

  662. 		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 

  663.             <pin_maps>

  664.               <pin_map port_index="0" component_pin="JC1"/> 

  665. 			</pin_maps>

  666. 		  </port_map>

  667. 		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 

  668.             <pin_maps>

  669.               <pin_map port_index="0" component_pin="JC1"/> 

  670. 			</pin_maps>

  671. 		  </port_map>

  672. 		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 

  673.             <pin_maps>

  674.               <pin_map port_index="0" component_pin="JC2"/> 

  675. 			</pin_maps>

  676. 		  </port_map>

  677. 		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 

  678.             <pin_maps>

  679.               <pin_map port_index="0" component_pin="JC2"/> 

  680. 			</pin_maps>

  681. 		  </port_map>

  682. 		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 

  683.             <pin_maps>

  684.               <pin_map port_index="0" component_pin="JC2"/> 

  685. 			</pin_maps>

  686. 		  </port_map>

  687. 		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 

  688.             <pin_maps>

  689.               <pin_map port_index="0" component_pin="JC3"/> 

  690. 			</pin_maps>

  691. 		  </port_map>

  692. 		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 

  693.             <pin_maps>

  694.               <pin_map port_index="0" component_pin="JC3"/> 

  695. 			</pin_maps>

  696. 		  </port_map>

  697. 		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 

  698.             <pin_maps>

  699.               <pin_map port_index="0" component_pin="JC3"/> 

  700. 			</pin_maps>

  701. 		  </port_map>

  702. 		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 

  703.             <pin_maps>

  704.               <pin_map port_index="0" component_pin="JC4"/> 

  705. 			</pin_maps>

  706. 		  </port_map>

  707. 		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 

  708.             <pin_maps>

  709.               <pin_map port_index="0" component_pin="JC4"/> 

  710. 			</pin_maps>

  711. 		  </port_map>

  712. 		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 

  713.             <pin_maps>

  714.               <pin_map port_index="0" component_pin="JC4"/> 

  715. 			</pin_maps>

  716. 		  </port_map>

  717. 		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 

  718.             <pin_maps>

  719.               <pin_map port_index="0" component_pin="JC7"/> 

  720. 			</pin_maps>

  721. 		  </port_map>

  722. 		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 

  723.             <pin_maps>

  724.               <pin_map port_index="0" component_pin="JC7"/> 

  725. 			</pin_maps>

  726. 		  </port_map>

  727. 		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 

  728.             <pin_maps>

  729.               <pin_map port_index="0" component_pin="JC7"/> 

  730. 			</pin_maps>

  731. 		  </port_map>

  732. 		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 

  733.             <pin_maps>

  734.               <pin_map port_index="0" component_pin="JC8"/> 

  735. 			</pin_maps>

  736. 		  </port_map>

  737. 		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 

  738.             <pin_maps>

  739.               <pin_map port_index="0" component_pin="JC8"/> 

  740. 			</pin_maps>

  741. 		  </port_map>

  742. 		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 

  743.             <pin_maps>

  744.               <pin_map port_index="0" component_pin="JC8"/> 

  745. 			</pin_maps>

  746. 		  </port_map>

  747. 		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 

  748.             <pin_maps>

  749.               <pin_map port_index="0" component_pin="JC9"/> 

  750. 			</pin_maps>

  751. 		  </port_map>

  752. 		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 

  753.             <pin_maps>

  754.               <pin_map port_index="0" component_pin="JC9"/> 

  755. 			</pin_maps>

  756. 		  </port_map>

  757. 		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 

  758.             <pin_maps>

  759.               <pin_map port_index="0" component_pin="JC9"/> 

  760. 			</pin_maps>

  761. 		  </port_map>

  762. 		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 

  763.             <pin_maps>

  764.               <pin_map port_index="0" component_pin="JC10"/> 

  765. 			</pin_maps>

  766. 		  </port_map>

  767. 		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 

  768.             <pin_maps>

  769.               <pin_map port_index="0" component_pin="JC10"/> 

  770. 			</pin_maps>

  771. 		  </port_map>

  772. 		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 

  773.             <pin_maps>

  774.               <pin_map port_index="0" component_pin="JC10"/> 

  775. 			</pin_maps>

  776. 		  </port_map>

  777.         </port_maps>

  778.       </interface>

  779. 	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">

  780.         <port_maps>

  781.           <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 

  782.             <pin_maps>

  783.               <pin_map port_index="0" component_pin="JD1"/> 

  784. 			</pin_maps>

  785. 		  </port_map>

  786. 		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 

  787.             <pin_maps>

  788.               <pin_map port_index="0" component_pin="JD1"/> 

  789. 			</pin_maps>

  790. 		  </port_map>

  791. 		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 

  792.             <pin_maps>

  793.               <pin_map port_index="0" component_pin="JD1"/> 

  794. 			</pin_maps>

  795. 		  </port_map>

  796. 		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 

  797.             <pin_maps>

  798.               <pin_map port_index="0" component_pin="JD2"/> 

  799. 			</pin_maps>

  800. 		  </port_map>

  801. 		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 

  802.             <pin_maps>

  803.               <pin_map port_index="0" component_pin="JD2"/> 

  804. 			</pin_maps>

  805. 		  </port_map>

  806. 		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 

  807.             <pin_maps>

  808.               <pin_map port_index="0" component_pin="JD2"/> 

  809. 			</pin_maps>

  810. 		  </port_map>

  811. 		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 

  812.             <pin_maps>

  813.               <pin_map port_index="0" component_pin="JD3"/> 

  814. 			</pin_maps>

  815. 		  </port_map>

  816. 		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 

  817.             <pin_maps>

  818.               <pin_map port_index="0" component_pin="JD3"/> 

  819. 			</pin_maps>

  820. 		  </port_map>

  821. 		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 

  822.             <pin_maps>

  823.               <pin_map port_index="0" component_pin="JD3"/> 

  824. 			</pin_maps>

  825. 		  </port_map>

  826. 		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 

  827.             <pin_maps>

  828.               <pin_map port_index="0" component_pin="JD4"/> 

  829. 			</pin_maps>

  830. 		  </port_map>

  831. 		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 

  832.             <pin_maps>

  833.               <pin_map port_index="0" component_pin="JD4"/> 

  834. 			</pin_maps>

  835. 		  </port_map>

  836. 		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 

  837.             <pin_maps>

  838.               <pin_map port_index="0" component_pin="JD4"/> 

  839. 			</pin_maps>

  840. 		  </port_map>

  841. 		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 

  842.             <pin_maps>

  843.               <pin_map port_index="0" component_pin="JD7"/> 

  844. 			</pin_maps>

  845. 		  </port_map>

  846. 		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 

  847.             <pin_maps>

  848.               <pin_map port_index="0" component_pin="JD7"/> 

  849. 			</pin_maps>

  850. 		  </port_map>

  851. 		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 

  852.             <pin_maps>

  853.               <pin_map port_index="0" component_pin="JD7"/> 

  854. 			</pin_maps>

  855. 		  </port_map>

  856. 		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 

  857.             <pin_maps>

  858.               <pin_map port_index="0" component_pin="JD8"/> 

  859. 			</pin_maps>

  860. 		  </port_map>

  861. 		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 

  862.             <pin_maps>

  863.               <pin_map port_index="0" component_pin="JD8"/> 

  864. 			</pin_maps>

  865. 		  </port_map>

  866. 		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 

  867.             <pin_maps>

  868.               <pin_map port_index="0" component_pin="JD8"/> 

  869. 			</pin_maps>

  870. 		  </port_map>

  871. 		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 

  872.             <pin_maps>

  873.               <pin_map port_index="0" component_pin="JD9"/> 

  874. 			</pin_maps>

  875. 		  </port_map>

  876. 		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 

  877.             <pin_maps>

  878.               <pin_map port_index="0" component_pin="JD9"/> 

  879. 			</pin_maps>

  880. 		  </port_map>

  881. 		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 

  882.             <pin_maps>

  883.               <pin_map port_index="0" component_pin="JD9"/> 

  884. 			</pin_maps>

  885. 		  </port_map>

  886. 		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 

  887.             <pin_maps>

  888.               <pin_map port_index="0" component_pin="JD10"/> 

  889. 			</pin_maps>

  890. 		  </port_map>

  891. 		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 

  892.             <pin_maps>

  893.               <pin_map port_index="0" component_pin="JD10"/> 

  894. 			</pin_maps>

  895. 		  </port_map>

  896. 		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 

  897.             <pin_maps>

  898.               <pin_map port_index="0" component_pin="JD10"/> 

  899. 			</pin_maps>

  900. 		  </port_map>

  901.         </port_maps>

  902.       </interface>

  903. 	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">

  904.         <port_maps>

  905.           <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 

  906.             <pin_maps>

  907.               <pin_map port_index="0" component_pin="JXADC1"/> 

  908. 			</pin_maps>

  909. 		  </port_map>

  910. 		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 

  911.             <pin_maps>

  912.               <pin_map port_index="0" component_pin="JXADC1"/> 

  913. 			</pin_maps>

  914. 		  </port_map>

  915. 		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 

  916.             <pin_maps>

  917.               <pin_map port_index="0" component_pin="JXADC1"/> 

  918. 			</pin_maps>

  919. 		  </port_map>

  920. 		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 

  921.             <pin_maps>

  922.               <pin_map port_index="0" component_pin="JXADC2"/> 

  923. 			</pin_maps>

  924. 		  </port_map>

  925. 		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 

  926.             <pin_maps>

  927.               <pin_map port_index="0" component_pin="JXADC2"/> 

  928. 			</pin_maps>

  929. 		  </port_map>

  930. 		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 

  931.             <pin_maps>

  932.               <pin_map port_index="0" component_pin="JXADC2"/> 

  933. 			</pin_maps>

  934. 		  </port_map>

  935. 		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 

  936.             <pin_maps>

  937.               <pin_map port_index="0" component_pin="JXADC3"/> 

  938. 			</pin_maps>

  939. 		  </port_map>

  940. 		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 

  941.             <pin_maps>

  942.               <pin_map port_index="0" component_pin="JXADC3"/> 

  943. 			</pin_maps>

  944. 		  </port_map>

  945. 		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 

  946.             <pin_maps>

  947.               <pin_map port_index="0" component_pin="JXADC3"/> 

  948. 			</pin_maps>

  949. 		  </port_map>

  950. 		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 

  951.             <pin_maps>

  952.               <pin_map port_index="0" component_pin="JXADC4"/> 

  953. 			</pin_maps>

  954. 		  </port_map>

  955. 		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 

  956.             <pin_maps>

  957.               <pin_map port_index="0" component_pin="JXADC4"/> 

  958. 			</pin_maps>

  959. 		  </port_map>

  960. 		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 

  961.             <pin_maps>

  962.               <pin_map port_index="0" component_pin="JXADC4"/> 

  963. 			</pin_maps>

  964. 		  </port_map>

  965. 		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 

  966.             <pin_maps>

  967.               <pin_map port_index="0" component_pin="JXADC7"/> 

  968. 			</pin_maps>

  969. 		  </port_map>

  970. 		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 

  971.             <pin_maps>

  972.               <pin_map port_index="0" component_pin="JXADC7"/> 

  973. 			</pin_maps>

  974. 		  </port_map>

  975. 		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 

  976.             <pin_maps>

  977.               <pin_map port_index="0" component_pin="JXADC7"/> 

  978. 			</pin_maps>

  979. 		  </port_map>

  980. 		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 

  981.             <pin_maps>

  982.               <pin_map port_index="0" component_pin="JXADC8"/> 

  983. 			</pin_maps>

  984. 		  </port_map>

  985. 		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 

  986.             <pin_maps>

  987.               <pin_map port_index="0" component_pin="JXADC8"/> 

  988. 			</pin_maps>

  989. 		  </port_map>

  990. 		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 

  991.             <pin_maps>

  992.               <pin_map port_index="0" component_pin="JXADC8"/> 

  993. 			</pin_maps>

  994. 		  </port_map>

  995. 		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 

  996.             <pin_maps>

  997.               <pin_map port_index="0" component_pin="JXADC9"/> 

  998. 			</pin_maps>

  999. 		  </port_map>

  1000. 		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 

  1001.             <pin_maps>

  1002.               <pin_map port_index="0" component_pin="JXADC9"/> 

  1003. 			</pin_maps>

  1004. 		  </port_map>

  1005. 		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 

  1006.             <pin_maps>

  1007.               <pin_map port_index="0" component_pin="JXADC9"/> 

  1008. 			</pin_maps>

  1009. 		  </port_map>

  1010. 		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 

  1011.             <pin_maps>

  1012.               <pin_map port_index="0" component_pin="JXADC10"/> 

  1013. 			</pin_maps>

  1014. 		  </port_map>

  1015. 		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 

  1016.             <pin_maps>

  1017.               <pin_map port_index="0" component_pin="JXADC10"/> 

  1018. 			</pin_maps>

  1019. 		  </port_map>

  1020. 		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 

  1021.             <pin_maps>

  1022.               <pin_map port_index="0" component_pin="JXADC10"/> 

  1023. 			</pin_maps>

  1024. 		  </port_map>

  1025.         </port_maps>

  1026.       </interface>

  1027. 	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">

  1028.        <preferred_ips>

  1029. 			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>

  1030. 			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>

  1031. 		</preferred_ips>

  1032. 		<port_maps>

  1033.           <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 

  1034.             <pin_maps>

  1035.               <pin_map port_index="0" component_pin="SD1"/> 

  1036. 			</pin_maps>

  1037. 		  </port_map>

  1038. 		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 

  1039.             <pin_maps>

  1040.               <pin_map port_index="0" component_pin="SD1"/> 

  1041. 			</pin_maps>

  1042. 		  </port_map>

  1043. 		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 

  1044.             <pin_maps>

  1045.               <pin_map port_index="0" component_pin="SD1"/> 

  1046. 			</pin_maps>

  1047. 		  </port_map>

  1048. 		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 

  1049.             <pin_maps>

  1050.               <pin_map port_index="0" component_pin="SD2"/> 

  1051. 			</pin_maps>

  1052. 		  </port_map>

  1053. 		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 

  1054.             <pin_maps>

  1055.               <pin_map port_index="0" component_pin="SD2"/> 

  1056. 			</pin_maps>

  1057. 		  </port_map>

  1058. 		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 

  1059.             <pin_maps>

  1060.               <pin_map port_index="0" component_pin="SD2"/> 

  1061. 			</pin_maps>

  1062. 		  </port_map>

  1063. 		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 

  1064.             <pin_maps>

  1065.               <pin_map port_index="0" component_pin="SD3"/> 

  1066. 			</pin_maps>

  1067. 		  </port_map>

  1068. 		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 

  1069.             <pin_maps>

  1070.               <pin_map port_index="0" component_pin="SD3"/> 

  1071. 			</pin_maps>

  1072. 		  </port_map>

  1073. 		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 

  1074.             <pin_maps>

  1075.               <pin_map port_index="0" component_pin="SD3"/> 

  1076. 			</pin_maps>

  1077. 		  </port_map>

  1078. 		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 

  1079.             <pin_maps>

  1080.               <pin_map port_index="0" component_pin="SD4"/> 

  1081. 			</pin_maps>

  1082. 		  </port_map>

  1083. 		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 

  1084.             <pin_maps>

  1085.               <pin_map port_index="0" component_pin="SD4"/> 

  1086. 			</pin_maps>

  1087. 		  </port_map>

  1088. 		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 

  1089.             <pin_maps>

  1090.               <pin_map port_index="0" component_pin="SD4"/> 

  1091. 			</pin_maps>

  1092. 		  </port_map>

  1093. 		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 

  1094.             <pin_maps>

  1095.               <pin_map port_index="0" component_pin="SD7"/> 

  1096. 			</pin_maps>

  1097. 		  </port_map>

  1098. 		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 

  1099.             <pin_maps>

  1100.               <pin_map port_index="0" component_pin="SD7"/> 

  1101. 			</pin_maps>

  1102. 		  </port_map>

  1103. 		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 

  1104.             <pin_maps>

  1105.               <pin_map port_index="0" component_pin="SD7"/> 

  1106. 			</pin_maps>

  1107. 		  </port_map>

  1108. 		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 

  1109.             <pin_maps>

  1110.               <pin_map port_index="0" component_pin="SD8"/> 

  1111. 			</pin_maps>

  1112. 		  </port_map>

  1113. 		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 

  1114.             <pin_maps>

  1115.               <pin_map port_index="0" component_pin="SD8"/> 

  1116. 			</pin_maps>

  1117. 		  </port_map>

  1118. 		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 

  1119.             <pin_maps>

  1120.               <pin_map port_index="0" component_pin="SD8"/> 

  1121. 			</pin_maps>

  1122. 		  </port_map>

  1123. 		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 

  1124.             <pin_maps>

  1125.               <pin_map port_index="0" component_pin="SD9"/> 

  1126. 			</pin_maps>

  1127. 		  </port_map>

  1128. 		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 

  1129.             <pin_maps>

  1130.               <pin_map port_index="0" component_pin="SD9"/> 

  1131. 			</pin_maps>

  1132. 		  </port_map>

  1133. 		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 

  1134.             <pin_maps>

  1135.               <pin_map port_index="0" component_pin="SD9"/> 

  1136. 			</pin_maps>

  1137. 		  </port_map>

  1138. 		  <port_map logical_port="PIN10_I" physical_port="SD10" dir="in"> 

  1139.             <pin_maps>

  1140.               <pin_map port_index="0" component_pin="SD10"/> 

  1141. 			</pin_maps>

  1142. 		  </port_map>

  1143. 		  <port_map logical_port="PIN10_O" physical_port="SD10" dir="out"> 

  1144.             <pin_maps>

  1145.               <pin_map port_index="0" component_pin="SD10"/> 

  1146. 			</pin_maps>

  1147. 		  </port_map>

  1148. 		  <port_map logical_port="PIN10_T" physical_port="SD10" dir="out"> 

  1149.             <pin_maps>

  1150.               <pin_map port_index="0" component_pin="SD10"/> 

  1151. 			</pin_maps>

  1152. 		  </port_map>

  1153. 		</port_maps>

  1154.       </interface>

  1155.     </interfaces>

  1156.   </component>

  1157.   <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">

  1158. 	<description>Accelerometer controlled through SPI</description>

  1159.   </component>

  1160.   <component name="ddr2_sdram" display_name="DDR2 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">

  1161.   <description>256 MB Onboard DDR Memory </description>

  1162. 	<parameters>

  1163.         <parameter name="ddr_type" value="ddr2"/>

  1164.         <parameter name="size" value="256MB"/>

  1165. 	</parameters>

  1166.   </component>

  1167.   <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">

  1168. 	<description>16 Switches</description>

  1169.   </component>

  1170.   <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">

  1171. 	<description>7 Segment Display Segment Control</description>

  1172.   </component>

  1173.   <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">

  1174. 	<description>16 LEDs</description>

  1175.   </component>

  1176.   <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">

  1177. 	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>

  1178.   </component>

  1179.   <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">

  1180. 	<description>QSPI Flash</description>

  1181.   </component>

  1182.   <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">

  1183. 	<description>Onboard Reset Button</description>

  1184.   </component>

  1185.   <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">

  1186. 	<description>2 RGB LEDs</description>

  1187.   </component>

  1188.   <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">

  1189. 	<description>7 Segment Display Anodes</description>

  1190.   </component>

  1191.   <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">

  1192. 	<description>100 MHz Single-Ended System Clock</description>

  1193.   </component>

  1194.   <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">

  1195. 	<description>SPI Controlled Temperature Sensor</description>

  1196.   </component>

  1197.   <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">

  1198. 	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>

  1199.   </component>

  1200.   <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">

  1201. 	<description>Pmod Connector JA</description>

  1202.   </component>

  1203.   <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">

  1204. 	<description>Pmod Connector JB</description>

  1205.   </component>

  1206.   <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">

  1207. 	<description>Pmod Connector JC</description>

  1208.   </component>

  1209.   <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">

  1210. 	<description>Pmod Connector JD</description>

  1211.   </component>

  1212.   <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">

  1213. 	<description>Pmod Connector JXADC</description>

  1214.   </component>

  1215.   <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">

  1216.   <component_modes>

  1217. 	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">

  1218. 	  <interfaces>

  1219. 		<interface name="sd"/>

  1220. 	  </interfaces>

  1221. 	  <preferred_ips>

  1222. 			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>

  1223. 	  </preferred_ips>

  1224. 	</component_mode>

  1225. 	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">

  1226. 	  <interfaces>

  1227. 		<interface name="sd"/>

  1228. 	  </interfaces>

  1229. 	  <preferred_ips>

  1230. 		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>

  1231. 	  </preferred_ips>

  1232. 	</component_mode>

  1233.   </component_modes>

  1234. 	<description>Onboard MicroSD Card Slot</description>

  1235.   </component>

  1236. </components>

  1237. <jtag_chains>

  1238.   <jtag_chain name="chain1">

  1239.     <position name="0" component="part0"/>

  1240.   </jtag_chain>

  1241. </jtag_chains>

  1242. <connections>

  1243.   <connection name="part0_acl_spi" component1="part0" component2="acl_spi">

  1244.     <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>

  1245.   </connection>

  1246.   <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">

  1247.     <connection_map name="part0_dip_switches_16bits_1" c1_st_index="5" c1_end_index="20" c2_st_index="0" c2_end_index="15"/>

  1248.   </connection>

  1249.   <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">

  1250.     <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="21" c1_end_index="28" c2_st_index="0" c2_end_index="7"/>

  1251.   </connection>

  1252.   <connection name="part0_led_16bits" component1="part0" component2="led_16bits">

  1253.     <connection_map name="part0_led_16bits_1" c1_st_index="38" c1_end_index="53" c2_st_index="0" c2_end_index="15"/>

  1254.   </connection>

  1255.   <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">

  1256.     <connection_map name="part0_push_buttons_5bits_1" c1_st_index="54" c1_end_index="58" c2_st_index="0" c2_end_index="4"/>

  1257.   </connection>

  1258.   <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">

  1259.     <connection_map name="part0_qspi_flash_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>

  1260.   </connection>

  1261.   <connection name="part0_reset" component1="part0" component2="reset">

  1262.     <connection_map name="part0_reset_1" c1_st_index="64" c1_end_index="64" c2_st_index="0" c2_end_index="0"/>

  1263.   </connection>

  1264.   <connection name="part0_rgb_led" component1="part0" component2="rgb_led">

  1265.     <connection_map name="part0_rgb_led_1" c1_st_index="65" c1_end_index="70" c2_st_index="0" c2_end_index="5"/>

  1266.   </connection>

  1267.   <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">

  1268.     <connection_map name="part0_seven_seg_led_an_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>

  1269.   </connection>

  1270.   <connection name="part0_sys_clock" component1="part0" component2="sys_clock">

  1271.     <connection_map name="part0_sys_clock_1" c1_st_index="4" c1_end_index="4" c2_st_index="0" c2_end_index="0"/>

  1272.   </connection>

  1273.   <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">

  1274.     <connection_map name="part0_temp_sensor_1" c1_st_index="79" c1_end_index="80" c2_st_index="0" c2_end_index="1"/>

  1275.   </connection>

  1276.   <connection name="part0_usb_uart" component1="part0" component2="usb_uart">

  1277.     <connection_map name="part0_usb_uart_1" c1_st_index="81" c1_end_index="82" c2_st_index="0" c2_end_index="1"/>

  1278. 	<connection_map name="part0_usb_uart_rts_cts" c1_st_index="179" c1_end_index="180" c2_st_index="2" c2_end_index="3"/>

  1279.   </connection>

  1280.   <connection name="part0_ja" component1="part0" component2="ja">

  1281.     <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>

  1282.   </connection>

  1283.   <connection name="part0_jb" component1="part0" component2="jb">

  1284.     <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>

  1285.   </connection>

  1286.   <connection name="part0_jc" component1="part0" component2="jc">

  1287.     <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>

  1288.   </connection>

  1289.   <connection name="part0_jd" component1="part0" component2="jd">

  1290.     <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>

  1291.   </connection>

  1292.   <connection name="part0_jxadc" component1="part0" component2="jxadc">

  1293.     <connection_map name="part0_jxadc_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>

  1294.   </connection>

  1295.   <connection name="part0_sd" component1="part0" component2="sd">

  1296.     <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>

  1297.   </connection>

  1298.   

  1299.  

  1300. </connections>

  1301. </board>