
*** Running vivado
    with args -log regler.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl



****** Vivado v2021.2 (64-bit)
  **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source regler.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1260.250 ; gain = 7.859
Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top regler -part xc7z010clg400-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Device 21-403] Loading part xc7z010clg400-1
WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 7236
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Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.250 ; gain = 0.000
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INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51]
WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51]
WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
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Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.250 ; gain = 0.000
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1260.250 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/regler_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1277.531 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1277.531 ; gain = 0.000
WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
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Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281
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Start Loading Part and Timing Information
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Loading part: xc7z010clg400-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281
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Start Applying 'set_property' XDC Constraints
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1277.531 ; gain = 17.281
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Start RTL Component Statistics 
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Detailed RTL Component Info : 
+---Adders : 
	  10 Input  148 Bit       Adders := 1     
	   2 Input  148 Bit       Adders := 2     
	   3 Input   64 Bit       Adders := 1     
	   2 Input   64 Bit       Adders := 1     
	   2 Input   20 Bit       Adders := 2     
	   2 Input   10 Bit       Adders := 1     
+---Registers : 
	               64 Bit    Registers := 1     
+---Multipliers : 
	              20x64  Multipliers := 1     
	              10x64  Multipliers := 1     
+---Muxes : 
	   2 Input  148 Bit        Muxes := 1     
	   2 Input   64 Bit        Muxes := 3     
	   2 Input   20 Bit        Muxes := 2     
	   2 Input   10 Bit        Muxes := 1     
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Finished RTL Component Statistics 
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Start Part Resource Summary
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Part Resources:
DSPs: 80 (col length:40)
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP I_k6, operation Mode is: A*B.
DSP Report: operator I_k6 is absorbed into DSP I_k6.
DSP Report: operator I_k6 is absorbed into DSP I_k6.
DSP Report: Generating DSP I_k6, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator I_k6 is absorbed into DSP I_k6.
DSP Report: operator I_k6 is absorbed into DSP I_k6.
DSP Report: Generating DSP I_k6, operation Mode is: A*B.
DSP Report: operator I_k6 is absorbed into DSP I_k6.
DSP Report: operator I_k6 is absorbed into DSP I_k6.
DSP Report: Generating DSP I_k6, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator I_k6 is absorbed into DSP I_k6.
DSP Report: operator I_k6 is absorbed into DSP I_k6.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: operator I_k5 is absorbed into DSP I_k5.
DSP Report: Generating DSP u3, operation Mode is: A*B.
DSP Report: operator u3 is absorbed into DSP u3.
DSP Report: operator u3 is absorbed into DSP u3.
DSP Report: Generating DSP u3, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator u3 is absorbed into DSP u3.
DSP Report: operator u3 is absorbed into DSP u3.
DSP Report: Generating DSP u3, operation Mode is: A*B.
DSP Report: operator u3 is absorbed into DSP u3.
DSP Report: operator u3 is absorbed into DSP u3.
DSP Report: Generating DSP u3, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator u3 is absorbed into DSP u3.
DSP Report: operator u3 is absorbed into DSP u3.
WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1277.531 ; gain = 17.281
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
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DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping    | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|regler      | A*B            | 20     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | (PCIN>>17)+A*B | 20     | 13     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 20     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | (PCIN>>17)+A*B | 20     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | (PCIN>>17)+A*B | 16     | 13     | -      | -      | 29     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | (PCIN>>17)+A*B | 18     | 13     | -      | -      | 46     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 13     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | PCIN+A*B       | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | PCIN+A*B       | 18     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 13     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | PCIN+A*B       | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | PCIN+A*B       | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 13     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | PCIN+A*B       | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | PCIN+A*B       | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | (PCIN>>17)+A*B | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | (PCIN>>17)+A*B | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | (PCIN>>17)+A*B | 13     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | A*B            | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|regler      | (PCIN>>17)+A*B | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.168 ; gain = 29.918
---------------------------------------------------------------------------------
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1300.332 ; gain = 40.082
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Start Technology Mapping
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---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 1358.793 ; gain = 98.543
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418
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Start Writing Synthesis Report
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Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+--------+------+
|      |Cell    |Count |
+------+--------+------+
|1     |BUFG    |     1|
|2     |CARRY4  |  2830|
|3     |DSP48E1 |    28|
|4     |LUT1    |   235|
|5     |LUT2    |   665|
|6     |LUT3    |   460|
|7     |LUT4    |   564|
|8     |LUT5    |  9401|
|9     |LUT6    |   140|
|10    |FDRE    |   212|
|11    |IBUF    |   224|
|12    |OBUF    |    64|
+------+--------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418
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Synthesis finished with 0 errors, 0 critical warnings and 11 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 1369.668 ; gain = 92.137
Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.193 . Memory (MB): peak = 1377.176 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1377.863 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Synth Design complete, checksum: 6d8170b6
INFO: [Common 17-83] Releasing license: Synthesis
21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 1377.863 ; gain = 117.613
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue May 31 21:52:26 2022...
