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-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.05.2022 14:01:29
-- Design Name: 
-- Module Name: fixedPointTest - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fixedPointTest is
    Port ( a : in sfixed (7 downto -6);     --7+6+1 = 14
           b : in sfixed (7 downto -6);
           c : out sfixed (8 downto -6));  --21+6+1 = 2*14 für Multiplikation
end fixedPointTest;

architecture Behavioral of fixedPointTest is

begin

process(a, b)
    begin

    c <= a + b;
        
end process;


end Behavioral;
