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-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.05.2022 14:05:03
-- Design Name: 
-- Module Name: fixedPointTest_db - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fixedPointTest_db is
--  Port ( );
end fixedPointTest_db;

architecture Behavioral of fixedPointTest_db is

component fixedPointTest is
    Port ( a : in sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen
           b : in sfixed (7 downto -6);
           c : out sfixed (8 downto -6));
end component;

--wendetangenten test
signal a : sfixed(7 downto -6) := to_sfixed (-3.125, 7, -6);
signal b : sfixed(7 downto -6) := to_sfixed (5.1111, 7, -6);
signal c : sfixed(8 downto -6);




begin

uutFixedPointTest: fixedPointTest PORT MAP(
    a => a,
    b => b,
    c => c
);

process
begin




end process;

end Behavioral;
