Vivado Simulator v2021.2
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Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip --snapshot fixedPointTest_db_behav xil_defaultlib.fixedPointTest_db -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-664] expression has 15 elements ; expected 28 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sim_1/new/fixedPointTest_db.vhd:46]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit fixedpointtest_db in library work failed.
