Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut".
INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut".
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package vl.vl_types
Compiling module xil_defaultlib.glbl
Compiling module simprims_ver.BUFG
Compiling module simprims_ver.IBUF
Compiling module simprims_ver.x_lut1_mux2
Compiling module simprims_ver.LUT1(INIT=2'b01)
Compiling module simprims_ver.FDCE_default
Compiling module simprims_ver.CARRY4
Compiling module simprims_ver.OBUF
Compiling module simprims_ver.latchsre_ldce
Compiling module simprims_ver.LDCE
Compiling module simprims_ver.x_lut2_mux4
Compiling module simprims_ver.LUT2
Compiling module xil_defaultlib.pwm_test
Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
Built simulation snapshot pwm_test_db_time_synth
