diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc index 881df7a..c9aa8fb 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc @@ -1,4 +1,4 @@ version:1 57656254616c6b5472616e736d697373696f6e417474656d70746564:13 -6d6f64655f636f756e7465727c4755494d6f6465:25 +6d6f64655f636f756e7465727c4755494d6f6465:28 eof: diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf index af7a8c1..bc6d378 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf @@ -38,7 +38,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333973:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313237342e3339314d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:31332e3933344d42:00:00 -eof:446781170 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343473:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313332322e3232334d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:36322e3331364d42:00:00 +eof:2782355530 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_70.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_70.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_70.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_71.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_71.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_71.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_72.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_72.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_72.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_73.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_73.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_73.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_74.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_74.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_74.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_75.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_75.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_75.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_76.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_76.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_76.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_77.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_77.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_77.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_78.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_78.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_78.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_79.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_79.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_79.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_80.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_80.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_80.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_81.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_81.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_81.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst index f054bd1..132fee5 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml index 19611ac..4f97434 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml @@ -1,11 +1,14 @@ - + + + + @@ -29,13 +32,6 @@ - - - - - - - @@ -127,7 +123,9 @@ - + + Vivado Synthesis Defaults + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf index cdc845e..4086de3 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf @@ -1,5 +1,5 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 @@ -13,7 +13,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313134:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313334:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 @@ -28,4 +28,4 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3035343861623234333065633433623139386531656634383534326531333964:506172656e742050412070726f6a656374204944:00 -eof:83681024 +eof:1371551499 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp index ed13f85..7caf7d4 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.tcl b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.tcl index 0318784..cb8ad55 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.tcl +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.tcl @@ -70,8 +70,6 @@ proc create_report { reportName command } { } } OPTRACE "synth_1" START { ROLLUP_AUTO } -set_param chipscope.maxJobs 3 -set_msg_config -id {Common 17-41} -limit 10000000 OPTRACE "Creating in-memory project" START { } create_project -in_memory -part xc7z010clg400-1 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds index 8556c85..688142f 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds @@ -2,8 +2,8 @@ # Vivado v2021.2 (64-bit) # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 -# Start of session at: Fri May 13 12:52:57 2022 -# Process ID: 2508 +# Start of session at: Wed May 18 20:50:48 2022 +# Process ID: 14452 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds @@ -11,7 +11,7 @@ # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB #----------------------------------------------------------- source regler.tcl -notrace -create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1260.457 ; gain = 7.594 +create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1259.906 ; gain = 8.973 Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes @@ -24,27 +24,58 @@ WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis b INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 12584 +INFO: [Synth 8-7075] Helper process launched with PID 15440 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43] -WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:97] -WARNING: [Synth 8-6014] Unused sequential element e_k2_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:98] -INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43] +INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:47] +WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:108] +INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:47] +WARNING: [Synth 8-7129] Port TV[31] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[30] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[29] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[28] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[27] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[26] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[25] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[24] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[23] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[22] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[21] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[20] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[19] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[18] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[17] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[16] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[15] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[14] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[13] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[12] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[11] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[10] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1259.906 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -55,47 +86,47 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1259.906 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1259.906 ; gain = 0.000 WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 3 Input 32 Bit Adders := 2 - 2 Input 32 Bit Adders := 1 - 2 Input 31 Bit Adders := 1 + 2 Input 32 Bit Adders := 4 + 3 Input 32 Bit Adders := 1 + 2 Input 31 Bit Adders := 3 +---Registers : - 32 Bit Registers := 2 + 32 Bit Registers := 1 +---Multipliers : - 1x32 Multipliers := 1 + 32x32 Multipliers := 1 +---Muxes : - 2 Input 32 Bit Muxes := 1 - 2 Input 31 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 2 + 2 Input 31 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -112,26 +143,100 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +DSP Report: Generating DSP I_k4, operation Mode is: A*B. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: Generating DSP I_k4, operation Mode is: A*B. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: Generating DSP u_reg1, operation Mode is: A*B. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: Generating DSP u_reg1, operation Mode is: A*B. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +WARNING: [Synth 8-7129] Port TV[31] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[30] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[29] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[28] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[27] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[26] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[25] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[24] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[23] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[22] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[21] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[20] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[19] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[18] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[17] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[16] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[15] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[14] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[13] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[12] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[11] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[10] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1259.906 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|regler | A*B | 15 | 15 | - | - | 15 | 0 | 0 | - | - | - | 0 | 0 | +|regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|regler | (PCIN>>17)+A*B | 15 | 15 | - | - | 15 | 0 | 0 | - | - | - | 0 | 0 | +|regler | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|regler | (PCIN>>17)+A*B | 15 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|regler | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1275.953 ; gain = 16.047 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1277.246 ; gain = 17.340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 1308.379 ; gain = 48.473 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -149,37 +254,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -192,42 +297,44 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |BUFG | 1| -|2 |CARRY4 | 104| -|3 |LUT1 | 66| -|4 |LUT2 | 59| -|5 |LUT3 | 182| -|6 |LUT4 | 138| -|7 |LUT5 | 49| -|8 |LUT6 | 186| -|9 |FDRE | 64| -|10 |IBUF | 65| -|11 |OBUF | 32| -+------+-------+------+ ++------+--------+------+ +| |Cell |Count | ++------+--------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 386| +|3 |DSP48E1 | 6| +|4 |LUT1 | 132| +|5 |LUT2 | 165| +|6 |LUT3 | 169| +|7 |LUT4 | 78| +|8 |LUT5 | 956| +|9 |LUT6 | 143| +|10 |FDRE | 64| +|11 |IBUF | 161| +|12 |OBUF | 32| ++------+--------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1274.391 ; gain = 13.934 -Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Synthesis finished with 0 errors, 0 critical warnings and 33 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:37 . Memory (MB): peak = 1322.223 ; gain = 62.316 +Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1286.504 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1334.242 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 392 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1290.160 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1338.902 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete, checksum: 235c9ea4 +Synth Design complete, checksum: 74f8d27b INFO: [Common 17-83] Releasing license: Synthesis -21 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +21 Infos, 69 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.160 ; gain = 29.703 +synth_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1338.902 ; gain = 78.996 INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri May 13 12:53:45 2022... +INFO: [Common 17-206] Exiting Vivado at Wed May 18 20:51:43 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.pb index e00eb9a..5075c7b 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.pb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt index bdbbd30..cde53ba 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 -| Date : Fri May 13 12:53:45 2022 +| Date : Wed May 18 20:51:43 2022 | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | Command : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | Design : regler @@ -31,8 +31,8 @@ Table of Contents +-------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+------+-------+------------+-----------+-------+ -| Slice LUTs* | 538 | 0 | 0 | 17600 | 3.06 | -| LUT as Logic | 538 | 0 | 0 | 17600 | 3.06 | +| Slice LUTs* | 1530 | 0 | 0 | 17600 | 8.69 | +| LUT as Logic | 1530 | 0 | 0 | 17600 | 8.69 | | LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 | | Slice Registers | 64 | 0 | 0 | 35200 | 0.18 | | Register as Flip Flop | 64 | 0 | 0 | 35200 | 0.18 | @@ -78,34 +78,35 @@ Table of Contents 3. DSP ------ -+-----------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-----------+------+-------+------------+-----------+-------+ -| DSPs | 0 | 0 | 0 | 80 | 0.00 | -+-----------+------+-------+------------+-----------+-------+ ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 6 | 0 | 0 | 80 | 7.50 | +| DSP48E1 only | 6 | | | | | ++----------------+------+-------+------------+-----------+-------+ 4. IO and GT Specific --------------------- -+-----------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-----------------------------+------+-------+------------+-----------+-------+ -| Bonded IOB | 97 | 0 | 0 | 100 | 97.00 | -| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | -| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 | -| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 | -| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 | -| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 | -| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 | -| IBUFDS | 0 | 0 | 0 | 96 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | -| ILOGIC | 0 | 0 | 0 | 100 | 0.00 | -| OLOGIC | 0 | 0 | 0 | 100 | 0.00 | -+-----------------------------+------+-------+------------+-----------+-------+ ++-----------------------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+--------+ +| Bonded IOB | 193 | 0 | 0 | 100 | 193.00 | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+------------+-----------+--------+ 5. Clocking @@ -147,16 +148,17 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT6 | 186 | LUT | -| LUT3 | 182 | LUT | -| LUT4 | 138 | LUT | -| CARRY4 | 104 | CarryLogic | -| LUT1 | 66 | LUT | -| IBUF | 65 | IO | +| LUT5 | 956 | LUT | +| CARRY4 | 386 | CarryLogic | +| LUT3 | 169 | LUT | +| LUT2 | 165 | LUT | +| IBUF | 161 | IO | +| LUT6 | 143 | LUT | +| LUT1 | 132 | LUT | +| LUT4 | 78 | LUT | | FDRE | 64 | Flop & Latch | -| LUT2 | 59 | LUT | -| LUT5 | 49 | LUT | | OBUF | 32 | IO | +| DSP48E1 | 6 | Block Arithmetic | | BUFG | 1 | Clock | +----------+------+---------------------+ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log index 6f259ff..52f6a06 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log @@ -10,7 +10,7 @@ ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. source regler.tcl -notrace -create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1260.457 ; gain = 7.594 +create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1259.906 ; gain = 8.973 Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes @@ -23,27 +23,58 @@ WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis b INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 12584 +INFO: [Synth 8-7075] Helper process launched with PID 15440 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43] -WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:97] -WARNING: [Synth 8-6014] Unused sequential element e_k2_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:98] -INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43] +INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:47] +WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:108] +INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:47] +WARNING: [Synth 8-7129] Port TV[31] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[30] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[29] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[28] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[27] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[26] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[25] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[24] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[23] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[22] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[21] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[20] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[19] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[18] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[17] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[16] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[15] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[14] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[13] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[12] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[11] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[10] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1259.906 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -54,47 +85,47 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1259.906 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1259.906 ; gain = 0.000 WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1259.906 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 3 Input 32 Bit Adders := 2 - 2 Input 32 Bit Adders := 1 - 2 Input 31 Bit Adders := 1 + 2 Input 32 Bit Adders := 4 + 3 Input 32 Bit Adders := 1 + 2 Input 31 Bit Adders := 3 +---Registers : - 32 Bit Registers := 2 + 32 Bit Registers := 1 +---Multipliers : - 1x32 Multipliers := 1 + 32x32 Multipliers := 1 +---Muxes : - 2 Input 32 Bit Muxes := 1 - 2 Input 31 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 2 + 2 Input 31 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -111,26 +142,100 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +DSP Report: Generating DSP I_k4, operation Mode is: A*B. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: Generating DSP I_k4, operation Mode is: A*B. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: operator I_k4 is absorbed into DSP I_k4. +DSP Report: Generating DSP u_reg1, operation Mode is: A*B. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: Generating DSP u_reg1, operation Mode is: A*B. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +DSP Report: operator u_reg1 is absorbed into DSP u_reg1. +WARNING: [Synth 8-7129] Port TV[31] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[30] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[29] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[28] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[27] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[26] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[25] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[24] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[23] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[22] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[21] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[20] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[19] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[18] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[17] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[16] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[15] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[14] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[13] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[12] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[11] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[10] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load +WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1259.906 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|regler | A*B | 15 | 15 | - | - | 15 | 0 | 0 | - | - | - | 0 | 0 | +|regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|regler | (PCIN>>17)+A*B | 15 | 15 | - | - | 15 | 0 | 0 | - | - | - | 0 | 0 | +|regler | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|regler | (PCIN>>17)+A*B | 15 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|regler | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1275.953 ; gain = 16.047 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1277.246 ; gain = 17.340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1260.457 ; gain = 0.000 +Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 1308.379 ; gain = 48.473 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -148,37 +253,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -191,42 +296,44 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |BUFG | 1| -|2 |CARRY4 | 104| -|3 |LUT1 | 66| -|4 |LUT2 | 59| -|5 |LUT3 | 182| -|6 |LUT4 | 138| -|7 |LUT5 | 49| -|8 |LUT6 | 186| -|9 |FDRE | 64| -|10 |IBUF | 65| -|11 |OBUF | 32| -+------+-------+------+ ++------+--------+------+ +| |Cell |Count | ++------+--------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 386| +|3 |DSP48E1 | 6| +|4 |LUT1 | 132| +|5 |LUT2 | 165| +|6 |LUT3 | 169| +|7 |LUT4 | 78| +|8 |LUT5 | 956| +|9 |LUT6 | 143| +|10 |FDRE | 64| +|11 |IBUF | 161| +|12 |OBUF | 32| ++------+--------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1274.391 ; gain = 13.934 -Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934 +Synthesis finished with 0 errors, 0 critical warnings and 33 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:37 . Memory (MB): peak = 1322.223 ; gain = 62.316 +Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1322.223 ; gain = 62.316 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1286.504 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1334.242 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 392 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1290.160 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1338.902 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete, checksum: 235c9ea4 +Synth Design complete, checksum: 74f8d27b INFO: [Common 17-83] Releasing license: Synthesis -21 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +21 Infos, 69 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.160 ; gain = 29.703 +synth_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1338.902 ; gain = 78.996 INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri May 13 12:53:45 2022... +INFO: [Common 17-206] Exiting Vivado at Wed May 18 20:51:43 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou index e275498..b081950 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2021.2 (64-bit) # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 -# Start of session at: Fri May 13 12:52:57 2022 -# Process ID: 2508 +# Start of session at: Wed May 18 20:50:48 2022 +# Process ID: 14452 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb index 4653870..5c49ea6 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat index 2ec2275..9bd4ba6 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat @@ -6,7 +6,7 @@ REM Filename : compile.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for compiling the simulation design source files REM -REM Generated by Vivado on Fri May 13 13:48:21 +0200 2022 +REM Generated by Vivado on Wed May 18 20:51:55 +0200 2022 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log index e69de29..82ff074 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log @@ -0,0 +1,6 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pt1' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat index 9818fb3..cb4b6fc 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat @@ -6,7 +6,7 @@ REM Filename : elaborate.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for elaborating the compiled design REM -REM Generated by Vivado on Fri May 13 13:48:23 +0200 2022 +REM Generated by Vivado on Wed May 18 20:51:57 +0200 2022 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 @@ -15,8 +15,8 @@ REM usage: elaborate.bat REM REM **************************************************************************** REM elaborate design -echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" -call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log if "%errorlevel%"=="0" goto SUCCESS if "%errorlevel%"=="1" goto END :END diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log index 1d8ca0a..18f1094 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log @@ -1,11 +1,19 @@ Vivado Simulator v2021.2 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log Using 2 slave threads. Starting static elaboration -WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] -WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] -WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69] Completed static elaboration Starting simulation data flow analysis -ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl index f6215eb..242489a 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl @@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } { } } -run 5 s +run 10 s diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb index ad9dd83..ee3e865 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat index e74d68f..fe4d2b8 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat @@ -6,7 +6,7 @@ REM Filename : simulate.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for simulating the design by launching the simulator REM -REM Generated by Vivado on Fri May 13 12:56:57 +0200 2022 +REM Generated by Vivado on Wed May 18 20:52:00 +0200 2022 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb index 5cb5bb9..66c2d84 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt index ab9565f..e2d8861 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt @@ -1 +1 @@ ---incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "ieee_proposed" -L "secureip" -L "xpm" --snapshot "pwm_test_db_behav" "xil_defaultlib.pwm_test_db" -log "elaborate.log" +--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "pwm_test_db_behav" "xil_defaultlib.pwm_test_db" -log "elaborate.log" diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj index 3e951d3..d0746c4 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c index 336da4d..5efc2da 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c @@ -54,21 +54,20 @@ #endif typedef void (*funcp)(char *, char *); extern int main(int, char**); -IKI_DLLESPEC extern void execute_51(char*, char *); -IKI_DLLESPEC extern void execute_52(char*, char *); -IKI_DLLESPEC extern void execute_46(char*, char *); -IKI_DLLESPEC extern void execute_48(char*, char *); -IKI_DLLESPEC extern void execute_50(char*, char *); +IKI_DLLESPEC extern void execute_13(char*, char *); +IKI_DLLESPEC extern void execute_14(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_12(char*, char *); IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[7] = {(funcp)execute_51, (funcp)execute_52, (funcp)execute_46, (funcp)execute_48, (funcp)execute_50, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; -const int NumRelocateId= 7; +funcp funcTab[6] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_10, (funcp)execute_12, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 6; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 7); - iki_vhdl_file_variable_register(dp + 6536); - iki_vhdl_file_variable_register(dp + 6592); + iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 6); + iki_vhdl_file_variable_register(dp + 6736); + iki_vhdl_file_variable_register(dp + 6792); /*Populate the transaction function pointer field in the whole net structure */ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj index 86d942c..1e05112 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg index a74ace7..95f2909 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem index 0f434c2..df8cd52 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc index d616940..92fc3f8 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx index 11f575e..22e7070 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx @@ -1,8 +1,8 @@ { - crc : 2044015283218523224 , + crc : 5187086932114409812 , ccp_crc : 0 , - cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , + cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , buildDate : "Oct 19 2021" , buildTime : "03:16:22" , linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_behav/xsimk.exe\" \"xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti index dcfb1b2..8666ee4 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type index f7f2085..c8c14f8 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg index 9961c12..38341e3 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe index 55f621f..dda6d49 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log index 5c20574..25fcd30 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log @@ -1,7 +1,4 @@ -Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 53693 +Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 51353 Design successfully loaded -Design Loading Memory Usage: 7256 KB (Peak: 7256 KB) -Design Loading CPU Usage: 15 ms -Simulation completed -Simulation Memory Usage: 7792 KB (Peak: 7792 KB) -Simulation CPU Usage: 15 ms +Design Loading Memory Usage: 7312 KB (Peak: 7312 KB) +Design Loading CPU Usage: 0 ms diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb index c10dde5..1db3529 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb index 1388390..54d8311 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb index 7de8aeb..ed801ef 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index c01d11b..28d488b 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -2,7 +2,6 @@ 2020.2 Oct 19 2021 03:16:22 -C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652442389,vhdl,,,,pwm_test_db,,,,,,,, -C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1651498208,vhdl,,,,pt1,,,,,,,, -C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652437038,vhdl,,,,regler,,,,,,,, -C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd,1652437027,vhdl,,,,wendetangente,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652899813,vhdl,,,,pwm_test_db,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1652899751,vhdl,,,,pt1,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652899626,vhdl,,,,regler,,,,,,,, diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log index e69de29..82ff074 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log @@ -0,0 +1,6 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pt1' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb index b155e40..fbc50c6 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd index 9cfb6ad..2616273 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd @@ -22,8 +22,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -library ieee_proposed; -use ieee_proposed.fixed_pkg.all; + --use IEEE.STD_LOGIC_1164.ALL; @@ -47,21 +46,23 @@ component regler is Port ( clk : in STD_LOGIC; --Clk -> Gibt Abtastzeit vor w : in integer := 0; --Sollwert y : in integer := 0; --Istwert - u : inout integer := 0); --Stellgöße + u : inout integer := 0; --Stellgöße + KR : in integer := 1; -- Verstärkung + T : in integer := 1000; -- Abtastzeit in us + TV : integer := 0; -- Vorhaltezeit für Differenzierer interesannt + TN : in integer := 1); -- Nachstellzeit end component; component pt1 is Port ( clk : in STD_LOGIC; u : in integer; - y : inout integer); + y : inout integer := 0; -- muss vielleicht initalisiert werden vorher!? + a : in integer :=1; + k : in integer := 1); end component; -component wendeTangente is - Port ( a : in sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen - b : in sfixed (7 downto -6); - c : out sfixed (7 downto -6)); -end component; + signal clk : std_logic := '0'; signal clk_100 : std_logic := '0'; @@ -72,11 +73,17 @@ signal y : integer := 0; signal cnt : integer := 0; signal risingEdge : std_logic := '0'; +--Streckenparameter +signal a : integer := 1; +signal k : integer := 1; + +--Reglerparameter +signal KR : integer := 1; -- Verstärkung +signal T : integer := 1000; -- Abtastzeit in ns = 1ms = 1000000ns +signal TV : integer := 0; -- Vorhaltezeit für Differenzierer interesannt +signal TN : integer := 10; -- Nachstellzeit + ---wendetangenten test -signal a : sfixed(7 downto -6) := to_sfixed (-3.125, 7, -6); -signal b : sfixed(7 downto -6) := to_sfixed (5.1111, 7, -6); -signal c : sfixed(7 downto -6); begin @@ -84,7 +91,11 @@ uut_regler: regler PORT MAP ( clk => clk, w => w, y => y, - u => u + u => u, + KR => KR, + T => T, + TV => TV, + TN => TN ); uut_pt1: pt1 PORT MAP ( @@ -93,11 +104,6 @@ uut_pt1: pt1 PORT MAP ( y => y ); -uutWendeTangente: wendeTangente PORT MAP( - a => a, - b => b, - c => c -); --generate clock clk <= not clk after 5 us; @@ -105,7 +111,7 @@ clk <= not clk after 5 us; process begin - w <= 1000000; + w <= 100000; -- if rising_edge(clk) and ( cnt >= 100) then -- clk_100 <= not clk_100; @@ -116,7 +122,7 @@ begin cnt <= cnt+1; risingEdge <= '1'; clk_100 <= '0'; - --a <= a + to_sfixed(1.111, 7, -6); + end if; if clk = '0' then diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd index 1e754df..b33063e 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd @@ -35,16 +35,19 @@ entity pt1 is Port ( clk : in STD_LOGIC; u : in integer := 0; - y : inout integer := 0); -- muss vielleicht initalisiert werden vorher!? + y : inout integer := 0; -- muss vielleicht initalisiert werden vorher!? + a : in integer := 1; + k : in integer := 1); end pt1; architecture Behavioral of pt1 is -signal stepWidth : integer := 10000; -- in ns -> 10 us später berechnet aus Clk und Prescaler +signal stepWidth : integer := 10; -- in us -> 10 us später berechnet aus Clk und Prescaler +signal prescaler : integer := 1000000; -- prescaler für Zeit -- Konstanten Streckenparameter -signal a : integer := 1; -signal k : integer := 2; +--signal a : integer := 1; +--signal k : integer := 1; -- signal u : integer := 100000; -- Eingangswert Strecke jetzt u aus port diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd index d265a00..97dae80 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd @@ -37,20 +37,25 @@ entity regler is Port ( clk : in STD_LOGIC; --Clk -> Gibt abtastzeit vor w : in integer := 0; --Sollwert y : in integer := 0; --Istwert - u : inout integer := 0); --Stellgöße + u : inout integer := 0; --Stellgöße + KR : in integer := 1; -- Verstärkung + T : in integer := 1000; -- Abtastzeit in us + TV : integer := 0; -- Vorhaltezeit für Differenzierer interesannt + TN : in integer := 1); -- Nachstellzeit end regler; architecture Behavioral of regler is --signal stepWidth : integer := 1; -- 10 us später berechnet aus Clk und Prescaler +signal prescaler : integer :=1000000; -- prescaler für Zeit -- Parameter aus Sprungantwort etc. -signal KR : integer := 1; -- Verstärkung -signal T : integer := 1; -- Abtastzeit in ns = 1ms = 1000000ns -signal TV : integer := 0; -- Vorhaltezeit für Differenzierer interesannt -signal TN : integer := 10; -- Nachstellzeit +--signal KR : integer := 1; -- Verstärkung +--signal T : integer := 1000; -- Abtastzeit in ns = 1ms = 1000000ns +--signal TV : integer := 0; -- Vorhaltezeit für Differenzierer interesannt +--signal TN : integer := 10; -- Nachstellzeit -- Konstanten Reglerparameter --signal a1 : integer ; @@ -71,6 +76,9 @@ signal e_k1 : integer := 0; -- letzte "" signal e_k2 : integer := 0; -- vorletzte "" +signal I_k : integer := 0; -- I-Anteil + + -- signal u : integer := 100000; -- Eingangswert Strecke --signal x : integer := 0; -- Ausgangssignal Strecke -> Stellgröße @@ -81,7 +89,10 @@ begin process(clk) - variable e_k : integer; + + variable e_k : integer := 0; -- aktuelle Reglerabweichung + --variable I_k : integer := 0; -- I-Anteil + --variable I_k1 : integer := 0; -- letzer I-Anteil begin @@ -93,11 +104,24 @@ process(clk) -- b1 <= -KR *(1 - T / TN + 2 * TV / T ); -- b2 <= KR * TV/T; - --u <= e; -- Regler überbrücken! - e_k := w - y; --Reglerdifferenzbilden - u <= (a1*u+b0*e_k+b1*e_k1+b2*e_k2)/1000; --Stellgröße u berechnen - e_k2 <= e_k1; - e_k1 <= e_k; + + e_k := w - y; --Reglerdifferenzbilden + + + -- PID-Regler --------------------------------------- + --u <= (a1*u+b0*e_k+b1*e_k1+b2*e_k2)/1000; --Stellgröße u berechnen, PID-Regler + + --e_k2 <= e_k1; + --e_k1 <= e_k; + + -- PI-Regler ---------------------------------------- + I_k <= I_k + T * 1 / TN * e_k / prescaler; -- I-Anteil berechnen + u <= KR * e_k + I_k; + + ----------------------------------------------------- + --u <= w; -- Regler überbrücken! + + end if; end process; diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd deleted file mode 100644 index a0f9a03..0000000 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd +++ /dev/null @@ -1,61 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13.05.2022 11:46:14 --- Design Name: --- Module Name: wendeTangente - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -library ieee_proposed; -use ieee_proposed.fixed_pkg.all; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity wendeTangente is - Port ( a : in sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen - b : in sfixed (7 downto -6); - c : out sfixed (7 downto -6)); -end wendeTangente; - -architecture Behavioral of wendeTangente is - - ---signal a, b, c : sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen - - -begin - -process(a,b) - -begin - - c <= a+b; - - -end process; - - -end Behavioral; diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr index cf9e0d0..15494f8 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr @@ -56,7 +56,7 @@