diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc index 867ac97..c571276 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc @@ -1,4 +1,4 @@ version:1 57656254616c6b5472616e736d697373696f6e417474656d70746564:13 -6d6f64655f636f756e7465727c4755494d6f6465:40 +6d6f64655f636f756e7465727c4755494d6f6465:42 eof: diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf index 095e565..225609d 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf @@ -38,7 +38,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353673:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313336392e3636384d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3130392e3431384d42:00:00 -eof:3780437457 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353473:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313337342e3832384d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3131332e3831364d42:00:00 +eof:1125365045 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_110.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_110.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_110.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_111.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_111.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_111.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_112.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_112.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_112.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_113.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_113.xml new file mode 100644 index 0000000..0a9890c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_113.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst index 260d1d6..5abb813 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml index 64a0032..d615c54 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf index d3c1316..ead5a0f 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf @@ -13,7 +13,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313731:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313736:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 @@ -28,4 +28,4 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3035343861623234333065633433623139386531656634383534326531333964:506172656e742050412070726f6a656374204944:00 -eof:1339287396 +eof:660781908 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp index d625ed8..47e93d8 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds index 67820fc..b1c8c25 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds @@ -2,8 +2,8 @@ # Vivado v2021.2 (64-bit) # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 -# Start of session at: Tue May 31 21:51:15 2022 -# Process ID: 7140 +# Start of session at: Wed Jun 1 16:02:24 2022 +# Process ID: 11440 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds @@ -11,7 +11,7 @@ # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB #----------------------------------------------------------- source regler.tcl -notrace -create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1260.250 ; gain = 7.859 +create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.012 ; gain = 6.973 Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes @@ -24,9 +24,9 @@ WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis b INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 7236 +INFO: [Synth 8-7075] Helper process launched with PID 14456 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.012 ; gain = 0.000 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51] WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115] @@ -43,18 +43,18 @@ WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.012 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.012 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.012 ; gain = 0.000 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1261.012 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -65,31 +65,31 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1277.531 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1279.703 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1277.531 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1279.703 ; gain = 0.000 WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -223,7 +223,7 @@ WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting @@ -271,19 +271,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.168 ; gain = 29.918 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1291.957 ; gain = 30.945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1300.332 ; gain = 40.082 +Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1302.121 ; gain = 41.109 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 1358.793 ; gain = 98.543 +Finished Technology Mapping : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.969 ; gain = 99.957 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -301,37 +301,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished IO Insertion : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -361,19 +361,19 @@ Report Cell Usage: |12 |OBUF | 64| +------+--------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 1369.668 ; gain = 92.137 -Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:39 ; elapsed = 00:00:47 . Memory (MB): peak = 1374.828 ; gain = 95.125 +Synthesis Optimization Complete : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.193 . Memory (MB): peak = 1377.176 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.235 . Memory (MB): peak = 1386.875 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1377.863 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1390.559 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. @@ -381,7 +381,7 @@ Synth Design complete, checksum: 6d8170b6 INFO: [Common 17-83] Releasing license: Synthesis 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 1377.863 ; gain = 117.613 +synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 1390.559 ; gain = 129.547 INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Tue May 31 21:52:26 2022... +INFO: [Common 17-206] Exiting Vivado at Wed Jun 1 16:03:33 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt index 71d1602..fb66759 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 -| Date : Tue May 31 21:52:26 2022 +| Date : Wed Jun 1 16:03:33 2022 | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | Command : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | Design : regler diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log index c17db77..06f37d4 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log @@ -10,7 +10,7 @@ ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. source regler.tcl -notrace -create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1260.250 ; gain = 7.859 +create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.012 ; gain = 6.973 Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes @@ -23,9 +23,9 @@ WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis b INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 7236 +INFO: [Synth 8-7075] Helper process launched with PID 14456 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.012 ; gain = 0.000 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51] WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115] @@ -42,18 +42,18 @@ WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.012 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.012 ; gain = 0.000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.012 ; gain = 0.000 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1260.250 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1261.012 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -64,31 +64,31 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1277.531 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1279.703 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1277.531 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1279.703 ; gain = 0.000 WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -222,7 +222,7 @@ WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1277.531 ; gain = 17.281 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1279.703 ; gain = 18.691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting @@ -270,19 +270,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.168 ; gain = 29.918 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1291.957 ; gain = 30.945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1300.332 ; gain = 40.082 +Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1302.121 ; gain = 41.109 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 1358.793 ; gain = 98.543 +Finished Technology Mapping : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.969 ; gain = 99.957 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -300,37 +300,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished IO Insertion : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -360,19 +360,19 @@ Report Cell Usage: |12 |OBUF | 64| +------+--------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 1369.668 ; gain = 92.137 -Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:39 ; elapsed = 00:00:47 . Memory (MB): peak = 1374.828 ; gain = 95.125 +Synthesis Optimization Complete : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.193 . Memory (MB): peak = 1377.176 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.235 . Memory (MB): peak = 1386.875 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1377.863 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1390.559 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. @@ -380,7 +380,7 @@ Synth Design complete, checksum: 6d8170b6 INFO: [Common 17-83] Releasing license: Synthesis 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 1377.863 ; gain = 117.613 +synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 1390.559 ; gain = 129.547 INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Tue May 31 21:52:26 2022... +INFO: [Common 17-206] Exiting Vivado at Wed Jun 1 16:03:33 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou index 119616a..406ada6 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2021.2 (64-bit) # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 -# Start of session at: Tue May 31 21:51:15 2022 -# Process ID: 7140 +# Start of session at: Wed Jun 1 16:02:24 2022 +# Process ID: 11440 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb index 9c6ed1e..c77368f 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat index 0d51a88..583db34 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat @@ -6,7 +6,7 @@ REM Filename : compile.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for compiling the simulation design source files REM -REM Generated by Vivado on Tue May 31 21:54:27 +0200 2022 +REM Generated by Vivado on Wed Jun 01 16:04:36 +0200 2022 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log index 8edd643..89afd59 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log @@ -1,2 +1,2 @@ -INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib -INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'autoTuning' diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat index 5116bf4..a5c9ca8 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat @@ -6,7 +6,7 @@ REM Filename : elaborate.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for elaborating the compiled design REM -REM Generated by Vivado on Tue May 31 21:54:29 +0200 2022 +REM Generated by Vivado on Wed Jun 01 16:04:38 +0200 2022 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb index 2b25258..2ab52ce 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat index ccc5bc0..d2d0441 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat @@ -6,7 +6,7 @@ REM Filename : simulate.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for simulating the design by launching the simulator REM -REM Generated by Vivado on Tue May 31 21:54:32 +0200 2022 +REM Generated by Vivado on Wed Jun 01 16:04:41 +0200 2022 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log index e69de29..3a14ee6 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1 @@ +Time resolution is 1 ps diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj index 99d63e5..369ff06 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c index 0594c15..62f590a 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c @@ -54,22 +54,23 @@ #endif typedef void (*funcp)(char *, char *); extern int main(int, char**); -IKI_DLLESPEC extern void execute_52(char*, char *); IKI_DLLESPEC extern void execute_53(char*, char *); -IKI_DLLESPEC extern void execute_47(char*, char *); -IKI_DLLESPEC extern void execute_49(char*, char *); -IKI_DLLESPEC extern void execute_51(char*, char *); +IKI_DLLESPEC extern void execute_54(char*, char *); +IKI_DLLESPEC extern void execute_48(char*, char *); +IKI_DLLESPEC extern void execute_50(char*, char *); +IKI_DLLESPEC extern void execute_52(char*, char *); IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[8] = {(funcp)execute_52, (funcp)execute_53, (funcp)execute_47, (funcp)execute_49, (funcp)execute_51, (funcp)transaction_0, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; -const int NumRelocateId= 8; +IKI_DLLESPEC extern void transaction_16(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[9] = {(funcp)execute_53, (funcp)execute_54, (funcp)execute_48, (funcp)execute_50, (funcp)execute_52, (funcp)transaction_0, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_16}; +const int NumRelocateId= 9; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 8); - iki_vhdl_file_variable_register(dp + 6952); - iki_vhdl_file_variable_register(dp + 7008); + iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 9); + iki_vhdl_file_variable_register(dp + 6992); + iki_vhdl_file_variable_register(dp + 7048); /*Populate the transaction function pointer field in the whole net structure */ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj index 12f622e..ff582bd 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg index 9976d2f..de188ab 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem index 30809e8..c8727a0 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc index 0e0f117..91b8d25 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx index a9901a6..145cef6 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx @@ -1,6 +1,6 @@ { - crc : 15251868591865205496 , + crc : 8097898048764610212 , ccp_crc : 0 , cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , buildDate : "Oct 19 2021" , diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti index 7f777a1..e5db668 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type index 6a0a6ca..69ad30a 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg index 0b9644f..7270def 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini index 6e943d7..f57c737 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini @@ -28,8 +28,8 @@ VARIABLE_PROTOINST_FILTER=true SCOPE_NAME_COLUMN_WIDTH=157 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 -OBJECT_NAME_COLUMN_WIDTH=156 -OBJECT_VALUE_COLUMN_WIDTH=49 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 OBJECT_DATA_TYPE_COLUMN_WIDTH=75 PROCESS_NAME_COLUMN_WIDTH=75 PROCESS_TYPE_COLUMN_WIDTH=75 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe index cc0fe8a..f13b8f7 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log index 2d1611c..8cfc0f3 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log @@ -1,4 +1,7 @@ -Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 50859 +Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 57302 Design successfully loaded -Design Loading Memory Usage: 7440 KB (Peak: 7440 KB) +Design Loading Memory Usage: 7444 KB (Peak: 7444 KB) Design Loading CPU Usage: 15 ms +Simulation completed +Simulation Memory Usage: 15968 KB (Peak: 15968 KB) +Simulation CPU Usage: 9640 ms diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/autotuning.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/autotuning.vdb index df096c1..56e911c 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/autotuning.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/autotuning.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb index 1eb35ca..bd46da1 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb index c5ecf6d..85a06c8 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb index 8969227..c274731 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index 3832264..5a5b9e2 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -2,7 +2,7 @@ 2020.2 Oct 19 2021 03:16:22 -C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1654026861,vhdl,,,,pwm_test_db,,,,,,,, -C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd,1654026641,vhdl,,,,autotuning,,,,,,,, -C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1653978411,vhdl,,,,pt1,,,,,,,, -C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1653978349,vhdl,,,,regler,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1654085243,vhdl,,,,pwm_test_db,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd,1654092136,vhdl,,,,autotuning,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1654085243,vhdl,,,,pt1,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1654085243,vhdl,,,,regler,,,,,,,, diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log index 8edd643..89afd59 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log @@ -1,2 +1,2 @@ -INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib -INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'autoTuning' diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb index 3a6973b..dde6834 100644 Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd index 4b6ad23..613d028 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd @@ -116,6 +116,8 @@ if(rising_edge(clk)) then end if; else + + if (falling_edge(start_Tuning)) then -- autoTuning beenden regler_bruecken <= '0'; counter := to_signed(0, 64); @@ -126,7 +128,7 @@ if(rising_edge(clk)) then dt := duration / to_signed(2000, 64); --schrittweite - for i in 1 to 2000 loop + for i in 1 to 1999 loop steigung_last := steigung; --steigung := (data(i) - data(i-1)) / dt; --"Richtig" steigung := (data(i) - data(i-1)); @@ -138,7 +140,7 @@ if(rising_edge(clk)) then -- y = mx + b b := data(data_pos_wendetangente) - steigung * to_signed(data_pos_wendetangente, 32); - Ks := data(2000); + Ks := data(1999); Tu := -b * dt / steigung; Tg := (Ks - b) * dt / steigung - Tu; @@ -148,7 +150,7 @@ if(rising_edge(clk)) then TV <= to_signed(0, 10); TN <= 4 * Tu; - + end if; end if; end if; diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr index d0208d9..727f0b4 100644 --- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr @@ -56,7 +56,7 @@