diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
index c9aa8fb..b4dd20c 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
@@ -1,4 +1,4 @@
 version:1
 57656254616c6b5472616e736d697373696f6e417474656d70746564:13
-6d6f64655f636f756e7465727c4755494d6f6465:28
+6d6f64655f636f756e7465727c4755494d6f6465:30
 eof:
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
index 737649b..27b1fd4 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
@@ -6,7 +6,7 @@ REM Filename    : compile.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for compiling the simulation design source files
 REM
-REM Generated by Vivado on Wed May 18 21:31:28 +0200 2022
+REM Generated by Vivado on Mon May 23 13:37:07 +0200 2022
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
index 52cff26..1efc2de 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
@@ -6,7 +6,7 @@ REM Filename    : elaborate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for elaborating the compiled design
 REM
-REM Generated by Vivado on Wed May 18 21:31:29 +0200 2022
+REM Generated by Vivado on Mon May 23 13:37:09 +0200 2022
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb
index ad4047b..d1834c3 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat
index c177709..247afc7 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat
@@ -6,7 +6,7 @@ REM Filename    : simulate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for simulating the design by launching the simulator
 REM
-REM Generated by Vivado on Wed May 18 21:31:32 +0200 2022
+REM Generated by Vivado on Mon May 23 13:37:11 +0200 2022
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log
index e69de29..3a14ee6 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj
index 37ffaf7..a1f7663 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg
index 697c33a..112687a 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem
index dd44aa1..cb1bbfe 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx
index 01ab5e7..2f143e4 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx
@@ -1,6 +1,6 @@
 
 { 
-    crc :  7823678164688294818  , 
+    crc :  17288891363008981436  , 
     ccp_crc :  0  , 
     cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , 
     buildDate : "Oct 19 2021" , 
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti
index f416042..425dbae 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type
index 5cc91be..b140331 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg
index b8495fa..ef160f4 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe
index 0487f33..98c0d26 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
index fea1dc8..e3dead7 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
@@ -1,4 +1,7 @@
-Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 55344
+Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 51806
 Design successfully loaded
-Design Loading Memory Usage: 7292 KB (Peak: 7292 KB)
-Design Loading CPU Usage: 15 ms
+Design Loading Memory Usage: 7288 KB (Peak: 7288 KB)
+Design Loading CPU Usage: 0 ms
+Simulation completed
+Simulation Memory Usage: 15780 KB (Peak: 15780 KB)
+Simulation CPU Usage: 1953 ms
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb
index e1838ee..6f75511 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
index 68248ae..a8a79cd 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -2,6 +2,6 @@
 2020.2
 Oct 19 2021
 03:16:22
-C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652902272,vhdl,,,,pwm_test_db,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1653305822,vhdl,,,,pwm_test_db,,,,,,,,
 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1652901752,vhdl,,,,pt1,,,,,,,,
 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652901648,vhdl,,,,regler,,,,,,,,
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
index aca90db..4f7c103 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
@@ -116,7 +116,8 @@ clk <= not clk after 5 us;
 
 process 
 begin
-    w <= 100000000;
+    --w <= 100000000;
+    w <= 1000000; --muss >= 1000000 sein!
     
 --    if rising_edge(clk) and ( cnt >= 100) then
 --        clk_100 <= not clk_100;
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
index 55bbf01..3e3c184 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
@@ -56,7 +56,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="zybo-z7-10"/>
-    <Option Name="WTXSimLaunchSim" Val="145"/>
+    <Option Name="WTXSimLaunchSim" Val="148"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -249,9 +249,7 @@
   <Runs Version="1" Minor="15">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
@@ -260,9 +258,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
index a7f062a..23036be 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
@@ -2,10 +2,10 @@
 # Vivado v2021.2 (64-bit)
 # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Wed May 18 19:29:49 2022
-# Process ID: 18960
+# Start of session at: Mon May 23 20:31:11 2022
+# Process ID: 10504
 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7676 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
 # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
 # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
 # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
@@ -13,140 +13,3 @@
 start_gui
 open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
 update_compile_order -fileset sources_1
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]
-save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
index 8c302bc..3bcbdc0 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
@@ -2,10 +2,10 @@
 # Vivado v2021.2 (64-bit)
 # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Wed May 18 19:29:49 2022
-# Process ID: 18960
+# Start of session at: Mon May 23 20:31:11 2022
+# Process ID: 10504
 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7676 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
 # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
 # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
 # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
@@ -66,1659 +66,5 @@ Finished scanning sources
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 INFO: [IP_Flow 19-1704] No user IP repositories specified
 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
-open_project: Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 1251.465 ; gain = 0.000
+open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000
 update_compile_order -fileset sources_1
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-launch_runs synth_1 -jobs 6
-[Wed May 18 19:58:12 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-xsim: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 1251.465 ; gain = 0.000
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1251.465 ; gain = 0.000
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1251.465 ; gain = 0.000
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:04:35 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1254.031 ; gain = 0.000
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:09:08 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-reset_run synth_1
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:09:25 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1255.961 ; gain = 0.000
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:13:37 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1257.480 ; gain = 0.000
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:15:34 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:19:22 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:22:54 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1257.480 ; gain = 0.000
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:30:29 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1295.145 ; gain = 20.746
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1295.742 ; gain = 0.598
-set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]
-save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1320.121 ; gain = 0.000
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1381.312 ; gain = 25.016
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 20:50:45 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1388.887 ; gain = 7.539
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 21:06:16 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1391.688 ; gain = 2.801
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1391.777 ; gain = 0.090
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1392.230 ; gain = 0.430
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1393.195 ; gain = 0.777
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-ERROR: File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd Line: 118 : Division by zero is not allowed.
-Time: 986 us  Iteration: 1  Process: /pwm_test_db/uut_regler/line__91
-  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
-
-HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:118
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1393.648 ; gain = 0.453
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 21:16:15 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1394.277 ; gain = 0.629
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1394.953 ; gain = 0.676
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Wed May 18 21:23:02 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1395.184 ; gain = 0.207
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1396.844 ; gain = 0.105
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 10 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 10 s
-launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1408.062 ; gain = 11.219
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.jou
new file mode 100644
index 0000000..c45f327
--- /dev/null
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.jou
@@ -0,0 +1,153 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Wed May 18 19:29:49 2022
+# Process ID: 18960
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+update_compile_order -fileset sources_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.log
new file mode 100644
index 0000000..05ae7b5
--- /dev/null
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.log
@@ -0,0 +1,1728 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Wed May 18 19:29:49 2022
+# Process ID: 18960
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
+Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
+INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
+Scanning sources...
+Finished scanning sources
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+open_project: Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 1251.465 ; gain = 0.000
+update_compile_order -fileset sources_1
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+launch_runs synth_1 -jobs 6
+[Wed May 18 19:58:12 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+xsim: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 1251.465 ; gain = 0.000
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1251.465 ; gain = 0.000
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1251.465 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:04:35 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1254.031 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:09:08 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+reset_run synth_1
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:09:25 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1255.961 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:13:37 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1257.480 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:15:34 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:19:22 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:22:54 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1257.480 ; gain = 0.000
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:30:29 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1295.145 ; gain = 20.746
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1295.742 ; gain = 0.598
+set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1320.121 ; gain = 0.000
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1381.312 ; gain = 25.016
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 20:50:45 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1388.887 ; gain = 7.539
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 21:06:16 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1391.688 ; gain = 2.801
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1391.777 ; gain = 0.090
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1392.230 ; gain = 0.430
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1393.195 ; gain = 0.777
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+ERROR: File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd Line: 118 : Division by zero is not allowed.
+Time: 986 us  Iteration: 1  Process: /pwm_test_db/uut_regler/line__91
+  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
+
+HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:118
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1393.648 ; gain = 0.453
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 21:16:15 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1394.277 ; gain = 0.629
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1394.953 ; gain = 0.676
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Wed May 18 21:23:02 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1395.184 ; gain = 0.207
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1396.844 ; gain = 0.105
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 10 s
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 10 s
+launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1408.062 ; gain = 11.219
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+exit
+INFO: [Common 17-206] Exiting Vivado at Wed May 18 21:41:31 2022...
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3672.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3672.backup.jou
deleted file mode 100644
index acae59a..0000000
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3672.backup.jou
+++ /dev/null
@@ -1,17 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2021.2 (64-bit)
-# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
-# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Fri May 13 11:28:18 2022
-# Process ID: 3672
-# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11452 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
-# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
-# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
-#-----------------------------------------------------------
-start_gui
-open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
-update_compile_order -fileset sources_1
-launch_runs impl_1 -jobs 6
-ns synth_1 -jobs 6
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3672.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3672.backup.log
deleted file mode 100644
index 6ff6dea..0000000
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3672.backup.log
+++ /dev/null
@@ -1,84 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2021.2 (64-bit)
-# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
-# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Fri May 13 11:28:18 2022
-# Process ID: 3672
-# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11452 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
-# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
-# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
-#-----------------------------------------------------------
-start_gui
-open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
-INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
-Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
-WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
-INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save.
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save.
-INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
-INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
-WARNING: [Project 1-312] File not found as 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp'; using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp' instead.
-Scanning sources...
-Finished scanning sources
-WARNING: [Project 1-312] File not found as 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp'; using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp' instead.
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
-open_project: Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 1576.332 ; gain = 0.000
-update_compile_order -fileset sources_1
-WARNING: [Common 17-9] Error reading message records.
-WARNING: [Common 17-9] Error reading message records.
-WARNING: [Common 17-9] Error reading message records.
-launch_runs impl_1 -jobs 6
-[Fri May 13 11:32:24 2022] Launched impl_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log
-Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Fri May 13 11:29:15 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid18360.str b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid10504.str
similarity index 72%
rename from StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid18360.str
rename to StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid10504.str
index b1c2287..96588b9 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid18360.str
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid10504.str
@@ -4,11 +4,11 @@ Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
 SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
 IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
 
-Process ID (PID): 18360
+Process ID (PID): 10504
 License: Customer
 Mode: GUI Mode
 
-Current time: 	Fri May 13 11:28:40 CEST 2022
+Current time: 	Mon May 23 20:31:24 CEST 2022
 Time zone: 	Central European Standard Time (Europe/Berlin)
 
 OS: Windows 10
@@ -48,7 +48,7 @@ Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/da
 PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
 Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
 Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
-Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-18360-DESKTOP-PAACOM8
+Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-10504-DESKTOP-PAACOM8
 
 Xilinx Environment Variables
 ----------------------------
@@ -61,16 +61,15 @@ XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
 XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
 
 
-GUI allocated memory:	256 MB
+GUI allocated memory:	319 MB
 GUI max memory:		3,072 MB
-Engine allocated memory: 1,262 MB
+Engine allocated memory: 1,307 MB
 
 Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 
 */
 
 // TclEventType: START_GUI
-// WARNING: HEventQueue.dispatchEvent() is taking  1129 ms.
 // Tcl Message: start_gui 
 // TclEventType: PROJECT_OPEN_DIALOG
 // Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 
@@ -78,12 +77,10 @@ Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 // TclEventType: FLOW_ADDED
 // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
 // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 55 MB. Current time: 5/13/22, 11:28:41 AM CEST
+// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 55 MB. Current time: 5/23/22, 8:31:25 PM CEST
 // TclEventType: MSGMGR_MOVEMSG
 // TclEventType: FILE_SET_CHANGE
 // TclEventType: FILE_SET_NEW
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
 // TclEventType: RUN_CURRENT
 // TclEventType: PROJECT_DASHBOARD_NEW
 // TclEventType: PROJECT_DASHBOARD_GADGET_NEW
@@ -99,43 +96,17 @@ Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 // TclEventType: PROJECT_DASHBOARD_GADGET_NEW
 // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
 // TclEventType: PROJECT_NEW
+// [GUI Memory]: 70 MB (+71283kb) [00:00:14]
+// [Engine Memory]: 1,307 MB (+1219381kb) [00:00:14]
+// [GUI Memory]: 109 MB (+37180kb) [00:00:15]
+// WARNING: HEventQueue.dispatchEvent() is taking  2465 ms.
 // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
 // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
+// Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 
 // Tcl Message: Scanning sources... Finished scanning sources 
-// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified 
-// TclEventType: PROJECT_NEW
-// [GUI Memory]: 78 MB (+79097kb) [00:00:27]
-// [Engine Memory]: 1,262 MB (+1171794kb) [00:00:27]
-// WARNING: HEventQueue.dispatchEvent() is taking  5264 ms.
-// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
-// [GUI Memory]: 105 MB (+24789kb) [00:00:32]
-// Tcl Message: open_project: Time (s): cpu = 00:00:37 ; elapsed = 00:00:17 . Memory (MB): peak = 1250.551 ; gain = 0.000 
+// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
+// [GUI Memory]: 117 MB (+2679kb) [00:00:16]
 // Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
+// Tcl Message: open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000 
 dismissDialog("Open Project"); // bA
 // Tcl Message: update_compile_order -fileset sources_1 
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_STATUS_CHANGE
-// [GUI Memory]: 111 MB (+540kb) [00:01:34]
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 205 seconds
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs impl_1 -jobs 6 
-// Tcl Message: [Fri May 13 11:32:24 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log 
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:32:53 AM CEST
-// TclEventType: RUN_FAILED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 58 seconds
-selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a
-// 'c' command handler elapsed time: 59 seconds
-// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:33:24 AM CEST
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid18960.str b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid18960.str
deleted file mode 100644
index 39ca81b..0000000
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid18960.str
+++ /dev/null
@@ -1,5030 +0,0 @@
-/*
-
-Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
-SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
-IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
-
-Process ID (PID): 18960
-License: Customer
-Mode: GUI Mode
-
-Current time: 	Wed May 18 19:30:05 CEST 2022
-Time zone: 	Central European Standard Time (Europe/Berlin)
-
-OS: Windows 10
-OS Version: 10.0
-OS Architecture: amd64
-Available processors (cores): 12
-
-Screen size: 1920x1080
-Screen resolution (DPI): 100
-Available screens: 2
-Default font: family=Dialog,name=Dialog,style=plain,size=12
-Scale size: 12
-
-Java version: 	11.0.11 64-bit
-Java home: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9
-Java executable: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe
-Java arguments: 	[-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
-Java initial memory (-Xms): 	256 MB
-Java maximum memory (-Xmx):	 3 GB
-
-
-User name: 	Felix
-User home directory: C:/Users/Felix
-User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-User country: 	DE
-User language: 	de
-User locale: 	de_DE
-
-RDI_BASEROOT: C:/Xilinx/Vivado
-HDI_APPROOT: C:/Xilinx/Vivado/2021.2
-RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data
-RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin
-
-Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml
-Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/
-Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts
-PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
-Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
-Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-18960-DESKTOP-PAACOM8
-
-Xilinx Environment Variables
-----------------------------
-TWINCATSDK: C:\TwinCAT\3.1\SDK\
-XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
-XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
-XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2
-XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2
-XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
-XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
-
-
-GUI allocated memory:	256 MB
-GUI max memory:		3,072 MB
-Engine allocated memory: 1,269 MB
-
-Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-
-*/
-
-// TclEventType: START_GUI
-// Tcl Message: start_gui 
-// TclEventType: PROJECT_OPEN_DIALOG
-// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 
-// TclEventType: DEBUG_PROBE_SET_CHANGE
-// TclEventType: FLOW_ADDED
-// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
-// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 55 MB. Current time: 5/18/22, 7:30:06 PM CEST
-// TclEventType: MSGMGR_MOVEMSG
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: FILE_SET_NEW
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_CURRENT
-// TclEventType: PROJECT_DASHBOARD_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_NEW
-// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
-// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 
-// Tcl Message: Scanning sources... Finished scanning sources 
-// TclEventType: PROJECT_NEW
-// [GUI Memory]: 77 MB (+77943kb) [00:00:17]
-// [Engine Memory]: 1,269 MB (+1178896kb) [00:00:17]
-// WARNING: HEventQueue.dispatchEvent() is taking  3307 ms.
-// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
-// Tcl Message: open_project: Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 1251.465 ; gain = 0.000 
-// [GUI Memory]: 98 MB (+18139kb) [00:00:20]
-// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
-dismissDialog("Open Project"); // bA
-// Tcl Message: update_compile_order -fileset sources_1 
-// [GUI Memory]: 125 MB (+22967kb) [00:00:25]
-// PAPropertyPanels.initPanels (pwm_test.vhd) elapsed time: 0.3s
-// Elapsed time: 25 seconds
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false, false, false, false, false, true); // D - Double Click
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D
-// WARNING: HEventQueue.dispatchEvent() is taking  4107 ms.
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false); // D
-// [GUI Memory]: 133 MB (+2284kb) [00:00:52]
-// Elapsed time: 10 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 1); // m
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false, false, false, false, false, true); // D - Double Click
-dismissDialog("Opening Editor"); // bA
-// Elapsed time: 118 seconds
-selectCodeEditor("pwm_test.vhd", 229, 337); // be
-selectCodeEditor("pwm_test.vhd", 84, 362); // be
-selectCodeEditor("pwm_test.vhd", 348, 361); // be
-selectCodeEditor("pwm_test.vhd", 285, 293); // be
-selectCodeEditor("pwm_test.vhd", 271, 312); // be
-selectCodeEditor("pwm_test.vhd", 94, 265); // be
-selectCodeEditor("pwm_test.vhd", 96, 263); // be
-selectCodeEditor("pwm_test.vhd", 7, 95); // be
-selectCodeEditor("pwm_test.vhd", 209, 290); // be
-// Elapsed time: 49 seconds
-selectCodeEditor("pwm_test.vhd", 93, 197); // be
-selectCodeEditor("pwm_test.vhd", 89, 182); // be
-// Elapsed time: 223 seconds
-selectCodeEditor("pwm_test.vhd", 290, 316); // be
-selectCodeEditor("pwm_test.vhd", 182, 210); // be
-selectCodeEditor("pwm_test.vhd", 182, 210, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 498, 297); // be
-// Elapsed time: 60 seconds
-selectCodeEditor("pwm_test.vhd", 162, 111); // be
-selectCodeEditor("pwm_test.vhd", 162, 111, false, false, false, false, true); // be - Double Click
-// Elapsed time: 21 seconds
-selectCodeEditor("pwm_test.vhd", 180, 164); // be
-selectCodeEditor("pwm_test.vhd", 541, 273); // be
-selectCodeEditor("pwm_test.vhd", 170, 154); // be
-selectCodeEditor("pwm_test.vhd", 228, 416); // be
-// Elapsed time: 22 seconds
-selectCodeEditor("pwm_test.vhd", 95, 266); // be
-selectCodeEditor("pwm_test.vhd", 96, 266); // be
-selectCodeEditor("pwm_test.vhd", 138, 280); // be
-selectCodeEditor("pwm_test.vhd", 97, 281); // be
-selectCodeEditor("pwm_test.vhd", 131, 277); // be
-selectCodeEditor("pwm_test.vhd", 211, 177); // be
-// Elapsed time: 116 seconds
-selectCodeEditor("pwm_test.vhd", 163, 296); // be
-selectCodeEditor("pwm_test.vhd", 135, 298); // be
-selectCodeEditor("pwm_test.vhd", 287, 296); // be
-selectCodeEditor("pwm_test.vhd", 222, 333); // be
-selectCodeEditor("pwm_test.vhd", 111, 369); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'v'); // be
-selectCodeEditor("pwm_test.vhd", 116, 353); // be
-// Elapsed time: 15 seconds
-selectCodeEditor("pwm_test.vhd", 94, 420); // be
-selectCodeEditor("pwm_test.vhd", 88, 416); // be
-selectCodeEditor("pwm_test.vhd", 393, 266); // be
-selectCodeEditor("pwm_test.vhd", 358, 264); // be
-// Elapsed time: 19 seconds
-selectCodeEditor("pwm_test.vhd", 392, 426); // be
-selectCodeEditor("pwm_test.vhd", 126, 280); // be
-selectCodeEditor("pwm_test.vhd", 119, 96); // be
-// Elapsed time: 33 seconds
-selectCodeEditor("pwm_test.vhd", 129, 378); // be
-// Elapsed time: 49 seconds
-selectCodeEditor("pwm_test.vhd", 124, 388); // be
-// Elapsed time: 12 seconds
-selectCodeEditor("pwm_test.vhd", 225, 376); // be
-selectCodeEditor("pwm_test.vhd", 225, 376, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 263, 380); // be
-selectCodeEditor("pwm_test.vhd", 181, 95); // be
-selectCodeEditor("pwm_test.vhd", 227, 65); // be
-selectCodeEditor("pwm_test.vhd", 231, 74); // be
-selectCodeEditor("pwm_test.vhd", 301, 267); // be
-selectCodeEditor("pwm_test.vhd", 235, 86); // be
-selectCodeEditor("pwm_test.vhd", 121, 283); // be
-selectCodeEditor("pwm_test.vhd", 93, 96); // be
-selectCodeEditor("pwm_test.vhd", 83, 285); // be
-selectCodeEditor("pwm_test.vhd", 130, 273); // be
-// Elapsed time: 53 seconds
-selectCodeEditor("pwm_test.vhd", 316, 359); // be
-// Elapsed time: 11 seconds
-selectCodeEditor("pwm_test.vhd", 342, 260); // be
-selectCodeEditor("pwm_test.vhd", 93, 260); // be
-// Elapsed time: 23 seconds
-selectCodeEditor("pwm_test.vhd", 98, 261); // be
-selectCodeEditor("pwm_test.vhd", 96, 253); // be
-selectCodeEditor("pwm_test.vhd", 101, 249); // be
-selectCodeEditor("pwm_test.vhd", 114, 261); // be
-// Elapsed time: 21 seconds
-selectCodeEditor("pwm_test.vhd", 121, 108); // be
-selectCodeEditor("pwm_test.vhd", 206, 128); // be
-selectCodeEditor("pwm_test.vhd", 239, 100); // be
-selectCodeEditor("pwm_test.vhd", 237, 122); // be
-selectCodeEditor("pwm_test.vhd", 239, 114); // be
-selectCodeEditor("pwm_test.vhd", 237, 89); // be
-selectCodeEditor("pwm_test.vhd", 248, 109); // be
-// Elapsed time: 63 seconds
-selectCodeEditor("pwm_test.vhd", 275, 109); // be
-// Elapsed time: 43 seconds
-selectCodeEditor("pwm_test.vhd", 276, 374); // be
-// Elapsed time: 47 seconds
-selectCodeEditor("pwm_test.vhd", 370, 447, false, false, false, true, false); // be - Popup Trigger
-selectCodeEditor("pwm_test.vhd", 296, 328); // be
-selectCodeEditor("pwm_test.vhd", 92, 346); // be
-selectCodeEditor("pwm_test.vhd", 93, 355); // be
-selectCodeEditor("pwm_test.vhd", 355, 265); // be
-selectCodeEditor("pwm_test.vhd", 141, 302); // be
-selectCodeEditor("pwm_test.vhd", 144, 300); // be
-// Elapsed time: 103 seconds
-selectCodeEditor("pwm_test.vhd", 335, 297); // be
-selectCodeEditor("pwm_test.vhd", 317, 295); // be
-// Elapsed time: 12 seconds
-selectCodeEditor("pwm_test.vhd", 106, 404); // be
-selectCodeEditor("pwm_test.vhd", 159, 429); // be
-selectCodeEditor("pwm_test.vhd", 97, 402); // be
-selectCodeEditor("pwm_test.vhd", 105, 397); // be
-selectCodeEditor("pwm_test.vhd", 112, 399); // be
-selectCodeEditor("pwm_test.vhd", 90, 422); // be
-selectCodeEditor("pwm_test.vhd", 129, 404); // be
-selectCodeEditor("pwm_test.vhd", 120, 417); // be
-// Elapsed time: 73 seconds
-selectCodeEditor("pwm_test.vhd", 194, 391); // be
-selectCodeEditor("pwm_test.vhd", 168, 415); // be
-// Elapsed time: 27 seconds
-selectCodeEditor("pwm_test.vhd", 267, 418); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Elapsed time: 37 seconds
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false, false, false, false, false, true); // D - Double Click
-// WARNING: HEventQueue.dispatchEvent() is taking  1243 ms.
-dismissDialog("Opening Editor"); // bA
-// Elapsed time: 33 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 1); // m
-// Elapsed time: 11 seconds
-selectCodeEditor("pwm_test.vhd", 167, 419); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 1); // m
-// Elapsed time: 11 seconds
-selectCodeEditor("pwm_test.vhd", 161, 398); // be
-selectCodeEditor("pwm_test.vhd", 167, 398); // be
-selectCodeEditor("pwm_test.vhd", 167, 398, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 237, 368); // be
-// Elapsed time: 69 seconds
-selectCodeEditor("pwm_test.vhd", 286, 307); // be
-selectCodeEditor("pwm_test.vhd", 586, 275); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 2); // m
-selectCodeEditor("pt1.vhd", 195, 249); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 1); // m
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 6); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 7, true); // D - Node
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 7); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 9, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 9, true, false, false, false, false, true); // D - Double Click - Node
-// WARNING: HEventQueue.dispatchEvent() is taking  1144 ms.
-dismissDialog("Opening Editor"); // bA
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Wed May 18 19:58:12 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 60 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-// [GUI Memory]: 145 MB (+5677kb) [00:29:20]
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'regler' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// TclEventType: LOAD_FEATURE
-// Tcl Message: Built simulation snapshot pwm_test_db_behav 
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 85 MB. Current time: 5/18/22, 7:59:27 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: xsim: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 1251.465 ; gain = 0.000 
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1251.465 ; gain = 0.000 
-// 'd' command handler elapsed time: 12 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:35 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 7:59:35 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 92 MB. Current time: 5/18/22, 7:59:35 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:35 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:35 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 85 MB. Current time: 5/18/22, 7:59:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 89 MB. Current time: 5/18/22, 7:59:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 89 MB. Current time: 5/18/22, 7:59:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:37 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:37 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 89 MB. Current time: 5/18/22, 7:59:37 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:37 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 89 MB. Current time: 5/18/22, 7:59:37 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:37 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:37 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:37 PM CEST
-// Elapsed time: 10 seconds
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 111, 77); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 133, 67); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 142, 64); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 84 MB. Current time: 5/18/22, 7:59:43 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 498, 81); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 134, 242); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 149, 162); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 7:59:48 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 173, 268); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 205, 163); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// Elapsed time: 14 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// Elapsed time: 20 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 110, 315); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 8:00:30 PM CEST
-// Elapsed time: 13 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 150, 178); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 96, 254); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 39, 192); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 83 MB. Current time: 5/18/22, 8:00:47 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 89, 265); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-// Elapsed time: 96 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 86, 92); // be
-selectCodeEditor("pwm_test_db.vhd", 86, 92, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 407, 280); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 88 MB. Current time: 5/18/22, 8:02:55 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1251.465 ; gain = 0.000 
-// 'd' command handler elapsed time: 11 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// Elapsed time: 12 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 376, 256); // b
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:03:10 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 91 MB. Current time: 5/18/22, 8:03:10 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 95 MB. Current time: 5/18/22, 8:03:10 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:10 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:10 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 92, 95); // b
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:20 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:20 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 94 MB. Current time: 5/18/22, 8:03:20 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:21 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:21 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:21 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:21 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 611, 112); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 87 MB. Current time: 5/18/22, 8:03:22 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-// Elapsed time: 43 seconds
-selectCodeEditor("pwm_test.vhd", 188, 179); // be
-selectCodeEditor("pwm_test.vhd", 186, 164); // be
-selectCodeEditor("pwm_test.vhd", 179, 143); // be
-selectCodeEditor("pwm_test.vhd", 708, 287); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  1143 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Wed May 18 20:04:35 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 53 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'regler' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 92 MB. Current time: 5/18/22, 8:05:42 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1254.031 ; gain = 0.000 
-// 'd' command handler elapsed time: 11 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 227, 331); // b
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 92 MB. Current time: 5/18/22, 8:05:47 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// Elapsed time: 20 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 255, 170); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 143, 103); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 194, 277); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 92 MB. Current time: 5/18/22, 8:06:11 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 202, 269); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// Elapsed time: 20 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-// Elapsed time: 14 seconds
-selectCodeEditor("pwm_test.vhd", 170, 199); // be
-// Elapsed time: 79 seconds
-selectCodeEditor("pwm_test.vhd", 131, 451); // be
-selectCodeEditor("pwm_test.vhd", 131, 451, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 400, 450); // be
-selectCodeEditor("pwm_test.vhd", 453, 222); // be
-// Elapsed time: 21 seconds
-selectCodeEditor("pwm_test.vhd", 376, 479); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'c'); // be
-selectCodeEditor("pwm_test.vhd", 232, 223); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'v'); // be
-selectCodeEditor("pwm_test.vhd", 44, 223); // be
-selectCodeEditor("pwm_test.vhd", 45, 217); // be
-selectCodeEditor("pwm_test.vhd", 22, 294); // be
-selectCodeEditor("pwm_test.vhd", 31, 296); // be
-selectCodeEditor("pwm_test.vhd", 30, 313); // be
-selectCodeEditor("pwm_test.vhd", 111, 311); // be
-selectCodeEditor("pwm_test.vhd", 281, 322); // be
-selectCodeEditor("pwm_test.vhd", 282, 331); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a
-// TclEventType: DG_GRAPH_STALE
-// [GUI Memory]: 155 MB (+2670kb) [00:39:10]
-// WARNING: HEventQueue.dispatchEvent() is taking  1589 ms.
-dismissDialog("Save Project"); // al
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: RUN_MODIFY
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: RUN_MODIFY
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_MODIFY
-// Tcl Message: [Wed May 18 20:09:08 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 5 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_STATUS_CHANGE
-selectCodeEditor("pwm_test.vhd", 375, 412); // be
-selectTab((HResource) null, (HResource) null, "Messages", 1); // aL
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "OK"); // JButton
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// Tcl Message: reset_run synth_1 
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: RUN_LAUNCH
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Wed May 18 20:09:25 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 3 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// Elapsed time: 18 seconds
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Vivado 12-1017] Problems encountered:. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1. . ]", 36, true); // ah - Node
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 45 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "Cancel"); // JButton
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'regler' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 97 MB. Current time: 5/18/22, 8:10:43 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1255.961 ; gain = 0.000 
-// 'd' command handler elapsed time: 11 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 187, 56); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 245, 65); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 96 MB. Current time: 5/18/22, 8:10:57 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 178, 404); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-// Elapsed time: 16 seconds
-selectCodeEditor("pt1.vhd", 161, 385); // be
-selectCodeEditor("pt1.vhd", 380, 484); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 159, 197); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  2496 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 2184 ms. Increasing delay to 6552 ms.
-// Elapsed time: 45 seconds
-selectCodeEditor("pt1.vhd", 272, 217); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 305, 478); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 167, 62); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 487, 128); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'c'); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 709, 207); // be
-typeControlKey((HResource) null, "pt1.vhd", 'v'); // be
-selectCodeEditor("pt1.vhd", 269, 245); // be
-selectCodeEditor("pt1.vhd", 205, 225); // be
-selectCodeEditor("pt1.vhd", 226, 213); // be
-selectCodeEditor("pt1.vhd", 491, 320); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  2421 ms.
-// TclEventType: DG_GRAPH_STALE
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// TclEventType: FILE_SET_CHANGE
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "OK"); // JButton
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-// Elapsed time: 15 seconds
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Wed May 18 20:13:37 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 17 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 60 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pt1' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: Time resolution is 1 ps 
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:14:54 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1257.480 ; gain = 0.000 
-// 'd' command handler elapsed time: 13 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// Elapsed time: 13 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 74, 77); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 77, 77); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 84, 145); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:15:12 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 100, 158); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 106, 145); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 106, 145, false, false, false, false, true); // b - Double Click
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 100 MB. Current time: 5/18/22, 8:15:14 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 108, 145); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 100 MB. Current time: 5/18/22, 8:15:14 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 114, 144); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 114, 144, false, false, false, false, true); // b - Double Click
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 100 MB. Current time: 5/18/22, 8:15:15 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 117, 145); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 118, 146); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 100 MB. Current time: 5/18/22, 8:15:15 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 120, 147); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 130, 154); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 100 MB. Current time: 5/18/22, 8:15:15 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 239, 192); // be
-selectCodeEditor("pt1.vhd", 467, 219); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  3154 ms.
-dismissDialog("Save Project"); // al
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: RUN_MODIFY
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: RUN_MODIFY
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: [Wed May 18 20:15:34 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 7 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_STATUS_CHANGE
-selectCodeEditor("pt1.vhd", 376, 201); // be
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 61 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pt1' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// [GUI Memory]: 167 MB (+4784kb) [00:46:59]
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:16:53 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000 
-// 'd' command handler elapsed time: 10 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// Elapsed time: 26 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 172, 216); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 100, 191); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 98, 180); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:17:21 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-// Elapsed time: 14 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-// Elapsed time: 14 seconds
-selectCodeEditor("pwm_test_db.vhd", 166, 303, false, false, false, true, false); // be - Popup Trigger
-selectCodeEditor("pwm_test_db.vhd", 112, 263); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 67, 359); // be
-selectCodeEditor("pwm_test_db.vhd", 67, 359, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 56, 318); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 219, 195); // be
-selectCodeEditor("pt1.vhd", 219, 195, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pt1.vhd", 222, 252); // be
-selectCodeEditor("pt1.vhd", 221, 196); // be
-selectCodeEditor("pt1.vhd", 221, 196, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pt1.vhd", 224, 262); // be
-selectCodeEditor("pt1.vhd", 308, 196); // be
-selectCodeEditor("pt1.vhd", 343, 192); // be
-selectCodeEditor("pt1.vhd", 354, 192); // be
-selectCodeEditor("pt1.vhd", 282, 209); // be
-selectCodeEditor("pt1.vhd", 263, 196); // be
-selectCodeEditor("pt1.vhd", 304, 263); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 99, 198); // be
-selectCodeEditor("pwm_test_db.vhd", 307, 340); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 224, 203); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  3622 ms.
-// TclEventType: DG_GRAPH_STALE
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-// TclEventType: FILE_SET_CHANGE
-selectCodeEditor("pwm_test.vhd", 228, 289); // be
-selectCodeEditor("pwm_test.vhd", 174, 214); // be
-selectCodeEditor("pwm_test.vhd", 203, 263); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 323, 384); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  3837 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "OK"); // JButton
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Wed May 18 20:19:22 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 4 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 66 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pt1' INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 102 MB. Current time: 5/18/22, 8:20:41 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000 
-// 'd' command handler elapsed time: 10 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 52, 102); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 135, 95); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 102 MB. Current time: 5/18/22, 8:20:49 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 201, 92); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 250, 101); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 6, 105); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 102 MB. Current time: 5/18/22, 8:20:55 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 14, 104); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectButton(RDIResource.WaveformView_PREVIOUS_TRANSITION, "Waveform Viewer_waveformPreviousTransition"); // D
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:20:58 PM CEST
-selectButton(RDIResource.WaveformView_PREVIOUS_TRANSITION, "Waveform Viewer_waveformPreviousTransition"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:20:59 PM CEST
-selectButton(RDIResource.WaveformView_PREVIOUS_TRANSITION, "Waveform Viewer_waveformPreviousTransition"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:21:00 PM CEST
-selectButton(RDIResource.WaveformView_PREVIOUS_TRANSITION, "Waveform Viewer_waveformPreviousTransition"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:21:00 PM CEST
-selectButton(RDIResource.WaveformView_PREVIOUS_TRANSITION, "Waveform Viewer_waveformPreviousTransition"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:21:02 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:21:02 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 101 MB. Current time: 5/18/22, 8:21:04 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// Elapsed time: 46 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-// Elapsed time: 29 seconds
-selectCodeEditor("pwm_test.vhd", 167, 274); // be
-selectCodeEditor("pwm_test.vhd", 431, 348); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 222, 195); // be
-selectCodeEditor("pt1.vhd", 369, 133); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  3931 ms.
-// TclEventType: DG_GRAPH_STALE
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-// TclEventType: FILE_SET_CHANGE
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  4332 ms.
-dismissDialog("Save Project"); // al
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: RUN_MODIFY
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-selectCheckBox(PAResourceItoN.LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN, "Don't show this dialog again", true); // g: TRUE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// HOptionPane Warning: 'A background task is running. Please wait until it completes and try again. (Background Task)'
-// TclEventType: FILE_SET_CHANGE
-selectButton("OptionPane.button", "OK"); // JButton
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_STATUS_CHANGE
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Wed May 18 20:22:54 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 14 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 65 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pt1' INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'regler' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:13 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1257.480 ; gain = 0.000 
-// 'd' command handler elapsed time: 10 seconds
-dismissDialog("Run Simulation"); // e
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 78, 181); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 90, 114); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:19 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 70, 170); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:23 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:23 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:23 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 115 MB. Current time: 5/18/22, 8:24:24 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:24 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:24 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:25 PM CEST
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:25 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:25 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:26 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:26 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:31 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:31 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:32 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:32 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:33 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:33 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:34 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:35 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:35 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:36 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:36 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:37 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:38 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:38 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:38 PM CEST
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:39 PM CEST
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 108 MB. Current time: 5/18/22, 8:24:39 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:39 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:39 PM CEST
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:39 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:40 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:41 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:41 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:42 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:42 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 104 MB. Current time: 5/18/22, 8:24:42 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 105 MB. Current time: 5/18/22, 8:24:43 PM CEST
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 161, 283); // be
-selectCodeEditor("pwm_test.vhd", 161, 283, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 210, 337); // be
-// Elapsed time: 14 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 164, 258); // be
-// Elapsed time: 40 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 22, 181); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 89, 345); // be
-selectCodeEditor("pwm_test_db.vhd", 302, 243); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  4576 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: FILE_SET_CHANGE
-dismissDialog("Save Simulation Sources"); // c
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:35 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000 
-// 'd' command handler elapsed time: 18 seconds
-dismissDialog("Run Simulation"); // e
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 118, 184); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 232, 186); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:40 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 451, 197); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 8, 185); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:46 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:47 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:47 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:49 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:50 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:52 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:26:52 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 211, 238); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 141, 203); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 108 MB. Current time: 5/18/22, 8:26:56 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 33, 188); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 130, 200); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 141, 199); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 108 MB. Current time: 5/18/22, 8:27:00 PM CEST
-// Elapsed time: 46 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 216, 202); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 228, 203); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:27:47 PM CEST
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 280, 198); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 171, 198); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// Elapsed time: 31 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-// Elapsed time: 30 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 125, 145); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:29:04 PM CEST
-// Elapsed time: 28 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 179, 223); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 177, 197); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 109 MB. Current time: 5/18/22, 8:29:34 PM CEST
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 165, 124); // be
-selectCodeEditor("pwm_test.vhd", 165, 124, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 239, 175); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 218, 200); // be
-selectCodeEditor("pt1.vhd", 218, 200, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pt1.vhd", 234, 263); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 196, 148); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 44, 148); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 2, 105); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 108 MB. Current time: 5/18/22, 8:29:59 PM CEST
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 173, 158); // be
-selectCodeEditor("pwm_test.vhd", 507, 282); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  6260 ms.
-dismissDialog("Save Project"); // al
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: RUN_MODIFY
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_RESET
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 5964 ms. Increasing delay to 17892 ms.
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: [Wed May 18 20:30:29 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 10 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 7 ms. Decreasing delay to 2007 ms.
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 56 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'regler' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:31:39 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1295.145 ; gain = 20.746 
-// 'd' command handler elapsed time: 10 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 39, 99); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:31:46 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:31:47 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:31:48 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:31:48 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:31:49 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:31:51 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 292, 181); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:31:53 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 421, 167); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 442, 132); // b
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:31:54 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 431, 121); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 39, 273); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 113 MB. Current time: 5/18/22, 8:31:59 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 89, 273); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 120, 273); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 113 MB. Current time: 5/18/22, 8:32:01 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 116, 57); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 112, 64); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 529, 115); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 113 MB. Current time: 5/18/22, 8:32:05 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 544, 114); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 634, 112); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 113 MB. Current time: 5/18/22, 8:32:07 PM CEST
-// Elapsed time: 12 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 576, 115); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 653, 123); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 734, 128); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 114 MB. Current time: 5/18/22, 8:32:21 PM CEST
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 77, 251); // be
-selectCodeEditor("pwm_test_db.vhd", 228, 234); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  6354 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: FILE_SET_CHANGE
-dismissDialog("Save Simulation Sources"); // c
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 5988 ms. Increasing delay to 17964 ms.
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:32:48 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1295.742 ; gain = 0.598 
-// 'd' command handler elapsed time: 19 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 160, 188); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 944, 165); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 7 ms. Decreasing delay to 2007 ms.
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:32:56 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 941, 174); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 244, 227); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 117 MB. Current time: 5/18/22, 8:33:02 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 7, 200); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 9, 101); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:05 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:07 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 117 MB. Current time: 5/18/22, 8:33:08 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:10 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:12 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 132 MB. Current time: 5/18/22, 8:33:13 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:16 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:17 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:20 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:20 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 118 MB. Current time: 5/18/22, 8:33:21 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 303, 18); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 57, 112); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false, false, false, false, true, false); // n - Popup Trigger
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_SETTINGS, "Simulation Settings..."); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_SETTINGS
-// Tcl Command: 'rdi::info_commands {device::*}'
-// Tcl Command: 'rdi::info_commands {debug::*}'
-// Tcl Command: 'rdi::info_commands {*}'
-// WARNING: HEventQueue.dispatchEvent() is taking  2138 ms.
-selectTab(PAResourceOtoP.ProjectSettingsSimulationPanel_TABBED_PANE, PAResourceOtoP.ProjectSettingsSimulationPanel_ADVANCED, "Advanced", 4); // i
-selectTab(PAResourceOtoP.ProjectSettingsSimulationPanel_TABBED_PANE, PAResourceOtoP.ProjectSettingsSimulationPanel_NETLIST, "Netlist", 3); // i
-selectTab(PAResourceOtoP.ProjectSettingsSimulationPanel_TABBED_PANE, PAResourceOtoP.ProjectSettingsSimulationPanel_SIMULATION, "Simulation", 2); // i
-selectButton(RDIResource.BaseDialog_APPLY, "Apply"); // a
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1] 
-// [GUI Memory]: 199 MB (+24049kb) [01:03:50]
-selectTab(PAResourceOtoP.ProjectSettingsSimulationPanel_TABBED_PANE, PAResourceOtoP.ProjectSettingsSimulationPanel_ELABORATION, "Elaboration", 1); // i
-selectTab(PAResourceOtoP.ProjectSettingsSimulationPanel_TABBED_PANE, PAResourceOtoP.ProjectSettingsSimulationPanel_COMPILATION, "Compilation", 0); // i
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Settings"); // d
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 333, 417); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResourceCommand.RDICommands_WAVEFORM_SAVE_CONFIGURATION, "Waveform Viewer_waveform_save_configuration"); // D
-// Run Command: RDIResourceCommand.RDICommands_WAVEFORM_SAVE_CONFIGURATION
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// Tcl Message: save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} 
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-// TclEventType: FILE_SET_CHANGE
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 10 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:03 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 10 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1320.121 ; gain = 0.000 
-// 'd' command handler elapsed time: 12 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 53, 140); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:07 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 90, 95); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 6, 105); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:14 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:15 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:15 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:16 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 20, 107); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:18 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 7, 112); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:21 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 138 MB. Current time: 5/18/22, 8:34:21 PM CEST
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 154, 214); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 224, 213); // be
-selectCodeEditor("pt1.vhd", 224, 213, false, false, false, false, true); // be - Double Click
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 394, 316); // be
-typeControlKey(null, null, 'z');
-typeControlKey(null, null, 'z');
-typeControlKey(null, null, 'z');
-selectCodeEditor("pwm_test_db.vhd", 148, 208); // be
-selectCodeEditor("pwm_test_db.vhd", 151, 211); // be
-selectCodeEditor("pwm_test_db.vhd", 233, 208); // be
-selectCodeEditor("pwm_test_db.vhd", 152, 210); // be
-selectCodeEditor("pwm_test_db.vhd", 152, 210, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 386, 269); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 288, 304); // be
-selectCodeEditor("pt1.vhd", 381, 195); // be
-selectCodeEditor("pt1.vhd", 381, 195, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pt1.vhd", 381, 194); // be
-selectCodeEditor("pt1.vhd", 559, 246); // be
-selectCodeEditor("pt1.vhd", 233, 211); // be
-selectCodeEditor("pt1.vhd", 237, 219); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 206, 240); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 162, 125); // be
-selectCodeEditor("pwm_test.vhd", 162, 124, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 252, 300); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 190, 277); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  10828 ms.
-// Thread: SyntheticaAnimation 50
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at de.javasoft.plaf.synthetica.painter.AnimationThreadFactory$AnimationThread.run(AnimationThreadFactory.java:119)
-// Thread: Attach Listener
-// Thread: SyntheticaCleanerThread
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at de.javasoft.plaf.synthetica.StyleFactory$ComponentPropertyStore$1.run(StyleFactory.java:1885)
-// Thread: pool-2-thread-1
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.await(AbstractQueuedSynchronizer.java:2081)
-// 	at java.base@11.0.11/java.util.concurrent.LinkedBlockingQueue.take(LinkedBlockingQueue.java:433)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.getTask(ThreadPoolExecutor.java:1054)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1114)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: ForkJoinPool.commonPool-worker-1
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.parkUntil(LockSupport.java:275)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1619)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: Finalizer
-// 	at java.base@11.0.11/java.lang.Object.wait(Native Method)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:155)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:176)
-// 	at java.base@11.0.11/java.lang.ref.Finalizer$FinalizerThread.run(Finalizer.java:170)
-// Thread: AWT-Windows
-// 	at java.desktop@11.0.11/sun.awt.windows.WToolkit.eventLoop(Native Method)
-// 	at java.desktop@11.0.11/sun.awt.windows.WToolkit.run(WToolkit.java:305)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: pool-4-thread-1
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.await(AbstractQueuedSynchronizer.java:2081)
-// 	at java.base@11.0.11/java.util.concurrent.LinkedBlockingQueue.take(LinkedBlockingQueue.java:433)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.getTask(ThreadPoolExecutor.java:1054)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1114)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: AWT-EventQueue-0
-// 	at java.base@11.0.11/sun.nio.fs.WindowsNativeDispatcher.GetFileAttributesEx0(Native Method)
-// 	at java.base@11.0.11/sun.nio.fs.WindowsNativeDispatcher.GetFileAttributesEx(WindowsNativeDispatcher.java:380)
-// 	at java.base@11.0.11/sun.nio.fs.WindowsFileAttributes.get(WindowsFileAttributes.java:307)
-// 	at java.base@11.0.11/sun.nio.fs.WindowsUriSupport.toUri(WindowsUriSupport.java:108)
-// 	at java.base@11.0.11/sun.nio.fs.WindowsPath.toUri(WindowsPath.java:867)
-// 	at ui.k.c.af$$Lambda$366/0x0000000800b8bc40.apply(Unknown Source)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline$3$1.accept(ReferencePipeline.java:195)
-// 	at java.base@11.0.11/java.util.stream.ForEachOps$ForEachOp$OfRef.accept(ForEachOps.java:183)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline$2$1.accept(ReferencePipeline.java:177)
-// 	at java.base@11.0.11/java.util.stream.ForEachOps$ForEachOp$OfRef.accept(ForEachOps.java:183)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline$3$1.accept(ReferencePipeline.java:195)
-// 	at java.base@11.0.11/java.util.Iterator.forEachRemaining(Iterator.java:133)
-// 	at java.base@11.0.11/java.util.Spliterators$IteratorSpliterator.forEachRemaining(Spliterators.java:1801)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.copyInto(AbstractPipeline.java:484)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.wrapAndCopyInto(AbstractPipeline.java:474)
-// 	at java.base@11.0.11/java.util.stream.ForEachOps$ForEachOp.evaluateSequential(ForEachOps.java:150)
-// 	at java.base@11.0.11/java.util.stream.ForEachOps$ForEachOp$OfRef.evaluateSequential(ForEachOps.java:173)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.evaluate(AbstractPipeline.java:234)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline.forEach(ReferencePipeline.java:497)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline$7$1.accept(ReferencePipeline.java:274)
-// 	at java.base@11.0.11/java.util.ArrayList$ArrayListSpliterator.forEachRemaining(ArrayList.java:1655)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.copyInto(AbstractPipeline.java:484)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.wrapAndCopyInto(AbstractPipeline.java:474)
-// 	at java.base@11.0.11/java.util.stream.ForEachOps$ForEachOp.evaluateSequential(ForEachOps.java:150)
-// 	at java.base@11.0.11/java.util.stream.ForEachOps$ForEachOp$OfRef.evaluateSequential(ForEachOps.java:173)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.evaluate(AbstractPipeline.java:234)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline.forEach(ReferencePipeline.java:497)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline$7$1.accept(ReferencePipeline.java:274)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline$3$1.accept(ReferencePipeline.java:195)
-// 	at java.base@11.0.11/java.util.AbstractList$RandomAccessSpliterator.forEachRemaining(AbstractList.java:720)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.copyInto(AbstractPipeline.java:484)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.wrapAndCopyInto(AbstractPipeline.java:474)
-// 	at java.base@11.0.11/java.util.stream.ReduceOps$ReduceOp.evaluateSequential(ReduceOps.java:913)
-// 	at java.base@11.0.11/java.util.stream.AbstractPipeline.evaluate(AbstractPipeline.java:234)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline.collect(ReferencePipeline.java:578)
-// 	at ui.k.c.af.a(SourceFile:401)
-// 	at ui.k.c.v.a(SourceFile:368)
-// 	at ui.k.c.v.abv(SourceFile:342)
-// 	at ui.k.c.v.yO(SourceFile:206)
-// 	at ui.k.c.v.gJl(SourceFile:151)
-// 	at ui.k.c.L.a(SourceFile:219)
-// 	at ui.k.c.L$$Lambda$521/0x0000000800d14840.accept(Unknown Source)
-// 	at java.base@11.0.11/java.util.concurrent.CompletableFuture.uniAcceptNow(CompletableFuture.java:753)
-// 	at java.base@11.0.11/java.util.concurrent.CompletableFuture.uniAcceptStage(CompletableFuture.java:731)
-// 	at java.base@11.0.11/java.util.concurrent.CompletableFuture.thenAccept(CompletableFuture.java:2108)
-// 	at ui.k.c.L.a(SourceFile:214)
-// 	at ui.k.c.L$$Lambda$520/0x0000000800d15440.accept(Unknown Source)
-// 	at java.base@11.0.11/java.util.Optional.ifPresent(Optional.java:183)
-// 	at ui.k.c.L.run(SourceFile:212)
-// 	at ui.views.U.a.n.hv(SourceFile:1740)
-// 	at ui.views.U.a.a.b(SourceFile:1784)
-// 	at ui.views.U.a.a.a(SourceFile:1701)
-// 	at ui.views.U.a.a.f(SourceFile:1697)
-// 	at ui.k.c.E.fCL(SourceFile:268)
-// 	at ui.views.U.a.aK.actionPerformed(SourceFile:548)
-// 	at com.jidesoft.editor.action.InputHandler.executeAction(Unknown Source)
-// 	at com.jidesoft.editor.action.InputHandler.keyPressed(Unknown Source)
-// 	at com.jidesoft.editor.CodeEditor.processKeyEvent(Unknown Source)
-// 	at ui.views.U.a.a.processKeyEvent(SourceFile:2840)
-// 	at java.desktop@11.0.11/java.awt.Component.processEvent(Component.java:6412)
-// 	at java.desktop@11.0.11/java.awt.Container.processEvent(Container.java:2263)
-// 	at ui.views.U.a.a.processEvent(SourceFile:2846)
-// 	at java.desktop@11.0.11/java.awt.Component.dispatchEventImpl(Component.java:5011)
-// 	at java.desktop@11.0.11/java.awt.Container.dispatchEventImpl(Container.java:2321)
-// 	at java.desktop@11.0.11/java.awt.Component.dispatchEvent(Component.java:4843)
-// 	at java.desktop@11.0.11/java.awt.KeyboardFocusManager.redispatchEvent(KeyboardFocusManager.java:1950)
-// 	at java.desktop@11.0.11/java.awt.DefaultKeyboardFocusManager.dispatchKeyEvent(DefaultKeyboardFocusManager.java:870)
-// 	at java.desktop@11.0.11/java.awt.DefaultKeyboardFocusManager.preDispatchKeyEvent(DefaultKeyboardFocusManager.java:1139)
-// 	at java.desktop@11.0.11/java.awt.DefaultKeyboardFocusManager.typeAheadAssertions(DefaultKeyboardFocusManager.java:1009)
-// 	at java.desktop@11.0.11/java.awt.DefaultKeyboardFocusManager.dispatchEvent(DefaultKeyboardFocusManager.java:835)
-// 	at java.desktop@11.0.11/java.awt.Component.dispatchEventImpl(Component.java:4892)
-// 	at java.desktop@11.0.11/java.awt.Container.dispatchEventImpl(Container.java:2321)
-// 	at java.desktop@11.0.11/java.awt.Window.dispatchEventImpl(Window.java:2772)
-// 	at java.desktop@11.0.11/java.awt.Component.dispatchEvent(Component.java:4843)
-// 	at java.desktop@11.0.11/java.awt.EventQueue.dispatchEventImpl(EventQueue.java:772)
-// 	at java.desktop@11.0.11/java.awt.EventQueue$4.run(EventQueue.java:721)
-// 	at java.desktop@11.0.11/java.awt.EventQueue$4.run(EventQueue.java:715)
-// 	at java.base@11.0.11/java.security.AccessController.doPrivileged(Native Method)
-// 	at java.base@11.0.11/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:85)
-// 	at java.base@11.0.11/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:95)
-// 	at java.desktop@11.0.11/java.awt.EventQueue$5.run(EventQueue.java:745)
-// 	at java.desktop@11.0.11/java.awt.EventQueue$5.run(EventQueue.java:743)
-// 	at java.base@11.0.11/java.security.AccessController.doPrivileged(Native Method)
-// 	at java.base@11.0.11/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:85)
-// 	at java.desktop@11.0.11/java.awt.EventQueue.dispatchEvent(EventQueue.java:742)
-// 	at ui.frmwork.a.d.dispatchEvent(SourceFile:92)
-// 	at java.desktop@11.0.11/java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:203)
-// 	at java.desktop@11.0.11/java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:124)
-// 	at java.desktop@11.0.11/java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:113)
-// 	at java.desktop@11.0.11/java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:109)
-// 	at java.desktop@11.0.11/java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:101)
-// 	at java.desktop@11.0.11/java.awt.EventDispatchThread.run(EventDispatchThread.java:90)
-// Thread: ForkJoinPool.commonPool-worker-25
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1628)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: TimerQueue
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.parkNanos(LockSupport.java:234)
-// 	at java.base@11.0.11/java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.awaitNanos(AbstractQueuedSynchronizer.java:2123)
-// 	at java.base@11.0.11/java.util.concurrent.DelayQueue.take(DelayQueue.java:229)
-// 	at java.desktop@11.0.11/javax.swing.TimerQueue.run(TimerQueue.java:171)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: pool-3-thread-1
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.await(AbstractQueuedSynchronizer.java:2081)
-// 	at java.base@11.0.11/java.util.concurrent.LinkedBlockingQueue.take(LinkedBlockingQueue.java:433)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.getTask(ThreadPoolExecutor.java:1054)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1114)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: OutputGobbler
-// 	at java.base@11.0.11/java.io.FileInputStream.readBytes(Native Method)
-// 	at java.base@11.0.11/java.io.FileInputStream.read(FileInputStream.java:279)
-// 	at java.base@11.0.11/java.io.BufferedInputStream.read1(BufferedInputStream.java:290)
-// 	at java.base@11.0.11/java.io.BufferedInputStream.read(BufferedInputStream.java:351)
-// 	at java.base@11.0.11/sun.nio.cs.StreamDecoder.readBytes(StreamDecoder.java:284)
-// 	at java.base@11.0.11/sun.nio.cs.StreamDecoder.implRead(StreamDecoder.java:326)
-// 	at java.base@11.0.11/sun.nio.cs.StreamDecoder.read(StreamDecoder.java:178)
-// 	at java.base@11.0.11/java.io.InputStreamReader.read(InputStreamReader.java:181)
-// 	at java.base@11.0.11/java.io.BufferedReader.fill(BufferedReader.java:161)
-// 	at java.base@11.0.11/java.io.BufferedReader.readLine(BufferedReader.java:326)
-// 	at java.base@11.0.11/java.io.BufferedReader.readLine(BufferedReader.java:392)
-// 	at java.base@11.0.11/java.io.BufferedReader$1.hasNext(BufferedReader.java:574)
-// 	at java.base@11.0.11/java.util.Iterator.forEachRemaining(Iterator.java:132)
-// 	at java.base@11.0.11/java.util.Spliterators$IteratorSpliterator.forEachRemaining(Spliterators.java:1801)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline$Head.forEach(ReferencePipeline.java:658)
-// 	at com.sigasi.lcm.C.run(SourceFile:43)
-// Thread: Common-Cleaner
-// 	at java.base@11.0.11/java.lang.Object.wait(Native Method)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:155)
-// 	at java.base@11.0.11/jdk.internal.ref.CleanerImpl.run(CleanerImpl.java:148)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// 	at java.base@11.0.11/jdk.internal.misc.InnocuousThread.run(InnocuousThread.java:134)
-// Thread: Life support thread
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at com.sigasi.lcm.l.run(SourceFile:82)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: ForkJoinPool.commonPool-worker-15
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.parkUntil(LockSupport.java:275)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1619)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: main
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at ui.PlanAhead.c(SourceFile:1150)
-// 	at ui.PlanAhead.jswMain(SourceFile:1197)
-// Thread: pool-6-thread-1
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.parkNanos(LockSupport.java:234)
-// 	at java.base@11.0.11/java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.awaitNanos(AbstractQueuedSynchronizer.java:2123)
-// 	at java.base@11.0.11/java.util.concurrent.ScheduledThreadPoolExecutor$DelayedWorkQueue.take(ScheduledThreadPoolExecutor.java:1182)
-// 	at java.base@11.0.11/java.util.concurrent.ScheduledThreadPoolExecutor$DelayedWorkQueue.take(ScheduledThreadPoolExecutor.java:899)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.getTask(ThreadPoolExecutor.java:1054)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1114)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: ForkJoinPool.commonPool-worker-21
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.parkUntil(LockSupport.java:275)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1619)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: AWT-Shutdown
-// 	at java.base@11.0.11/java.lang.Object.wait(Native Method)
-// 	at java.base@11.0.11/java.lang.Object.wait(Object.java:328)
-// 	at java.desktop@11.0.11/sun.awt.AWTAutoShutdown.run(AWTAutoShutdown.java:291)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: Monitor HEventQueue Thread
-// 	at java.base@11.0.11/java.lang.Thread.dumpThreads(Native Method)
-// 	at java.base@11.0.11/java.lang.Thread.getAllStackTraces(Thread.java:1653)
-// 	at ui.utils.d.c.iPe(SourceFile:589)
-// 	at ui.frmwork.a.e.aXx(SourceFile:144)
-// 	at ui.frmwork.y.run(SourceFile:206)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: Refresh Filesets Swing Worker Thread
-// 	at ui.data.design.p.cfd(SourceFile:2144)
-// 	at ui.data.design.p.cfc(SourceFile:2139)
-// 	at ui.data.design.z.aXx(SourceFile:2521)
-// 	at ui.frmwork.y.run(SourceFile:206)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: Swing-Shell
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.await(AbstractQueuedSynchronizer.java:2081)
-// 	at java.base@11.0.11/java.util.concurrent.LinkedBlockingQueue.take(LinkedBlockingQueue.java:433)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.getTask(ThreadPoolExecutor.java:1054)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1114)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
-// 	at java.desktop@11.0.11/sun.awt.shell.Win32ShellFolderManager2$ComInvoker$1.run(Win32ShellFolderManager2.java:586)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: Batik CleanerThread
-// 	at java.base@11.0.11/java.lang.Object.wait(Native Method)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:155)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:176)
-// 	at org.apache.batik.util.CleanerThread.run(CleanerThread.java:106)
-// Thread: Reference Handler
-// 	at java.base@11.0.11/java.lang.ref.Reference.waitForReferencePendingList(Native Method)
-// 	at java.base@11.0.11/java.lang.ref.Reference.processPendingReferences(Reference.java:241)
-// 	at java.base@11.0.11/java.lang.ref.Reference$ReferenceHandler.run(Reference.java:213)
-// Thread: ForkJoinPool.commonPool-worker-9
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.parkUntil(LockSupport.java:275)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1619)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: Update Runs Swing Worker Thread
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at ui.data.experiment.F.aXx(SourceFile:373)
-// 	at ui.frmwork.y.run(SourceFile:206)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: Thread-1
-// Thread: ForkJoinPool.commonPool-worker-19
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1628)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: ForkJoinPool.commonPool-worker-29
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1628)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: Signal Dispatcher
-// Thread: pool-7-thread-1
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.await(AbstractQueuedSynchronizer.java:2081)
-// 	at java.base@11.0.11/java.util.concurrent.LinkedBlockingQueue.take(LinkedBlockingQueue.java:433)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.getTask(ThreadPoolExecutor.java:1054)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1114)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: hw_ila_monitor
-// 	at java.base@11.0.11/java.lang.Object.wait(Native Method)
-// 	at java.base@11.0.11/java.lang.Object.wait(Object.java:328)
-// 	at java.base@11.0.11/java.util.TimerThread.mainLoop(Timer.java:527)
-// 	at java.base@11.0.11/java.util.TimerThread.run(Timer.java:506)
-// Thread: EMF Reference Cleaner
-// 	at java.base@11.0.11/java.lang.Object.wait(Native Method)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:155)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:176)
-// 	at org.eclipse.emf.common.util.CommonUtil$1ReferenceClearingQueuePollingThread.run(CommonUtil.java:70)
-// Thread: ErrorGobbler
-// 	at java.base@11.0.11/java.io.FileInputStream.readBytes(Native Method)
-// 	at java.base@11.0.11/java.io.FileInputStream.read(FileInputStream.java:279)
-// 	at java.base@11.0.11/sun.nio.cs.StreamDecoder.readBytes(StreamDecoder.java:284)
-// 	at java.base@11.0.11/sun.nio.cs.StreamDecoder.implRead(StreamDecoder.java:326)
-// 	at java.base@11.0.11/sun.nio.cs.StreamDecoder.read(StreamDecoder.java:178)
-// 	at java.base@11.0.11/java.io.InputStreamReader.read(InputStreamReader.java:181)
-// 	at java.base@11.0.11/java.io.BufferedReader.fill(BufferedReader.java:161)
-// 	at java.base@11.0.11/java.io.BufferedReader.readLine(BufferedReader.java:326)
-// 	at java.base@11.0.11/java.io.BufferedReader.readLine(BufferedReader.java:392)
-// 	at java.base@11.0.11/java.io.BufferedReader$1.hasNext(BufferedReader.java:574)
-// 	at java.base@11.0.11/java.util.Iterator.forEachRemaining(Iterator.java:132)
-// 	at java.base@11.0.11/java.util.Spliterators$IteratorSpliterator.forEachRemaining(Spliterators.java:1801)
-// 	at java.base@11.0.11/java.util.stream.ReferencePipeline$Head.forEach(ReferencePipeline.java:658)
-// 	at com.sigasi.lcm.C.run(SourceFile:43)
-// Thread: Protocol translation thread 0
-// 	at java.base@11.0.11/java.net.SocketInputStream.socketRead0(Native Method)
-// 	at java.base@11.0.11/java.net.SocketInputStream.socketRead(SocketInputStream.java:115)
-// 	at java.base@11.0.11/java.net.SocketInputStream.read(SocketInputStream.java:168)
-// 	at java.base@11.0.11/java.net.SocketInputStream.read(SocketInputStream.java:140)
-// 	at java.base@11.0.11/sun.security.ssl.SSLSocketInputRecord.read(SSLSocketInputRecord.java:478)
-// 	at java.base@11.0.11/sun.security.ssl.SSLSocketInputRecord.readHeader(SSLSocketInputRecord.java:472)
-// 	at java.base@11.0.11/sun.security.ssl.SSLSocketInputRecord.bytesInCompletePacket(SSLSocketInputRecord.java:70)
-// 	at java.base@11.0.11/sun.security.ssl.SSLSocketImpl.readApplicationRecord(SSLSocketImpl.java:1364)
-// 	at java.base@11.0.11/sun.security.ssl.SSLSocketImpl$AppInputStream.read(SSLSocketImpl.java:973)
-// 	at java.base@11.0.11/sun.security.ssl.SSLSocketImpl$AppInputStream.read(SSLSocketImpl.java:880)
-// 	at com.sigasi.hdt.epl.lsp4j.PatchedStreamMessageProducer.listen(PatchedStreamMessageProducer.java:78)
-// 	at org.eclipse.lsp4j.jsonrpc.json.ConcurrentMessageProcessor.run(ConcurrentMessageProcessor.java:113)
-// 	at java.base@11.0.11/java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:515)
-// 	at java.base@11.0.11/java.util.concurrent.FutureTask.run(FutureTask.java:264)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
-// 	at java.base@11.0.11/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: SyntheticaAnimation 70
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at de.javasoft.plaf.synthetica.painter.AnimationThreadFactory$AnimationThread.run(AnimationThreadFactory.java:119)
-// Thread: Process Messages Thread
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at ui.frmwork.c.h.aXx(SourceFile:133)
-// 	at ui.frmwork.y.run(SourceFile:206)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: Java2D Disposer
-// 	at java.base@11.0.11/java.lang.Object.wait(Native Method)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:155)
-// 	at java.base@11.0.11/java.lang.ref.ReferenceQueue.remove(ReferenceQueue.java:176)
-// 	at java.desktop@11.0.11/sun.java2d.Disposer.run(Disposer.java:144)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: Thread-18
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at ui.k.c.z.iHj(SourceFile:136)
-// 	at ui.k.c.z$$Lambda$253/0x0000000800802840.run(Unknown Source)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// Thread: SyntheticaAnimation 50
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at ui.utils.lnf.b.run(SourceFile:100)
-// Thread: ForkJoinPool.commonPool-worker-7
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1628)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: ForkJoinPool.commonPool-worker-11
-// 	at java.base@11.0.11/jdk.internal.misc.Unsafe.park(Native Method)
-// 	at java.base@11.0.11/java.util.concurrent.locks.LockSupport.park(LockSupport.java:194)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1628)
-// 	at java.base@11.0.11/java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:183)
-// Thread: SyntheticaAnimation 25
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at de.javasoft.plaf.synthetica.painter.AnimationThreadFactory$AnimationThread.run(AnimationThreadFactory.java:119)
-// Thread: Watchdog Thread for com.sigasi.lsp.server.BootstrappedLspServer
-// 	at java.base@11.0.11/java.lang.Thread.sleep(Native Method)
-// 	at com.sigasi.lcm.B.run(SourceFile:66)
-// Thread: Refresh Sources (EDT) Thread
-// 	at java.base@11.0.11/java.lang.Object.wait(Native Method)
-// 	at java.base@11.0.11/java.lang.Object.wait(Object.java:328)
-// 	at java.desktop@11.0.11/java.awt.EventQueue.invokeAndWait(EventQueue.java:1361)
-// 	at java.desktop@11.0.11/java.awt.EventQueue.invokeAndWait(EventQueue.java:1342)
-// 	at java.desktop@11.0.11/javax.swing.SwingUtilities.invokeAndWait(SwingUtilities.java:1480)
-// 	at ui.frmwork.E.fireTclEvent(SourceFile:120)
-// 	at ui.data.design.dai.HADAFileMgr_refreshFileSets(Native Method)
-// 	at ui.data.design.p.cfd(SourceFile:2148)
-// 	at ui.data.design.y.aXx(SourceFile:2131)
-// 	at ui.frmwork.y.run(SourceFile:206)
-// 	at java.base@11.0.11/java.lang.Thread.run(Thread.java:829)
-// WARNING: HEventQueue.dispatchEvent() is taking  2269 ms.
-// TclEventType: DG_GRAPH_STALE
-// Elapsed time: 13 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-// TclEventType: FILE_SET_CHANGE
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 11936 ms. Increasing delay to 35808 ms.
-selectCodeEditor("pwm_test.vhd", 227, 381); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  11073 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Elapsed time: 12 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 112, 124); // be
-selectCodeEditor("pwm_test_db.vhd", 123, 126); // be
-selectCodeEditor("pwm_test_db.vhd", 323, 265); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-selectCheckBox((HResource) null, "pwm_test_db.vhd", true); // g: TRUE
-// TclEventType: DG_GRAPH_STALE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// WARNING: HEventQueue.dispatchEvent() is taking  8711 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: FILE_SET_CHANGE
-dismissDialog("Save Simulation Sources"); // c
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 10 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 144 MB. Current time: 5/18/22, 8:36:45 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 10 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1381.312 ; gain = 25.016 
-// 'd' command handler elapsed time: 23 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 11, 97); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:36:50 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 420, 115); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 955, 60); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:36:55 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 6, 79); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:36:59 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:00 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:01 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:04 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:04 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:04 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 151 MB. Current time: 5/18/22, 8:37:04 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:04 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:05 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:05 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:05 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 149 MB. Current time: 5/18/22, 8:37:05 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:05 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:05 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:05 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:06 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:07 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:07 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:07 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:07 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:07 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:08 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:08 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:08 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:08 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:09 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:09 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:09 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 6 ms. Decreasing delay to 2006 ms.
-// Elapsed time: 14 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 174, 233); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:15 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 711, 216); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 15, 218); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 7, 215); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:18 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 9, 169); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 118, 169); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:22 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 418, 171); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 552, 159); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 8, 194); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 142 MB. Current time: 5/18/22, 8:37:27 PM CEST
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 138, 115); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 359, 140); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 49, 166); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:37:47 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 134, 167); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 5, 152); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-// Elapsed time: 200 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 92, 282); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 143 MB. Current time: 5/18/22, 8:41:14 PM CEST
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 239, 283); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 356, 369); // be
-// Elapsed time: 41 seconds
-selectCodeEditor("pwm_test.vhd", 246, 60); // be
-selectCodeEditor("pwm_test.vhd", 220, 76); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'v'); // be
-selectCodeEditor("pwm_test.vhd", 234, 62); // be
-selectCodeEditor("pwm_test.vhd", 219, 80); // be
-selectCodeEditor("pwm_test.vhd", 252, 73); // be
-// Elapsed time: 12 seconds
-selectCodeEditor("pwm_test.vhd", 92, 89); // be
-// Elapsed time: 12 seconds
-selectCodeEditor("pwm_test.vhd", 225, 83); // be
-selectCodeEditor("pwm_test.vhd", 251, 90); // be
-selectCodeEditor("pwm_test.vhd", 329, 334); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'c'); // be
-selectCodeEditor("pwm_test.vhd", 260, 86); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'v'); // be
-selectCodeEditor("pwm_test.vhd", 245, 137); // be
-selectCodeEditor("pwm_test.vhd", 367, 78); // be
-// Elapsed time: 27 seconds
-selectCodeEditor("pwm_test.vhd", 332, 245); // be
-selectCodeEditor("pwm_test.vhd", 143, 88); // be
-selectCodeEditor("pwm_test.vhd", 143, 88, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 327, 249); // be
-selectCodeEditor("pwm_test.vhd", 569, 325); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'c'); // be
-selectCodeEditor("pwm_test.vhd", 433, 88); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'v'); // be
-selectCodeEditor("pwm_test.vhd", 277, 186); // be
-selectCodeEditor("pwm_test.vhd", 112, 113); // be
-selectCodeEditor("pwm_test.vhd", 112, 113, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test.vhd", 89, 117); // be
-selectCodeEditor("pwm_test.vhd", 89, 112); // be
-selectCodeEditor("pwm_test.vhd", 84, 108); // be
-selectCodeEditor("pwm_test.vhd", 3, 315); // be
-selectCodeEditor("pwm_test.vhd", 353, 370); // be
-selectButton(RDIResourceCommand.RDICommands_LINE_COMMENT, (String) null); // D
-selectCodeEditor("pwm_test.vhd", 477, 318); // be
-selectCodeEditor("pwm_test.vhd", 315, 194); // be
-selectCodeEditor("pwm_test.vhd", 394, 276); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'c'); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 362, 199); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 262, 374); // be
-selectCodeEditor("pwm_test_db.vhd", 110, 243); // be
-// Elapsed time: 38 seconds
-selectCodeEditor("pwm_test_db.vhd", 242, 296); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 281, 246); // be
-selectCodeEditor("pwm_test.vhd", 389, 229); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'c'); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 274, 131); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 72, 163); // be
-typeControlKey(null, null, 'z');
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 422, 206); // be
-typeControlKey(null, null, 'z');
-typeControlKey(null, null, 'z');
-typeControlKey(null, null, 'z');
-typeControlKey(null, null, 'z');
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 119, 292); // be
-selectCodeEditor("pwm_test.vhd", 375, 267); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'c'); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 18, 160); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 188, 244); // be
-selectCodeEditor("pwm_test_db.vhd", 400, 209); // be
-selectButton(RDIResourceCommand.RDICommands_LINE_COMMENT, (String) null); // D
-selectCodeEditor("pwm_test_db.vhd", 148, 260); // be
-// Elapsed time: 49 seconds
-selectCodeEditor("pwm_test_db.vhd", 165, 246); // be
-selectCodeEditor("pwm_test_db.vhd", 252, 155); // be
-selectCodeEditor("pwm_test_db.vhd", 231, 181); // be
-selectCodeEditor("pwm_test_db.vhd", 319, 258); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  7228 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 6520 ms. Increasing delay to 19560 ms.
-// Elapsed time: 20 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 231, 340); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 0); // m
-selectCodeEditor("pwm_test.vhd", 262, 207); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  8200 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 182, 57); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-// Elapsed time: 10 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 583, 258); // be
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 7 ms. Decreasing delay to 2007 ms.
-selectCodeEditor("pt1.vhd", 217, 264); // be
-selectCodeEditor("pt1.vhd", 122, 286); // be
-selectCodeEditor("pt1.vhd", 162, 278); // be
-selectCodeEditor("pt1.vhd", 133, 274); // be
-selectCodeEditor("pt1.vhd", 111, 282); // be
-selectCodeEditor("pt1.vhd", 111, 282, false, false, false, false, true); // be - Double Click
-// Elapsed time: 19 seconds
-selectCodeEditor("pt1.vhd", 77, 307); // be
-selectCodeEditor("pt1.vhd", 239, 324); // be
-selectCodeEditor("pt1.vhd", 283, 168); // be
-selectCodeEditor("pt1.vhd", 277, 176); // be
-selectCodeEditor("pt1.vhd", 191, 250); // be
-selectCodeEditor("pt1.vhd", 230, 200); // be
-selectCodeEditor("pt1.vhd", 162, 193); // be
-selectCodeEditor("pt1.vhd", 212, 193); // be
-selectCodeEditor("pt1.vhd", 219, 196); // be
-typeControlKey((HResource) null, "pt1.vhd", 'c'); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 224, 310); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 298, 335); // be
-selectCodeEditor("pwm_test_db.vhd", 51, 315); // be
-selectCodeEditor("pwm_test_db.vhd", 54, 330); // be
-selectCodeEditor("pwm_test_db.vhd", 57, 354); // be
-selectCodeEditor("pwm_test_db.vhd", 85, 335); // be
-selectCodeEditor("pwm_test_db.vhd", 239, 197); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 1); // m
-selectCodeEditor("pt1.vhd", 80, 224); // be
-selectCodeEditor("pt1.vhd", 0, 352); // be
-selectCodeEditor("pt1.vhd", 184, 364); // be
-typeControlKey((HResource) null, "pt1.vhd", 'c'); // be
-selectCodeEditor("pt1.vhd", 1, 348); // be
-selectCodeEditor("pt1.vhd", 176, 99); // be
-selectCodeEditor("pt1.vhd", 191, 153); // be
-selectCodeEditor("pt1.vhd", 217, 292); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  8061 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 6339 ms. Increasing delay to 19017 ms.
-// Elapsed time: 10 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 194, 270); // be
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  7966 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Elapsed time: 11 seconds
-selectCodeEditor("pwm_test_db.vhd", 16, 131); // be
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 7 ms. Decreasing delay to 2007 ms.
-selectCodeEditor("pwm_test_db.vhd", 42, 127); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 103, 149); // be
-selectCodeEditor("pwm_test_db.vhd", 273, 209); // be
-selectCodeEditor("pwm_test_db.vhd", 0, 162); // be
-selectCodeEditor("pwm_test_db.vhd", 59, 144); // be
-selectCodeEditor("pwm_test_db.vhd", 10, 177); // be
-selectCodeEditor("pwm_test_db.vhd", 159, 192); // be
-selectCodeEditor("pwm_test_db.vhd", 29, 151); // be
-selectCodeEditor("pwm_test_db.vhd", 29, 151, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 339, 243); // be
-selectCodeEditor("pwm_test_db.vhd", 297, 339); // be
-// TclEventType: DG_GRAPH_STALE
-// [GUI Memory]: 212 MB (+3955kb) [01:20:19]
-// WARNING: HEventQueue.dispatchEvent() is taking  8093 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Elapsed time: 11 seconds
-selectCodeEditor("pwm_test_db.vhd", 484, 315); // be
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 6855 ms. Increasing delay to 20565 ms.
-// Elapsed time: 17 seconds
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 1259, 37); // dT
-selectCodeEditor("pwm_test_db.vhd", 305, 414); // be
-selectCodeEditor("pwm_test_db.vhd", 282, 251); // be
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 6 ms. Decreasing delay to 2006 ms.
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Wed May 18 20:50:45 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 63 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectCodeEditor("pwm_test_db.vhd", 143, 276); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 10 s 
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 148 MB. Current time: 5/18/22, 8:52:03 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 10 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1388.887 ; gain = 7.539 
-// 'd' command handler elapsed time: 12 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 49, 141); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 147 MB. Current time: 5/18/22, 8:52:07 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 90, 47); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 24, 97); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 147 MB. Current time: 5/18/22, 8:52:20 PM CEST
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 13, 81); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 147 MB. Current time: 5/18/22, 8:52:22 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 147 MB. Current time: 5/18/22, 8:52:23 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 147 MB. Current time: 5/18/22, 8:52:24 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:27 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 154 MB. Current time: 5/18/22, 8:52:27 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:27 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:27 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 154 MB. Current time: 5/18/22, 8:52:27 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 156 MB. Current time: 5/18/22, 8:52:27 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 156 MB. Current time: 5/18/22, 8:52:27 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 160 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 154 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 150 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 153 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:28 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:29 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,269 MB. GUI used memory: 146 MB. Current time: 5/18/22, 8:52:29 PM CEST
-selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 337, 243); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 254, 421); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 2); // m
-selectCodeEditor("pwm_test_db.vhd", 199, 369); // be
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid3672.str b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid3672.str
deleted file mode 100644
index 7cb53a6..0000000
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid3672.str
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
-
-Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
-SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
-IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
-
-Process ID (PID): 3672
-License: Customer
-Mode: GUI Mode
-
-Current time: 	Fri May 13 11:28:40 CEST 2022
-Time zone: 	Central European Standard Time (Europe/Berlin)
-
-OS: Windows 10
-OS Version: 10.0
-OS Architecture: amd64
-Available processors (cores): 12
-
-Screen size: 1920x1080
-Screen resolution (DPI): 100
-Available screens: 2
-Default font: family=Dialog,name=Dialog,style=plain,size=12
-Scale size: 12
-
-Java version: 	11.0.11 64-bit
-Java home: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9
-Java executable: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe
-Java arguments: 	[-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
-Java initial memory (-Xms): 	256 MB
-Java maximum memory (-Xmx):	 3 GB
-
-
-User name: 	Felix
-User home directory: C:/Users/Felix
-User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-User country: 	DE
-User language: 	de
-User locale: 	de_DE
-
-RDI_BASEROOT: C:/Xilinx/Vivado
-HDI_APPROOT: C:/Xilinx/Vivado/2021.2
-RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data
-RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin
-
-Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml
-Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/
-Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts
-PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
-Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
-Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-3672-DESKTOP-PAACOM8
-
-Xilinx Environment Variables
-----------------------------
-TWINCATSDK: C:\TwinCAT\3.1\SDK\
-XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
-XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
-XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2
-XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2
-XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
-XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
-
-
-GUI allocated memory:	256 MB
-GUI max memory:		3,072 MB
-Engine allocated memory: 1,300 MB
-
-Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-
-*/
-
-// TclEventType: START_GUI
-// Tcl Message: start_gui 
-// TclEventType: PROJECT_OPEN_DIALOG
-// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 
-// TclEventType: DEBUG_PROBE_SET_CHANGE
-// TclEventType: FLOW_ADDED
-// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
-// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 57 MB. Current time: 5/13/22, 11:28:41 AM CEST
-// TclEventType: MSGMGR_MOVEMSG
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: FILE_SET_NEW
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_CURRENT
-// TclEventType: PROJECT_DASHBOARD_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_NEW
-// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
-// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// Tcl Message: INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save. 
-// Tcl Message: INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 
-// Tcl Message: Scanning sources... Finished scanning sources 
-// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified 
-// TclEventType: PROJECT_NEW
-// [GUI Memory]: 79 MB (+80353kb) [00:00:27]
-// [Engine Memory]: 1,300 MB (+1211828kb) [00:00:27]
-// WARNING: HEventQueue.dispatchEvent() is taking  7148 ms.
-// WARNING: HEventQueue.dispatchEvent() is taking  1355 ms.
-// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
-// [GUI Memory]: 107 MB (+24993kb) [00:00:34]
-// Tcl Message: open_project: Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 1576.332 ; gain = 0.000 
-// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
-dismissDialog("Open Project"); // bA
-// Tcl Message: update_compile_order -fileset sources_1 
-// Elapsed time: 10 seconds
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "OK"); // JButton
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_STATUS_CHANGE
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Fri May 13 11:29:15 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// TclEventType: RUN_STATUS_CHANGE
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:29:44 AM CEST
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:30:15 AM CEST
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:30:45 AM CEST
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:32:14 AM CEST
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:32:45 AM CEST
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:33:15 AM CEST
-// Elapsed time: 245 seconds
-selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a
-// 'k' command handler elapsed time: 249 seconds
-closeMainWindow("Coraz7_Test - [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr] - Vivado 2021.2"); // bb
-// HOptionPane Warning: 'A background task is running. Please wait until it completes to exit Vivado. If you choose to abort background task and exit immediately, you will lose all unsaved changes to project. (Background Task)'