diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
index 9570c6a..881df7a 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
@@ -1,4 +1,4 @@
 version:1
 57656254616c6b5472616e736d697373696f6e417474656d70746564:13
-6d6f64655f636f756e7465727c4755494d6f6465:23
+6d6f64655f636f756e7465727c4755494d6f6465:25
 eof:
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml
index eb61f2c..19611ac 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml
@@ -1,14 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1652439174" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp">
   <File Type="PA-TCL" Name="regler.tcl"/>
-  <File Type="RDS-PROPCONSTRS" Name="regler_drc_synth.rpt"/>
   <File Type="REPORTS-TCL" Name="regler_reports.tcl"/>
   <File Type="RDS-RDS" Name="regler.vds"/>
   <File Type="RDS-UTIL" Name="regler_utilization_synth.rpt"/>
   <File Type="RDS-UTIL-PB" Name="regler_utilization_synth.pb"/>
   <File Type="RDS-DCP" Name="regler.dcp"/>
-  <File Type="VDS-TIMINGSUMMARY" Name="regler_timing_summary_synth.rpt"/>
-  <File Type="VDS-TIMING-PB" Name="regler_timing_summary_synth.pb"/>
   <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
     <Filter Type="Srcs"/>
     <File Path="$PSRCDIR/sources_1/new/pwm_test.vhd">
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
index 273a853..2ec2275 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
@@ -6,7 +6,7 @@ REM Filename    : compile.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for compiling the simulation design source files
 REM
-REM Generated by Vivado on Fri May 13 12:56:52 +0200 2022
+REM Generated by Vivado on Fri May 13 13:48:21 +0200 2022
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log
index 8edd643..e69de29 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log
@@ -1,2 +0,0 @@
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
index 6a213b9..9818fb3 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
@@ -6,7 +6,7 @@ REM Filename    : elaborate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for elaborating the compiled design
 REM
-REM Generated by Vivado on Fri May 13 12:56:53 +0200 2022
+REM Generated by Vivado on Fri May 13 13:48:23 +0200 2022
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log
index 8184d8e..1d8ca0a 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log
@@ -8,17 +8,4 @@ WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users
 WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
 Completed static elaboration
 Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling package ieee.numeric_std
-Compiling package ieee.fixed_float_types
-Compiling package ieee.fixed_pkg
-Compiling package ieee.math_real
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
+ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb
index 135cf7d..ad9dd83 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb
index fe19bc3..5cb5bb9 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini
index 5345cb8..33023c2 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini
@@ -28,7 +28,7 @@ VARIABLE_PROTOINST_FILTER=true
 SCOPE_NAME_COLUMN_WIDTH=157
 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
-OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=156
 OBJECT_VALUE_COLUMN_WIDTH=75
 OBJECT_DATA_TYPE_COLUMN_WIDTH=75
 PROCESS_NAME_COLUMN_WIDTH=75
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
index 5cfdf92..5c20574 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
@@ -2,3 +2,6 @@ Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_beha
 Design successfully loaded
 Design Loading Memory Usage: 7256 KB (Peak: 7256 KB)
 Design Loading CPU Usage: 15 ms
+Simulation completed
+Simulation Memory Usage: 7792 KB (Peak: 7792 KB)
+Simulation CPU Usage: 15 ms
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb
index c047b93..1388390 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
index 5a0c577..c01d11b 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -2,7 +2,7 @@
 2020.2
 Oct 19 2021
 03:16:22
-C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652439407,vhdl2008,,,,pwm_test_db,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652442389,vhdl,,,,pwm_test_db,,,,,,,,
 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1651498208,vhdl,,,,pt1,,,,,,,,
 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652437038,vhdl,,,,regler,,,,,,,,
 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd,1652437027,vhdl,,,,wendetangente,,,,,,,,
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log
index 8edd643..e69de29 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log
@@ -1,2 +0,0 @@
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb
index 3a6973b..b155e40 100644
Binary files a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
index 92566fd..9cfb6ad 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
@@ -116,7 +116,7 @@ begin
         cnt <= cnt+1;
         risingEdge <= '1';
         clk_100 <= '0';
-        a <= a + to_sfixed(1.111, 7, -6);
+        --a <= a + to_sfixed(1.111, 7, -6);
     end if;
     
     if clk = '0' then
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
index f093a63..cf9e0d0 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
@@ -56,7 +56,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="zybo-z7-10"/>
-    <Option Name="WTXSimLaunchSim" Val="116"/>
+    <Option Name="WTXSimLaunchSim" Val="119"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -177,7 +177,7 @@
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
       <File Path="$PSRCDIR/sim_1/new/pwm_test_db.vhd">
-        <FileInfo SFType="VHDL2008">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
index c7cf45c..7a5978b 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
@@ -2,10 +2,10 @@
 # Vivado v2021.2 (64-bit)
 # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Fri May 13 11:33:33 2022
-# Process ID: 5492
+# Start of session at: Fri May 13 14:02:42 2022
+# Process ID: 17732
 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
 # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
 # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
 # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
@@ -13,67 +13,3 @@
 start_gui
 open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
 update_compile_order -fileset sources_1
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-launch_runs impl_1 -jobs 6
-wait_on_run impl_1
-close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ]
-add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
-update_compile_order -fileset sources_1
-open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}
-import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl}
-update_compile_order -fileset sources_1
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]
-set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]
-set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]
-set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]
-set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-launch_runs impl_1 -jobs 6
-wait_on_run impl_1
-open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-launch_simulation
-launch_simulation
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd]
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-current_wave_config {pwm_test_db_func_synth.wcfg}
-add_wave {{/pwm_test_db/uutWendeTangente/a}} 
-current_wave_config {pwm_test_db_func_synth.wcfg}
-add_wave {{/pwm_test_db/uutWendeTangente/b}} 
-current_wave_config {pwm_test_db_func_synth.wcfg}
-add_wave {{/pwm_test_db/uutWendeTangente/c}} 
-save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55
-remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
index ecdb65c..24f845a 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
@@ -2,10 +2,10 @@
 # Vivado v2021.2 (64-bit)
 # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Fri May 13 11:33:33 2022
-# Process ID: 5492
+# Start of session at: Fri May 13 14:02:42 2022
+# Process ID: 17732
 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
 # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
 # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
 # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
@@ -66,710 +66,5 @@ Finished scanning sources
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 INFO: [IP_Flow 19-1704] No user IP repositories specified
 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
-open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000
+open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.184 ; gain = 0.000
 update_compile_order -fileset sources_1
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-launch_runs synth_1 -jobs 6
-[Fri May 13 11:34:46 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-launch_runs impl_1 -jobs 6
-[Fri May 13 11:36:03 2022] Launched impl_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log
-close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ]
-add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
-update_compile_order -fileset sources_1
-open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}
-Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>...
-INFO: [Common 17-41] Interrupt caught. Command should exit soon.
-INFO: [Common 17-344] 'source' was cancelled
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
- - 
-    while executing
-"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
-ERROR: [Ip 78-89] Error in evaluating command source init.tcl
- - 
-    while executing
-"source init.tcl"
-1
-INFO: [BD 41-1808] Open Block Design has been cancelled.
-INFO: [Common 17-344] 'open_bd_design' was cancelled
-import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl}
-update_compile_order -fileset sources_1
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]
-set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]
-set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]
-set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]
-set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-launch_runs synth_1 -jobs 6
-[Fri May 13 12:17:21 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-launch_runs impl_1 -jobs 6
-[Fri May 13 12:18:35 2022] Launched impl_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log
-open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}
-Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>...
-Successfully read diagram <design_1> from block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-launch_runs synth_1 -jobs 6
-[Fri May 13 12:28:24 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl" into library ieee_proposed
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl" into library ieee_proposed
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl" into library ieee_proposed
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl" into library ieee_proposed
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'wendeTangente'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-Completed static elaboration
-Starting simulation data flow analysis
-ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
-Printing stacktrace...
-
-[0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]
-[1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]
-[2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]
-[3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]
-[4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]
-[5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff914b26443]
-[6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff914b29088]
-[7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]
-[8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]
-[9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]
-[10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]
-[11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]
-[12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]
-[13]  [0x7ff65f3a24cf]
-[14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]
-[15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]
-[16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]
-[17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]
-
-Done
-INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
-INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
-ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
-ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
-launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000
-ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-Completed static elaboration
-Starting simulation data flow analysis
-ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
-Printing stacktrace...
-
-[0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]
-[1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]
-[2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]
-[3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]
-[4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]
-[5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9180a6443]
-[6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9180a9088]
-[7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]
-[8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]
-[9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]
-[10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]
-[11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]
-[12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]
-[13]  [0x7ff65f3a24cf]
-[14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]
-[15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]
-[16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]
-[17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]
-
-Done
-INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
-INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
-ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
-ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
-launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.359 ; gain = 0.000
-ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
-set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd]
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling package ieee.numeric_std
-Compiling package ieee.fixed_float_types
-Compiling package ieee.fixed_pkg
-Compiling package ieee.math_real
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
-Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
-  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
-
-HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1580.359 ; gain = 0.000
-current_wave_config {pwm_test_db_func_synth.wcfg}
-pwm_test_db_func_synth.wcfg
-add_wave {{/pwm_test_db/uutWendeTangente/a}} 
-current_wave_config {pwm_test_db_func_synth.wcfg}
-pwm_test_db_func_synth.wcfg
-add_wave {{/pwm_test_db/uutWendeTangente/b}} 
-current_wave_config {pwm_test_db_func_synth.wcfg}
-pwm_test_db_func_synth.wcfg
-add_wave {{/pwm_test_db/uutWendeTangente/c}} 
-save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
-Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
-  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
-
-HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55
-remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
-Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
-  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
-
-HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling package ieee.numeric_std
-Compiling package ieee.fixed_float_types
-Compiling package ieee.fixed_pkg
-Compiling package ieee.math_real
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
-Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
-  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
-
-HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000
-save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Fri May 13 12:52:54 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:46]
-ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:53]
-ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:65]
-ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:66]
-ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:72]
-ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:83]
-ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:90]
-ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:102]
-ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:116]
-ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:117]
-ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114]
-ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114]
-ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:122]
-ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121]
-ERROR: [VRFC 10-2123] 0 definitions of operator "??" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121]
-ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:126]
-ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:43]
-INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd' ignored due to errors
-INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
-INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log'
-ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
-ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
-ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
-WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling package ieee.numeric_std
-Compiling package ieee.fixed_float_types
-Compiling package ieee.fixed_pkg
-Compiling package ieee.math_real
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
-Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
-  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
-
-HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.jou
deleted file mode 100644
index 4a1ebb9..0000000
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.jou
+++ /dev/null
@@ -1,14 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2021.2 (64-bit)
-# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
-# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Wed May  4 17:41:44 2022
-# Process ID: 17388
-# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22812 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
-# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
-# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
-#-----------------------------------------------------------sstart_guiopen_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
-update_compile_order -fileset sources_1
-
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.jou
new file mode 100644
index 0000000..868220a
--- /dev/null
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.jou
@@ -0,0 +1,16 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 13:47:22 2022
+# Process ID: 19540
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17020 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+update_compile_order -fileset sources_1
+launch_simulation
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.log
similarity index 64%
rename from StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.log
rename to StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.log
index be43c05..c896a04 100644
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.log
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.log
@@ -2,21 +2,24 @@
 # Vivado v2021.2 (64-bit)
 # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Wed May  4 17:41:44 2022
-# Process ID: 17388
-# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22812 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
-# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
+# Start of session at: Fri May 13 13:47:22 2022
+# Process ID: 19540
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17020 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
 # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
-#-----------------------------------------------------------sstart_guiopen_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
 INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
-Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
-WWARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
@@ -56,12 +59,71 @@ WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 avai
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not availableIINFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' since last save.INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
-IINFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.Scanning sources...
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
+INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
+Scanning sources...
 Finished scanning sources
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 INFO: [IP_Flow 19-1704] No user IP repositories specified
-IINFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.open_project: Time (s): cpu = 00:00:36 ; elapsed = 00:00:19 . Memory (MB): peak = 1250.172 ; gain = 0.000
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+open_project: Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 1251.859 ; gain = 0.000
 update_compile_order -fileset sources_1
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+Starting simulation data flow analysis
+ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
+Printing stacktrace...
+
+[0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]
+[1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]
+[2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]
+[3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]
+[4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]
+[5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff90fea6443]
+[6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff90fea9088]
+[7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]
+[8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]
+[9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]
+[10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]
+[11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]
+[12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]
+[13]  [0x7ff65f3a24cf]
+[14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]
+[15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]
+[16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]
+[17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]
+
+Done
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
 exit
-INFO: [Common 17-206] Exiting Vivado at Wed May  4 17:58:54 2022...
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 13:50:06 2022...
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.jou
deleted file mode 100644
index a8fcf30..0000000
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.jou
+++ /dev/null
@@ -1,43 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2021.2 (64-bit)
-# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
-# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Mon May  2 13:48:39 2022
-# Process ID: 3460
-# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9928 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
-# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log
-# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou
-# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
-#-----------------------------------------------------------
-start_gui
-open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
-update_compile_order -fileset sources_1
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 61
-remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 61
-remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62
-remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.log
deleted file mode 100644
index 85d3d27..0000000
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.log
+++ /dev/null
@@ -1,295 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2021.2 (64-bit)
-# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
-# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Mon May  2 13:48:39 2022
-# Process ID: 3460
-# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9928 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
-# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log
-# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou
-# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
-#-----------------------------------------------------------
-start_gui
-open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
-INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
-Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim'
-WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
-INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
-INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
-Scanning sources...
-Finished scanning sources
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
-open_project: Time (s): cpu = 00:00:31 ; elapsed = 00:00:12 . Memory (MB): peak = 1254.516 ; gain = 0.000
-update_compile_order -fileset sources_1
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1271.582 ; gain = 17.066
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Mon May  2 13:54:34 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 61
-remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 61
-remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62
-remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62
-add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Mon May  2 14:46:17 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-WARNING: [Simulator 45-24] Previous breakpoint at line 62 in file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd' not restored because it is no longer a breakable line.
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1271.582 ; gain = 0.000
-reset_run synth_1
-INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
-WARNING: [Vivado 12-1017] Problems encountered:
-1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Mon May  2 14:59:49 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-Command: launch_simulation 
-INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
-WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
-INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
-INFO: [USF-XSim-7] Finding pre-compiled libraries...
-INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'pt1'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'regler'
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
-Vivado Simulator v2021.2
-Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
-Using 2 slave threads.
-Starting static elaboration
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
-Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
-Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
-Built simulation snapshot pwm_test_db_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
-   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Time resolution is 1 ps
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-#   if { [llength [get_objects]] > 0} {
-#     add_wave /
-#     set_property needs_save false [current_wave_config]
-#   } else {
-#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-#   }
-# }
-# run 5 s
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 5 s
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1271.582 ; gain = 0.000
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-exit
-INFO: [Common 17-206] Exiting Vivado at Mon May  2 15:30:20 2022...
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.jou
new file mode 100644
index 0000000..30919ad
--- /dev/null
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.jou
@@ -0,0 +1,83 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 11:33:33 2022
+# Process ID: 5492
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+update_compile_order -fileset sources_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_runs impl_1 -jobs 6
+wait_on_run impl_1
+close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ]
+add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
+update_compile_order -fileset sources_1
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}
+import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl}
+update_compile_order -fileset sources_1
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]
+set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]
+set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]
+set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]
+set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_runs impl_1 -jobs 6
+wait_on_run impl_1
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_simulation
+launch_simulation
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd]
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+current_wave_config {pwm_test_db_func_synth.wcfg}
+add_wave {{/pwm_test_db/uutWendeTangente/a}} 
+current_wave_config {pwm_test_db_func_synth.wcfg}
+add_wave {{/pwm_test_db/uutWendeTangente/b}} 
+current_wave_config {pwm_test_db_func_synth.wcfg}
+add_wave {{/pwm_test_db/uutWendeTangente/c}} 
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55
+remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+set_property file_type VHDL [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd]
+close_sim
+launch_simulation
+launch_simulation
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.log
new file mode 100644
index 0000000..e4fff47
--- /dev/null
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.log
@@ -0,0 +1,900 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 11:33:33 2022
+# Process ID: 5492
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
+Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
+INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
+Scanning sources...
+Finished scanning sources
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000
+update_compile_order -fileset sources_1
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+launch_runs synth_1 -jobs 6
+[Fri May 13 11:34:46 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 6
+[Fri May 13 11:36:03 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log
+close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ]
+add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
+update_compile_order -fileset sources_1
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}
+Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>...
+INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+INFO: [Common 17-344] 'source' was cancelled
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]
+ - 
+    while executing
+"source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"
+ERROR: [Ip 78-89] Error in evaluating command source init.tcl
+ - 
+    while executing
+"source init.tcl"
+1
+INFO: [BD 41-1808] Open Block Design has been cancelled.
+INFO: [Common 17-344] 'open_bd_design' was cancelled
+import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl}
+update_compile_order -fileset sources_1
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]
+set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]
+set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]
+set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]
+set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+launch_runs synth_1 -jobs 6
+[Fri May 13 12:17:21 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 6
+[Fri May 13 12:18:35 2022] Launched impl_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log
+open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}
+Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>...
+Successfully read diagram <design_1> from block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+launch_runs synth_1 -jobs 6
+[Fri May 13 12:28:24 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pt1'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'regler'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl" into library ieee_proposed
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl" into library ieee_proposed
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl" into library ieee_proposed
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl" into library ieee_proposed
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'wendeTangente'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+Starting simulation data flow analysis
+ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
+Printing stacktrace...
+
+[0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]
+[1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]
+[2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]
+[3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]
+[4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]
+[5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff914b26443]
+[6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff914b29088]
+[7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]
+[8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]
+[9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]
+[10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]
+[11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]
+[12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]
+[13]  [0x7ff65f3a24cf]
+[14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]
+[15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]
+[16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]
+[17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]
+
+Done
+INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
+INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+Starting simulation data flow analysis
+ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
+Printing stacktrace...
+
+[0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]
+[1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]
+[2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]
+[3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]
+[4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]
+[5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9180a6443]
+[6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9180a9088]
+[7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]
+[8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]
+[9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]
+[10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]
+[11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]
+[12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]
+[13]  [0x7ff65f3a24cf]
+[14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]
+[15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]
+[16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]
+[17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]
+
+Done
+INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
+INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.359 ; gain = 0.000
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd]
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package ieee.fixed_float_types
+Compiling package ieee.fixed_pkg
+Compiling package ieee.math_real
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
+Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
+  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
+
+HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1580.359 ; gain = 0.000
+current_wave_config {pwm_test_db_func_synth.wcfg}
+pwm_test_db_func_synth.wcfg
+add_wave {{/pwm_test_db/uutWendeTangente/a}} 
+current_wave_config {pwm_test_db_func_synth.wcfg}
+pwm_test_db_func_synth.wcfg
+add_wave {{/pwm_test_db/uutWendeTangente/b}} 
+current_wave_config {pwm_test_db_func_synth.wcfg}
+pwm_test_db_func_synth.wcfg
+add_wave {{/pwm_test_db/uutWendeTangente/c}} 
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
+Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
+  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
+
+HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000
+add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55
+remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
+Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
+  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
+
+HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package ieee.fixed_float_types
+Compiling package ieee.fixed_pkg
+Compiling package ieee.math_real
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
+Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
+  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
+
+HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
+reset_run synth_1
+INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
+WARNING: [Vivado 12-1017] Problems encountered:
+1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
+
+launch_runs synth_1 -jobs 6
+[Fri May 13 12:52:54 2022] Launched synth_1...
+Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:46]
+ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:53]
+ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:65]
+ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:66]
+ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:72]
+ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:83]
+ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:90]
+ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:102]
+ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:116]
+ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:117]
+ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114]
+ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114]
+ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:122]
+ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121]
+ERROR: [VRFC 10-2123] 0 definitions of operator "??" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121]
+ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:126]
+ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:43]
+INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd' ignored due to errors
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log'
+ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package ieee.fixed_float_types
+Compiling package ieee.fixed_pkg
+Compiling package ieee.math_real
+Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
+Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
+Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]
+Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
+Built simulation snapshot pwm_test_db_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+   with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+#   if { [llength [get_objects]] > 0} {
+#     add_wave /
+#     set_property needs_save false [current_wave_config]
+#   } else {
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+#   }
+# }
+# run 5 s
+ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements
+Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51
+  File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd
+
+HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 5 s
+launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000
+set_property file_type VHDL [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd]
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+Starting simulation data flow analysis
+ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
+Printing stacktrace...
+
+[0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]
+[1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]
+[2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]
+[3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]
+[4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]
+[5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9830a6443]
+[6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9830a9088]
+[7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]
+[8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]
+[9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]
+[10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]
+[11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]
+[12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]
+[13]  [0x7ff65f3a24cf]
+[14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]
+[15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]
+[16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]
+[17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]
+
+Done
+INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
+INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation 
+INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
+WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
+INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
+"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
+WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
+Completed static elaboration
+Starting simulation data flow analysis
+ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
+Printing stacktrace...
+
+[0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]
+[1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]
+[2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]
+[3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]
+[4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]
+[5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff90fad6443]
+[6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff90fad9088]
+[7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]
+[8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]
+[9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]
+[10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]
+[11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]
+[12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]
+[13]  [0x7ff65f3a24cf]
+[14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]
+[15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]
+[16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]
+[17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]
+
+Done
+INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
+INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+exit
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 13:47:14 2022...
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid17732.str b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid17732.str
new file mode 100644
index 0000000..1e93c8e
--- /dev/null
+++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid17732.str
@@ -0,0 +1,154 @@
+/*
+
+Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
+SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
+IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
+
+Process ID (PID): 17732
+License: Customer
+Mode: GUI Mode
+
+Current time: 	Fri May 13 14:02:56 CEST 2022
+Time zone: 	Central European Standard Time (Europe/Berlin)
+
+OS: Windows 10
+OS Version: 10.0
+OS Architecture: amd64
+Available processors (cores): 12
+
+Screen size: 1920x1080
+Screen resolution (DPI): 100
+Available screens: 2
+Default font: family=Dialog,name=Dialog,style=plain,size=12
+Scale size: 12
+
+Java version: 	11.0.11 64-bit
+Java home: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9
+Java executable: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe
+Java arguments: 	[-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
+Java initial memory (-Xms): 	256 MB
+Java maximum memory (-Xmx):	 3 GB
+
+
+User name: 	Felix
+User home directory: C:/Users/Felix
+User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
+User country: 	DE
+User language: 	de
+User locale: 	de_DE
+
+RDI_BASEROOT: C:/Xilinx/Vivado
+HDI_APPROOT: C:/Xilinx/Vivado/2021.2
+RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data
+RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin
+
+Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml
+Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/
+Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts
+PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
+Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
+Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-17732-DESKTOP-PAACOM8
+
+Xilinx Environment Variables
+----------------------------
+TWINCATSDK: C:\TwinCAT\3.1\SDK\
+XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
+XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
+XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2
+XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2
+XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
+XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
+
+
+GUI allocated memory:	342 MB
+GUI max memory:		3,072 MB
+Engine allocated memory: 1,325 MB
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+*/
+
+// TclEventType: START_GUI
+// Tcl Message: start_gui 
+// TclEventType: PROJECT_OPEN_DIALOG
+// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// TclEventType: FLOW_ADDED
+// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
+// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
+// HMemoryUtils.trashcanNow. Engine heap size: 1,325 MB. GUI used memory: 56 MB. Current time: 5/13/22, 2:02:57 PM CEST
+// TclEventType: MSGMGR_MOVEMSG
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_NEW
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_CURRENT
+// TclEventType: PROJECT_DASHBOARD_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_NEW
+// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
+// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
+// Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 
+// Tcl Message: Scanning sources... Finished scanning sources 
+// TclEventType: PROJECT_NEW
+// [GUI Memory]: 77 MB (+78665kb) [00:00:15]
+// [Engine Memory]: 1,325 MB (+1237477kb) [00:00:15]
+// WARNING: HEventQueue.dispatchEvent() is taking  3112 ms.
+// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
+// [GUI Memory]: 102 MB (+21713kb) [00:00:18]
+// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
+// Tcl Message: open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.184 ; gain = 0.000 
+dismissDialog("Open Project"); // bA
+// Tcl Message: update_compile_order -fileset sources_1 
+// PAPropertyPanels.initPanels (pwm_test.vhd) elapsed time: 0.2s
+// Elapsed time: 11 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false, false, false, false, false, true); // D - Double Click
+// WARNING: HEventQueue.dispatchEvent() is taking  1801 ms.
+// [GUI Memory]: 134 MB (+27930kb) [00:00:32]
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false, false, false, false, false, true); // D - Double Click
+// WARNING: HEventQueue.dispatchEvent() is taking  1441 ms.
+// Elapsed time: 10 seconds
+selectCodeEditor("pt1.vhd", 88, 451); // be
+selectCodeEditor("pt1.vhd", 11, 348, false, false, false, true, false); // be - Popup Trigger
+selectMenuItem(RDIResourceCommand.RDICommands_COPY, "Copy"); // ao
+// Elapsed time: 24 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false, false, false, false, false, true); // D - Double Click
+// WARNING: HEventQueue.dispatchEvent() is taking  1130 ms.
+dismissDialog("Opening Editor"); // bA
+selectCodeEditor("wendeTangente.vhd", 126, 259); // be
+typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be
+// Elapsed time: 82 seconds
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 7); // D
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 8); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 10, true); // D - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd), uut_regler : regler(Behavioral) (pwm_test.vhd)]", 11, false, false, false, false, false, true); // D - Double Click
+// WARNING: HEventQueue.dispatchEvent() is taking  1115 ms.
+// [GUI Memory]: 145 MB (+4836kb) [00:02:44]
+dismissDialog("Opening Editor"); // bA
+selectCodeEditor("pwm_test_db.vhd", 149, 169); // be
+typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
+// Elapsed time: 45 seconds
+selectCodeEditor("pwm_test_db.vhd", 251, 110); // be
+typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
+selectCodeEditor("pwm_test_db.vhd", 83, 268); // be
+typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
+// Elapsed time: 50 seconds
+selectCodeEditor("pwm_test_db.vhd", 217, 345); // be
+// Elapsed time: 732 seconds
+selectCodeEditor("pwm_test_db.vhd", 229, 347); // be
+// HMemoryUtils.trashcanNow. Engine heap size: 1,325 MB. GUI used memory: 81 MB. Current time: 5/13/22, 2:32:57 PM CEST
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid5492.str b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid5492.str
deleted file mode 100644
index 83c518b..0000000
--- a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid5492.str
+++ /dev/null
@@ -1,1973 +0,0 @@
-/*
-
-Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
-SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
-IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
-
-Process ID (PID): 5492
-License: Customer
-Mode: GUI Mode
-
-Current time: 	Fri May 13 11:33:46 CEST 2022
-Time zone: 	Central European Standard Time (Europe/Berlin)
-
-OS: Windows 10
-OS Version: 10.0
-OS Architecture: amd64
-Available processors (cores): 12
-
-Screen size: 1920x1080
-Screen resolution (DPI): 100
-Available screens: 2
-Default font: family=Dialog,name=Dialog,style=plain,size=12
-Scale size: 12
-
-Java version: 	11.0.11 64-bit
-Java home: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9
-Java executable: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe
-Java arguments: 	[-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
-Java initial memory (-Xms): 	256 MB
-Java maximum memory (-Xmx):	 3 GB
-
-
-User name: 	Felix
-User home directory: C:/Users/Felix
-User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-User country: 	DE
-User language: 	de
-User locale: 	de_DE
-
-RDI_BASEROOT: C:/Xilinx/Vivado
-HDI_APPROOT: C:/Xilinx/Vivado/2021.2
-RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data
-RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin
-
-Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml
-Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/
-Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts
-PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
-Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
-Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-5492-DESKTOP-PAACOM8
-
-Xilinx Environment Variables
-----------------------------
-TWINCATSDK: C:\TwinCAT\3.1\SDK\
-XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
-XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
-XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2
-XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2
-XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
-XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
-
-
-GUI allocated memory:	324 MB
-GUI max memory:		3,072 MB
-Engine allocated memory: 1,307 MB
-
-Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-
-*/
-
-// TclEventType: START_GUI
-// Tcl Message: start_gui 
-// TclEventType: PROJECT_OPEN_DIALOG
-// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 
-// TclEventType: DEBUG_PROBE_SET_CHANGE
-// TclEventType: FLOW_ADDED
-// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
-// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 57 MB. Current time: 5/13/22, 11:33:47 AM CEST
-// TclEventType: MSGMGR_MOVEMSG
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: FILE_SET_NEW
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_FAILED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_CURRENT
-// TclEventType: PROJECT_DASHBOARD_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_NEW
-// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
-// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 
-// Tcl Message: Scanning sources... Finished scanning sources 
-// TclEventType: PROJECT_NEW
-// [GUI Memory]: 81 MB (+82453kb) [00:00:14]
-// [Engine Memory]: 1,307 MB (+1218722kb) [00:00:14]
-// WARNING: HEventQueue.dispatchEvent() is taking  2855 ms.
-// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
-// Tcl Message: open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000 
-// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
-dismissDialog("Open Project"); // bA
-// [GUI Memory]: 115 MB (+31765kb) [00:00:19]
-selectButton(PAResourceQtoS.RunGadget_SHOW_ERROR, "5 errors"); // g
-// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW
-// Tcl Message: update_compile_order -fileset sources_1 
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints]", 4); // D
-// PAPropertyPanels.initPanels (Cora-Z7-10-Master.xdc) elapsed time: 0.2s
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Cora-Z7-10-Master.xdc]", 6, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Cora-Z7-10-Master.xdc]", 6, false, false, false, false, false, true); // D - Double Click
-// [GUI Memory]: 128 MB (+7607kb) [00:00:27]
-// WARNING: HEventQueue.dispatchEvent() is taking  1562 ms.
-dismissDialog("Opening Editor"); // bA
-selectCodeEditor("Cora-Z7-10-Master.xdc", 78, 103); // be
-selectMenuItem(RDIResourceCommand.RDICommands_COPY, "Copy"); // ao
-// Elapsed time: 21 seconds
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_STATUS_CHANGE
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Fri May 13 11:34:46 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// [GUI Memory]: 136 MB (+1534kb) [00:02:03]
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 74 seconds
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_STATUS_CHANGE
-// Tcl Message: launch_runs impl_1 -jobs 6 
-// Tcl Message: [Fri May 13 11:36:03 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log 
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// TclEventType: RUN_FAILED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 56 seconds
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW
-dismissDialog("Implementation Failed"); // ag
-// TclEventType: FILE_SET_CHANGE
-// Elapsed time: 218 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // m
-// Elapsed time: 41 seconds
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false, false, false, false, false, true); // D - Double Click
-// WARNING: HEventQueue.dispatchEvent() is taking  1116 ms.
-dismissDialog("Opening Editor"); // bA
-// Elapsed time: 190 seconds
-selectCodeEditor("pwm_test.vhd", 212, 280); // be
-selectCodeEditor("pwm_test.vhd", 47, 263); // be
-selectCodeEditor("pwm_test.vhd", 474, 312); // be
-selectCodeEditor("pwm_test.vhd", 58, 355); // be
-typeControlKey((HResource) null, "pwm_test.vhd", 'v'); // be
-selectCodeEditor("pwm_test.vhd", 184, 376); // be
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 3, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true, false, false, false, true, false); // D - Popup Trigger - Node
-selectMenu(PAResourceCommand.PACommandNames_AUTO_UPDATE_HIER, "Hierarchy Update"); // al
-selectMenu(PAResourceQtoS.SrcMenu_IP_HIERARCHY, "IP Hierarchy"); // al
-selectMenuItem(PAResourceCommand.PACommandNames_ADD_SOURCES, "Add Sources..."); // ao
-// Run Command: PAResourceCommand.PACommandNames_ADD_SOURCES
-selectButton("NEXT", "Next >"); // JButton
-selectButton(PAResourceQtoS.SrcChooserPanel_CREATE_FILE, "Create File"); // a
-selectComboBox(PAResourceAtoD.CreateSrcFileDialog_FILE_TYPE, "VHDL", 3); // cm
-// Elapsed time: 33 seconds
-setText(PAResourceAtoD.CreateSrcFileDialog_FILE_NAME, "wendeTangente"); // aa
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Create Source File"); // F
-selectButton("FINISH", "Finish"); // JButton
-// 'g' command handler elapsed time: 48 seconds
-dismissDialog("Add Sources"); // c
-// Tcl Message: close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] 
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd 
-selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, " ; in ; false ; 0 ; 0", 0, "in", 1); // ab
-selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, " ; in ; false ; 0 ; 0", 0, (String) null, 0); // ab
-selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, null, -1, null, -1); // ab
-editTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, "value", 0, "Port Name", 0); // ab
-selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, " ; in ; false ; 0 ; 0", 1, "in", 1); // ab
-editTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, "out", 1, "Direction", 1); // ab
-selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, " ; out ; false ; 0 ; 0", 1, (String) null, 0); // ab
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-editTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, "param1", 1, "Port Name", 0); // ab
-// TclEventType: FILE_SET_CHANGE
-dismissDialog("Define Module"); // I
-selectCodeEditor("pwm_test.vhd", 607, 348); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// [GUI Memory]: 144 MB (+960kb) [00:12:40]
-// Tcl Message: update_compile_order -fileset sources_1 
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 3, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 4, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 4, false, false, false, false, false, true); // D - Double Click
-// WARNING: HEventQueue.dispatchEvent() is taking  1093 ms.
-dismissDialog("Opening Editor"); // bA
-selectCodeEditor("wendeTangente.vhd", 79, 426); // be
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 4, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false); // D
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-// Elapsed time: 18 seconds
-selectCodeEditor("wendeTangente.vhd", 59, 446); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Cora-Z7-10-Master.xdc", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectCodeEditor("wendeTangente.vhd", 62, 314); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectCodeEditor("wendeTangente.vhd", 28, 285); // be
-selectCodeEditor("wendeTangente.vhd", 26, 300); // be
-selectCodeEditor("wendeTangente.vhd", 28, 331); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be
-selectCodeEditor("wendeTangente.vhd", 108, 351); // be
-selectCodeEditor("wendeTangente.vhd", 80, 403); // be
-selectCodeEditor("wendeTangente.vhd", 208, 149); // be
-// Elapsed time: 17 seconds
-selectCodeEditor("wendeTangente.vhd", 245, 193); // be
-selectCodeEditor("wendeTangente.vhd", 116, 301); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectCodeEditor("wendeTangente.vhd", 124, 324); // be
-// Elapsed time: 16 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-// [GUI Memory]: 152 MB (+678kb) [00:14:45]
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectCodeEditor("wendeTangente.vhd", 122, 375); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectCodeEditor("wendeTangente.vhd", 102, 413); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectCodeEditor("wendeTangente.vhd", 369, 205); // be
-selectCodeEditor("wendeTangente.vhd", 121, 277); // be
-selectCodeEditor("wendeTangente.vhd", 69, 214); // be
-// Elapsed time: 264 seconds
-selectCodeEditor("wendeTangente.vhd", 141, 255); // be
-selectCodeEditor("wendeTangente.vhd", 140, 241); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be
-selectCodeEditor("wendeTangente.vhd", 391, 297); // be
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 81 MB. Current time: 5/13/22, 12:03:47 PM CEST
-// Elapsed time: 931 seconds
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true, false, false, false, true, false); // D - Popup Trigger - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D
-selectCodeEditor("wendeTangente.vhd", 2, 251); // be
-selectCodeEditor("wendeTangente.vhd", 243, 261); // be
-selectCodeEditor("wendeTangente.vhd", 0, 239); // be
-selectCodeEditor("wendeTangente.vhd", 0, 229); // be
-selectCodeEditor("wendeTangente.vhd", 215, 325); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, design_1 (design_1.bd)]", 1, false, false, false, false, false, true); // D - Double Click
-// TclEventType: LOAD_FEATURE
-// TclEventType: RSB_SCRIPT_TASK
-// Tcl Message: open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} 
-// Tcl Message: Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... 
-selectButton(RDIResource.ProgressDialog_CANCEL, "Cancel"); // a
-// Tcl Message: INFO: [Common 17-41] Interrupt caught. Command should exit soon. INFO: [Common 17-344] 'source' was cancelled 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]  -      while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl  -      while executing "source init.tcl" 
-// Tcl Message: 1 
-// TclEventType: RSB_CHANGE_CURRENT_DIAGRAM
-// TclEventType: RSB_SCRIPT_TASK
-// TclEventType: RSB_CHANGE_CURRENT_DIAGRAM
-// Tcl Message: INFO: [BD 41-1808] Open Block Design has been cancelled. INFO: [Common 17-344] 'open_bd_design' was cancelled 
-// CommandFailedException: ERROR: [Common 17-69] Command failed:  
-dismissDialog("Open Block Design"); // bA
-selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f
-dismissDialog("Critical Messages"); // a
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true, false, false, false, true, false); // D - Popup Trigger - Node
-selectButton(PAResourceCommand.PACommandNames_ADD_SOURCES, "Sources_add_sources"); // D
-// Run Command: PAResourceCommand.PACommandNames_ADD_SOURCES
-// Elapsed time: 12 seconds
-selectButton("NEXT", "Next >"); // JButton
-selectButton(PAResourceQtoS.SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE, "Add"); // D
-selectMenuItem(PAResourceQtoS.SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT, "Add Files..."); // ao
-// Elapsed time: 12 seconds
-String[] filenames31467 = {"C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl", "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl", "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl", "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl"};
-setFileChooser(filenames31467);
-// Elapsed time: 28 seconds
-selectCheckBox(PAResourceQtoS.SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO, "Copy sources into project", true); // g: TRUE
-selectButton("FINISH", "Finish"); // JButton
-// 'g' command handler elapsed time: 65 seconds
-dismissDialog("Add Sources"); // c
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} 
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: update_compile_order -fileset sources_1 
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // D - Node
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, fixed_generic_pkg-body.vhdl]", 2, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, design_1 (design_1.bd)]", 4, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, fixed_generic_pkg-body.vhdl]", 2, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, fixed_generic_pkg-body.vhdl]", 2, false, false, false, false, false, true); // D - Double Click
-// WARNING: HEventQueue.dispatchEvent() is taking  1943 ms.
-dismissDialog("Opening Editor"); // bA
-// Elapsed time: 38 seconds
-selectTab(RDIResource.PropertiesView_TABBED_PANE, (HResource) null, "Properties", 1); // i
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i
-// Elapsed time: 19 seconds
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced]", 4); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_float_types.vhdl]", 8, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_pkg.vhdl]", 7, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_pkg.vhdl]", 7, false); // D
-// Elapsed time: 10 seconds
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_pkg.vhdl]", 7, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_float_types.vhdl]", 8, false); // D
-selectTab(RDIResource.PropertiesView_TABBED_PANE, (HResource) null, "General", 0); // i
-selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s
-selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] 
-dismissDialog("Set Type"); // ac
-selectButton(PAResourceQtoS.SrcFilePropPanels_LIBRARY, (String) null); // s
-setText(PAResourceQtoS.SpecifyLibraryDialog_LIBRARY_NAME, "ieee_proposed"); // k
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] 
-dismissDialog("Set Library"); // ad
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008]", 10); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg-body.vhdl]", 9, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_pkg.vhdl]", 7, false, true, true, false, false, false); // D - Shift Key - Control Key
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg.vhdl]", 8, false, false, true, false, false, false); // D - Control Key
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg-body.vhdl]", 9, false, false, true, false, false, false); // D - Control Key
-selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s
-selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] 
-dismissDialog("Set Type"); // ac
-selectButton(PAResourceQtoS.SrcFilePropPanels_LIBRARY, (String) null); // s
-selectComboBox(PAResourceQtoS.SpecifyLibraryDialog_LIBRARY_NAME, "ieee_proposed", 0); // K
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] 
-dismissDialog("Set Library"); // ad
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, ieee_proposed, Unreferenced, fixed_float_types.vhdl]", 13, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, ieee_proposed, Unreferenced, fixed_pkg.vhdl]", 12, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, ieee_proposed, Unreferenced, fixed_float_types.vhdl]", 13, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg-body.vhdl]", 8, false); // D
-selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s
-selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] 
-dismissDialog("Set Type"); // ac
-selectButton(PAResourceQtoS.SrcFilePropPanels_LIBRARY, (String) null); // s
-selectComboBox(PAResourceQtoS.SpecifyLibraryDialog_LIBRARY_NAME, "ieee_proposed", 0); // K
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] 
-dismissDialog("Set Library"); // ad
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg.vhdl]", 7, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg.vhdl]", 7, false); // D
-selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s
-selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] 
-dismissDialog("Set Type"); // ac
-selectButton(PAResourceQtoS.SrcFilePropPanels_LIBRARY, (String) null); // s
-selectComboBox(PAResourceQtoS.SpecifyLibraryDialog_LIBRARY_NAME, "ieee_proposed", 0); // K
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] 
-dismissDialog("Set Library"); // ad
-// Elapsed time: 63 seconds
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false, false, false, false, false, true); // D - Double Click
-dismissDialog("Opening Editor"); // bA
-selectCodeEditor("wendeTangente.vhd", 464, 183); // be
-selectCodeEditor("wendeTangente.vhd", 17, 226); // be
-selectCodeEditor("wendeTangente.vhd", 185, 265); // be
-selectCodeEditor("wendeTangente.vhd", 244, 194); // be
-// Elapsed time: 44 seconds
-selectCodeEditor("wendeTangente.vhd", 248, 258); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be
-selectCodeEditor("wendeTangente.vhd", 558, 347); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectCodeEditor("wendeTangente.vhd", 70, 366); // be
-selectCodeEditor("wendeTangente.vhd", 78, 227); // be
-selectCodeEditor("wendeTangente.vhd", 28, 384); // be
-// Elapsed time: 16 seconds
-selectCodeEditor("wendeTangente.vhd", 360, 336); // be
-selectCodeEditor("wendeTangente.vhd", 2, 384); // be
-selectCodeEditor("wendeTangente.vhd", 134, 428); // be
-selectCodeEditor("wendeTangente.vhd", 101, 87); // be
-selectCodeEditor("wendeTangente.vhd", 95, 98); // be
-selectCodeEditor("wendeTangente.vhd", 95, 98, false, false, false, false, true); // be - Double Click
-selectCodeEditor("wendeTangente.vhd", 102, 108); // be
-selectCodeEditor("wendeTangente.vhd", 102, 108, false, false, false, false, true); // be - Double Click
-selectCodeEditor("wendeTangente.vhd", 200, 90); // be
-selectCodeEditor("wendeTangente.vhd", 210, 90); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be
-selectCodeEditor("wendeTangente.vhd", 217, 82); // be
-selectCodeEditor("wendeTangente.vhd", 204, 95); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be
-selectCodeEditor("wendeTangente.vhd", 27, 112); // be
-selectCodeEditor("wendeTangente.vhd", 82, 110); // be
-selectCodeEditor("wendeTangente.vhd", 140, 229); // be
-selectCodeEditor("wendeTangente.vhd", 140, 229, false, false, false, false, true); // be - Double Click
-selectCodeEditor("wendeTangente.vhd", 261, 228); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be
-selectCodeEditor("wendeTangente.vhd", 150, 87); // be
-selectCodeEditor("wendeTangente.vhd", 150, 85, false, false, false, false, true); // be - Double Click
-typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be
-selectCodeEditor("wendeTangente.vhd", 168, 98); // be
-selectCodeEditor("wendeTangente.vhd", 168, 98, false, false, false, false, true); // be - Double Click
-selectCodeEditor("wendeTangente.vhd", 171, 111); // be
-selectCodeEditor("wendeTangente.vhd", 171, 111, false, false, false, false, true); // be - Double Click
-typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be
-selectCodeEditor("wendeTangente.vhd", 179, 121); // be
-selectCodeEditor("wendeTangente.vhd", 103, 200); // be
-selectCodeEditor("wendeTangente.vhd", 149, 132); // be
-selectCodeEditor("wendeTangente.vhd", 149, 132, false, false, false, false, true); // be - Double Click
-typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be
-selectCodeEditor("wendeTangente.vhd", 263, 288); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectCodeEditor("wendeTangente.vhd", 250, 368); // be
-selectCodeEditor("wendeTangente.vhd", 0, 230); // be
-selectCodeEditor("wendeTangente.vhd", 334, 337); // be
-// [GUI Memory]: 163 MB (+3607kb) [00:43:11]
-selectCodeEditor("wendeTangente.vhd", 67, 312); // be
-selectCodeEditor("wendeTangente.vhd", 67, 312, false, false, false, false, true); // be - Double Click
-selectCodeEditor("wendeTangente.vhd", 321, 364); // be
-selectCodeEditor("wendeTangente.vhd", 562, 220); // be
-selectCodeEditor("wendeTangente.vhd", 333, 229); // be
-selectCodeEditor("wendeTangente.vhd", 287, 237); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be
-selectCodeEditor("wendeTangente.vhd", 313, 95); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be
-selectCodeEditor("wendeTangente.vhd", 302, 273); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "fixed_generic_pkg-body.vhdl", 4); // m
-closeView(PAResourceOtoP.PAViews_CODE, "Code"); // D
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a
-// TclEventType: DG_GRAPH_STALE
-dismissDialog("Save Project"); // al
-// TclEventType: RUN_MODIFY
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: RUN_MODIFY
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// Tcl Message: reset_run synth_1 
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// TclEventType: RUN_MODIFY
-// Tcl Message: [Fri May 13 12:17:21 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 4 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 69 seconds
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs impl_1 -jobs 6 
-// Tcl Message: [Fri May 13 12:18:35 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log 
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 28 seconds
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl.  - .     while executing. source init.tcl. ]", 3, false, false, false, false, false, true); // ah - Double Click
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl.  - .     while executing. source init.tcl. ]", 3, false); // ah
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl.  - .     while executing. source init.tcl. ]", 3, false, false, false, false, false, true); // ah - Double Click
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl.  - .     while executing. source init.tcl. ]", 3, false); // ah
-// TclEventType: RUN_FAILED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 138 seconds
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW
-dismissDialog("Implementation Failed"); // ag
-// Elapsed time: 14 seconds
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, (String) null, 5, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, (String) null, 5, true, false, false, false, false, true); // ah - Double Click - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, (String) null, 5, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, (String) null, 5, true, false, false, false, false, true); // ah - Double Click - Node
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, design_1 (design_1.bd)]", 2, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, design_1 (design_1.bd)]", 2, false, false, false, false, false, true); // D - Double Click
-// TclEventType: RSB_SCRIPT_TASK
-// TclEventType: RSB_CHANGE_CURRENT_DIAGRAM
-// TclEventType: RSB_LOCK_CHANGE
-// TclEventType: RSB_SCRIPT_TASK
-// TclEventType: RSB_OPEN_DIAGRAM
-// Tcl Message: open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} 
-// Tcl Message: Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... Successfully read diagram <design_1> from block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd> 
-closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
-dismissDialog("Open Block Design"); // bA
-selectTree(PAResourceQtoS.SystemTreeView_SYSTEM_TREE, "[design_1]", 0, false); // a
-selectTree(PAResourceQtoS.SystemTreeView_SYSTEM_TREE, "[design_1]", 0, false, false, false, false, false, true); // a - Double Click
-selectTab((HResource) null, (HResource) null, "Sources", 0); // aL
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false, false, false, false, false, true); // D - Double Click
-dismissDialog("Opening Editor"); // bA
-// Elapsed time: 10 seconds
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false, false, false, false, false, true); // D - Double Click
-// WARNING: HEventQueue.dispatchEvent() is taking  1097 ms.
-dismissDialog("Opening Editor"); // bA
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false, false, false, false, false, true); // D - Double Click
-dismissDialog("Opening Editor"); // bA
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 9); // D
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 10); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true, false, false, false, false, true); // D - Double Click - Node
-// WARNING: HEventQueue.dispatchEvent() is taking  1102 ms.
-dismissDialog("Opening Editor"); // bA
-// Elapsed time: 10 seconds
-selectCodeEditor("pwm_test_db.vhd", 267, 259); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectCodeEditor("wendeTangente.vhd", 1, 112); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 4); // m
-// Elapsed time: 12 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 5); // m
-selectCodeEditor("pwm_test_db.vhd", 28, 264); // be
-selectCodeEditor("pwm_test_db.vhd", 10, 292); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 20, 242); // be
-selectCodeEditor("pwm_test_db.vhd", 20, 242, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 91, 322); // be
-selectCodeEditor("pwm_test_db.vhd", 74, 316); // be
-selectCodeEditor("pwm_test_db.vhd", 74, 316, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 247, 299); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m
-selectCodeEditor("wendeTangente.vhd", 193, 216); // be
-selectCodeEditor("wendeTangente.vhd", 245, 128); // be
-typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 5); // m
-selectCodeEditor("pwm_test_db.vhd", 229, 126); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 380, 150); // be
-// Elapsed time: 11 seconds
-selectCodeEditor("pwm_test_db.vhd", 306, 90); // be
-selectCodeEditor("pwm_test_db.vhd", 76, 54); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
-selectCodeEditor("pwm_test_db.vhd", 295, 221); // be
-selectCodeEditor("pwm_test_db.vhd", 24, 267); // be
-selectCodeEditor("pwm_test_db.vhd", 20, 265, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 20, 265); // be
-typeControlKey(null, null, 'z');
-typeControlKey(null, null, 'z');
-// Elapsed time: 12 seconds
-selectCodeEditor("pwm_test_db.vhd", 176, 19); // be
-selectCodeEditor("pwm_test_db.vhd", 115, 302); // be
-selectCodeEditor("pwm_test_db.vhd", 176, 245); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
-selectCodeEditor("pwm_test_db.vhd", 141, 268); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-// Elapsed time: 32 seconds
-selectCodeEditor("pwm_test_db.vhd", 359, 285); // be
-selectCodeEditor("pwm_test_db.vhd", 210, 205); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 328, 212); // be
-selectCodeEditor("pwm_test_db.vhd", 329, 210, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 378, 252); // be
-selectCodeEditor("pwm_test_db.vhd", 435, 213); // be
-selectCodeEditor("pwm_test_db.vhd", 444, 207); // be
-selectCodeEditor("pwm_test_db.vhd", 448, 208); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
-selectCodeEditor("pwm_test_db.vhd", 425, 218); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 450, 249); // be
-selectCodeEditor("pwm_test_db.vhd", 52, 246); // be
-selectCodeEditor("pwm_test_db.vhd", 223, 252); // be
-selectCodeEditor("pwm_test_db.vhd", 325, 231); // be
-selectCodeEditor("pwm_test_db.vhd", 325, 231, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 357, 226); // be
-selectCodeEditor("pwm_test_db.vhd", 318, 279); // be
-selectCodeEditor("pwm_test_db.vhd", 325, 273); // be
-selectCodeEditor("pwm_test_db.vhd", 52, 206); // be
-selectCodeEditor("pwm_test_db.vhd", 56, 201); // be
-// Elapsed time: 25 seconds
-selectCodeEditor("pwm_test_db.vhd", 135, 223); // be
-selectCodeEditor("pwm_test_db.vhd", 135, 223, false, false, false, false, true); // be - Double Click
-// Elapsed time: 46 seconds
-selectCodeEditor("pwm_test_db.vhd", 249, 352); // be
-selectCodeEditor("pwm_test_db.vhd", 190, 413); // be
-selectCodeEditor("pwm_test_db.vhd", 121, 77); // be
-selectCodeEditor("pwm_test_db.vhd", 121, 77, false, false, false, false, true); // be - Double Click
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
-selectCodeEditor("pwm_test_db.vhd", 172, 280); // be
-selectCodeEditor("pwm_test_db.vhd", 172, 280, false, false, false, false, true); // be - Double Click
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 142, 318); // be
-// Elapsed time: 11 seconds
-selectCodeEditor("pwm_test_db.vhd", 56, 181); // be
-selectCodeEditor("pwm_test_db.vhd", 102, 197); // be
-selectCodeEditor("pwm_test_db.vhd", 138, 247); // be
-// Elapsed time: 39 seconds
-selectCodeEditor("pwm_test_db.vhd", 222, 193); // be
-selectCodeEditor("pwm_test_db.vhd", 221, 293); // be
-selectCodeEditor("pwm_test_db.vhd", 57, 247); // be
-selectCodeEditor("pwm_test_db.vhd", 208, 212); // be
-// Elapsed time: 20 seconds
-selectCodeEditor("pwm_test_db.vhd", 289, 129); // be
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "OK"); // JButton
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Fri May 13 12:28:24 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 4 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 59 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-selectCodeEditor("pwm_test_db.vhd", 332, 290); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' 
-// Tcl Message: ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 
-// Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. 
-// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.  
-// HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.  (Run Simulation)'
-// 'd' command handler elapsed time: 13 seconds
-// Elapsed time: 13 seconds
-selectButton("OptionPane.button", "OK"); // JButton
-selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f
-dismissDialog("Critical Messages"); // a
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 620, 122); // dT
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 621, 122, false, false, false, false, true); // dT - Double Click
-// Elapsed time: 125 seconds
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 365, 91); // dT
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 389, 88); // dT
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 659, 97); // dT
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 174, 111); // dT
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 289, 113); // dT
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 275, 172); // dT
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 275, 172, false, false, false, false, true); // dT - Double Click
-// Elapsed time: 26 seconds
-selectButton(RDIResource.TclConsoleView_CLEAR_ALL_OUTPUT_IN_TCL_CONSOLE, "Tcl Console_remove"); // D
-selectButton("OptionPane.button", "Yes"); // JButton
-selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 554, 99); // dT
-selectCodeEditor("pwm_test_db.vhd", 222, 436); // be
-selectCodeEditor("pwm_test_db.vhd", 249, 331); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' 
-// Tcl Message: ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.359 ; gain = 0.000 
-// Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. 
-// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.  
-// HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.  (Run Simulation)'
-// 'd' command handler elapsed time: 34 seconds
-// Elapsed time: 34 seconds
-selectButton("OptionPane.button", "OK"); // JButton
-// Elapsed time: 10 seconds
-selectButton(PAResourceAtoD.CmdMsgDialog_OPEN_MESSAGES_VIEW, "Open Messages View"); // a
-// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW
-dismissDialog("Critical Messages"); // a
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node
-// Elapsed time: 14 seconds
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Utility Sources]", 18); // D
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Waveform Configuration File]", 17); // D
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 85 MB. Current time: 5/13/22, 12:33:48 PM CEST
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Compile Order", 3); // i
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true, false, false, false, true, false); // D - Popup Trigger - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true); // D - Node
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true); // D - Node
-selectTab(RDIResource.PropertiesView_TABBED_PANE, (HResource) null, "Properties", 1); // i
-selectTab(RDIResource.PropertiesView_TABBED_PANE, (HResource) null, "General", 0); // i
-selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s
-selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: FILE_SET_CHANGE
-// Tcl Message: set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] 
-dismissDialog("Set Type"); // ac
-// Elapsed time: 15 seconds
-selectCodeEditor("pwm_test_db.vhd", 488, 154); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "Cancel"); // JButton
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// TclEventType: LOAD_FEATURE
-// Tcl Message: Built simulation snapshot pwm_test_db_behav 
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 94 MB. Current time: 5/13/22, 12:34:41 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_STOPPED
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd  HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1580.359 ; gain = 0.000 
-// 'd' command handler elapsed time: 8 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 147, 182); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, clk_100]", 3, false); // l
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, cnt]", 4, false); // l
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 99, 124); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true); // c - Node
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "b[7:-6] ; 0147 ; Array", 1, "b[7:-6]", 0, true); // c - Node
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "a[7:-6] ; 3f38 ; Array", 0, "a[7:-6]", 0, true); // c - Node
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "a[7:-6] ; 3f38 ; Array", 0, "a[7:-6]", 0, true, false, false, false, false, true); // c - Double Click - Node
-// TclEventType: SIMULATION_OPEN_SOURCE
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "b[7:-6] ; 0147 ; Array", 1, "b[7:-6]", 0, true); // c - Node
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 158, 204); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, cnt]", 4, false, false, false, false, true, false); // l - Popup Trigger
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true); // c - Node
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true, false, false, false, true, false); // c - Popup Trigger - Node
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "a[7:-6] ; 3f38 ; Array", 0, "a[7:-6]", 0, true); // c - Node
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "a[7:-6] ; 3f38 ; Array", 0, "a[7:-6]", 0, true, false, false, false, true, false); // c - Popup Trigger - Node
-selectMenuItem((HResource) null, "Add to Wave Window"); // ao
-// Tcl Command: 'current_wave_config {pwm_test_db_func_synth.wcfg}'
-// Tcl Message: current_wave_config {pwm_test_db_func_synth.wcfg} 
-// Tcl Message: pwm_test_db_func_synth.wcfg 
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// Tcl Message: add_wave {{/pwm_test_db/uutWendeTangente/a}}  
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "b[7:-6] ; 0147 ; Array", 1, "b[7:-6]", 0, true); // c - Node
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "b[7:-6] ; 0147 ; Array", 1, "b[7:-6]", 0, true, false, false, false, true, false); // c - Popup Trigger - Node
-selectMenuItem((HResource) null, "Add to Wave Window"); // ao
-// Tcl Command: 'current_wave_config {pwm_test_db_func_synth.wcfg}'
-// Tcl Message: current_wave_config {pwm_test_db_func_synth.wcfg} 
-// Tcl Message: pwm_test_db_func_synth.wcfg 
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// Tcl Message: add_wave {{/pwm_test_db/uutWendeTangente/b}}  
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true); // c - Node
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true, false, false, false, true, false); // c - Popup Trigger - Node
-selectMenuItem((HResource) null, "Add to Wave Window"); // ao
-// Tcl Command: 'current_wave_config {pwm_test_db_func_synth.wcfg}'
-// Tcl Message: current_wave_config {pwm_test_db_func_synth.wcfg} 
-// Tcl Message: pwm_test_db_func_synth.wcfg 
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// Tcl Message: add_wave {{/pwm_test_db/uutWendeTangente/c}}  
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_UPDATE_TITLE
-selectButton("OptionPane.button", "Save"); // JButton
-// Tcl Message: save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} 
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 106 MB. Current time: 5/13/22, 12:35:22 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_STOPPED
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd  HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 
-// 'd' command handler elapsed time: 10 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_ADD_BREAKPOINT
-// Tcl Message: add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 
-// TclEventType: SIMULATION_DELETE_BREAKPOINT
-// Tcl Message: remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 87, 183); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 87, 183, false, false, false, false, true); // b - Double Click
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 96 MB. Current time: 5/13/22, 12:35:42 PM CEST
-// Elapsed time: 12 seconds
-selectButton(RDIResource.TclConsoleView_CLEAR_ALL_OUTPUT_IN_TCL_CONSOLE, "Tcl Console_remove"); // D
-selectButton("OptionPane.button", "Yes"); // JButton
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 100 MB. Current time: 5/13/22, 12:36:02 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_STOPPED
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd  HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 
-// 'd' command handler elapsed time: 8 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// Elapsed time: 17 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 99 MB. Current time: 5/13/22, 12:36:21 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, b[7:-6]]", 5); // l
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 4); // l
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 4); // l
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, c[7:-6]]", 13); // l
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, c[7:-6]]", 11); // l
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 100 MB. Current time: 5/13/22, 12:36:31 PM CEST
-collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, b[7:-6]]", 4); // l
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Cora-Z7-10-Master.xdc", 0); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m
-// Elapsed time: 25 seconds
-selectCodeEditor("pwm_test_db.vhd", 71, 124); // be
-selectCodeEditor("pwm_test_db.vhd", 356, 188); // be
-selectCodeEditor("pwm_test_db.vhd", 72, 128); // be
-selectCodeEditor("pwm_test_db.vhd", 72, 128, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 240, 229); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
-selectCodeEditor("pwm_test_db.vhd", 61, 232); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 167, 227); // be
-selectCodeEditor("pwm_test_db.vhd", 167, 227, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 171, 329); // be
-// Elapsed time: 47 seconds
-selectCodeEditor("pwm_test_db.vhd", 64, 224); // be
-selectCodeEditor("pwm_test_db.vhd", 304, 254); // be
-selectCodeEditor("pwm_test_db.vhd", 191, 326); // be
-selectCodeEditor("pwm_test_db.vhd", 90, 234); // be
-selectCodeEditor("pwm_test_db.vhd", 113, 281); // be
-// Elapsed time: 147 seconds
-selectCodeEditor("pwm_test_db.vhd", 193, 310); // be
-// Elapsed time: 11 seconds
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 407, 21); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
-selectCodeEditor("pwm_test_db.vhd", 187, 229); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 215, 223); // be
-selectCodeEditor("pwm_test_db.vhd", 215, 223, false, false, false, false, true); // be - Double Click
-selectCodeEditor("pwm_test_db.vhd", 204, 289); // be
-selectCodeEditor("pwm_test_db.vhd", 361, 229); // be
-selectCodeEditor("pwm_test_db.vhd", 118, 257); // be
-selectButton(RDIResourceCommand.RDICommands_SAVE_FILE, (String) null); // D
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  1774 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 103 MB. Current time: 5/13/22, 12:41:46 PM CEST
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_STOPPED
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: Time resolution is 1 ps 
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd  HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 
-// 'd' command handler elapsed time: 9 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 25, 286); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 42, 302); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 103 MB. Current time: 5/13/22, 12:41:51 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 40, 326); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 31, 359); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 5); // l
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 5); // l
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 241, 207); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation]", 9, true, false, false, false, true, false); // n - Popup Trigger - Node
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_SETTINGS, "Simulation Settings..."); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_SETTINGS
-// Tcl Command: 'rdi::info_commands {device::*}'
-// Tcl Command: 'rdi::info_commands {debug::*}'
-// Tcl Command: 'rdi::info_commands {*}'
-// WARNING: HEventQueue.dispatchEvent() is taking  1449 ms.
-// Elapsed time: 18 seconds
-dismissDialog("Settings"); // d
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 5, true); // l - Node
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 5, true, false, false, false, true, false); // l - Popup Trigger - Node
-selectMenu("Name"); // al
-selectMenu("Waveform Style"); // al
-selectMenu("Signal Color"); // al
-selectMenu("Radix"); // al
-selectMenu("Radix"); // al
-selectMenuItem((HResource) null, "Real Settings..."); // ao
-selectRadioButton(RDIResource.WaveformRealSettingsDialog_FIXED_POINT, "Fixed point"); // a
-selectRadioButton(RDIResource.WaveformRealSettingsDialog_SIGNED, "Signed"); // a
-setSpinner(RDIResource.WaveformRealSettingsDialog_BINARY_POINT, "28"); // V
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_TITLE
-dismissDialog("Real Settings"); // h
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectMenu("Waveform Style"); // al
-selectMenu("Signal Color"); // al
-selectMenu("Radix"); // al
-selectMenu("Radix"); // al
-selectMenuItem((HResource) null, "Real Settings..."); // ao
-selectRadioButton(RDIResource.WaveformRealSettingsDialog_FIXED_POINT, "Fixed point"); // a
-selectRadioButton(RDIResource.WaveformRealSettingsDialog_SIGNED, "Signed"); // a
-setSpinner(RDIResource.WaveformRealSettingsDialog_BINARY_POINT, "28"); // V
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_TITLE
-dismissDialog("Real Settings"); // h
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// [GUI Memory]: 175 MB (+3967kb) [01:09:21]
-selectMenu("Waveform Style"); // al
-selectMenu("Signal Color"); // al
-selectMenu("Radix"); // al
-selectMenu("Radix"); // al
-selectMenuItem((HResource) null, "Real Settings..."); // ao
-selectRadioButton(RDIResource.WaveformRealSettingsDialog_FIXED_POINT, "Fixed point"); // a
-selectRadioButton(RDIResource.WaveformRealSettingsDialog_SIGNED, "Signed"); // a
-setSpinner(RDIResource.WaveformRealSettingsDialog_BINARY_POINT, "28"); // V
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_UPDATE_TITLE
-dismissDialog("Real Settings"); // h
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 25, 444); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 67, 397); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// Run Command: RDIResourceCommand.RDICommands_WAVEFORM_SAVE_CONFIGURATION
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// Tcl Message: save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} 
-// TclEventType: FILE_SET_CHANGE
-// Elapsed time: 15 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 214, 544); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:23 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 70, 401); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:24 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:25 PM CEST
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:25 PM CEST
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:25 PM CEST
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:26 PM CEST
-selectButton(RDIResource.WaveformView_NEXT_TRANSITION, "Waveform Viewer_waveformNextTransition"); // D
-selectButton(RDIResource.WaveformView_PREVIOUS_TRANSITION, "Waveform Viewer_waveformPreviousTransition"); // D
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// Elapsed time: 31 seconds
-selectTab((HResource) null, (HResource) null, "Sources", 1); // aL
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008]", 21); // D
-collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File]", 24); // D
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File]", 24); // D
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 114 MB. Current time: 5/13/22, 12:44:14 PM CEST
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false, false, false, false, true, false); // D - Popup Trigger
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false, false, false, false, false, true); // D - Double Click
-selectButton(PAResourceOtoP.OpenFileAction_CANCEL, "Cancel"); // a
-dismissDialog("Unable to Open File"); // ag
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 115 MB. Current time: 5/13/22, 12:44:23 PM CEST
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false, false, false, false, false, true); // D - Double Click
-dismissDialog("Opening Editor"); // bA
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D
-selectTab((HResource) null, (HResource) null, "Messages", 1); // aL
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Compile Order", 3); // i
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false, false, false, false, true, false); // D - Popup Trigger
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false, false, false, false, true, false); // D - Popup Trigger
-// Elapsed time: 148 seconds
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i
-// Elapsed time: 10 seconds
-expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Utility Sources, utils_1, Design Checkpoint]", 21); // D
-selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Utility Sources, utils_1, Design Checkpoint, pwm_test.dcp]", 22, false); // D
-// Elapsed time: 22 seconds
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 5, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 5, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 5, true, false, false, false, false, true); // ah - Double Click - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 7, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 7, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 7, true, false, false, false, false, true); // ah - Double Click - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. , [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 8, false); // ah
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. , [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 8, false, false, false, false, false, true); // ah - Double Click
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. , [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 8, false); // ah
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. , [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 8, false, false, false, false, false, true); // ah - Double Click
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node
-expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2); // ah
-selectCheckBox(PAResourceItoN.MsgView_ERROR_MESSAGES, (String) null, true); // g: TRUE
-// Elapsed time: 17 seconds
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl].  - .     while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl.  - .     while executing. source init.tcl. ]", 3, false, false, false, false, false, true); // ah - Double Click
-// Elapsed time: 11 seconds
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages]", 33, true); // ah - Node
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 34, true); // ah - Node
-// Elapsed time: 12 seconds
-expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 34); // ah
-// Elapsed time: 26 seconds
-selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 34, true); // ah - Node
-// Elapsed time: 69 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 1); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 2); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 3); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Cora-Z7-10-Master.xdc", 0); // m
-selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i
-collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008]", 21); // D
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 165, 131); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 93, 160); // b
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aL
-// Elapsed time: 91 seconds
-selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 221, 277); // b
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_UPDATE_COMMANDS
-// TclEventType: WAVEFORM_MOVE_CURSOR
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 13, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "OK"); // JButton
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Fri May 13 12:52:54 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// 'k' command handler elapsed time: 3 seconds
-dismissDialog("Starting Design Runs"); // bA
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 57 seconds
-selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
-dismissDialog("Synthesis Completed"); // ag
-// Elapsed time: 32 seconds
-selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m
-// Elapsed time: 37 seconds
-selectCodeEditor("pwm_test_db.vhd", 6, 121); // be
-selectCodeEditor("pwm_test_db.vhd", 232, 120); // be
-selectCodeEditor("pwm_test_db.vhd", 281, 184); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 42, 123); // be
-typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be
-selectCodeEditor("pwm_test_db.vhd", 2, 118); // be
-selectCodeEditor("pwm_test_db.vhd", 0, 126); // be
-selectCodeEditor("pwm_test_db.vhd", 244, 215); // be
-// Elapsed time: 14 seconds
-selectCodeEditor("pwm_test_db.vhd", 11, 109); // be
-selectCodeEditor("pwm_test_db.vhd", 3, 205); // be
-selectCodeEditor("pwm_test_db.vhd", 468, 130); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Run Implementation]", 16, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
-selectButton(PAResourceQtoS.SaveProjectUtils_CANCEL, "Cancel"); // a
-dismissDialog("Save Project"); // al
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation]", 9, true); // n - Node
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton("OptionPane.button", "Yes"); // JButton
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  2453 ms.
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: FILE_SET_CHANGE
-dismissDialog("Save Simulation Sources"); // c
-// TclEventType: WAVEFORM_CLOSE_WCFG
-// TclEventType: SIMULATION_CLOSE_SIMULATION
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 1089 ms. Increasing delay to 3267 ms.
-// Tcl Message: close_sim 
-// Tcl Message: INFO: [Simtcl 6-16] Simulation closed 
-dismissDialog("Close"); // bA
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' 
-// Tcl Message: ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. 
-// Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. 
-// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.  
-// HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.  (Run Simulation)'
-// 'd' command handler elapsed time: 15 seconds
-selectButton("OptionPane.button", "OK"); // JButton
-selectList(PAResourceAtoD.CmdMsgDialog_MESSAGES, "[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.", 0); // b
-selectList(PAResourceAtoD.CmdMsgDialog_MESSAGES, "[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.", 0); // b
-selectList(PAResourceAtoD.CmdMsgDialog_MESSAGES, "[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.", 0, false, false, false, false, true); // b - Double Click
-// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW
-dismissDialog("Critical Messages"); // a
-selectCodeEditor("pwm_test_db.vhd", 15, 109); // be
-selectCodeEditor("pwm_test_db.vhd", 17, 128); // be
-selectCodeEditor("pwm_test_db.vhd", 249, 176); // be
-// Elapsed time: 17 seconds
-selectCodeEditor("pwm_test_db.vhd", 236, 152); // be
-selectCodeEditor("pwm_test_db.vhd", 167, 202); // be
-selectCodeEditor("pwm_test_db.vhd", 14, 126); // be
-selectCodeEditor("pwm_test_db.vhd", 301, 169); // be
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
-selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a
-// TclEventType: DG_GRAPH_STALE
-// WARNING: HEventQueue.dispatchEvent() is taking  3243 ms.
-dismissDialog("Save Project"); // al
-// TclEventType: DG_GRAPH_STALE
-// TclEventType: FILE_SET_CHANGE
-// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 2972 ms. Increasing delay to 8916 ms.
-// TclEventType: LAUNCH_SIM
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: launch_simulation 
-// Tcl Message: Command: launch_simulation  
-// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' 
-// Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" 
-// TclEventType: LAUNCH_SIM_LOG
-// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' 
-// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' 
-// Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" 
-// TclEventType: LAUNCH_SIM
-// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim 
-// Tcl Message:    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" 
-// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature 
-// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_UPDATE_TITLE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// Tcl Message: Time resolution is 1 ps 
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
-// TclEventType: WAVEFORM_OPEN_WCFG
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
-// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: SIMULATION_UPDATE_LATEST_TIME
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
-// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
-// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
-// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
-// TclEventType: SIMULATION_UPDATE_LOCALS
-// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
-// TclEventType: SIMULATION_UPDATE_STACKS
-// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
-// TclEventType: SIMULATION_STOPPED
-// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
-// Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg 
-// Tcl Message: source pwm_test_db.tcl 
-// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { #   if { [llength [get_objects]] > 0} { #     add_wave / #     set_property needs_save false [current_wave_config] #   } else { #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." #   } # } # run 5 s 
-// Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd  HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 
-// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s 
-// Tcl Message: launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 
-// 'd' command handler elapsed time: 12 seconds
-// Elapsed time: 11 seconds
-dismissDialog("Run Simulation"); // e
-// TclEventType: WAVEFORM_MODEL_EVENT
-// TclEventType: WAVEFORM_UPDATE_WAVEFORM
-// TclEventType: WAVEFORM_MODEL_EVENT
-// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 118 MB. Current time: 5/13/22, 1:14:23 PM CEST
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/sim/ssm.db b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/sim/ssm.db
new file mode 100644
index 0000000..01d1d4e
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/sim/ssm.db
@@ -0,0 +1,10 @@
+################################################################################
+#                            DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Fri May 13 14:10:49 2022)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+#                            DONOT REMOVE THIS FILE
+################################################################################
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/project.wpc b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/project.wpc
new file mode 100644
index 0000000..9b34209
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/synthesis.wdf b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/synthesis.wdf
new file mode 100644
index 0000000..b4d1993
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/synthesis.wdf
@@ -0,0 +1,44 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303130636c673430302d31:00:00
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+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/synthesis_details.wdf b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000..78f8d66
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/webtalk_pa.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000..7483320
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Fri May 13 14:42:26 2022">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="7a8e7c8ef7e84daa83c28bbcb851b3c5" type="ProjectID"/>
+<property name="ProjectIteration" value="5" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/xsim.wdf b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/xsim.wdf
new file mode 100644
index 0000000..50afb2c
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/xsim.wdf
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+version:1
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.hw/fixedPointTest.lpr b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.hw/fixedPointTest.lpr
new file mode 100644
index 0000000..3d39574
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.hw/fixedPointTest.lpr
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.ip_user_files/README.txt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_1.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000..39a3ca2
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_2.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000..39a3ca2
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_3.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_3.xml
new file mode 100644
index 0000000..39a3ca2
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_4.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_4.xml
new file mode 100644
index 0000000..109cb06
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_4.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_5.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_5.xml
new file mode 100644
index 0000000..2d23805
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_5.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_6.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_6.xml
new file mode 100644
index 0000000..37e8917
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_6.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_7.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_7.xml
new file mode 100644
index 0000000..109cb06
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_7.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_8.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_8.xml
new file mode 100644
index 0000000..2d23805
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_8.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.Vivado_Implementation.queue.rst
similarity index 100%
rename from StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log
rename to StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.Vivado_Implementation.queue.rst
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.init_design.begin.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000..0141774
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108">
+    </Process>
+</ProcessHandle>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.init_design.end.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.opt_design.begin.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000..0141774
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108">
+    </Process>
+</ProcessHandle>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.opt_design.end.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.phys_opt_design.begin.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.phys_opt_design.begin.rst
new file mode 100644
index 0000000..0141774
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.phys_opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108">
+    </Process>
+</ProcessHandle>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.phys_opt_design.end.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.phys_opt_design.end.rst
new file mode 100644
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.place_design.begin.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000..0141774
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108">
+    </Process>
+</ProcessHandle>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.place_design.end.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.place_design.end.rst
new file mode 100644
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.route_design.begin.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000..0141774
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108">
+    </Process>
+</ProcessHandle>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.route_design.end.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.vivado.begin.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000..2accd32
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,10 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="13680" HostCore="12" HostMemory="016927088640">
+    </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17920" HostCore="12" HostMemory="016927088640">
+    </Process>
+</ProcessHandle>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.vivado.end.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.vivado.error.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.vivado.error.rst
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.write_bitstream.begin.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000..6e00f76
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="11092">
+    </Process>
+</ProcessHandle>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.write_bitstream.error.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.write_bitstream.error.rst
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/ISEWrap.js b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/ISEWrap.js
new file mode 100644
index 0000000..db0a510
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/ISEWrap.js
@@ -0,0 +1,269 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\" HostCore=\"" + ISEHOSTCORE +
+			    "\" HostMemory=\"" + ISEMEMTOTAL +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/ISEWrap.sh b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/ISEWrap.sh
new file mode 100644
index 0000000..c2fbbb6
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,84 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+cmd_exists()
+{
+  command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.tcl b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.tcl
new file mode 100644
index 0000000..d609402
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.tcl
@@ -0,0 +1,157 @@
+# 
+# Report generation script generated by Vivado
+# 
+
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+namespace eval ::optrace {
+  variable script "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.tcl"
+  variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+proc start_step { step } {
+  set stopFile ".stop.rst"
+  if {[file isfile .stop.rst]} {
+    puts ""
+    puts "*** Halting run - EA reset detected ***"
+    puts ""
+    puts ""
+    return -code error
+  }
+  set beginFile ".$step.begin.rst"
+  set platform "$::tcl_platform(platform)"
+  set user "$::tcl_platform(user)"
+  set pid [pid]
+  set host ""
+  if { [string equal $platform unix] } {
+    if { [info exist ::env(HOSTNAME)] } {
+      set host $::env(HOSTNAME)
+    } elseif { [info exist ::env(HOST)] } {
+      set host $::env(HOST)
+    }
+  } else {
+    if { [info exist ::env(COMPUTERNAME)] } {
+      set host $::env(COMPUTERNAME)
+    }
+  }
+  set ch [open $beginFile w]
+  puts $ch "<?xml version=\"1.0\"?>"
+  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+  puts $ch "    </Process>"
+  puts $ch "</ProcessHandle>"
+  close $ch
+}
+
+proc end_step { step } {
+  set endFile ".$step.end.rst"
+  set ch [open $endFile w]
+  close $ch
+}
+
+proc step_failed { step } {
+  set endFile ".$step.error.rst"
+  set ch [open $endFile w]
+  close $ch
+OPTRACE "impl_1" END { }
+}
+
+set_msg_config -id {Synth 8-256} -limit 10000
+set_msg_config -id {Synth 8-638} -limit 10000
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+  create_msg_db write_bitstream.pb
+  set_param checkpoint.writeSynthRtdsInDcp 1
+  set_param chipscope.maxJobs 3
+  open_checkpoint fixedPointTest_routed.dcp
+  set_property webtalk.parent_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt [current_project]
+set_property TOP fixedPointTest [current_fileset]
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+  catch { write_mem_info -force -no_partial_mmi fixedPointTest.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+  write_bitstream -force fixedPointTest.bit 
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+  catch {write_debug_probes -quiet -force fixedPointTest}
+  catch {file copy -force fixedPointTest.ltx debug_nets.ltx}
+  close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+  step_failed write_bitstream
+  return -code error $RESULT
+} else {
+  end_step write_bitstream
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
new file mode 100644
index 0000000..9e670ac
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
@@ -0,0 +1,600 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:41:22 2022
+# Process ID: 17108
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1
+# Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
+create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 10.250
+Command: link_design -top fixedPointTest -part xc7z010clg400-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.340 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.340 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+7 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 0.000
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.340 ; gain = 0.000
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1387.457 ; gain = 126.117
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1683.215 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+24 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1683.215 ; gain = 421.875
+INFO: [Timing 38-480] Writing timing data to binary archive.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+Command: report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c5371e47
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170083491
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.149 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.152 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.4 Global Placement Core
+WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
+Phase 2.4 Global Placement Core | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.699 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+Phase 4.1 Post Commit Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.773 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Ending Placer Task | Checksum: 1c0019b8b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+43 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file fixedPointTest_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+51 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: faca7d44 ConstDB: 0 ShapeSum: c5371e47 RouteDB: 0
+Post Restoration Checksum: NetGraph: 54150718 NumContArr: b3d68f27 Constraints: 0 Timing: 0
+Phase 1 Build RT Design | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1757.188 ; gain = 23.668
+
+Phase 2 Router Initialization
+INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699
+ Number of Nodes with overlaps = 0
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 46
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 46
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: d7f76c92
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: d7f76c92
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 3 Initial Routing | Checksum: aa1bb3ea
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 0
+Phase 4.1 Global Iteration 0 | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 4 Rip-up And Reroute | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 5 Delay and Skew Optimization
+Phase 5 Delay and Skew Optimization | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+Phase 6.1 Hold Fix Iter | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 6 Post Hold Fix | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0663007 %
+  Global Horizontal Routing Utilization  = 0.0248162 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Congestion Report
+North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions.
+
+------------------------------
+Reporting congestion hotspots
+------------------------------
+Direction: North
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: South
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: East
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: West
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+
+Phase 7 Route finalize | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 156fe757f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+61 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1765.430 ; gain = 43.164
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1775.246 ; gain = 9.816
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+Command: report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+Command: report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+Command: report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
+Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+73 Infos, 9 Warnings, 7 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file fixedPointTest_route_status.rpt -pb fixedPointTest_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+INFO: [runtcl-4] Executing : report_incremental_reuse -file fixedPointTest_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:42:11 2022...
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:42:39 2022
+# Process ID: 11092
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1
+# Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
+Command: open_checkpoint fixedPointTest_routed.dcp
+
+Starting open_checkpoint Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1251.590 ; gain = 0.000
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1251.590 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Timing 38-478] Restoring timing data from binary archive.
+INFO: [Timing 38-479] Binary timing data restore complete.
+INFO: [Project 1-856] Restoring constraints from binary archive.
+INFO: [Project 1-853] Binary constraint restore complete.
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1387.207 ; gain = 17.668
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1387.207 ; gain = 17.668
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1387.207 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Project 1-604] Checkpoint was created with Vivado v2021.2 (64-bit) build 3367213
+open_checkpoint: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1387.207 ; gain = 135.617
+Command: write_bitstream -force fixedPointTest.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+INFO: [DRC 23-27] Running DRC with 2 threads
+ERROR: [DRC NSTD-1] Unspecified I/O Standard: 43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], and c[8:-6].
+ERROR: [DRC UCIO-1] Unconstrained Logical Port: 43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: a[7:-6], b[7:-6], and c[8:-6].
+WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
+INFO: [Common 17-83] Releasing license: Implementation
+19 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered.
+write_bitstream failed
+ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
+
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:43:07 2022...
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_11388.backup.vdi b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_11388.backup.vdi
new file mode 100644
index 0000000..3ae2c16
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_11388.backup.vdi
@@ -0,0 +1,512 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:31:34 2022
+# Process ID: 11388
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1
+# Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
+create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.066 ; gain = 9.613
+Command: link_design -top fixedPointTest -part xc7z010clg400-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.066 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.066 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.066 ; gain = 0.000
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.066 ; gain = 0.000
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1385.141 ; gain = 124.074
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1680.863 ; gain = 0.000
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1680.863 ; gain = 0.000
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1680.863 ; gain = 0.000
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1680.863 ; gain = 0.000
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1680.863 ; gain = 0.000
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1680.863 ; gain = 0.000
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1680.863 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1680.863 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1680.863 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1680.863 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1680.863 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1680.863 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1680.863 ; gain = 419.797
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+Command: report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c5371e47
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170083491
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.220 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.254 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.264 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.272 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.273 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.273 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 2.4 Global Placement Core
+WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
+Phase 2.4 Global Placement Core | Checksum: 17701980b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.793 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 17701980b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.797 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 17701980b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.800 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.806 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.814 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.855 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.856 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.857 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+Phase 4.1 Post Commit Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.873 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.875 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.877 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.877 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1718.922 ; gain = 0.000
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.878 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.878 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Ending Placer Task | Checksum: 1c0019b8b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.879 . Memory (MB): peak = 1718.922 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+41 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 1718.922 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file fixedPointTest_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.079 . Memory (MB): peak = 1718.922 ; gain = 0.000
+INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1718.922 ; gain = 0.000
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+48 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1718.922 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: faca7d44 ConstDB: 0 ShapeSum: c5371e47 RouteDB: 0
+Post Restoration Checksum: NetGraph: 54150718 NumContArr: b3d68f27 Constraints: 0 Timing: 0
+Phase 1 Build RT Design | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1755.223 ; gain = 25.043
+
+Phase 2 Router Initialization
+INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1761.215 ; gain = 31.035
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1761.215 ; gain = 31.035
+ Number of Nodes with overlaps = 0
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 46
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 46
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: d7f76c92
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: d7f76c92
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+Phase 3 Initial Routing | Checksum: aa1bb3ea
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 0
+Phase 4.1 Global Iteration 0 | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+Phase 4 Rip-up And Reroute | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+
+Phase 5 Delay and Skew Optimization
+Phase 5 Delay and Skew Optimization | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+Phase 6.1 Hold Fix Iter | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+Phase 6 Post Hold Fix | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0663007 %
+  Global Horizontal Routing Utilization  = 0.0248162 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Congestion Report
+North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions.
+
+------------------------------
+Reporting congestion hotspots
+------------------------------
+Direction: North
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: South
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: East
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: West
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+
+Phase 7 Route finalize | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.297 ; gain = 34.117
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 156fe757f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.297 ; gain = 34.117
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.297 ; gain = 34.117
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+57 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1764.297 ; gain = 45.375
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1774.078 ; gain = 9.781
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+Command: report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+Command: report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+Command: report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
+Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+68 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file fixedPointTest_route_status.rpt -pb fixedPointTest_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+INFO: [runtcl-4] Executing : report_incremental_reuse -file fixedPointTest_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:32:21 2022...
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_17108.backup.vdi b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_17108.backup.vdi
new file mode 100644
index 0000000..cd9ddd8
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_17108.backup.vdi
@@ -0,0 +1,540 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:41:22 2022
+# Process ID: 17108
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1
+# Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
+create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 10.250
+Command: link_design -top fixedPointTest -part xc7z010clg400-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.340 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.340 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+7 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 0.000
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.340 ; gain = 0.000
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1387.457 ; gain = 126.117
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1683.215 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+24 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1683.215 ; gain = 421.875
+INFO: [Timing 38-480] Writing timing data to binary archive.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+Command: report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c5371e47
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170083491
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.149 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.152 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.4 Global Placement Core
+WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
+Phase 2.4 Global Placement Core | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.699 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+Phase 4.1 Post Commit Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.773 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Ending Placer Task | Checksum: 1c0019b8b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+43 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file fixedPointTest_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+51 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: faca7d44 ConstDB: 0 ShapeSum: c5371e47 RouteDB: 0
+Post Restoration Checksum: NetGraph: 54150718 NumContArr: b3d68f27 Constraints: 0 Timing: 0
+Phase 1 Build RT Design | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1757.188 ; gain = 23.668
+
+Phase 2 Router Initialization
+INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699
+ Number of Nodes with overlaps = 0
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 46
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 46
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: d7f76c92
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: d7f76c92
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 3 Initial Routing | Checksum: aa1bb3ea
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 0
+Phase 4.1 Global Iteration 0 | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 4 Rip-up And Reroute | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 5 Delay and Skew Optimization
+Phase 5 Delay and Skew Optimization | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+Phase 6.1 Hold Fix Iter | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 6 Post Hold Fix | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0663007 %
+  Global Horizontal Routing Utilization  = 0.0248162 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Congestion Report
+North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions.
+
+------------------------------
+Reporting congestion hotspots
+------------------------------
+Direction: North
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: South
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: East
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: West
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+
+Phase 7 Route finalize | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 156fe757f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+61 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1765.430 ; gain = 43.164
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1775.246 ; gain = 9.816
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+Command: report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+Command: report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+Command: report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
+Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+73 Infos, 9 Warnings, 7 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file fixedPointTest_route_status.rpt -pb fixedPointTest_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+INFO: [runtcl-4] Executing : report_incremental_reuse -file fixedPointTest_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:42:11 2022...
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.pb
new file mode 100644
index 0000000..3390588
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.rpt
new file mode 100644
index 0000000..44e8639
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.rpt
@@ -0,0 +1,15 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:42:11 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx
+| Design       : fixedPointTest
+| Device       : 7z010-clg400
+| Speed File   : -1  PRODUCTION 1.12 2019-11-22
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.rpx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.rpx
new file mode 100644
index 0000000..19e17c8
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.rpx differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_clock_utilization_routed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_clock_utilization_routed.rpt
new file mode 100644
index 0000000..e7cca16
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_clock_utilization_routed.rpt
@@ -0,0 +1,90 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:42:11 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt
+| Design       : fixedPointTest
+| Device       : 7z010-clg400
+| Speed File   : -1  PRODUCTION 1.12 2019-11-22
+| Design State : Routed
+--------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type     | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL |    0 |        32 |   0 |            0 |      0 |
+| BUFH     |    0 |        48 |   0 |            0 |      0 |
+| BUFIO    |    0 |         8 |   0 |            0 |      0 |
+| BUFMR    |    0 |         4 |   0 |            0 |      0 |
+| BUFR     |    0 |         8 |   0 |            0 |      0 |
+| MMCM     |    0 |         2 |   0 |            0 |      0 |
+| PLL      |    0 |         2 |   0 |            0 |      0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |  1100 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1100 |    0 |   350 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X0Y1              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |  1100 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1100 |    0 |   350 |    0 |    40 |    0 |    20 |    0 |    20 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+|    | X0 | X1 |
++----+----+----+
+| Y1 |  0 |  0 |
+| Y0 |  0 |  0 |
++----+----+----+
+
+
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_control_sets_placed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_control_sets_placed.rpt
new file mode 100644
index 0000000..5b5cadb
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_control_sets_placed.rpt
@@ -0,0 +1,77 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:41:53 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt
+| Design       : fixedPointTest
+| Device       : xc7z010
+-------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+|                          Status                          | Count |
++----------------------------------------------------------+-------+
+| Total control sets                                       |     0 |
+|    Minimum number of control sets                        |     0 |
+|    Addition due to synthesis replication                 |     0 |
+|    Addition due to physical synthesis replication        |     0 |
+| Unused register locations in slices containing registers |     0 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+|       Fanout       | Count |
++--------------------+-------+
+| Total control sets |     0 |
+| >= 0 to < 4        |     0 |
+| >= 4 to < 6        |     0 |
+| >= 6 to < 8        |     0 |
+| >= 8 to < 10       |     0 |
+| >= 10 to < 12      |     0 |
+| >= 12 to < 14      |     0 |
+| >= 14 to < 16      |     0 |
+| >= 16              |     0 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No           | No                    | No                     |               0 |            0 |
+| No           | No                    | Yes                    |               0 |            0 |
+| No           | Yes                   | No                     |               0 |            0 |
+| Yes          | No                    | No                     |               0 |            0 |
+| Yes          | No                    | Yes                    |               0 |            0 |
+| Yes          | Yes                   | No                     |               0 |            0 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++--------------+---------------+------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++--------------+---------------+------------------+------------------+----------------+--------------+
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.pb
new file mode 100644
index 0000000..0158a2a
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt
new file mode 100644
index 0000000..d38937f
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt
@@ -0,0 +1,53 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:41:51 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+| Design       : fixedPointTest
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 3
++--------+------------------+----------------------------+------------+
+| Rule   | Severity         | Description                | Violations |
++--------+------------------+----------------------------+------------+
+| NSTD-1 | Critical Warning | Unspecified I/O Standard   | 1          |
+| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1          |
+| ZPS7-1 | Warning          | PS7 block required         | 1          |
++--------+------------------+----------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+NSTD-1#1 Critical Warning
+Unspecified I/O Standard  
+43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], c[8:-6].
+Related violations: <none>
+
+UCIO-1#1 Critical Warning
+Unconstrained Logical Port  
+43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: a[7:-6], b[7:-6], c[8:-6].
+Related violations: <none>
+
+ZPS7-1#1 Warning
+PS7 block required  
+The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+Related violations: <none>
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpx
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index 0000000..b4c3b77
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.pb
new file mode 100644
index 0000000..0158a2a
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt
new file mode 100644
index 0000000..6b54444
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt
@@ -0,0 +1,53 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:42:09 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+| Design       : fixedPointTest
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Fully Routed
+------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 3
++--------+------------------+----------------------------+------------+
+| Rule   | Severity         | Description                | Violations |
++--------+------------------+----------------------------+------------+
+| NSTD-1 | Critical Warning | Unspecified I/O Standard   | 1          |
+| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1          |
+| ZPS7-1 | Warning          | PS7 block required         | 1          |
++--------+------------------+----------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+NSTD-1#1 Critical Warning
+Unspecified I/O Standard  
+43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], c[8:-6].
+Related violations: <none>
+
+UCIO-1#1 Critical Warning
+Unconstrained Logical Port  
+43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: a[7:-6], b[7:-6], c[8:-6].
+Related violations: <none>
+
+ZPS7-1#1 Warning
+PS7 block required  
+The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+Related violations: <none>
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpx
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index 0000000..41a0868
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_io_placed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_io_placed.rpt
new file mode 100644
index 0000000..3159bd4
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_io_placed.rpt
@@ -0,0 +1,442 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------
+| Tool Version              : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date                      : Fri May 13 14:41:53 2022
+| Host                      : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command                   : report_io -file fixedPointTest_io_placed.rpt
+| Design                    : fixedPointTest
+| Device                    : xc7z010
+| Speed File                : -1
+| Package                   : clg400
+| Package Version           : FINAL 2012-10-23
+| Package Pin Delay Version : VERS. 2.0 2012-10-23
+-------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+|            43 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type  | Pin Name                | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1         |             |            | PS_DDR_DM0_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A2         |             |            | PS_DDR_DQ2_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A3         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| A4         |             |            | PS_DDR_DQ3_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A5         |             |            | PS_MIO6_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A6         |             |            | PS_MIO5_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A7         |             |            | PS_MIO1_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A9         |             |            | PS_MIO43_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A10        |             |            | PS_MIO37_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A11        |             |            | PS_MIO36_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A12        |             |            | PS_MIO34_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A13        |             |            | VCCO_MIO1_501           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| A14        |             |            | PS_MIO32_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A15        |             |            | PS_MIO26_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A16        |             |            | PS_MIO24_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A17        |             |            | PS_MIO20_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A18        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A19        |             |            | PS_MIO16_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A20        |             | High Range | IO_L2N_T0_AD8N_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B1         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B2         |             |            | PS_DDR_DQS_N0_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B3         |             |            | PS_DDR_DQ1_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B4         |             |            | PS_DDR_DRST_B_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B5         |             |            | PS_MIO9_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B6         |             |            | VCCO_MIO0_500           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| B7         |             |            | PS_MIO4_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B8         |             |            | PS_MIO2_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B9         |             |            | PS_MIO51_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B10        |             |            | PS_SRST_B_501           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B12        |             |            | PS_MIO48_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B13        |             |            | PS_MIO50_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B14        |             |            | PS_MIO47_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B15        |             |            | PS_MIO45_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B16        |             |            | VCCO_MIO1_501           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| B17        |             |            | PS_MIO22_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B18        |             |            | PS_MIO18_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B19        |             | High Range | IO_L2P_T0_AD8P_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B20        |             | High Range | IO_L1N_T0_AD0N_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C1         |             |            | PS_DDR_DQ6_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C2         |             |            | PS_DDR_DQS_P0_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C3         |             |            | PS_DDR_DQ0_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C4         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C5         |             |            | PS_MIO14_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C6         |             |            | PS_MIO11_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C7         |             |            | PS_POR_B_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C8         |             |            | PS_MIO15_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C9         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C10        |             |            | PS_MIO52_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C11        |             |            | PS_MIO53_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C12        |             |            | PS_MIO49_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C13        |             |            | PS_MIO29_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C14        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C15        |             |            | PS_MIO30_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C16        |             |            | PS_MIO28_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C17        |             |            | PS_MIO41_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C18        |             |            | PS_MIO39_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C19        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| C20        |             | High Range | IO_L1P_T0_AD0P_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D1         |             |            | PS_DDR_DQ5_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D2         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| D3         |             |            | PS_DDR_DQ4_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D4         |             |            | PS_DDR_A13_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D5         |             |            | PS_MIO8_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D6         |             |            | PS_MIO3_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D7         |             |            | VCCO_MIO0_500           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| D8         |             |            | PS_MIO7_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D9         |             |            | PS_MIO12_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D10        |             |            | PS_MIO19_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D11        |             |            | PS_MIO23_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D12        |             |            | VCCO_MIO1_501           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| D13        |             |            | PS_MIO27_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D14        |             |            | PS_MIO40_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D15        |             |            | PS_MIO33_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D16        |             |            | PS_MIO46_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D17        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D18        |             | High Range | IO_L3N_T0_DQS_AD1N_35   | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D19        |             | High Range | IO_L4P_T0_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D20        |             | High Range | IO_L4N_T0_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E1         |             |            | PS_DDR_DQ7_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E2         |             |            | PS_DDR_DQ8_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E3         |             |            | PS_DDR_DQ9_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E4         |             |            | PS_DDR_A12_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E5         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| E6         |             |            | PS_MIO0_500             | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E7         |             |            | PS_CLK_500              | PSS Clock     |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E8         |             |            | PS_MIO13_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E9         |             |            | PS_MIO10_500            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E10        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E11        |             |            | PS_MIO_VREF_501         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E12        |             |            | PS_MIO42_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E13        |             |            | PS_MIO38_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E14        |             |            | PS_MIO17_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E15        |             |            | VCCO_MIO1_501           | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| E16        |             |            | PS_MIO31_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E17        |             | High Range | IO_L3P_T0_DQS_AD1P_35   | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E18        |             | High Range | IO_L5P_T0_AD9P_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E19        |             | High Range | IO_L5N_T0_AD9N_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E20        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F1         |             |            | PS_DDR_DM1_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F2         |             |            | PS_DDR_DQS_N1_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F3         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F4         |             |            | PS_DDR_A14_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F5         |             |            | PS_DDR_A10_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F6         |             | Dedicated  | TDO_0                   | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F8         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F9         |             | Dedicated  | TCK_0                   | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F10        |             |            | RSVDGND                 | GND           |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F11        |             | Dedicated  | VCCBATT_0               | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F12        |             |            | PS_MIO35_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F13        |             |            | PS_MIO44_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F14        |             |            | PS_MIO21_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F15        |             |            | PS_MIO25_501            | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F16        |             | High Range | IO_L6P_T0_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F17        |             | High Range | IO_L6N_T0_VREF_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F18        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| F19        |             | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F20        |             | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G1         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| G2         |             |            | PS_DDR_DQS_P1_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G3         |             |            | PS_DDR_DQ10_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G4         |             |            | PS_DDR_A11_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G5         |             |            | PS_DDR_VRN_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G6         |             | Dedicated  | TDI_0                   | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G8         |             |            | VCCPLL                  | PSS VCCPLL    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G9         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G10        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G11        |             |            | VCCBRAM                 | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G14        |             | High Range | IO_0_35                 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G15        |             | High Range | IO_L19N_T3_VREF_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G16        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G17        |             | High Range | IO_L16P_T2_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G18        |             | High Range | IO_L16N_T2_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G19        |             | High Range | IO_L18P_T2_AD13P_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G20        |             | High Range | IO_L18N_T2_AD13N_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H1         |             |            | PS_DDR_DQ14_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H2         |             |            | PS_DDR_DQ13_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H3         |             |            | PS_DDR_DQ11_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H4         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| H5         |             |            | PS_DDR_VRP_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H6         |             |            | PS_DDR_VREF0_502        | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H8         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H9         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H10        |             |            | VCCBRAM                 | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H12        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H14        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| H15        |             | High Range | IO_L19P_T3_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H16        |             | High Range | IO_L13P_T2_MRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H17        |             | High Range | IO_L13N_T2_MRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H18        |             | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H19        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H20        |             | High Range | IO_L17N_T2_AD5N_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J1         |             |            | PS_DDR_DQ15_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J2         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J3         |             |            | PS_DDR_DQ12_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J4         |             |            | PS_DDR_A9_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J5         |             |            | PS_DDR_BA2_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J6         |             | Dedicated  | TMS_0                   | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J9         |             | Dedicated  | VCCADC_0                | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J10        |             | Dedicated  | GNDADC_0                | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J11        |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| J12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J14        |             | High Range | IO_L20N_T3_AD6N_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J15        |             | High Range | IO_25_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J16        |             | High Range | IO_L24N_T3_AD15N_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J17        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| J18        |             | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J19        |             | High Range | IO_L10N_T1_AD11N_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J20        |             | High Range | IO_L17P_T2_AD5P_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K1         |             |            | PS_DDR_A8_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K2         |             |            | PS_DDR_A1_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K3         |             |            | PS_DDR_A3_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K4         |             |            | PS_DDR_A7_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K5         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K6         |             | Dedicated  | VCCO_0                  | VCCO          |             |       0 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| K7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K8         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K9         |             | Dedicated  | VP_0                    | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K10        |             | Dedicated  | VREFN_0                 | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K12        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K14        |             | High Range | IO_L20P_T3_AD6P_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K15        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K16        |             | High Range | IO_L24P_T3_AD15P_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K17        |             | High Range | IO_L12P_T1_MRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K18        |             | High Range | IO_L12N_T1_MRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K19        |             | High Range | IO_L10P_T1_AD11P_35     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K20        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| L1         |             |            | PS_DDR_A5_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L2         |             |            | PS_DDR_CKP_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L3         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| L4         |             |            | PS_DDR_A6_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L5         |             |            | PS_DDR_BA0_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L6         |             | Dedicated  | PROGRAM_B_0             | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L9         |             | Dedicated  | VREFP_0                 | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L10        |             | Dedicated  | VN_0                    | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L11        |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| L12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L14        |             | High Range | IO_L22P_T3_AD7P_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L15        |             | High Range | IO_L22N_T3_AD7N_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L16        |             | High Range | IO_L11P_T1_SRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L17        |             | High Range | IO_L11N_T1_SRCC_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L18        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L19        |             | High Range | IO_L9P_T1_DQS_AD3P_35   | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L20        |             | High Range | IO_L9N_T1_DQS_AD3N_35   | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M1         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M2         |             |            | PS_DDR_CKN_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M3         |             |            | PS_DDR_A2_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M4         |             |            | PS_DDR_A4_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M5         |             |            | PS_DDR_WE_B_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M6         |             | Dedicated  | CFGBVS_0                | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M8         |             |            | VCCPAUX                 | PSS VCCAUX    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M9         |             | Dedicated  | DXP_0                   | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M10        |             | Dedicated  | DXN_0                   | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M12        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M14        |             | High Range | IO_L23P_T3_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M15        |             | High Range | IO_L23N_T3_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M16        |             | High Range | VCCO_35                 | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| M17        |             | High Range | IO_L8P_T1_AD10P_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M18        |             | High Range | IO_L8N_T1_AD10N_35      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M19        |             | High Range | IO_L7P_T1_AD2P_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M20        |             | High Range | IO_L7N_T1_AD2N_35       | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N1         |             |            | PS_DDR_CS_B_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N2         |             |            | PS_DDR_A0_502           | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N3         |             |            | PS_DDR_CKE_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N4         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N5         |             |            | PS_DDR_ODT_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N6         |             |            | RSVDVCC3                | Reserved      |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N9         |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| N10        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N11        |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| N12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N14        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N15        |             | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N16        |             | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N17        | a[-2]       | High Range | IO_L23P_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| N18        | b[4]        | High Range | IO_L13P_T2_MRCC_34      | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| N19        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| N20        | b[2]        | High Range | IO_L14P_T2_SRCC_34      | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| P1         |             |            | PS_DDR_DQ16_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P2         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| P3         |             |            | PS_DDR_DQ17_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P4         |             |            | PS_DDR_RAS_B_502        | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P5         |             |            | PS_DDR_CAS_B_502        | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P6         |             |            | PS_DDR_VREF1_502        | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P8         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P9         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P10        |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| P11        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P12        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P14        | c[4]        | High Range | IO_L6P_T0_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| P15        | a[-4]       | High Range | IO_L24P_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| P16        | a[-5]       | High Range | IO_L24N_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| P17        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P18        | a[-3]       | High Range | IO_L23N_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| P19        | b[3]        | High Range | IO_L13N_T2_MRCC_34      | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| P20        | b[1]        | High Range | IO_L14N_T2_SRCC_34      | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| R1         |             |            | PS_DDR_DQ19_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R2         |             |            | PS_DDR_DQS_P2_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R3         |             |            | PS_DDR_DQ18_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R4         |             |            | PS_DDR_BA1_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R5         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| R6         |             |            | RSVDVCC2                | Reserved      |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R7         |             |            | VCCPINT                 | PSS VCCINT    |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R8         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| R9         |             |            | VCCAUX                  | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| R10        |             | Dedicated  | INIT_B_0                | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R11        |             | Dedicated  | DONE_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| R13        |             |            | VCCINT                  | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R14        | c[3]        | High Range | IO_L6N_T0_VREF_34       | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| R15        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| R16        | a[6]        | High Range | IO_L19P_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| R17        | a[5]        | High Range | IO_L19N_T3_VREF_34      | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| R18        | a[3]        | High Range | IO_L20N_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| R19        |             | High Range | IO_0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R20        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T1         |             |            | PS_DDR_DM2_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T2         |             |            | PS_DDR_DQS_N2_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T3         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T4         |             |            | PS_DDR_DQ20_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T5         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T6         |             |            | RSVDVCC1                | Reserved      |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T7         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T8         |             | Dedicated  | VCCO_13                 | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| T9         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T10        |             | High Range | IO_L1N_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T11        |             | High Range | IO_L1P_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T12        |             | High Range | IO_L2P_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T13        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T14        | c[6]        | High Range | IO_L5P_T0_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| T15        | c[5]        | High Range | IO_L5N_T0_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| T16        | c[-2]       | High Range | IO_L9P_T1_DQS_34        | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| T17        | a[4]        | High Range | IO_L20P_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| T18        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| T19        | a[-6]       | High Range | IO_25_34                | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| T20        | b[0]        | High Range | IO_L15P_T2_DQS_34       | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| U1         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| U2         |             |            | PS_DDR_DQ22_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U3         |             |            | PS_DDR_DQ23_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U4         |             |            | PS_DDR_DQ21_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U5         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U6         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U7         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U8         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U9         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U10        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U11        |             | Dedicated  | VCCO_13                 | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| U12        |             | High Range | IO_L2N_T0_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U13        |             | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U14        | c[-6]       | High Range | IO_L11P_T1_SRCC_34      | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| U15        | b[7]        | High Range | IO_L11N_T1_SRCC_34      | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| U16        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U17        | c[-3]       | High Range | IO_L9N_T1_DQS_34        | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| U18        | b[6]        | High Range | IO_L12P_T1_MRCC_34      | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| U19        | b[5]        | High Range | IO_L12N_T1_MRCC_34      | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| U20        | b[-1]       | High Range | IO_L15N_T2_DQS_34       | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| V1         |             |            | PS_DDR_DQ24_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V2         |             |            | PS_DDR_DQ30_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V3         |             |            | PS_DDR_DQ31_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V4         |             |            | VCCO_DDR_502            | VCCO          |             |         |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| V5         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V6         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V7         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V8         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V9         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V10        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V11        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V12        | c[8]        | High Range | IO_L4P_T0_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| V13        |             | High Range | IO_L3N_T0_DQS_34        | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V14        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| V15        | c[-4]       | High Range | IO_L10P_T1_34           | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| V16        | b[-6]       | High Range | IO_L18P_T2_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| V17        | a[2]        | High Range | IO_L21P_T3_DQS_34       | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| V18        | a[1]        | High Range | IO_L21N_T3_DQS_34       | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| V19        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V20        | b[-2]       | High Range | IO_L16P_T2_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| W1         |             |            | PS_DDR_DQ26_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W2         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W3         |             |            | PS_DDR_DQ29_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W4         |             |            | PS_DDR_DQS_N3_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W5         |             |            | PS_DDR_DQS_P3_502       | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W6         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W7         |             | Dedicated  | VCCO_13                 | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| W8         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W9         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W10        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W11        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W12        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W13        | c[7]        | High Range | IO_L4N_T0_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| W14        | c[0]        | High Range | IO_L8P_T1_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| W15        | c[-5]       | High Range | IO_L10N_T1_34           | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| W16        | a[7]        | High Range | IO_L18N_T2_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| W17        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| W18        | a[0]        | High Range | IO_L22P_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| W19        | a[-1]       | High Range | IO_L22N_T3_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| W20        | b[-3]       | High Range | IO_L16N_T2_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| Y1         |             |            | PS_DDR_DM3_502          | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y2         |             |            | PS_DDR_DQ28_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y3         |             |            | PS_DDR_DQ25_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y4         |             |            | PS_DDR_DQ27_502         | PSS IO        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y5         |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| Y6         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y7         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y8         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y9         |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y10        |             | Dedicated  | VCCO_13                 | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| Y11        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y12        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y13        |             |            | NC                      | Not Connected |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y14        | c[-1]       | High Range | IO_L8N_T1_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| Y15        |             |            | GND                     | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| Y16        | c[2]        | High Range | IO_L7P_T1_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| Y17        | c[1]        | High Range | IO_L7N_T1_34            | OUTPUT        | LVCMOS18*   |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| Y18        | b[-4]       | High Range | IO_L17P_T2_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| Y19        | b[-5]       | High Range | IO_L17N_T2_34           | INPUT         | LVCMOS18*   |      34 |            |      |                     |                 NONE |         | UNFIXED    |           |          |      | NONE             |              |                   |              |
+| Y20        |             | High Range | VCCO_34                 | VCCO          |             |      34 |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.pb
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt
new file mode 100644
index 0000000..12dba56
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt
@@ -0,0 +1,34 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:42:10 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+| Design       : fixedPointTest
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Fully Routed
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+             Max violations: <unlimited>
+             Violations found: 0
++------+----------+-------------+------------+
+| Rule | Severity | Description | Violations |
++------+----------+-------------+------------+
++------+----------+-------------+------------+
+
+2. REPORT DETAILS
+-----------------
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpx
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_power_routed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_power_routed.rpt
new file mode 100644
index 0000000..ab774f1
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_power_routed.rpt
@@ -0,0 +1,149 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version     : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date             : Fri May 13 14:42:10 2022
+| Host             : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command          : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+| Design           : fixedPointTest
+| Device           : xc7z010clg400-1
+| Design State     : routed
+| Grade            : commercial
+| Process          : typical
+| Characterization : Production
+----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+----------------------------------+
+| Total On-Chip Power (W)  | 10.945 (Junction temp exceeded!) |
+| Design Power Budget (W)  | Unspecified*                     |
+| Power Budget Margin (W)  | NA                               |
+| Dynamic (W)              | 10.198                           |
+| Device Static (W)        | 0.747                            |
+| Effective TJA (C/W)      | 11.5                             |
+| Max Ambient (C)          | 0.0                              |
+| Junction Temperature (C) | 125.0                            |
+| Confidence Level         | Low                              |
+| Setting File             | ---                              |
+| Simulation Activity File | ---                              |
+| Design Nets Matched      | NA                               |
++--------------------------+----------------------------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Slice Logic    |     0.051 |       21 |       --- |             --- |
+|   LUT as Logic |     0.032 |       14 |     17600 |            0.08 |
+|   CARRY4       |     0.019 |        4 |      4400 |            0.09 |
+|   Others       |     0.000 |        2 |       --- |             --- |
+| Signals        |     0.294 |       46 |       --- |             --- |
+| I/O            |     9.853 |       43 |       100 |           43.00 |
+| Static Power   |     0.747 |          |           |                 |
+| Total          |    10.945 |          |           |                 |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint    |       1.000 |     0.586 |       0.457 |      0.129 |       NA    | Unspecified | NA         |
+| Vccaux    |       1.800 |     0.838 |       0.797 |      0.040 |       NA    | Unspecified | NA         |
+| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco18    |       1.800 |     4.615 |       4.614 |      0.001 |       NA    | Unspecified | NA         |
+| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccbram   |       1.000 |     0.011 |       0.000 |      0.011 |       NA    | Unspecified | NA         |
+| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccpint   |       1.000 |     0.473 |       0.000 |      0.473 |       NA    | Unspecified | NA         |
+| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |       NA    | Unspecified | NA         |
+| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |       NA    | Unspecified | NA         |
+| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High       | Design is routed                                       |                                                                                                            |
+| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
+| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
+| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models               | High       | Device models are Production                           |                                                                                                            |
+|                             |            |                                                        |                                                                                                            |
+| Overall confidence level    | Low        |                                                        |                                                                                                            |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+------------------------+
+| Ambient Temp (C)      | 25.0                   |
+| ThetaJA (C/W)         | 11.5                   |
+| Airflow (LFM)         | 250                    |
+| Heat Sink             | none                   |
+| ThetaSA (C/W)         | 0.0                    |
+| Board Selection       | medium (10"x10")       |
+| # of Board Layers     | 8to11 (8 to 11 Layers) |
+| Board Temperature (C) | 25.0                   |
++-----------------------+------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++-------+--------+-----------------+
+| Clock | Domain | Constraint (ns) |
++-------+--------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++----------------+-----------+
+| Name           | Power (W) |
++----------------+-----------+
+| fixedPointTest |    10.198 |
++----------------+-----------+
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_power_routed.rpx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_power_routed.rpx
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_power_summary_routed.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_power_summary_routed.pb
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_route_status.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_route_status.pb
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_route_status.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_route_status.rpt
new file mode 100644
index 0000000..039ffc2
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+   # of logical nets.......................... :         106 :
+       # of nets not needing routing.......... :          58 :
+           # of internally routed nets........ :          58 :
+       # of routable nets..................... :          48 :
+           # of fully routed nets............. :          48 :
+       # of nets with routing errors.......... :           0 :
+   ------------------------------------------- : ----------- :
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.pb
new file mode 100644
index 0000000..4526e93
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.pb
@@ -0,0 +1,2 @@
+
+2012.4’)Timing analysis from Implemented netlist.
\ No newline at end of file
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.rpt
new file mode 100644
index 0000000..01209cc
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.rpt
@@ -0,0 +1,805 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:42:10 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation
+| Design       : fixedPointTest
+| Device       : 7z010-clg400
+| Speed File   : -1  PRODUCTION 1.12 2019-11-22
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+  Enable Multi Corner Analysis               :  Yes
+  Enable Pessimism Removal                   :  Yes
+  Pessimism Removal Resolution               :  Nearest Common Node
+  Enable Input Delay Default Clock           :  No
+  Enable Preset / Clear Arcs                 :  No
+  Disable Flight Delays                      :  No
+  Ignore I/O Paths                           :  No
+  Timing Early Launch at Borrowing Latches   :  No
+  Borrow Time for Max Delay Exceptions       :  Yes
+  Merge Timing Exceptions                    :  Yes
+
+  Corner  Analyze    Analyze    
+  Name    Max Paths  Min Paths  
+  ------  ---------  ---------  
+  Slow    Yes        Yes        
+  Fast    Yes        Yes        
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule  Severity  Description  Violations  
+----  --------  -----------  ----------  
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (0)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (0)
+5. checking no_input_delay (0)
+6. checking no_output_delay (0)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (0)
+------------------------
+ There are 0 register/latch pins with no clock.
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (0)
+------------------------------------------------
+ There are 0 pins that are not constrained for maximum delay.
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (0)
+------------------------------
+ There are 0 input ports with no input delay specified.
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (0)
+-------------------------------
+ There are 0 ports with no output delay specified.
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+        inf        0.000                      0                   15          inf        0.000                      0                   15           NA           NA                      NA                    NA  
+
+
+There are no user specified timing constraints.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| User Ignored Path Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock    
+----------    ----------    --------    
+
+
+------------------------------------------------------------------------------------------------
+| Unconstrained Path Table
+| ------------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock    
+----------    ----------    --------    
+(none)                                    
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  
+  To Clock:  
+
+Max Delay            15 Endpoints
+Min Delay            15 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[7]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.462ns  (logic 4.925ns (52.050%)  route 4.537ns (47.950%))
+  Logic Levels:           7  (CARRY4=4 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.825 r  c_OBUF[5]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.825    c_OBUF[5]_inst_i_1_n_0
+    SLICE_X43Y21         CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     4.159 r  c_OBUF[8]_inst_i_1/O[1]
+                         net (fo=1, routed)           2.437     6.596    c_OBUF[7]
+    W13                  OBUF (Prop_obuf_I_O)         2.866     9.462 r  c_OBUF[7]_inst/O
+                         net (fo=0)                   0.000     9.462    c[7]
+    W13                                                               r  c[7] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[8]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.266ns  (logic 4.823ns (52.047%)  route 4.443ns (47.953%))
+  Logic Levels:           7  (CARRY4=4 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.825 r  c_OBUF[5]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.825    c_OBUF[5]_inst_i_1_n_0
+    SLICE_X43Y21         CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     4.064 r  c_OBUF[8]_inst_i_1/O[2]
+                         net (fo=1, routed)           2.343     6.407    c_OBUF[8]
+    V12                  OBUF (Prop_obuf_I_O)         2.858     9.266 r  c_OBUF[8]_inst/O
+                         net (fo=0)                   0.000     9.266    c[8]
+    V12                                                               r  c[8] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[6]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.175ns  (logic 4.778ns (52.082%)  route 4.396ns (47.918%))
+  Logic Levels:           7  (CARRY4=4 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.825 r  c_OBUF[5]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.825    c_OBUF[5]_inst_i_1_n_0
+    SLICE_X43Y21         CARRY4 (Prop_carry4_CI_O[0])
+                                                      0.222     4.047 r  c_OBUF[8]_inst_i_1/O[0]
+                         net (fo=1, routed)           2.296     6.343    c_OBUF[6]
+    T14                  OBUF (Prop_obuf_I_O)         2.831     9.175 r  c_OBUF[6]_inst/O
+                         net (fo=0)                   0.000     9.175    c[6]
+    T14                                                               r  c[6] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[3]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.173ns  (logic 4.784ns (52.155%)  route 4.389ns (47.845%))
+  Logic Levels:           6  (CARRY4=3 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     4.045 r  c_OBUF[5]_inst_i_1/O[1]
+                         net (fo=1, routed)           2.289     6.334    c_OBUF[3]
+    R14                  OBUF (Prop_obuf_I_O)         2.839     9.173 r  c_OBUF[3]_inst/O
+                         net (fo=0)                   0.000     9.173    c[3]
+    R14                                                               r  c[3] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[5]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.153ns  (logic 4.765ns (52.061%)  route 4.388ns (47.939%))
+  Logic Levels:           6  (CARRY4=3 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_O[3])
+                                                      0.313     4.024 r  c_OBUF[5]_inst_i_1/O[3]
+                         net (fo=1, routed)           2.288     6.312    c_OBUF[5]
+    T15                  OBUF (Prop_obuf_I_O)         2.841     9.153 r  c_OBUF[5]_inst/O
+                         net (fo=0)                   0.000     9.153    c[5]
+    T15                                                               r  c[5] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.090ns  (logic 4.700ns (51.703%)  route 4.390ns (48.297%))
+  Logic Levels:           5  (CARRY4=2 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_O[3])
+                                                      0.313     3.910 r  c_OBUF[1]_inst_i_1/O[3]
+                         net (fo=1, routed)           2.290     6.201    c_OBUF[1]
+    Y17                  OBUF (Prop_obuf_I_O)         2.890     9.090 r  c_OBUF[1]_inst/O
+                         net (fo=0)                   0.000     9.090    c[1]
+    Y17                                                               r  c[1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[-1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.079ns  (logic 4.743ns (52.242%)  route 4.336ns (47.758%))
+  Logic Levels:           5  (CARRY4=2 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     3.931 r  c_OBUF[1]_inst_i_1/O[1]
+                         net (fo=1, routed)           2.236     6.167    c_OBUF[-1]
+    Y14                  OBUF (Prop_obuf_I_O)         2.912     9.079 r  c_OBUF[-1]_inst/O
+                         net (fo=0)                   0.000     9.079    c[-1]
+    Y14                                                               r  c[-1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[4]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        9.079ns  (logic 4.693ns (51.693%)  route 4.386ns (48.307%))
+  Logic Levels:           6  (CARRY4=3 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     3.950 r  c_OBUF[5]_inst_i_1/O[2]
+                         net (fo=1, routed)           2.286     6.236    c_OBUF[4]
+    P14                  OBUF (Prop_obuf_I_O)         2.843     9.079 r  c_OBUF[4]_inst/O
+                         net (fo=0)                   0.000     9.079    c[4]
+    P14                                                               r  c[4] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[2]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        8.971ns  (logic 4.723ns (52.647%)  route 4.248ns (47.353%))
+  Logic Levels:           6  (CARRY4=3 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_O[0])
+                                                      0.222     3.933 r  c_OBUF[5]_inst_i_1/O[0]
+                         net (fo=1, routed)           2.148     6.081    c_OBUF[2]
+    Y16                  OBUF (Prop_obuf_I_O)         2.890     8.971 r  c_OBUF[2]_inst/O
+                         net (fo=0)                   0.000     8.971    c[2]
+    Y16                                                               r  c[2] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[-3]
+                            (input port)
+  Destination:            c[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        8.884ns  (logic 4.645ns (52.282%)  route 4.239ns (47.718%))
+  Logic Levels:           5  (CARRY4=2 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    P18                                               0.000     0.000 r  a[-3] (IN)
+                         net (fo=0)                   0.000     0.000    a[-3]
+    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
+                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
+                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
+                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     3.836 r  c_OBUF[1]_inst_i_1/O[2]
+                         net (fo=1, routed)           2.139     5.975    c_OBUF[0]
+    W14                  OBUF (Prop_obuf_I_O)         2.909     8.884 r  c_OBUF[0]_inst/O
+                         net (fo=0)                   0.000     8.884    c[0]
+    W14                                                               r  c[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 b[-3]
+                            (input port)
+  Destination:            c[-3]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.431ns  (logic 1.568ns (64.485%)  route 0.863ns (35.515%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W20                                               0.000     0.000 r  b[-3] (IN)
+                         net (fo=0)                   0.000     0.000    b[-3]
+    W20                  IBUF (Prop_ibuf_I_O)         0.206     0.206 r  b_IBUF[-3]_inst/O
+                         net (fo=1, routed)           0.329     0.534    b_IBUF[-3]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I1_O)        0.045     0.579 r  c_OBUF[-3]_inst_i_2/O
+                         net (fo=1, routed)           0.000     0.579    c_OBUF[-3]_inst_i_2_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_O[3])
+                                                      0.063     0.642 r  c_OBUF[-3]_inst_i_1/O[3]
+                         net (fo=1, routed)           0.535     1.177    c_OBUF[-3]
+    U17                  OBUF (Prop_obuf_I_O)         1.254     2.431 r  c_OBUF[-3]_inst/O
+                         net (fo=0)                   0.000     2.431    c[-3]
+    U17                                                               r  c[-3] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 b[-5]
+                            (input port)
+  Destination:            c[-5]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.505ns  (logic 1.604ns (64.018%)  route 0.901ns (35.982%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    Y19                                               0.000     0.000 r  b[-5] (IN)
+                         net (fo=0)                   0.000     0.000    b[-5]
+    Y19                  IBUF (Prop_ibuf_I_O)         0.205     0.205 r  b_IBUF[-5]_inst/O
+                         net (fo=1, routed)           0.375     0.580    b_IBUF[-5]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I1_O)        0.045     0.625 r  c_OBUF[-3]_inst_i_4/O
+                         net (fo=1, routed)           0.000     0.625    c_OBUF[-3]_inst_i_4_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[1]_O[1])
+                                                      0.065     0.690 r  c_OBUF[-3]_inst_i_1/O[1]
+                         net (fo=1, routed)           0.527     1.217    c_OBUF[-5]
+    W15                  OBUF (Prop_obuf_I_O)         1.288     2.505 r  c_OBUF[-5]_inst/O
+                         net (fo=0)                   0.000     2.505    c[-5]
+    W15                                                               r  c[-5] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 b[-6]
+                            (input port)
+  Destination:            c[-6]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.520ns  (logic 1.587ns (62.965%)  route 0.933ns (37.035%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    V16                                               0.000     0.000 r  b[-6] (IN)
+                         net (fo=0)                   0.000     0.000    b[-6]
+    V16                  IBUF (Prop_ibuf_I_O)         0.185     0.185 r  b_IBUF[-6]_inst/O
+                         net (fo=1, routed)           0.461     0.646    b_IBUF[-6]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I1_O)        0.045     0.691 r  c_OBUF[-3]_inst_i_5/O
+                         net (fo=1, routed)           0.000     0.691    c_OBUF[-3]_inst_i_5_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[0]_O[0])
+                                                      0.070     0.761 r  c_OBUF[-3]_inst_i_1/O[0]
+                         net (fo=1, routed)           0.473     1.233    c_OBUF[-6]
+    U14                  OBUF (Prop_obuf_I_O)         1.287     2.520 r  c_OBUF[-6]_inst/O
+                         net (fo=0)                   0.000     2.520    c[-6]
+    U14                                                               r  c[-6] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 b[-2]
+                            (input port)
+  Destination:            c[-2]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.529ns  (logic 1.573ns (62.198%)  route 0.956ns (37.802%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    V20                                               0.000     0.000 r  b[-2] (IN)
+                         net (fo=0)                   0.000     0.000    b[-2]
+    V20                  IBUF (Prop_ibuf_I_O)         0.204     0.204 r  b_IBUF[-2]_inst/O
+                         net (fo=1, routed)           0.419     0.622    b_IBUF[-2]
+    SLICE_X43Y19         LUT2 (Prop_lut2_I1_O)        0.045     0.667 r  c_OBUF[1]_inst_i_5/O
+                         net (fo=1, routed)           0.000     0.667    c_OBUF[1]_inst_i_5_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_S[0]_O[0])
+                                                      0.070     0.737 r  c_OBUF[1]_inst_i_1/O[0]
+                         net (fo=1, routed)           0.537     1.275    c_OBUF[-2]
+    T16                  OBUF (Prop_obuf_I_O)         1.254     2.529 r  c_OBUF[-2]_inst/O
+                         net (fo=0)                   0.000     2.529    c[-2]
+    T16                                                               r  c[-2] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 b[-1]
+                            (input port)
+  Destination:            c[-1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.576ns  (logic 1.613ns (62.626%)  route 0.963ns (37.374%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U20                                               0.000     0.000 r  b[-1] (IN)
+                         net (fo=0)                   0.000     0.000    b[-1]
+    U20                  IBUF (Prop_ibuf_I_O)         0.193     0.193 r  b_IBUF[-1]_inst/O
+                         net (fo=1, routed)           0.375     0.567    b_IBUF[-1]
+    SLICE_X43Y19         LUT2 (Prop_lut2_I1_O)        0.045     0.612 r  c_OBUF[1]_inst_i_4/O
+                         net (fo=1, routed)           0.000     0.612    c_OBUF[1]_inst_i_4_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_S[1]_O[1])
+                                                      0.065     0.677 r  c_OBUF[1]_inst_i_1/O[1]
+                         net (fo=1, routed)           0.588     1.265    c_OBUF[-1]
+    Y14                  OBUF (Prop_obuf_I_O)         1.311     2.576 r  c_OBUF[-1]_inst/O
+                         net (fo=0)                   0.000     2.576    c[-1]
+    Y14                                                               r  c[-1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 b[0]
+                            (input port)
+  Destination:            c[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.593ns  (logic 1.617ns (62.342%)  route 0.977ns (37.658%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    T20                                               0.000     0.000 r  b[0] (IN)
+                         net (fo=0)                   0.000     0.000    b[0]
+    T20                  IBUF (Prop_ibuf_I_O)         0.196     0.196 r  b_IBUF[0]_inst/O
+                         net (fo=1, routed)           0.420     0.616    b_IBUF[0]
+    SLICE_X43Y19         LUT2 (Prop_lut2_I1_O)        0.045     0.661 r  c_OBUF[1]_inst_i_3/O
+                         net (fo=1, routed)           0.000     0.661    c_OBUF[1]_inst_i_3_n_0
+    SLICE_X43Y19         CARRY4 (Prop_carry4_S[2]_O[2])
+                                                      0.066     0.727 r  c_OBUF[1]_inst_i_1/O[2]
+                         net (fo=1, routed)           0.557     1.284    c_OBUF[0]
+    W14                  OBUF (Prop_obuf_I_O)         1.309     2.593 r  c_OBUF[0]_inst/O
+                         net (fo=0)                   0.000     2.593    c[0]
+    W14                                                               r  c[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[5]
+                            (input port)
+  Destination:            c[5]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.595ns  (logic 1.510ns (58.186%)  route 1.085ns (41.814%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    R17                                               0.000     0.000 r  a[5] (IN)
+                         net (fo=0)                   0.000     0.000    a[5]
+    R17                  IBUF (Prop_ibuf_I_O)         0.161     0.161 r  a_IBUF[5]_inst/O
+                         net (fo=2, routed)           0.467     0.628    a_IBUF[5]
+    SLICE_X43Y20         LUT2 (Prop_lut2_I0_O)        0.045     0.673 r  c_OBUF[5]_inst_i_2/O
+                         net (fo=1, routed)           0.000     0.673    c_OBUF[5]_inst_i_2_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_S[3]_O[3])
+                                                      0.063     0.736 r  c_OBUF[5]_inst_i_1/O[3]
+                         net (fo=1, routed)           0.618     1.354    c_OBUF[5]
+    T15                  OBUF (Prop_obuf_I_O)         1.241     2.595 r  c_OBUF[5]_inst/O
+                         net (fo=0)                   0.000     2.595    c[5]
+    T15                                                               r  c[5] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 b[-5]
+                            (input port)
+  Destination:            c[-4]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.603ns  (logic 1.698ns (65.228%)  route 0.905ns (34.772%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    Y19                                               0.000     0.000 r  b[-5] (IN)
+                         net (fo=0)                   0.000     0.000    b[-5]
+    Y19                  IBUF (Prop_ibuf_I_O)         0.205     0.205 r  b_IBUF[-5]_inst/O
+                         net (fo=1, routed)           0.375     0.580    b_IBUF[-5]
+    SLICE_X43Y18         LUT2 (Prop_lut2_I1_O)        0.045     0.625 r  c_OBUF[-3]_inst_i_4/O
+                         net (fo=1, routed)           0.000     0.625    c_OBUF[-3]_inst_i_4_n_0
+    SLICE_X43Y18         CARRY4 (Prop_carry4_S[1]_O[2])
+                                                      0.152     0.777 r  c_OBUF[-3]_inst_i_1/O[2]
+                         net (fo=1, routed)           0.531     1.307    c_OBUF[-4]
+    V15                  OBUF (Prop_obuf_I_O)         1.296     2.603 r  c_OBUF[-4]_inst/O
+                         net (fo=0)                   0.000     2.603    c[-4]
+    V15                                                               r  c[-4] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 b[2]
+                            (input port)
+  Destination:            c[2]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.608ns  (logic 1.615ns (61.934%)  route 0.993ns (38.066%))
+  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    N20                                               0.000     0.000 r  b[2] (IN)
+                         net (fo=0)                   0.000     0.000    b[2]
+    N20                  IBUF (Prop_ibuf_I_O)         0.208     0.208 r  b_IBUF[2]_inst/O
+                         net (fo=1, routed)           0.435     0.643    b_IBUF[2]
+    SLICE_X43Y20         LUT2 (Prop_lut2_I1_O)        0.045     0.688 r  c_OBUF[5]_inst_i_5/O
+                         net (fo=1, routed)           0.000     0.688    c_OBUF[5]_inst_i_5_n_0
+    SLICE_X43Y20         CARRY4 (Prop_carry4_S[0]_O[0])
+                                                      0.070     0.758 r  c_OBUF[5]_inst_i_1/O[0]
+                         net (fo=1, routed)           0.558     1.316    c_OBUF[2]
+    Y16                  OBUF (Prop_obuf_I_O)         1.293     2.608 r  c_OBUF[2]_inst/O
+                         net (fo=0)                   0.000     2.608    c[2]
+    Y16                                                               r  c[2] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 a[2]
+                            (input port)
+  Destination:            c[3]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.631ns  (logic 1.552ns (58.994%)  route 1.079ns (41.006%))
+  Logic Levels:           3  (CARRY4=1 IBUF=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    V17                                               0.000     0.000 r  a[2] (IN)
+                         net (fo=0)                   0.000     0.000    a[2]
+    V17                  IBUF (Prop_ibuf_I_O)         0.190     0.190 r  a_IBUF[2]_inst/O
+                         net (fo=2, routed)           0.467     0.657    a_IBUF[2]
+    SLICE_X43Y20         CARRY4 (Prop_carry4_DI[0]_O[1])
+                                                      0.124     0.781 r  c_OBUF[5]_inst_i_1/O[1]
+                         net (fo=1, routed)           0.612     1.393    c_OBUF[3]
+    R14                  OBUF (Prop_obuf_I_O)         1.239     2.631 r  c_OBUF[3]_inst/O
+                         net (fo=0)                   0.000     2.631    c[3]
+    R14                                                               r  c[3] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.rpx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.rpx
new file mode 100644
index 0000000..3be9fe6
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.rpx differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_utilization_placed.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_utilization_placed.pb
new file mode 100644
index 0000000..16e09b3
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_utilization_placed.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_utilization_placed.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_utilization_placed.rpt
new file mode 100644
index 0000000..cc6ae63
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_utilization_placed.rpt
@@ -0,0 +1,199 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:41:53 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb
+| Design       : fixedPointTest
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Fully Placed
+-------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs              |   14 |     0 |          0 |     17600 |  0.08 |
+|   LUT as Logic          |   14 |     0 |          0 |     17600 |  0.08 |
+|   LUT as Memory         |    0 |     0 |          0 |      6000 |  0.00 |
+| Slice Registers         |    0 |     0 |          0 |     35200 |  0.00 |
+|   Register as Flip Flop |    0 |     0 |          0 |     35200 |  0.00 |
+|   Register as Latch     |    0 |     0 |          0 |     35200 |  0.00 |
+| F7 Muxes                |    0 |     0 |          0 |      8800 |  0.00 |
+| F8 Muxes                |    0 |     0 |          0 |      4400 |  0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 0     |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++------------------------------------------+------+-------+------------+-----------+-------+
+|                 Site Type                | Used | Fixed | Prohibited | Available | Util% |
++------------------------------------------+------+-------+------------+-----------+-------+
+| Slice                                    |    4 |     0 |          0 |      4400 |  0.09 |
+|   SLICEL                                 |    4 |     0 |            |           |       |
+|   SLICEM                                 |    0 |     0 |            |           |       |
+| LUT as Logic                             |   14 |     0 |          0 |     17600 |  0.08 |
+|   using O5 output only                   |    0 |       |            |           |       |
+|   using O6 output only                   |   13 |       |            |           |       |
+|   using O5 and O6                        |    1 |       |            |           |       |
+| LUT as Memory                            |    0 |     0 |          0 |      6000 |  0.00 |
+|   LUT as Distributed RAM                 |    0 |     0 |            |           |       |
+|   LUT as Shift Register                  |    0 |     0 |            |           |       |
+| Slice Registers                          |    0 |     0 |          0 |     35200 |  0.00 |
+|   Register driven from within the Slice  |    0 |       |            |           |       |
+|   Register driven from outside the Slice |    0 |       |            |           |       |
+| Unique Control Sets                      |    0 |       |          0 |      4400 |  0.00 |
++------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile |    0 |     0 |          0 |        60 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |          0 |        60 |  0.00 |
+|   RAMB18       |    0 |     0 |          0 |       120 |  0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |        80 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   43 |     0 |          0 |       100 | 43.00 |
+|   IOB Master Pads           |   21 |       |            |           |       |
+|   IOB Slave Pads            |   21 |       |            |           |       |
+| Bonded IPADs                |    0 |     0 |          0 |         2 |  0.00 |
+| Bonded IOPADs               |    0 |     0 |          0 |       130 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |         2 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |         2 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |         8 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |         8 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |          0 |         2 |  0.00 |
+| IBUFDS                      |    0 |     0 |          0 |        96 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |         8 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |         8 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       100 |  0.00 |
+| ILOGIC                      |    0 |     0 |          0 |       100 |  0.00 |
+| OLOGIC                      |    0 |     0 |          0 |       100 |  0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+|  Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL   |    0 |     0 |          0 |        32 |  0.00 |
+| BUFIO      |    0 |     0 |          0 |         8 |  0.00 |
+| MMCME2_ADV |    0 |     0 |          0 |         2 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |          0 |         2 |  0.00 |
+| BUFMRCE    |    0 |     0 |          0 |         4 |  0.00 |
+| BUFHCE     |    0 |     0 |          0 |        48 |  0.00 |
+| BUFR       |    0 |     0 |          0 |         8 |  0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| IBUF     |   28 |                  IO |
+| OBUF     |   15 |                  IO |
+| LUT2     |   14 |                 LUT |
+| CARRY4   |    4 |          CarryLogic |
+| LUT1     |    1 |                 LUT |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/gen_run.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000..b89cf32
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/gen_run.xml
@@ -0,0 +1,170 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7z010clg400-1" LaunchTime="1652445674">
+  <File Type="ROUTE-PWR" Name="fixedPointTest_power_routed.rpt"/>
+  <File Type="PA-TCL" Name="fixedPointTest.tcl"/>
+  <File Type="BITSTR-MMI" Name="fixedPointTest.mmi"/>
+  <File Type="OPT-METHODOLOGY-DRC" Name="fixedPointTest_methodology_drc_opted.rpt"/>
+  <File Type="INIT-TIMING" Name="fixedPointTest_timing_summary_init.rpt"/>
+  <File Type="ROUTE-PWR-SUM" Name="fixedPointTest_power_summary_routed.pb"/>
+  <File Type="REPORTS-TCL" Name="fixedPointTest_reports.tcl"/>
+  <File Type="OPT-TIMING" Name="fixedPointTest_timing_summary_opted.rpt"/>
+  <File Type="OPT-DCP" Name="fixedPointTest_opt.dcp"/>
+  <File Type="OPT-DRC" Name="fixedPointTest_drc_opted.rpt"/>
+  <File Type="OPT-HWDEF" Name="fixedPointTest.hwdef"/>
+  <File Type="PWROPT-DCP" Name="fixedPointTest_pwropt.dcp"/>
+  <File Type="PWROPT-DRC" Name="fixedPointTest_drc_pwropted.rpt"/>
+  <File Type="PWROPT-TIMING" Name="fixedPointTest_timing_summary_pwropted.rpt"/>
+  <File Type="PLACE-DCP" Name="fixedPointTest_placed.dcp"/>
+  <File Type="PLACE-IO" Name="fixedPointTest_io_placed.rpt"/>
+  <File Type="PLACE-CLK" Name="fixedPointTest_clock_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL" Name="fixedPointTest_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL-PB" Name="fixedPointTest_utilization_placed.pb"/>
+  <File Type="PLACE-CTRL" Name="fixedPointTest_control_sets_placed.rpt"/>
+  <File Type="PLACE-SIMILARITY" Name="fixedPointTest_incremental_reuse_placed.rpt"/>
+  <File Type="PLACE-PRE-SIMILARITY" Name="fixedPointTest_incremental_reuse_pre_placed.rpt"/>
+  <File Type="BG-BIN" Name="fixedPointTest.bin"/>
+  <File Type="PLACE-TIMING" Name="fixedPointTest_timing_summary_placed.rpt"/>
+  <File Type="POSTPLACE-PWROPT-DCP" Name="fixedPointTest_postplace_pwropt.dcp"/>
+  <File Type="BITSTR-MSK" Name="fixedPointTest.msk"/>
+  <File Type="POSTPLACE-PWROPT-TIMING" Name="fixedPointTest_timing_summary_postplace_pwropted.rpt"/>
+  <File Type="PHYSOPT-DCP" Name="fixedPointTest_physopt.dcp"/>
+  <File Type="PHYSOPT-DRC" Name="fixedPointTest_drc_physopted.rpt"/>
+  <File Type="BITSTR-RBT" Name="fixedPointTest.rbt"/>
+  <File Type="PHYSOPT-TIMING" Name="fixedPointTest_timing_summary_physopted.rpt"/>
+  <File Type="ROUTE-ERROR-DCP" Name="fixedPointTest_routed_error.dcp"/>
+  <File Type="ROUTE-DCP" Name="fixedPointTest_routed.dcp"/>
+  <File Type="ROUTE-BLACKBOX-DCP" Name="fixedPointTest_routed_bb.dcp"/>
+  <File Type="ROUTE-DRC" Name="fixedPointTest_drc_routed.rpt"/>
+  <File Type="ROUTE-DRC-PB" Name="fixedPointTest_drc_routed.pb"/>
+  <File Type="ROUTE-DRC-RPX" Name="fixedPointTest_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="fixedPointTest_methodology_drc_routed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="fixedPointTest_methodology_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="fixedPointTest_methodology_drc_routed.pb"/>
+  <File Type="ROUTE-PWR-RPX" Name="fixedPointTest_power_routed.rpx"/>
+  <File Type="ROUTE-STATUS" Name="fixedPointTest_route_status.rpt"/>
+  <File Type="ROUTE-STATUS-PB" Name="fixedPointTest_route_status.pb"/>
+  <File Type="ROUTE-TIMINGSUMMARY" Name="fixedPointTest_timing_summary_routed.rpt"/>
+  <File Type="ROUTE-TIMING-PB" Name="fixedPointTest_timing_summary_routed.pb"/>
+  <File Type="ROUTE-TIMING-RPX" Name="fixedPointTest_timing_summary_routed.rpx"/>
+  <File Type="ROUTE-SIMILARITY" Name="fixedPointTest_incremental_reuse_routed.rpt"/>
+  <File Type="ROUTE-CLK" Name="fixedPointTest_clock_utilization_routed.rpt"/>
+  <File Type="ROUTE-BUS-SKEW" Name="fixedPointTest_bus_skew_routed.rpt"/>
+  <File Type="ROUTE-BUS-SKEW-PB" Name="fixedPointTest_bus_skew_routed.pb"/>
+  <File Type="ROUTE-BUS-SKEW-RPX" Name="fixedPointTest_bus_skew_routed.rpx"/>
+  <File Type="POSTROUTE-PHYSOPT-DCP" Name="fixedPointTest_postroute_physopt.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="fixedPointTest_postroute_physopt_bb.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="fixedPointTest_timing_summary_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="fixedPointTest_timing_summary_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="fixedPointTest_timing_summary_postroute_physopted.rpx"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="fixedPointTest_bus_skew_postroute_physopted.rpt"/>
+  <File Type="BG-BIT" Name="fixedPointTest.bit"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="fixedPointTest_bus_skew_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="fixedPointTest_bus_skew_postroute_physopted.rpx"/>
+  <File Type="BITSTR-NKY" Name="fixedPointTest.nky"/>
+  <File Type="BITSTR-BMM" Name="fixedPointTest_bd.bmm"/>
+  <File Type="PDI-FILE" Name="fixedPointTest.pdi"/>
+  <File Type="RCFI_FILE" Name="fixedPointTest.rcfi"/>
+  <File Type="CFI_FILE" Name="fixedPointTest.cfi"/>
+  <File Type="RNPI_FILE" Name="fixedPointTest.rnpi"/>
+  <File Type="NPI_FILE" Name="fixedPointTest.npi"/>
+  <File Type="RBD_FILE" Name="fixedPointTest.rbd"/>
+  <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+  <File Type="BITSTR-LTX" Name="fixedPointTest.ltx"/>
+  <File Type="BITSTR-SYSDEF" Name="fixedPointTest.sysdef"/>
+  <File Type="BG-BGN" Name="fixedPointTest.bgn"/>
+  <File Type="BG-DRC" Name="fixedPointTest.drc"/>
+  <File Type="RDI-RDI" Name="fixedPointTest.vdi"/>
+  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_float_types.vhdl">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="Library" Val="ieee_proposed"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_float_types.vhdl"/>
+        <Attr Name="ImportTime" Val="1652436395"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="Library" Val="ieee_proposed"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl"/>
+        <Attr Name="ImportTime" Val="1652436398"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="Library" Val="ieee_proposed"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl"/>
+        <Attr Name="ImportTime" Val="1652436400"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_pkg.vhdl">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="Library" Val="ieee_proposed"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_pkg.vhdl"/>
+        <Attr Name="ImportTime" Val="1652436402"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/new/fixedPointTest.vhd">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="fixedPointTest"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc"/>
+        <Attr Name="ImportTime" Val="1648802911"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+    <Filter Type="Utils"/>
+    <File Path="$PSRCDIR/utils_1/imports/synth_1/fixedPointTest.dcp">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedInSteps" Val="synth_1"/>
+        <Attr Name="AutoDcp" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
+      <Desc>Default settings for Implementation.</Desc>
+    </StratHandle>
+    <Step Id="init_design"/>
+    <Step Id="opt_design"/>
+    <Step Id="power_opt_design"/>
+    <Step Id="place_design"/>
+    <Step Id="post_place_power_opt_design"/>
+    <Step Id="phys_opt_design"/>
+    <Step Id="route_design"/>
+    <Step Id="post_route_phys_opt_design"/>
+    <Step Id="write_bitstream"/>
+  </Strategy>
+</GenRun>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/htr.txt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/htr.txt
new file mode 100644
index 0000000..b068790
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/htr.txt
@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log fixedPointTest.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/init_design.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/init_design.pb
new file mode 100644
index 0000000..1e3e324
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/init_design.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/opt_design.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000..b1619f0
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/opt_design.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/phys_opt_design.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/phys_opt_design.pb
new file mode 100644
index 0000000..e5f4f4c
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/phys_opt_design.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/place_design.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/place_design.pb
new file mode 100644
index 0000000..ee265ea
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/place_design.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/project.wdf b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/project.wdf
new file mode 100644
index 0000000..694142c
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/route_design.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/route_design.pb
new file mode 100644
index 0000000..90c0b50
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/route_design.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/rundef.js b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/rundef.js
new file mode 100644
index 0000000..6920a76
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/rundef.js
@@ -0,0 +1,40 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;";
+} else {
+  PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "write_bitstream", "begin" );
+ISEStep( "vivado",
+         "-log fixedPointTest.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.bat b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.bat
new file mode 100644
index 0000000..6c4f290
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.bat
@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.log
new file mode 100644
index 0000000..f25d040
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.log
@@ -0,0 +1,596 @@
+
+*** Running vivado
+    with args -log fixedPointTest.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+
+
+
+****** Vivado v2021.2 (64-bit)
+  **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+source fixedPointTest.tcl -notrace
+create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 10.250
+Command: link_design -top fixedPointTest -part xc7z010clg400-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.340 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.340 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+7 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 0.000
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.340 ; gain = 0.000
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1387.457 ; gain = 126.117
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: d688f8fa
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 9d9fcb97
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1683.215 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: f158031e
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+24 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1683.215 ; gain = 421.875
+INFO: [Timing 38-480] Writing timing data to binary archive.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+Command: report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c5371e47
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170083491
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.149 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.152 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e3fab18a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 2.4 Global Placement Core
+WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
+Phase 2.4 Global Placement Core | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 17701980b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.699 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+Phase 4.1 Post Commit Optimization | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.773 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236ae8e9c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Ending Placer Task | Checksum: 1c0019b8b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+43 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file fixedPointTest_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1722.266 ; gain = 0.000
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+51 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1722.266 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: faca7d44 ConstDB: 0 ShapeSum: c5371e47 RouteDB: 0
+Post Restoration Checksum: NetGraph: 54150718 NumContArr: b3d68f27 Constraints: 0 Timing: 0
+Phase 1 Build RT Design | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1757.188 ; gain = 23.668
+
+Phase 2 Router Initialization
+INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 107eb963f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699
+ Number of Nodes with overlaps = 0
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 46
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 46
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: d7f76c92
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: d7f76c92
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 3 Initial Routing | Checksum: aa1bb3ea
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 0
+Phase 4.1 Global Iteration 0 | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 4 Rip-up And Reroute | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 5 Delay and Skew Optimization
+Phase 5 Delay and Skew Optimization | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+Phase 6.1 Hold Fix Iter | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+Phase 6 Post Hold Fix | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0663007 %
+  Global Horizontal Routing Utilization  = 0.0248162 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Congestion Report
+North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions.
+
+------------------------------
+Reporting congestion hotspots
+------------------------------
+Direction: North
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: South
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: East
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+Direction: West
+----------------
+Congested clusters found at Level 0
+Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
+
+Phase 7 Route finalize | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1a2c45faa
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 156fe757f
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+61 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1765.430 ; gain = 43.164
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1775.246 ; gain = 9.816
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+Command: report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+Command: report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+Command: report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
+Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+73 Infos, 9 Warnings, 7 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file fixedPointTest_route_status.rpt -pb fixedPointTest_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
+INFO: [runtcl-4] Executing : report_incremental_reuse -file fixedPointTest_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:42:11 2022...
+
+*** Running vivado
+    with args -log fixedPointTest.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+
+
+
+****** Vivado v2021.2 (64-bit)
+  **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+source fixedPointTest.tcl -notrace
+Command: open_checkpoint fixedPointTest_routed.dcp
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1251.590 ; gain = 0.000
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1251.590 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2021.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Timing 38-478] Restoring timing data from binary archive.
+INFO: [Timing 38-479] Binary timing data restore complete.
+INFO: [Project 1-856] Restoring constraints from binary archive.
+INFO: [Project 1-853] Binary constraint restore complete.
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1387.207 ; gain = 17.668
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1387.207 ; gain = 17.668
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1387.207 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Project 1-604] Checkpoint was created with Vivado v2021.2 (64-bit) build 3367213
+open_checkpoint: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1387.207 ; gain = 135.617
+Command: write_bitstream -force fixedPointTest.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
+INFO: [DRC 23-27] Running DRC with 2 threads
+ERROR: [DRC NSTD-1] Unspecified I/O Standard: 43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], and c[8:-6].
+ERROR: [DRC UCIO-1] Unconstrained Logical Port: 43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: a[7:-6], b[7:-6], and c[8:-6].
+WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
+INFO: [Common 17-83] Releasing license: Implementation
+19 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered.
+write_bitstream failed
+ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
+
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:43:07 2022...
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.sh b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.sh
new file mode 100644
index 0000000..2fb2482
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/runme.sh
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin
+else
+  PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+# pre-commands:
+/bin/touch .write_bitstream.begin.rst
+EAStep vivado -log fixedPointTest.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado.jou b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado.jou
new file mode 100644
index 0000000..77fa8a1
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:42:39 2022
+# Process ID: 11092
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1
+# Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado.pb
new file mode 100644
index 0000000..b155e40
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record

\ No newline at end of file
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado_11388.backup.jou b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado_11388.backup.jou
new file mode 100644
index 0000000..cce670c
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado_11388.backup.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:31:34 2022
+# Process ID: 11388
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1
+# Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado_17108.backup.jou b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado_17108.backup.jou
new file mode 100644
index 0000000..7a763f9
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/vivado_17108.backup.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:41:22 2022
+# Process ID: 17108
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1
+# Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/write_bitstream.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000..9fbeb25
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/write_bitstream.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/.Vivado_Synthesis.queue.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/.vivado.begin.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000..bee7d51
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="8116" HostCore="12" HostMemory="016927088640">
+    </Process>
+</ProcessHandle>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/.vivado.end.rst b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/ISEWrap.js b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/ISEWrap.js
new file mode 100644
index 0000000..db0a510
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/ISEWrap.js
@@ -0,0 +1,269 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\" HostCore=\"" + ISEHOSTCORE +
+			    "\" HostMemory=\"" + ISEMEMTOTAL +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/ISEWrap.sh b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/ISEWrap.sh
new file mode 100644
index 0000000..c2fbbb6
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,84 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+cmd_exists()
+{
+  command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/__synthesis_is_complete__ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.dcp b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.dcp
new file mode 100644
index 0000000..f5088bd
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.dcp differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.tcl b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.tcl
new file mode 100644
index 0000000..9e87516
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.tcl
@@ -0,0 +1,135 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+namespace eval ::optrace {
+  variable script "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.tcl"
+  variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param checkpoint.writeSynthRtdsInDcp 1
+set_param chipscope.maxJobs 3
+set_param synth.incrementalSynthesisCache C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-13096-DESKTOP-PAACOM8/incrSyn
+set_msg_config -id {Synth 8-256} -limit 10000
+set_msg_config -id {Synth 8-638} -limit 10000
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7z010clg400-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt [current_project]
+set_property parent.project_path C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property board_part digilentinc.com:cora-z7-10:part0:1.1 [current_project]
+set_property ip_output_repo c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -vhdl2008 -library ieee_proposed {
+  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl
+  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl
+  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl
+  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl
+}
+read_vhdl -vhdl2008 -library xil_defaultlib C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc
+set_property used_in_implementation false [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+
+read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top fixedPointTest -part xc7z010clg400-1
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef fixedPointTest.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file fixedPointTest_utilization_synth.rpt -pb fixedPointTest_utilization_synth.pb"
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.vds b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.vds
new file mode 100644
index 0000000..9896cd8
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.vds
@@ -0,0 +1,236 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:37:49 2022
+# Process ID: 5756
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1
+# Command line: vivado.exe -log fixedPointTest.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fixedPointTest.tcl
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.vds
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
+create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.055 ; gain = 6.996
+Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top fixedPointTest -part xc7z010clg400-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 15968
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'fixedPointTest' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd:44]
+INFO: [Synth 8-256] done synthesizing module 'fixedPointTest' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd:44]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.055 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.055 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1261.055 ; gain = 0.000
+WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z010clg400-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input   15 Bit       Adders := 1     
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 80 (col length:40)
+BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |CARRY4 |     4|
+|2     |LUT1   |     1|
+|3     |LUT2   |    14|
+|4     |IBUF   |    28|
+|5     |OBUF   |    15|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1261.055 ; gain = 0.000
+Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.055 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1265.289 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete, checksum: 8d17ae10
+INFO: [Common 17-83] Releasing license: Synthesis
+20 Infos, 10 Warnings, 7 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1265.289 ; gain = 4.234
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_synth.rpt -pb fixedPointTest_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:38:30 2022...
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest_utilization_synth.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest_utilization_synth.pb
new file mode 100644
index 0000000..16e09b3
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest_utilization_synth.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest_utilization_synth.rpt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest_utilization_synth.rpt
new file mode 100644
index 0000000..2405260
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest_utilization_synth.rpt
@@ -0,0 +1,173 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+| Date         : Fri May 13 14:38:30 2022
+| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
+| Command      : report_utilization -file fixedPointTest_utilization_synth.rpt -pb fixedPointTest_utilization_synth.pb
+| Design       : fixedPointTest
+| Device       : xc7z010clg400-1
+| Speed File   : -1
+| Design State : Synthesized
+-----------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs*             |   14 |     0 |          0 |     17600 |  0.08 |
+|   LUT as Logic          |   14 |     0 |          0 |     17600 |  0.08 |
+|   LUT as Memory         |    0 |     0 |          0 |      6000 |  0.00 |
+| Slice Registers         |    0 |     0 |          0 |     35200 |  0.00 |
+|   Register as Flip Flop |    0 |     0 |          0 |     35200 |  0.00 |
+|   Register as Latch     |    0 |     0 |          0 |     35200 |  0.00 |
+| F7 Muxes                |    0 |     0 |          0 |      8800 |  0.00 |
+| F8 Muxes                |    0 |     0 |          0 |      4400 |  0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 0     |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile |    0 |     0 |          0 |        60 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |          0 |        60 |  0.00 |
+|   RAMB18       |    0 |     0 |          0 |       120 |  0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |        80 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   43 |     0 |          0 |       100 | 43.00 |
+| Bonded IPADs                |    0 |     0 |          0 |         2 |  0.00 |
+| Bonded IOPADs               |    0 |     0 |          0 |       130 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |         2 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |         2 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |         8 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |         8 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |          0 |         2 |  0.00 |
+| IBUFDS                      |    0 |     0 |          0 |        96 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |         8 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |         8 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       100 |  0.00 |
+| ILOGIC                      |    0 |     0 |          0 |       100 |  0.00 |
+| OLOGIC                      |    0 |     0 |          0 |       100 |  0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+|  Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL   |    0 |     0 |          0 |        32 |  0.00 |
+| BUFIO      |    0 |     0 |          0 |         8 |  0.00 |
+| MMCME2_ADV |    0 |     0 |          0 |         2 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |          0 |         2 |  0.00 |
+| BUFMRCE    |    0 |     0 |          0 |         4 |  0.00 |
+| BUFHCE     |    0 |     0 |          0 |        48 |  0.00 |
+| BUFR       |    0 |     0 |          0 |         8 |  0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| IBUF     |   28 |                  IO |
+| OBUF     |   15 |                  IO |
+| LUT2     |   14 |                 LUT |
+| CARRY4   |    4 |          CarryLogic |
+| LUT1     |    1 |                 LUT |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/gen_run.xml b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000..5ab0ffe
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/gen_run.xml
@@ -0,0 +1,96 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1652445466" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/fixedPointTest.dcp">
+  <File Type="PA-TCL" Name="fixedPointTest.tcl"/>
+  <File Type="RDS-PROPCONSTRS" Name="fixedPointTest_drc_synth.rpt"/>
+  <File Type="REPORTS-TCL" Name="fixedPointTest_reports.tcl"/>
+  <File Type="RDS-RDS" Name="fixedPointTest.vds"/>
+  <File Type="RDS-UTIL" Name="fixedPointTest_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="fixedPointTest_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="fixedPointTest.dcp"/>
+  <File Type="VDS-TIMINGSUMMARY" Name="fixedPointTest_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="fixedPointTest_timing_summary_synth.pb"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_float_types.vhdl">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="Library" Val="ieee_proposed"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_float_types.vhdl"/>
+        <Attr Name="ImportTime" Val="1652436395"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="Library" Val="ieee_proposed"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl"/>
+        <Attr Name="ImportTime" Val="1652436398"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="Library" Val="ieee_proposed"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl"/>
+        <Attr Name="ImportTime" Val="1652436400"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_pkg.vhdl">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="Library" Val="ieee_proposed"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_pkg.vhdl"/>
+        <Attr Name="ImportTime" Val="1652436402"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/new/fixedPointTest.vhd">
+      <FileInfo SFType="VHDL2008">
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="fixedPointTest"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc"/>
+        <Attr Name="ImportTime" Val="1648802911"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+    <Filter Type="Utils"/>
+    <File Path="$PSRCDIR/utils_1/imports/synth_1/fixedPointTest.dcp">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedInSteps" Val="synth_1"/>
+        <Attr Name="AutoDcp" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
+      <Desc>Vivado Synthesis Defaults</Desc>
+    </StratHandle>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/htr.txt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/htr.txt
new file mode 100644
index 0000000..3226c4b
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/htr.txt
@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log fixedPointTest.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fixedPointTest.tcl
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/rundef.js b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/rundef.js
new file mode 100644
index 0000000..72f6146
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/rundef.js
@@ -0,0 +1,36 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;";
+} else {
+  PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log fixedPointTest.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fixedPointTest.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.bat b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.bat
new file mode 100644
index 0000000..6c4f290
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.bat
@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.log
new file mode 100644
index 0000000..e8b0159
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.log
@@ -0,0 +1,235 @@
+
+*** Running vivado
+    with args -log fixedPointTest.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fixedPointTest.tcl
+
+
+
+****** Vivado v2021.2 (64-bit)
+  **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+
+source fixedPointTest.tcl -notrace
+create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.055 ; gain = 6.996
+Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top fixedPointTest -part xc7z010clg400-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
+INFO: [Device 21-403] Loading part xc7z010clg400-1
+WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 15968
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'fixedPointTest' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd:44]
+INFO: [Synth 8-256] done synthesizing module 'fixedPointTest' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd:44]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.055 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.055 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1261.055 ; gain = 0.000
+WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z010clg400-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input   15 Bit       Adders := 1     
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 80 (col length:40)
+BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |CARRY4 |     4|
+|2     |LUT1   |     1|
+|3     |LUT2   |    14|
+|4     |IBUF   |    28|
+|5     |OBUF   |    15|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1261.055 ; gain = 0.000
+Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 1261.055 ; gain = 0.000
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.055 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1265.289 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete, checksum: 8d17ae10
+INFO: [Common 17-83] Releasing license: Synthesis
+20 Infos, 10 Warnings, 7 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1265.289 ; gain = 4.234
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_synth.rpt -pb fixedPointTest_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:38:30 2022...
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.sh b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.sh
new file mode 100644
index 0000000..42b4704
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin
+else
+  PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log fixedPointTest.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fixedPointTest.tcl
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/vivado.jou b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/vivado.jou
new file mode 100644
index 0000000..7be783e
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/vivado.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Fri May 13 14:37:49 2022
+# Process ID: 5756
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1
+# Command line: vivado.exe -log fixedPointTest.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fixedPointTest.tcl
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.vds
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+source fixedPointTest.tcl -notrace
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/vivado.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/vivado.pb
new file mode 100644
index 0000000..a445fa2
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/vivado.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/compile.bat b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/compile.bat
new file mode 100644
index 0000000..b327de7
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/compile.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Fri May 13 14:28:30 +0200 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj fixedPointTest_db_vhdl.prj"
+call xvhdl  --incr --relax -prj fixedPointTest_db_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/compile.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/compile.log
new file mode 100644
index 0000000..b1caf8b
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/compile.log
@@ -0,0 +1,2 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sim_1/new/fixedPointTest_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'fixedPointTest_db'
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/elaborate.bat b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/elaborate.bat
new file mode 100644
index 0000000..68021ab
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/elaborate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Fri May 13 14:28:32 +0200 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip --snapshot fixedPointTest_db_behav xil_defaultlib.fixedPointTest_db -log elaborate.log"
+call xelab  --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip --snapshot fixedPointTest_db_behav xil_defaultlib.fixedPointTest_db -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/elaborate.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000..69b7ab8
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,19 @@
+Vivado Simulator v2021.2
+Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip --snapshot fixedPointTest_db_behav xil_defaultlib.fixedPointTest_db -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package ieee.fixed_float_types
+Compiling package ieee.fixed_pkg
+Compiling package ieee.math_real
+Compiling architecture behavioral of entity xil_defaultlib.fixedPointTest [fixedpointtest_default]
+Compiling architecture behavioral of entity xil_defaultlib.fixedpointtest_db
+Built simulation snapshot fixedPointTest_db_behav
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/fixedPointTest_db.tcl b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/fixedPointTest_db.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/fixedPointTest_db.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/fixedPointTest_db_behav.wdb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/fixedPointTest_db_behav.wdb
new file mode 100644
index 0000000..d38294b
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/fixedPointTest_db_behav.wdb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/simulate.bat b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/simulate.bat
new file mode 100644
index 0000000..fa7742a
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/simulate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2021.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Fri May 13 14:28:35 +0200 2022
+REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+REM
+REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim fixedPointTest_db_behav -key {Behavioral:sim_1:Functional:fixedPointTest_db} -tclbatch fixedPointTest_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest_db_behav.wcfg -log simulate.log"
+call xsim  fixedPointTest_db_behav -key {Behavioral:sim_1:Functional:fixedPointTest_db} -tclbatch fixedPointTest_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest_db_behav.wcfg -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/simulate.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000..3a14ee6
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xelab.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000..dfce976
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/Compile_Options.txt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/Compile_Options.txt
new file mode 100644
index 0000000..61dfbba
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "ieee_proposed" -L "secureip" --snapshot "fixedPointTest_db_behav" "xil_defaultlib.fixedPointTest_db" -log "elaborate.log" 
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/TempBreakPointFile.txt b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/obj/xsim_0.win64.obj b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..ba92a6e
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/obj/xsim_0.win64.obj differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/obj/xsim_1.c b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/obj/xsim_1.c
new file mode 100644
index 0000000..ce20ea8
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/obj/xsim_1.c
@@ -0,0 +1,107 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[2] = {(funcp)execute_44, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 2;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/fixedPointTest_db_behav/xsim.reloc",  (void **)funcTab, 2);
+	iki_vhdl_file_variable_register(dp + 2304);
+	iki_vhdl_file_variable_register(dp + 2360);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/fixedPointTest_db_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/fixedPointTest_db_behav/xsim.reloc");
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/fixedPointTest_db_behav/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/fixedPointTest_db_behav/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/fixedPointTest_db_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/obj/xsim_1.win64.obj b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..6dd2694
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.dbg b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.dbg
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index 0000000..f66b786
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.mem b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.mem
new file mode 100644
index 0000000..cada92d
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.reloc b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.reloc
new file mode 100644
index 0000000..b831a9d
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.rlx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.rlx
new file mode 100644
index 0000000..9b1233b
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  8255003257521880315  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip --snapshot fixedPointTest_db_behav xil_defaultlib.fixedPointTest_db" , 
+    buildDate : "Oct 19 2021" , 
+    buildTime : "03:16:22" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/fixedPointTest_db_behav/xsimk.exe\"   \"xsim.dir/fixedPointTest_db_behav/obj/xsim_0.win64.obj\" \"xsim.dir/fixedPointTest_db_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.rtti b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.rtti
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.svtype b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.svtype
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.type b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.type
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.xdbg b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsim.xdbg
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index 0000000..11f311b
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimSettings.ini b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimSettings.ini
new file mode 100644
index 0000000..7922b03
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=157
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=156
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimcrash.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimk.exe b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimk.exe
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index 0000000..45978be
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimkernel.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimkernel.log
new file mode 100644
index 0000000..cf6e0f3
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/fixedPointTest_db_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/fixedPointTest_db_behav/xsimk.exe -simmode gui -wdb fixedPointTest_db_behav.wdb -simrunnum 0 -socket 50146
+Design successfully loaded
+Design Loading Memory Usage: 7264 KB (Peak: 7264 KB)
+Design Loading CPU Usage: 0 ms
+Simulation completed
+Simulation Memory Usage: 7760 KB (Peak: 7760 KB)
+Simulation CPU Usage: 15 ms
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/ieee_proposed_2008/fixed_float_types.vdb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/ieee_proposed_2008/fixed_float_types.vdb
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/ieee_proposed_2008/fixed_pkg.vdb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/ieee_proposed_2008/fixed_pkg.vdb
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/ieee_proposed_2008/ieee_proposed.rlx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/ieee_proposed_2008/ieee_proposed.rlx
new file mode 100644
index 0000000..3328a2f
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/ieee_proposed_2008/ieee_proposed.rlx
@@ -0,0 +1,8 @@
+0.7
+2020.2
+Oct 19 2021
+03:16:22
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl,1652436395,vhdl2008,,,,fixed_float_types,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl,1652436400,vhdl2008,,,,,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl,1652436398,vhdl2008,C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl,,,fixed_generic_pkg,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl,1652436402,vhdl2008,C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sim_1/new/fixedPointTest_db.vhd,,,fixed_pkg,,,,,,,,
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fixedpointtest.vdb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fixedpointtest.vdb
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index 0000000..2a9869c
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fixedpointtest_db.vdb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fixedpointtest_db.vdb
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index 0000000..356736e
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..e86f064
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,6 @@
+0.7
+2020.2
+Oct 19 2021
+03:16:22
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sim_1/new/fixedPointTest_db.vhd,1652443777,vhdl2008,,,,fixedpointtest_db,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd,1652443777,vhdl2008,,,,fixedpointtest,,,,,,,,
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.ini b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..f98f5c5
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1,2 @@
+ieee_proposed=xsim.dir/ieee_proposed
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xvhdl.log b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000..b1caf8b
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,2 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sim_1/new/fixedPointTest_db.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'fixedPointTest_db'
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xvhdl.pb b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000..21ae3f5
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diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc
new file mode 100644
index 0000000..c67066e
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc
@@ -0,0 +1,154 @@
+## This file is a general .xdc for the Cora Z7-10 Rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## PL System Clock
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
+
+## RGB LEDs
+set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
+set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g
+set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
+#set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports led]
+set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_0_35 Sch=led1_b
+set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g
+set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r
+
+## Buttons
+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1]
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L17P_T2_34 Sch=ja_p[1]
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L17N_T2_34 Sch=ja_n[1]
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L7P_T1_34 Sch=ja_p[2]
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L7N_T1_34 Sch=ja_n[2]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4]
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4]
+
+## Pmod Header JB
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
+
+## Crypto SDA
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }];
+
+## Dedicated Analog Inputs
+#set_property -dict { PACKAGE_PIN K9    IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p
+#set_property -dict { PACKAGE_PIN L10   IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n
+
+## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
+## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
+## ChipKit Outer Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using these ports as digital I/O.
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L10N_T1_AD11N_35 Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L12P_T1_MRCC_35 Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L6P_T0_34 Sch=ck_a[5]
+
+## ChipKit Inner Analog Header - as Differential Analog Inputs
+## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
+## WARNING: Do not use both sets of constraints at the same time!
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
+## ChipKit Inner Analog Header - as Digital I/O
+## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
+
+## ChipKit Outer Digital Header
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L5P_T0_34 Sch=ck_io[2]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L5N_T0_34 Sch=ck_io[3]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L21P_T3_DQS_34 Sch=ck_io[4]
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L21N_T3_DQS_34 Sch=ck_io[5]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19N_T3_VREF_34 Sch=ck_io[6]
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L19N_T3_VREF_35 Sch=ck_io[13]
+
+## ChipKit Inner Digital Header
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19P_T3_34 Sch=ck_io[26]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L2N_T0_34 Sch=ck_io[27]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[28]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L10P_T1_34 Sch=ck_io[29]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L9P_T1_DQS_34 Sch=ck_io[30]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L9N_T1_DQS_34 Sch=ck_io[31]
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L20P_T3_34 Sch=ck_io[32]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_34 Sch=ck_io[33]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L23N_T3_34 Sch=ck_io[34]
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L23P_T3_34 Sch=ck_io[35]
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_AD10P_35 Sch=ck_io[36]
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L11N_T1_SRCC_35 Sch=ck_io[37]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L13N_T2_MRCC_35 Sch=ck_io[38]
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=ck_io[39]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_35 Sch=ck_io[40]
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9N_T1_DQS_AD3N_35 Sch=ck_io[41]
+
+## ChipKit SPI
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss
+
+## ChipKit I2C
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda
+
+##Misc. ChipKit signals
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L7N_T1_AD2N_35 Sch=ck_ioa
+
+## User Digital I/O Header J1
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[1] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=user_dio[1]
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[2] }]; #IO_L7P_T1_AD2P_35 Sch=user_dio[2]
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[3] }]; #IO_L14P_T2_SRCC_34 Sch=user_dio[3]
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[4] }]; #IO_L14N_T2_SRCC_34 Sch=user_dio[4]
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[5] }]; #IO_L13N_T2_MRCC_34 Sch=user_dio[5]
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[6] }]; #IO_0_34 Sch=user_dio[6]
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[7] }]; #IO_L15P_T2_DQS_34 Sch=user_dio[7]
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[8] }]; #IO_25_34 Sch=user_dio[8]
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[9] }]; #IO_L15N_T2_DQS_34 Sch=user_dio[9]
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[10] }]; #IO_L16P_T2_34 Sch=user_dio[10]
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { user_dio[11] }]; #IO_L16N_T2_34 Sch=user_dio[11]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { user_dio[12] }]; #IO_L10P_T1_AD11P_35 Sch=user_dio[12]
+
+
+
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sim_1/new/fixedPointTest_db.vhd b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sim_1/new/fixedPointTest_db.vhd
new file mode 100644
index 0000000..506f841
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sim_1/new/fixedPointTest_db.vhd
@@ -0,0 +1,73 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 13.05.2022 14:05:03
+-- Design Name: 
+-- Module Name: fixedPointTest_db - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library ieee_proposed;
+use ieee_proposed.fixed_pkg.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fixedPointTest_db is
+--  Port ( );
+end fixedPointTest_db;
+
+architecture Behavioral of fixedPointTest_db is
+
+component fixedPointTest is
+    Port ( a : in sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen
+           b : in sfixed (7 downto -6);
+           c : out sfixed (8 downto -6));
+end component;
+
+--wendetangenten test
+signal a : sfixed(7 downto -6) := to_sfixed (-3.125, 7, -6);
+signal b : sfixed(7 downto -6) := to_sfixed (5.1111, 7, -6);
+signal c : sfixed(8 downto -6);
+
+
+
+
+begin
+
+uutFixedPointTest: fixedPointTest PORT MAP(
+    a => a,
+    b => b,
+    c => c
+);
+
+process
+begin
+
+
+
+
+end process;
+
+end Behavioral;
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl
new file mode 100644
index 0000000..6ad3e37
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl
@@ -0,0 +1,61 @@
+-- -----------------------------------------------------------------
+-- 
+-- Copyright 2019 IEEE P1076 WG Authors
+-- 
+-- See the LICENSE file distributed with this work for copyright and
+-- licensing information and the AUTHORS file.
+-- 
+-- This file to you under the Apache License, Version 2.0 (the "License").
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+-- implied.  See the License for the specific language governing
+-- permissions and limitations under the License.
+--
+--   Title      :  Fixed Point and Floating Point types package
+--
+--   Library   :  This package shall be compiled into a library
+--                symbolically named IEEE.
+--
+--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
+--
+--   Purpose   :  Definitions for use in fixed point and floating point
+--                arithmetic packages
+--
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+package fixed_float_types is
+
+  -- Types used for generics of fixed_generic_pkg
+
+  type fixed_round_style_type is (fixed_round, fixed_truncate);
+
+  type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
+
+  -- Type used for generics of float_generic_pkg
+
+  -- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
+  -- and FE_TOWARDZERO floating point rounding macros.
+
+  type round_type is (round_nearest,    -- Default, nearest LSB '0'
+                      round_inf,        -- Round toward positive infinity
+                      round_neginf,     -- Round toward negative infinity
+                      round_zero);      -- Round toward zero (truncate)
+
+end package fixed_float_types;
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl
new file mode 100644
index 0000000..b23f908
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl
@@ -0,0 +1,6360 @@
+-- -----------------------------------------------------------------
+-- 
+-- Copyright 2019 IEEE P1076 WG Authors
+-- 
+-- See the LICENSE file distributed with this work for copyright and
+-- licensing information and the AUTHORS file.
+-- 
+-- This file to you under the Apache License, Version 2.0 (the "License").
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+-- implied.  See the License for the specific language governing
+-- permissions and limitations under the License.
+--
+--   Title     :  Fixed-point package (Generic package body)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This packages defines basic binary fixed point arithmetic
+--             :  arithmetic functions
+--             :
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+package body fixed_generic_pkg is
+  -- Author David Bishop (dbishop@vhdl.org)
+  -- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
+  -- null array constants
+  constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
+  constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
+  constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
+
+  -- This differed constant will tell you if the package body is synthesizable
+  -- or implemented as real numbers, set to "true" if synthesizable.
+  constant fixedsynth_or_real : BOOLEAN := true;
+
+  -- Special version of "minimum" to do some boundary checking without errors
+  function mins (l, r : INTEGER)
+    return INTEGER is
+  begin  -- function mins
+    if (l = INTEGER'low or r = INTEGER'low) then
+      return 0;                         -- error condition, silent
+    end if;
+    return minimum (l, r);
+  end function mins;
+
+  -- Special version of "minimum" to do some boundary checking with errors
+  function mine (l, r : INTEGER)
+    return INTEGER is
+  begin  -- function mine
+    if (l = INTEGER'low or r = INTEGER'low) then
+      report fixed_generic_pkg'instance_name
+        & " Unbounded number passed, was a literal used?"
+        severity error;
+      return 0;
+    end if;
+    return minimum (l, r);
+  end function mine;
+
+  -- The following functions are used only internally.  Every function
+  -- calls "cleanvec" either directly or indirectly.
+  -- purpose: Fixes "downto" problem and resolves meta states
+  function cleanvec (
+    arg : UNRESOLVED_sfixed)            -- input
+    return UNRESOLVED_sfixed
+  is
+  begin  -- function cleanvec
+    assert not (arg'ascending and (arg'low /= INTEGER'low))
+      report fixed_generic_pkg'instance_name
+      & " Vector passed using a ""to"" range, expected is ""downto"""
+      severity error;
+    return arg;
+  end function cleanvec;
+
+  -- purpose: Fixes "downto" problem and resolves meta states
+  function cleanvec (
+    arg : UNRESOLVED_ufixed)            -- input
+    return UNRESOLVED_ufixed
+  is
+  begin  -- function cleanvec
+    assert not (arg'ascending and (arg'low /= INTEGER'low))
+      report fixed_generic_pkg'instance_name
+      & " Vector passed using a ""to"" range, expected is ""downto"""
+      severity error;
+    return arg;
+  end function cleanvec;
+
+  -- Type convert a "unsigned" into a "ufixed", used internally
+  function to_fixed (
+    arg                  : UNRESOLVED_UNSIGNED;  -- shifted vector
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (left_index downto right_index);
+  begin  -- function to_fixed
+    result := UNRESOLVED_ufixed(arg);
+    return result;
+  end function to_fixed;
+
+  -- Type convert a "signed" into an "sfixed", used internally
+  function to_fixed (
+    arg                  : UNRESOLVED_SIGNED;  -- shifted vector
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (left_index downto right_index);
+  begin  -- function to_fixed
+    result := UNRESOLVED_sfixed(arg);
+    return result;
+  end function to_fixed;
+
+  -- Type convert a "ufixed" into an "unsigned", used internally
+  function to_uns (
+    arg : UNRESOLVED_ufixed)            -- fp vector
+    return UNRESOLVED_UNSIGNED
+  is
+    subtype t is UNRESOLVED_UNSIGNED(arg'high - arg'low downto 0);
+    variable slv : t;
+  begin  -- function to_uns
+    slv := t(arg);
+    return slv;
+  end function to_uns;
+
+  -- Type convert an "sfixed" into a "signed", used internally
+  function to_s (
+    arg : UNRESOLVED_sfixed)            -- fp vector
+    return UNRESOLVED_SIGNED
+  is
+    subtype t is UNRESOLVED_SIGNED(arg'high - arg'low downto 0);
+    variable slv : t;
+  begin  -- function to_s
+    slv := t(arg);
+    return slv;
+  end function to_s;
+
+  -- adds 1 to the LSB of the number
+  procedure round_up (arg       : in  UNRESOLVED_ufixed;
+                      result    : out UNRESOLVED_ufixed;
+                      overflowx : out BOOLEAN) is
+    variable arguns, resuns : UNRESOLVED_UNSIGNED (arg'high-arg'low+1 downto 0)
+      := (others => '0');
+  begin  -- round_up
+    arguns (arguns'high-1 downto 0) := to_uns (arg);
+    resuns                          := arguns + 1;
+    result := to_fixed(resuns(arg'high-arg'low
+                              downto 0), arg'high, arg'low);
+    overflowx := (resuns(resuns'high) = '1');
+  end procedure round_up;
+
+  -- adds 1 to the LSB of the number
+  procedure round_up (arg       : in  UNRESOLVED_sfixed;
+                      result    : out UNRESOLVED_sfixed;
+                      overflowx : out BOOLEAN) is
+    variable args, ress : UNRESOLVED_SIGNED (arg'high-arg'low+1 downto 0);
+  begin  -- round_up
+    args (args'high-1 downto 0) := to_s (arg);
+    args(args'high)             := arg(arg'high);  -- sign extend
+    ress                        := args + 1;
+    result := to_fixed(ress (ress'high-1
+                             downto 0), arg'high, arg'low);
+    overflowx := ((arg(arg'high) /= ress(ress'high-1))
+                  and (or (STD_ULOGIC_VECTOR(ress)) /= '0'));
+  end procedure round_up;
+
+  -- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
+  -- when the remainder is > 0.5.  If the remainder IS 0.5 then if the
+  -- bottom bit is a "1" it is rounded, otherwise it remains the same.
+  function round_fixed (arg            : UNRESOLVED_ufixed;
+                        remainder      : UNRESOLVED_ufixed;
+                        overflow_style : fixed_overflow_style_type := fixed_overflow_style)
+    return UNRESOLVED_ufixed
+  is
+    variable rounds         : BOOLEAN;
+    variable round_overflow : BOOLEAN;
+    variable result         : UNRESOLVED_ufixed (arg'range);
+  begin
+    rounds := false;
+    if (remainder'length > 1) then
+      if (remainder (remainder'high) = '1') then
+        rounds := (arg(arg'low) = '1')
+                  or (or (to_sulv(remainder(remainder'high-1 downto
+                                           remainder'low))) = '1');
+      end if;
+    else
+      rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
+    end if;
+    if rounds then
+      round_up(arg       => arg,
+               result    => result,
+               overflowx => round_overflow);
+    else
+      result := arg;
+    end if;
+    if (overflow_style = fixed_saturate) and round_overflow then
+      result := saturate (result'high, result'low);
+    end if;
+    return result;
+  end function round_fixed;
+
+  -- Rounding case statement
+  function round_fixed (arg            : UNRESOLVED_sfixed;
+                        remainder      : UNRESOLVED_sfixed;
+                        overflow_style : fixed_overflow_style_type := fixed_overflow_style)
+    return UNRESOLVED_sfixed
+  is
+    variable rounds         : BOOLEAN;
+    variable round_overflow : BOOLEAN;
+    variable result         : UNRESOLVED_sfixed (arg'range);
+  begin
+    rounds := false;
+    if (remainder'length > 1) then
+      if (remainder (remainder'high) = '1') then
+        rounds := (arg(arg'low) = '1')
+                  or (or (to_sulv(remainder(remainder'high-1 downto
+                                           remainder'low))) = '1');
+      end if;
+    else
+      rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
+    end if;
+    if rounds then
+      round_up(arg       => arg,
+               result    => result,
+               overflowx => round_overflow);
+    else
+      result := arg;
+    end if;
+    if round_overflow then
+      if (overflow_style = fixed_saturate) then
+        if arg(arg'high) = '0' then
+          result := saturate (result'high, result'low);
+        else
+          result := not saturate (result'high, result'low);
+        end if;
+        -- Sign bit not fixed when wrapping
+      end if;
+    end if;
+    return result;
+  end function round_fixed;
+
+  -- converts an sfixed into a ufixed.  The output is the same length as the
+  -- input, because abs("1000") = "1000" = 8.
+  function to_ufixed (
+    arg : UNRESOLVED_sfixed)
+    return UNRESOLVED_ufixed
+  is
+    constant left_index  : INTEGER := arg'high;
+    constant right_index : INTEGER := mine(arg'low, arg'low);
+    variable xarg        : UNRESOLVED_sfixed(left_index+1 downto right_index);
+    variable result      : UNRESOLVED_ufixed(left_index downto right_index);
+  begin
+    if arg'length < 1 then
+      return NAUF;
+    end if;
+    xarg   := abs(arg);
+    result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
+    return result;
+  end function to_ufixed;
+
+-----------------------------------------------------------------------------
+-- Visible functions
+-----------------------------------------------------------------------------
+  -- Conversion functions.  These are needed for synthesis where typically
+  -- the only input and output type is a std_logic_vector.
+  function to_sulv (
+    arg : UNRESOLVED_ufixed)            -- fixed point vector
+    return STD_ULOGIC_VECTOR
+  is
+    variable intermediate_result : UNRESOLVED_ufixed(arg'length-1 downto 0);
+  begin
+    if arg'length < 1 then
+      return NSLV;
+    end if;
+    intermediate_result := arg;
+    return STD_ULOGIC_VECTOR (intermediate_result);
+  end function to_sulv;
+
+  function to_sulv (
+    arg : UNRESOLVED_sfixed)            -- fixed point vector
+    return STD_ULOGIC_VECTOR
+  is
+    variable intermediate_result : UNRESOLVED_sfixed(arg'length-1 downto 0);
+  begin
+    if arg'length < 1 then
+      return NSLV;
+    end if;
+    intermediate_result := arg;
+    return STD_ULOGIC_VECTOR (intermediate_result);
+  end function to_sulv;
+
+  function to_slv (
+    arg : UNRESOLVED_ufixed)            -- fixed point vector
+    return STD_LOGIC_VECTOR is
+  begin
+    return to_sulv(arg);
+  end function to_slv;
+
+  function to_slv (
+    arg : UNRESOLVED_sfixed)            -- fixed point vector
+    return STD_LOGIC_VECTOR is
+  begin
+    return to_sulv(arg);
+  end function to_slv;
+
+  function to_ufixed (
+    arg                  : STD_ULOGIC_VECTOR;  -- shifted vector
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (left_index downto right_index);
+  begin
+    if (arg'length < 1 or right_index > left_index) then
+      return NAUF;
+    end if;
+    if (arg'length /= result'length) then
+      report fixed_generic_pkg'instance_name & "TO_UFIXED(SLV) "
+        & "Vector lengths do not match.  Input length is "
+        & INTEGER'image(arg'length) & " and output will be "
+        & INTEGER'image(result'length) & " wide."
+        severity error;
+      return NAUF;
+    else
+      result := to_fixed (arg         => UNRESOLVED_UNSIGNED(arg),
+                          left_index  => left_index,
+                          right_index => right_index);
+      return result;
+    end if;
+  end function to_ufixed;
+
+  function to_sfixed (
+    arg                  : STD_ULOGIC_VECTOR;  -- shifted vector
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (left_index downto right_index);
+  begin
+    if (arg'length < 1 or right_index > left_index) then
+      return NASF;
+    end if;
+    if (arg'length /= result'length) then
+      report fixed_generic_pkg'instance_name & "TO_SFIXED(SLV) "
+        & "Vector lengths do not match.  Input length is "
+        & INTEGER'image(arg'length) & " and output will be "
+        & INTEGER'image(result'length) & " wide."
+        severity error;
+      return NASF;
+    else
+      result := to_fixed (arg         => UNRESOLVED_SIGNED(arg),
+                          left_index  => left_index,
+                          right_index => right_index);
+      return result;
+    end if;
+  end function to_sfixed;
+
+  -- Two's complement number, Grows the vector by 1 bit.
+  -- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
+  function "abs" (
+    arg : UNRESOLVED_sfixed)            -- fixed point input
+    return UNRESOLVED_sfixed
+  is
+    constant left_index  : INTEGER := arg'high;
+    constant right_index : INTEGER := mine(arg'low, arg'low);
+    variable ressns      : UNRESOLVED_SIGNED (arg'length downto 0);
+    variable result      : UNRESOLVED_sfixed (left_index+1 downto right_index);
+  begin
+    if (arg'length < 1 or result'length < 1) then
+      return NASF;
+    end if;
+    ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
+    ressns (arg'length)            := ressns (arg'length-1);  -- expand sign bit
+    result                         := to_fixed (abs(ressns), left_index+1, right_index);
+    return result;
+  end function "abs";
+
+  -- also grows the vector by 1 bit.
+  function "-" (
+    arg : UNRESOLVED_sfixed)            -- fixed point input
+    return UNRESOLVED_sfixed
+  is
+    constant left_index  : INTEGER := arg'high+1;
+    constant right_index : INTEGER := mine(arg'low, arg'low);
+    variable ressns      : UNRESOLVED_SIGNED (arg'length downto 0);
+    variable result      : UNRESOLVED_sfixed (left_index downto right_index);
+  begin
+    if (arg'length < 1 or result'length < 1) then
+      return NASF;
+    end if;
+    ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
+    ressns (arg'length)            := ressns (arg'length-1);  -- expand sign bit
+    result                         := to_fixed (-ressns, left_index, right_index);
+    return result;
+  end function "-";
+
+  -- Addition
+  function "+" (
+    l, r : UNRESOLVED_ufixed)    -- ufixed(a downto b) + ufixed(c downto d) =
+    return UNRESOLVED_ufixed     -- ufixed(max(a,c)+1 downto min(b,d))
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high)+1;
+    constant right_index      : INTEGER := mine(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable result           : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
+                                               downto 0);
+    variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
+                                               downto 0);
+  begin
+    if (l'length < 1 or r'length < 1 or result'length < 1) then
+      return NAUF;
+    end if;
+    lresize    := resize (l, left_index, right_index);
+    rresize    := resize (r, left_index, right_index);
+    lslv       := to_uns (lresize);
+    rslv       := to_uns (rresize);
+    result_slv := lslv + rslv;
+    result     := to_fixed(result_slv, left_index, right_index);
+    return result;
+  end function "+";
+
+  function "+" (
+    l, r : UNRESOLVED_sfixed)    -- sfixed(a downto b) + sfixed(c downto d) =
+    return UNRESOLVED_sfixed     -- sfixed(max(a,c)+1 downto min(b,d))
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high)+1;
+    constant right_index      : INTEGER := mine(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable result           : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (left_index-right_index downto 0);
+    variable result_slv       : UNRESOLVED_SIGNED (left_index-right_index downto 0);
+  begin
+    if (l'length < 1 or r'length < 1 or result'length < 1) then
+      return NASF;
+    end if;
+    lresize    := resize (l, left_index, right_index);
+    rresize    := resize (r, left_index, right_index);
+    lslv       := to_s (lresize);
+    rslv       := to_s (rresize);
+    result_slv := lslv + rslv;
+    result     := to_fixed(result_slv, left_index, right_index);
+    return result;
+  end function "+";
+
+  -- Subtraction
+  function "-" (
+    l, r : UNRESOLVED_ufixed)    -- ufixed(a downto b) - ufixed(c downto d) =
+    return UNRESOLVED_ufixed     -- ufixed(max(a,c)+1 downto min(b,d))
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high)+1;
+    constant right_index      : INTEGER := mine(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable result           : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
+                                               downto 0);
+    variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
+                                               downto 0);
+  begin
+    if (l'length < 1 or r'length < 1 or result'length < 1) then
+      return NAUF;
+    end if;
+    lresize    := resize (l, left_index, right_index);
+    rresize    := resize (r, left_index, right_index);
+    lslv       := to_uns (lresize);
+    rslv       := to_uns (rresize);
+    result_slv := lslv - rslv;
+    result     := to_fixed(result_slv, left_index, right_index);
+    return result;
+  end function "-";
+
+  function "-" (
+    l, r : UNRESOLVED_sfixed)    -- sfixed(a downto b) - sfixed(c downto d) =
+    return UNRESOLVED_sfixed     -- sfixed(max(a,c)+1 downto min(b,d))
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high)+1;
+    constant right_index      : INTEGER := mine(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable result           : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (left_index-right_index downto 0);
+    variable result_slv       : UNRESOLVED_SIGNED (left_index-right_index downto 0);
+  begin
+    if (l'length < 1 or r'length < 1 or result'length < 1) then
+      return NASF;
+    end if;
+    lresize    := resize (l, left_index, right_index);
+    rresize    := resize (r, left_index, right_index);
+    lslv       := to_s (lresize);
+    rslv       := to_s (rresize);
+    result_slv := lslv - rslv;
+    result     := to_fixed(result_slv, left_index, right_index);
+    return result;
+  end function "-";
+
+  function "*" (
+    l, r : UNRESOLVED_ufixed)    -- ufixed(a downto b) * ufixed(c downto d) =
+    return UNRESOLVED_ufixed     -- ufixed(a+c+1 downto b+d)
+  is
+    variable lslv       : UNRESOLVED_UNSIGNED (l'length-1 downto 0);
+    variable rslv       : UNRESOLVED_UNSIGNED (r'length-1 downto 0);
+    variable result_slv : UNRESOLVED_UNSIGNED (r'length+l'length-1 downto 0);
+    variable result     : UNRESOLVED_ufixed (l'high + r'high+1 downto
+                                             mine(l'low, l'low) + mine(r'low, r'low));
+  begin
+    if (l'length < 1 or r'length < 1 or
+        result'length /= result_slv'length) then
+      return NAUF;
+    end if;
+    lslv       := to_uns (cleanvec(l));
+    rslv       := to_uns (cleanvec(r));
+    result_slv := lslv * rslv;
+    result     := to_fixed (result_slv, result'high, result'low);
+    return result;
+  end function "*";
+
+  function "*" (
+    l, r : UNRESOLVED_sfixed)    -- sfixed(a downto b) * sfixed(c downto d) =
+    return UNRESOLVED_sfixed     -- sfixed(a+c+1 downto b+d)
+  is
+    variable lslv       : UNRESOLVED_SIGNED (l'length-1 downto 0);
+    variable rslv       : UNRESOLVED_SIGNED (r'length-1 downto 0);
+    variable result_slv : UNRESOLVED_SIGNED (r'length+l'length-1 downto 0);
+    variable result     : UNRESOLVED_sfixed (l'high + r'high+1 downto
+                                             mine(l'low, l'low) + mine(r'low, r'low));
+  begin
+    if (l'length < 1 or r'length < 1 or
+        result'length /= result_slv'length) then
+      return NASF;
+    end if;
+    lslv       := to_s (cleanvec(l));
+    rslv       := to_s (cleanvec(r));
+    result_slv := lslv * rslv;
+    result     := to_fixed (result_slv, result'high, result'low);
+    return result;
+  end function "*";
+
+  function "/" (
+    l, r : UNRESOLVED_ufixed)    -- ufixed(a downto b) / ufixed(c downto d) =
+    return UNRESOLVED_ufixed is         --  ufixed(a-d downto b-c-1)
+  begin
+    return divide (l, r);
+  end function "/";
+
+  function "/" (
+    l, r : UNRESOLVED_sfixed)    -- sfixed(a downto b) / sfixed(c downto d) =
+    return UNRESOLVED_sfixed is         -- sfixed(a-d+1 downto b-c)
+  begin
+    return divide (l, r);
+  end function "/";
+
+  -- This version of divide gives the user more control
+  -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
+  function divide (
+    l, r                 : UNRESOLVED_ufixed;
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_ufixed
+  is
+    variable result     : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
+                                         mine (l'low, l'low) - r'high -1);
+    variable dresult    : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
+    variable lresize    : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
+    variable lslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+    variable rslv       : UNRESOLVED_UNSIGNED (r'length-1 downto 0);
+    variable result_slv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1 or
+        mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+      return NAUF;
+    end if;
+    lresize := resize (arg            => l,
+                       left_index     => lresize'high,
+                       right_index    => lresize'low,
+                       overflow_style => fixed_wrap,   -- vector only grows
+                       round_style    => fixed_truncate);
+    lslv := to_uns (cleanvec (lresize));
+    rslv := to_uns (cleanvec (r));
+    if (rslv = 0) then
+      report fixed_generic_pkg'instance_name
+        & "DIVIDE(ufixed) Division by zero" severity error;
+      result := saturate (result'high, result'low);    -- saturate
+    else
+      result_slv := lslv / rslv;
+      dresult    := to_fixed (result_slv, dresult'high, dresult'low);
+      result := resize (arg            => dresult,
+                        left_index     => result'high,
+                        right_index    => result'low,
+                        overflow_style => fixed_wrap,  -- overflow impossible
+                        round_style    => round_style);
+    end if;
+    return result;
+  end function divide;
+
+  -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
+  function divide (
+    l, r                 : UNRESOLVED_sfixed;
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_sfixed
+  is
+    variable result     : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
+                                             mine (l'low, l'low) - r'high);
+    variable dresult    : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
+    variable lresize    : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
+    variable lslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+    variable rslv       : UNRESOLVED_SIGNED (r'length-1 downto 0);
+    variable result_slv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1 or
+        mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+      return NASF;
+    end if;
+    lresize := resize (arg            => l,
+                       left_index     => lresize'high,
+                       right_index    => lresize'low,
+                       overflow_style => fixed_wrap,   -- vector only grows
+                       round_style    => fixed_truncate);
+    lslv := to_s (cleanvec (lresize));
+    rslv := to_s (cleanvec (r));
+    if (rslv = 0) then
+      report fixed_generic_pkg'instance_name
+        & "DIVIDE(sfixed) Division by zero" severity error;
+      result := saturate (result'high, result'low);
+    else
+      result_slv := lslv / rslv;
+      dresult    := to_fixed (result_slv, dresult'high, dresult'low);
+      result := resize (arg            => dresult,
+                        left_index     => result'high,
+                        right_index    => result'low,
+                        overflow_style => fixed_wrap,  -- overflow impossible
+                        round_style    => round_style);
+    end if;
+    return result;
+  end function divide;
+
+  -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
+  function reciprocal (
+    arg                  : UNRESOLVED_ufixed;  -- fixed point input
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_ufixed
+  is
+    constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
+  begin
+    return divide (l           => one,
+                   r           => arg,
+                   round_style => round_style,
+                   guard_bits  => guard_bits);
+  end function reciprocal;
+
+  -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
+  function reciprocal (
+    arg                  : UNRESOLVED_sfixed;              -- fixed point input
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_sfixed
+  is
+    constant one     : UNRESOLVED_sfixed (1 downto 0) := "01";  -- extra bit.
+    variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
+  begin
+    if (arg'length < 1 or resultx'length < 1) then
+      return NASF;
+    else
+      resultx := divide (l           => one,
+                         r           => arg,
+                         round_style => round_style,
+                         guard_bits  => guard_bits);
+      return resultx (resultx'high-1 downto resultx'low);  -- remove extra bit
+    end if;
+  end function reciprocal;
+
+  -- ufixed (a downto b) rem ufixed (c downto d)
+  --        = ufixed (min(a,c) downto min(b,d))
+  function "rem" (
+    l, r : UNRESOLVED_ufixed)           -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return remainder (l, r);
+  end function "rem";
+
+  -- remainder
+  -- sfixed (a downto b) rem sfixed (c downto d)
+  --        = sfixed (min(a,c) downto min(b,d))
+  function "rem" (
+    l, r : UNRESOLVED_sfixed)           -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return remainder (l, r);
+  end function "rem";
+
+  -- ufixed (a downto b) rem ufixed (c downto d)
+  --        = ufixed (min(a,c) downto min(b,d))
+  function remainder (
+    l, r                 : UNRESOLVED_ufixed;            -- fixed point input
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_ufixed
+  is
+    variable result     : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
+                                             mine(l'low, r'low));
+    variable lresize    : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
+                                             mins(r'low, r'low)-guard_bits);
+    variable rresize    : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
+    variable dresult    : UNRESOLVED_ufixed (rresize'range);
+    variable lslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+    variable rslv       : UNRESOLVED_UNSIGNED (rresize'length-1 downto 0);
+    variable result_slv : UNRESOLVED_UNSIGNED (rslv'range);
+  begin
+    if (l'length < 1 or r'length < 1 or
+        mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+      return NAUF;
+    end if;
+    lresize := resize (arg            => l,
+                       left_index     => lresize'high,
+                       right_index    => lresize'low,
+                       overflow_style => fixed_wrap,     -- vector only grows
+                       round_style    => fixed_truncate);
+    lslv := to_uns (lresize);
+    rresize := resize (arg            => r,
+                       left_index     => rresize'high,
+                       right_index    => rresize'low,
+                       overflow_style => fixed_wrap,     -- vector only grows
+                       round_style    => fixed_truncate);
+    rslv := to_uns (rresize);
+    if (rslv = 0) then
+      report fixed_generic_pkg'instance_name
+        & "remainder(ufixed) Division by zero" severity error;
+      result := saturate (result'high, result'low);      -- saturate
+    else
+      if (r'low <= l'high) then
+        result_slv := lslv rem rslv;
+        dresult    := to_fixed (result_slv, dresult'high, dresult'low);
+        result := resize (arg            => dresult,
+                          left_index     => result'high,
+                          right_index    => result'low,
+                          overflow_style => fixed_wrap,  -- can't overflow
+                          round_style    => round_style);
+      end if;
+      if l'low < r'low then
+        result(mins(r'low-1, l'high) downto l'low) :=
+          cleanvec(l(mins(r'low-1, l'high) downto l'low));
+      end if;
+    end if;
+    return result;
+  end function remainder;
+
+  -- remainder
+  -- sfixed (a downto b) rem sfixed (c downto d)
+  --        = sfixed (min(a,c) downto min(b,d))
+  function remainder (
+    l, r                 : UNRESOLVED_sfixed;  -- fixed point input
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_sfixed
+  is
+    variable l_abs      : UNRESOLVED_ufixed (l'range);
+    variable r_abs      : UNRESOLVED_ufixed (r'range);
+    variable result     : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
+                                             mine(r'low, l'low));
+    variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
+                                             mins(r'low, l'low));
+  begin
+    if (l'length < 1 or r'length < 1 or
+        mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+      return NASF;
+    end if;
+    l_abs := to_ufixed (l);
+    r_abs := to_ufixed (r);
+    result := UNRESOLVED_sfixed (remainder (
+      l           => l_abs,
+      r           => r_abs,
+      round_style => round_style));
+    neg_result := -result;
+    if l(l'high) = '1' then
+      result := neg_result(result'range);
+    end if;
+    return result;
+  end function remainder;
+
+  -- modulo
+  -- ufixed (a downto b) mod ufixed (c downto d)
+  --        = ufixed (min(a,c) downto min(b, d))
+  function "mod" (
+    l, r : UNRESOLVED_ufixed)           -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return modulo (l, r);
+  end function "mod";
+
+  -- sfixed (a downto b) mod sfixed (c downto d)
+  --        = sfixed (c downto min(b, d))
+  function "mod" (
+    l, r : UNRESOLVED_sfixed)           -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return modulo(l, r);
+  end function "mod";
+
+  -- modulo
+  -- ufixed (a downto b) mod ufixed (c downto d)
+  --        = ufixed (min(a,c) downto min(b, d))
+  function modulo (
+    l, r                 : UNRESOLVED_ufixed;  -- fixed point input
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_ufixed is
+  begin
+    return remainder(l           => l,
+                     r           => r,
+                     round_style => round_style,
+                     guard_bits  => guard_bits);
+  end function modulo;
+
+  -- sfixed (a downto b) mod sfixed (c downto d)
+  --        = sfixed (c downto min(b, d))
+  function modulo (
+    l, r                    : UNRESOLVED_sfixed;  -- fixed point input
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)
+    return UNRESOLVED_sfixed
+  is
+    variable l_abs : UNRESOLVED_ufixed (l'range);
+    variable r_abs : UNRESOLVED_ufixed (r'range);
+    variable result : UNRESOLVED_sfixed (r'high downto
+                                         mine(r'low, l'low));
+    variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
+                                          mins(r'low, l'low));
+    variable dresult_not_zero : BOOLEAN;
+  begin
+    if (l'length < 1 or r'length < 1 or
+        mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+      return NASF;
+    end if;
+    l_abs := to_ufixed (l);
+    r_abs := to_ufixed (r);
+    dresult := "0" & UNRESOLVED_sfixed(remainder (l           => l_abs,
+                                                  r           => r_abs,
+                                                  round_style => round_style));
+    if (to_s(dresult) = 0) then
+      dresult_not_zero := false;
+    else
+      dresult_not_zero := true;
+    end if;
+    if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
+      and dresult_not_zero then
+      result := resize (arg            => r - dresult,
+                        left_index     => result'high,
+                        right_index    => result'low,
+                        overflow_style => overflow_style,
+                        round_style    => round_style);
+    elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
+      result := resize (arg            => -dresult,
+                        left_index     => result'high,
+                        right_index    => result'low,
+                        overflow_style => overflow_style,
+                        round_style    => round_style);
+    elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
+      and dresult_not_zero then
+      result := resize (arg            => dresult + r,
+                        left_index     => result'high,
+                        right_index    => result'low,
+                        overflow_style => overflow_style,
+                        round_style    => round_style);
+    else
+      result := resize (arg            => dresult,
+                        left_index     => result'high,
+                        right_index    => result'low,
+                        overflow_style => overflow_style,
+                        round_style    => round_style);
+    end if;
+    return result;
+  end function modulo;
+
+  -- Procedure for those who need an "accumulator" function
+  procedure add_carry (
+    L, R   : in  UNRESOLVED_ufixed;
+    c_in   : in  STD_ULOGIC;
+    result : out UNRESOLVED_ufixed;
+    c_out  : out STD_ULOGIC) is
+    constant left_index       : INTEGER := maximum(L'high, R'high)+1;
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
+                                               downto 0);
+    variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
+                                               downto 0);
+    variable cx : UNRESOLVED_UNSIGNED (0 downto 0);  -- Carry in
+  begin
+    if (L'length < 1 or R'length < 1) then
+      result := NAUF;
+      c_out  := '0';
+    else
+      cx (0)     := c_in;
+      lresize    := resize (L, left_index, right_index);
+      rresize    := resize (R, left_index, right_index);
+      lslv       := to_uns (lresize);
+      rslv       := to_uns (rresize);
+      result_slv := lslv + rslv + cx;
+      c_out      := result_slv(left_index-right_index);
+      result := to_fixed(result_slv (left_index-right_index-1 downto 0),
+                         left_index-1, right_index);
+    end if;
+  end procedure add_carry;
+
+  procedure add_carry (
+    L, R   : in  UNRESOLVED_sfixed;
+    c_in   : in  STD_ULOGIC;
+    result : out UNRESOLVED_sfixed;
+    c_out  : out STD_ULOGIC) is
+    constant left_index       : INTEGER := maximum(L'high, R'high)+1;
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index
+                                             downto 0);
+    variable result_slv : UNRESOLVED_SIGNED (left_index-right_index
+                                             downto 0);
+    variable cx : UNRESOLVED_SIGNED (1 downto 0);  -- Carry in
+  begin
+    if (L'length < 1 or R'length < 1) then
+      result := NASF;
+      c_out  := '0';
+    else
+      cx (1)     := '0';
+      cx (0)     := c_in;
+      lresize    := resize (L, left_index, right_index);
+      rresize    := resize (R, left_index, right_index);
+      lslv       := to_s (lresize);
+      rslv       := to_s (rresize);
+      result_slv := lslv + rslv + cx;
+      c_out      := result_slv(left_index-right_index);
+      result := to_fixed(result_slv (left_index-right_index-1 downto 0),
+                         left_index-1, right_index);
+    end if;
+  end procedure add_carry;
+
+  -- Scales the result by a power of 2.  Width of input = width of output with
+  -- the decimal point moved.
+  function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
+  begin
+    if y'length < 1 then
+      return NAUF;
+    else
+      result := y;
+      return result;
+    end if;
+  end function scalb;
+
+  function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED)
+    return UNRESOLVED_ufixed is
+  begin
+    return scalb (y => y,
+                  N => to_integer(N));
+  end function scalb;
+
+  function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
+  begin
+    if y'length < 1 then
+      return NASF;
+    else
+      result := y;
+      return result;
+    end if;
+  end function scalb;
+
+  function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED)
+    return UNRESOLVED_sfixed is
+  begin
+    return scalb (y => y,
+                  N => to_integer(N));
+  end function scalb;
+
+  function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
+  begin
+    if to_X01(arg(arg'high)) = '1' then
+      return true;
+    else
+      return false;
+    end if;
+  end function Is_Negative;
+
+  function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
+    return INTEGER is
+  begin
+    for_loop : for i in arg'reverse_range loop
+      if arg(i) ?= y then
+        return i;
+      end if;
+    end loop;
+    return arg'high+1;                  -- return out of bounds 'high
+  end function find_rightmost;
+
+  function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
+    return INTEGER is
+  begin
+    for_loop : for i in arg'range loop
+      if arg(i) ?= y then
+        return i;
+      end if;
+    end loop;
+    return arg'low-1;                   -- return out of bounds 'low
+  end function find_leftmost;
+
+  function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
+    return INTEGER is
+  begin
+    for_loop : for i in arg'reverse_range loop
+      if arg(i) ?= y then
+        return i;
+      end if;
+    end loop;
+    return arg'high+1;                  -- return out of bounds 'high
+  end function find_rightmost;
+
+  function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
+    return INTEGER is
+  begin
+    for_loop : for i in arg'range loop
+      if arg(i) ?= y then
+        return i;
+      end if;
+    end loop;
+    return arg'low-1;                   -- return out of bounds 'low
+  end function find_leftmost;
+
+  function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_ufixed (ARG'range);
+  begin
+    argslv := to_uns (ARG);
+    argslv := argslv sll COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "sll";
+
+  function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_ufixed (ARG'range);
+  begin
+    argslv := to_uns (ARG);
+    argslv := argslv srl COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "srl";
+
+  function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_ufixed (ARG'range);
+  begin
+    argslv := to_uns (ARG);
+    argslv := argslv rol COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "rol";
+
+  function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_ufixed (ARG'range);
+  begin
+    argslv := to_uns (ARG);
+    argslv := argslv ror COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "ror";
+
+  function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_ufixed (ARG'range);
+  begin
+    argslv := to_uns (ARG);
+    -- Arithmetic shift on an unsigned is a logical shift
+    argslv := argslv sll COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "sla";
+
+  function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_ufixed (ARG'range);
+  begin
+    argslv := to_uns (ARG);
+    -- Arithmetic shift on an unsigned is a logical shift
+    argslv := argslv srl COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "sra";
+
+  function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_sfixed (ARG'range);
+  begin
+    argslv := to_s (ARG);
+    argslv := argslv sll COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "sll";
+
+  function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_sfixed (ARG'range);
+  begin
+    argslv := to_s (ARG);
+    argslv := argslv srl COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "srl";
+
+  function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_sfixed (ARG'range);
+  begin
+    argslv := to_s (ARG);
+    argslv := argslv rol COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "rol";
+
+  function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_sfixed (ARG'range);
+  begin
+    argslv := to_s (ARG);
+    argslv := argslv ror COUNT;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "ror";
+
+  function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_sfixed (ARG'range);
+  begin
+    argslv := to_s (ARG);
+    if COUNT > 0 then
+      -- Arithmetic shift left on a 2's complement number is a logic shift
+      argslv := argslv sll COUNT;
+    else
+      argslv := argslv sra -COUNT;
+    end if;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "sla";
+
+  function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
+    variable result : UNRESOLVED_sfixed (ARG'range);
+  begin
+    argslv := to_s (ARG);
+    if COUNT > 0 then
+      argslv := argslv sra COUNT;
+    else
+      -- Arithmetic shift left on a 2's complement number is a logic shift
+      argslv := argslv sll -COUNT;
+    end if;
+    result := to_fixed (argslv, result'high, result'low);
+    return result;
+  end function "sra";
+
+  -- Because some people want the older functions.
+  function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    if (ARG'length < 1) then
+      return NAUF;
+    end if;
+    return ARG sla COUNT;
+  end function SHIFT_LEFT;
+
+  function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    if (ARG'length < 1) then
+      return NAUF;
+    end if;
+    return ARG sra COUNT;
+  end function SHIFT_RIGHT;
+
+  function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
+    return UNRESOLVED_sfixed is
+  begin
+    if (ARG'length < 1) then
+      return NASF;
+    end if;
+    return ARG sla COUNT;
+  end function SHIFT_LEFT;
+
+  function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
+    return UNRESOLVED_sfixed is
+  begin
+    if (ARG'length < 1) then
+      return NASF;
+    end if;
+    return ARG sra COUNT;
+  end function SHIFT_RIGHT;
+
+  ----------------------------------------------------------------------------
+  -- logical functions
+  ----------------------------------------------------------------------------
+  function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    RESULT := not to_sulv(L);
+    return to_ufixed(RESULT, L'high, L'low);
+  end function "not";
+
+  function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) and to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """and"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_ufixed(RESULT, L'high, L'low);
+  end function "and";
+
+  function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) or to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """or"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_ufixed(RESULT, L'high, L'low);
+  end function "or";
+
+  function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) nand to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """nand"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_ufixed(RESULT, L'high, L'low);
+  end function "nand";
+
+  function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) nor to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """nor"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_ufixed(RESULT, L'high, L'low);
+  end function "nor";
+
+  function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) xor to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """xor"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_ufixed(RESULT, L'high, L'low);
+  end function "xor";
+
+  function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) xnor to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """xnor"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_ufixed(RESULT, L'high, L'low);
+  end function "xnor";
+
+  function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    RESULT := not to_sulv(L);
+    return to_sfixed(RESULT, L'high, L'low);
+  end function "not";
+
+  function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) and to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """and"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_sfixed(RESULT, L'high, L'low);
+  end function "and";
+
+  function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) or to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """or"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_sfixed(RESULT, L'high, L'low);
+  end function "or";
+
+  function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) nand to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """nand"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_sfixed(RESULT, L'high, L'low);
+  end function "nand";
+
+  function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) nor to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """nor"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_sfixed(RESULT, L'high, L'low);
+  end function "nor";
+
+  function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) xor to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """xor"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_sfixed(RESULT, L'high, L'low);
+  end function "xor";
+
+  function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0);  -- force downto
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      RESULT := to_sulv(L) xnor to_sulv(R);
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """xnor"": Range error L'RANGE /= R'RANGE"
+        severity warning;
+      RESULT := (others => 'X');
+    end if;
+    return to_sfixed(RESULT, L'high, L'low);
+  end function "xnor";
+
+  -- Vector and std_ulogic functions, same as functions in numeric_std
+  function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L and R(i);
+    end loop;
+    return result;
+  end function "and";
+
+  function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) and R;
+    end loop;
+    return result;
+  end function "and";
+
+  function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L or R(i);
+    end loop;
+    return result;
+  end function "or";
+
+  function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) or R;
+    end loop;
+    return result;
+  end function "or";
+
+  function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L nand R(i);
+    end loop;
+    return result;
+  end function "nand";
+
+  function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) nand R;
+    end loop;
+    return result;
+  end function "nand";
+
+  function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L nor R(i);
+    end loop;
+    return result;
+  end function "nor";
+
+  function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) nor R;
+    end loop;
+    return result;
+  end function "nor";
+
+  function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L xor R(i);
+    end loop;
+    return result;
+  end function "xor";
+
+  function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) xor R;
+    end loop;
+    return result;
+  end function "xor";
+
+  function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L xnor R(i);
+    end loop;
+    return result;
+  end function "xnor";
+
+  function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) xnor R;
+    end loop;
+    return result;
+  end function "xnor";
+
+  function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L and R(i);
+    end loop;
+    return result;
+  end function "and";
+
+  function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) and R;
+    end loop;
+    return result;
+  end function "and";
+
+  function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L or R(i);
+    end loop;
+    return result;
+  end function "or";
+
+  function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) or R;
+    end loop;
+    return result;
+  end function "or";
+
+  function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L nand R(i);
+    end loop;
+    return result;
+  end function "nand";
+
+  function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) nand R;
+    end loop;
+    return result;
+  end function "nand";
+
+  function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L nor R(i);
+    end loop;
+    return result;
+  end function "nor";
+
+  function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) nor R;
+    end loop;
+    return result;
+  end function "nor";
+
+  function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L xor R(i);
+    end loop;
+    return result;
+  end function "xor";
+
+  function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) xor R;
+    end loop;
+    return result;
+  end function "xor";
+
+  function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (R'range);
+  begin
+    for i in result'range loop
+      result(i) := L xnor R(i);
+    end loop;
+    return result;
+  end function "xnor";
+
+  function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (L'range);
+  begin
+    for i in result'range loop
+      result(i) := L(i) xnor R;
+    end loop;
+    return result;
+  end function "xnor";
+
+  -- Reduction operators
+  function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
+  begin
+    return and to_sulv(l);
+  end function "and";
+
+  function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
+  begin
+    return nand to_sulv(l);
+  end function "nand";
+
+  function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
+  begin
+    return or to_sulv(l);
+  end function "or";
+
+  function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
+  begin
+    return nor to_sulv(l);
+  end function "nor";
+
+  function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
+  begin
+    return xor to_sulv(l);
+  end function "xor";
+
+  function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
+  begin
+    return xnor to_sulv(l);
+  end function "xnor";
+
+  function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
+  begin
+    return and to_sulv(l);
+  end function "and";
+
+  function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
+  begin
+    return nand to_sulv(l);
+  end function "nand";
+
+  function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
+  begin
+    return or to_sulv(l);
+  end function "or";
+
+  function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
+  begin
+    return nor to_sulv(l);
+  end function "nor";
+
+  function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
+  begin
+    return xor to_sulv(l);
+  end function "xor";
+
+  function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
+  begin
+    return xnor to_sulv(l);
+  end function "xnor";
+  -- End reduction operators
+
+  function "?=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin  -- ?=
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?="": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_uns (lresize);
+      rslv    := to_uns (rresize);
+      return lslv ?= rslv;
+    end if;
+  end function "?=";
+
+  function "?/=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin  -- ?/=
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?/="": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_uns (lresize);
+      rslv    := to_uns (rresize);
+      return lslv ?/= rslv;
+    end if;
+  end function "?/=";
+
+  function "?>" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin  -- ?>
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?>"": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_uns (lresize);
+      rslv    := to_uns (rresize);
+      return lslv ?> rslv;
+    end if;
+  end function "?>";
+
+  function "?>=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin  -- ?>=
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?>="": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_uns (lresize);
+      rslv    := to_uns (rresize);
+      return lslv ?>= rslv;
+    end if;
+  end function "?>=";
+
+  function "?<" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin  -- ?<
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?<"": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_uns (lresize);
+      rslv    := to_uns (rresize);
+      return lslv ?< rslv;
+    end if;
+  end function "?<";
+
+  function "?<=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin  -- ?<=
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?<="": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_uns (lresize);
+      rslv    := to_uns (rresize);
+      return lslv ?<= rslv;
+    end if;
+  end function "?<=";
+
+  function "?=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin  -- ?=
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?="": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_s (lresize);
+      rslv    := to_s (rresize);
+      return lslv ?= rslv;
+    end if;
+  end function "?=";
+
+  function "?/=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin  -- ?/=
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?/="": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_s (lresize);
+      rslv    := to_s (rresize);
+      return lslv ?/= rslv;
+    end if;
+  end function "?/=";
+
+  function "?>" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin  -- ?>
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?>"": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_s (lresize);
+      rslv    := to_s (rresize);
+      return lslv ?> rslv;
+    end if;
+  end function "?>";
+
+  function "?>=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin  -- ?>=
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?>="": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_s (lresize);
+      rslv    := to_s (rresize);
+      return lslv ?>= rslv;
+    end if;
+  end function "?>=";
+
+  function "?<" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin  -- ?<
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?<"": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_s (lresize);
+      rslv    := to_s (rresize);
+      return lslv ?< rslv;
+    end if;
+  end function "?<";
+
+  function "?<=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
+    constant left_index       : INTEGER := maximum(L'high, R'high);
+    constant right_index      : INTEGER := mins(L'low, R'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin  -- ?<=
+    if ((L'length < 1) or (R'length < 1)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """?<="": null detected, returning X"
+        severity warning;
+      return 'X';
+    else
+      lresize := resize (L, left_index, right_index);
+      rresize := resize (R, left_index, right_index);
+      lslv    := to_s (lresize);
+      rslv    := to_s (rresize);
+      return lslv ?<= rslv;
+    end if;
+  end function "?<=";
+
+  -- Match function, similar to "std_match" from numeric_std
+  function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      return std_match(to_sulv(L), to_sulv(R));
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+  end function std_match;
+
+  function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
+  begin
+    if (L'high = R'high and L'low = R'low) then
+      return std_match(to_sulv(L), to_sulv(R));
+    else
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+  end function std_match;
+
+  -- compare functions
+  function "=" (
+    l, r : UNRESOLVED_ufixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """="": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """="": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_uns (lresize);
+    rslv    := to_uns (rresize);
+    return lslv = rslv;
+  end function "=";
+
+  function "=" (
+    l, r : UNRESOLVED_sfixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """="": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """="": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_s (lresize);
+    rslv    := to_s (rresize);
+    return lslv = rslv;
+  end function "=";
+
+  function "/=" (
+    l, r : UNRESOLVED_ufixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """/="": null argument detected, returning TRUE"
+        severity warning;
+      return true;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """/="": metavalue detected, returning TRUE"
+        severity warning;
+      return true;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_uns (lresize);
+    rslv    := to_uns (rresize);
+    return lslv /= rslv;
+  end function "/=";
+
+  function "/=" (
+    l, r : UNRESOLVED_sfixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """/="": null argument detected, returning TRUE"
+        severity warning;
+      return true;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """/="": metavalue detected, returning TRUE"
+        severity warning;
+      return true;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_s (lresize);
+    rslv    := to_s (rresize);
+    return lslv /= rslv;
+  end function "/=";
+
+  function ">" (
+    l, r : UNRESOLVED_ufixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """>"": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """>"": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_uns (lresize);
+    rslv    := to_uns (rresize);
+    return lslv > rslv;
+  end function ">";
+
+  function ">" (
+    l, r : UNRESOLVED_sfixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """>"": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """>"": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_s (lresize);
+    rslv    := to_s (rresize);
+    return lslv > rslv;
+  end function ">";
+
+  function "<" (
+    l, r : UNRESOLVED_ufixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """<"": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """<"": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_uns (lresize);
+    rslv    := to_uns (rresize);
+    return lslv < rslv;
+  end function "<";
+
+  function "<" (
+    l, r : UNRESOLVED_sfixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """<"": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """<"": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_s (lresize);
+    rslv    := to_s (rresize);
+    return lslv < rslv;
+  end function "<";
+
+  function ">=" (
+    l, r : UNRESOLVED_ufixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """>="": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """>="": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_uns (lresize);
+    rslv    := to_uns (rresize);
+    return lslv >= rslv;
+  end function ">=";
+
+  function ">=" (
+    l, r : UNRESOLVED_sfixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """>="": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """>="": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    lslv    := to_s (lresize);
+    rslv    := to_s (rresize);
+    return lslv >= rslv;
+  end function ">=";
+
+  function "<=" (
+    l, r : UNRESOLVED_ufixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """<="": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """<="": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize     := resize (l, left_index, right_index);
+    rresize     := resize (r, left_index, right_index);
+    lslv        := to_uns (lresize);
+    rslv        := to_uns (rresize);
+    return lslv <= rslv;
+  end function "<=";
+
+  function "<=" (
+    l, r : UNRESOLVED_sfixed)           -- fixed point input
+    return BOOLEAN
+  is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+    variable lslv, rslv       : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """<="": null argument detected, returning FALSE"
+        severity warning;
+      return false;
+    elsif (Is_X(l) or Is_X(r)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & """<="": metavalue detected, returning FALSE"
+        severity warning;
+      return false;
+    end if;
+    lresize     := resize (l, left_index, right_index);
+    rresize     := resize (r, left_index, right_index);
+    lslv        := to_s (lresize);
+    rslv        := to_s (rresize);
+    return lslv <= rslv;
+  end function "<=";
+
+  -- overloads of the default maximum and minimum functions
+  function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      return NAUF;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    return to_fixed(maximum(to_uns(lresize), to_uns(rresize)),
+                    left_index, right_index);
+  end function maximum;
+
+  function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      return NASF;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    return to_fixed(maximum(to_s(lresize), to_s(rresize)),
+                    left_index, right_index);
+  end function maximum;
+
+  function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      return NAUF;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    return to_fixed(minimum(to_uns(lresize), to_uns(rresize)),
+                    left_index, right_index);
+  end function minimum;
+
+  function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
+    constant left_index       : INTEGER := maximum(l'high, r'high);
+    constant right_index      : INTEGER := mins(l'low, r'low);
+    variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
+  begin
+    if (l'length < 1 or r'length < 1) then
+      return NASF;
+    end if;
+    lresize := resize (l, left_index, right_index);
+    rresize := resize (r, left_index, right_index);
+    return to_fixed(minimum(to_s(lresize), to_s(rresize)),
+                    left_index, right_index);
+  end function minimum;
+
+  function to_ufixed (
+    arg                     : NATURAL;  -- integer
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER                   := 0;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed
+  is
+    constant fw      : INTEGER := mins (right_index, right_index);  -- catch literals
+    variable result  : UNRESOLVED_ufixed (left_index downto fw);
+    variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
+      (others => '0');  -- integer portion
+    variable argx    : NATURAL;         -- internal version of arg
+  begin
+    if (result'length < 1) then
+      return NAUF;
+    end if;
+    if arg /= 0 then
+      argx := arg;
+      for I in 0 to sresult'left loop
+        if (argx mod 2) = 0 then
+          sresult(I) := '0';
+        else
+          sresult(I) := '1';
+        end if;
+        argx := argx/2;
+      end loop;
+      if argx /= 0 then
+        assert no_warning
+          report fixed_generic_pkg'instance_name
+          & "TO_UFIXED(NATURAL): vector truncated"
+          severity warning;
+        if overflow_style = fixed_saturate then
+          return saturate (left_index, right_index);
+        end if;
+      end if;
+      result := resize (arg            => sresult,
+                        left_index     => left_index,
+                        right_index    => right_index,
+                        round_style    => round_style,
+                        overflow_style => overflow_style);
+    else
+      result := (others => '0');
+    end if;
+    return result;
+  end function to_ufixed;
+
+  function to_sfixed (
+    arg                     : INTEGER;  -- integer
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER                   := 0;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed
+  is
+    constant fw      : INTEGER := mins (right_index, right_index);  -- catch literals
+    variable result  : UNRESOLVED_sfixed (left_index downto fw);
+    variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
+      (others => '0');  -- integer portion
+    variable argx    : INTEGER;         -- internal version of arg
+    variable sign    : STD_ULOGIC;      -- sign of input
+  begin
+    if (result'length < 1) then         -- null range
+      return NASF;
+    end if;
+    if arg /= 0 then
+      if (arg < 0) then
+        sign := '1';
+        argx := -(arg + 1);
+      else
+        sign := '0';
+        argx := arg;
+      end if;
+      for I in 0 to sresult'left loop
+        if (argx mod 2) = 0 then
+          sresult(I) := sign;
+        else
+          sresult(I) := not sign;
+        end if;
+        argx := argx/2;
+      end loop;
+      if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
+        assert no_warning
+          report fixed_generic_pkg'instance_name
+          & "TO_SFIXED(INTEGER): vector truncated"
+          severity warning;
+        if overflow_style = fixed_saturate then                -- saturate
+          if arg < 0 then
+            result := not saturate (result'high, result'low);  -- underflow
+          else
+            result := saturate (result'high, result'low);      -- overflow
+          end if;
+          return result;
+        end if;
+      end if;
+      result := resize (arg            => sresult,
+                        left_index     => left_index,
+                        right_index    => right_index,
+                        round_style    => round_style,
+                        overflow_style => overflow_style);
+    else
+      result := (others => '0');
+    end if;
+    return result;
+  end function to_sfixed;
+
+  function to_ufixed (
+    arg                     : REAL;     -- real
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)  -- # of guard bits
+    return UNRESOLVED_ufixed
+  is
+    constant fw              : INTEGER := mins (right_index, right_index);  -- catch literals
+    variable result          : UNRESOLVED_ufixed (left_index downto fw) :=
+      (others => '0');
+    variable Xresult         : UNRESOLVED_ufixed (left_index downto
+                                                  fw-guard_bits) :=
+      (others => '0');
+    variable presult         : REAL;
+  begin
+    -- If negative or null range, return.
+    if (left_index < fw) then
+      return NAUF;
+    end if;
+    if (arg < 0.0) then
+      report fixed_generic_pkg'instance_name
+        & "TO_UFIXED: Negative argument passed "
+        & REAL'image(arg) severity error;
+      return result;
+    end if;
+    presult := arg;
+    if presult >= (2.0**(left_index+1)) then
+      assert no_warning report fixed_generic_pkg'instance_name
+        & "TO_UFIXED(REAL): vector truncated"
+        severity warning;
+      if overflow_style = fixed_wrap then
+        presult := presult mod (2.0**(left_index+1));  -- wrap
+      else
+        return saturate (result'high, result'low);
+      end if;
+    end if;
+    for i in Xresult'range loop
+      if presult >= 2.0**i then
+        Xresult(i) := '1';
+        presult    := presult - 2.0**i;
+      else
+        Xresult(i) := '0';
+      end if;
+    end loop;
+    if guard_bits > 0 and round_style = fixed_round then
+      result := round_fixed (arg => Xresult (left_index
+                                             downto right_index),
+                             remainder => Xresult (right_index-1 downto
+                                                   right_index-guard_bits),
+                             overflow_style => overflow_style);
+    else
+      result := Xresult (result'range);
+    end if;
+    return result;
+  end function to_ufixed;
+
+  function to_sfixed (
+    arg                     : REAL;     -- real
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)  -- # of guard bits
+    return UNRESOLVED_sfixed
+  is
+    constant fw     : INTEGER := mins (right_index, right_index);  -- catch literals
+    variable result : UNRESOLVED_sfixed (left_index downto fw) :=
+      (others => '0');
+    variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
+      (others => '0');
+    variable presult : REAL;
+  begin
+    if (left_index < fw) then           -- null range
+      return NASF;
+    end if;
+    if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
+      assert no_warning report fixed_generic_pkg'instance_name
+        & "TO_SFIXED(REAL): vector truncated"
+        severity warning;
+      if overflow_style = fixed_saturate then
+        if arg < 0.0 then               -- saturate
+          result := not saturate (result'high, result'low);        -- underflow
+        else
+          result := saturate (result'high, result'low);            -- overflow
+        end if;
+        return result;
+      else
+        presult := abs(arg) mod (2.0**(left_index+1));             -- wrap
+      end if;
+    else
+      presult := abs(arg);
+    end if;
+    for i in Xresult'range loop
+      if presult >= 2.0**i then
+        Xresult(i) := '1';
+        presult    := presult - 2.0**i;
+      else
+        Xresult(i) := '0';
+      end if;
+    end loop;
+    if arg < 0.0 then
+      Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
+    end if;
+    if guard_bits > 0 and round_style = fixed_round then
+      result := round_fixed (arg => Xresult (left_index
+                                             downto right_index),
+                             remainder => Xresult (right_index-1 downto
+                                                   right_index-guard_bits),
+                             overflow_style => overflow_style);
+    else
+      result := Xresult (result'range);
+    end if;
+    return result;
+  end function to_sfixed;
+
+  function to_ufixed (
+    arg                     : UNRESOLVED_UNSIGNED;             -- unsigned
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER                   := 0;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed
+  is
+    constant ARG_LEFT : INTEGER := arg'length-1;
+    alias XARG        : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is arg;
+    variable result   : UNRESOLVED_ufixed (left_index downto right_index);
+  begin
+    if arg'length < 1 or (left_index < right_index) then
+      return NAUF;
+    end if;
+    result := resize (arg            => UNRESOLVED_ufixed (XARG),
+                      left_index     => left_index,
+                      right_index    => right_index,
+                      round_style    => round_style,
+                      overflow_style => overflow_style);
+    return result;
+  end function to_ufixed;
+
+  -- converted version
+  function to_ufixed (
+    arg : UNRESOLVED_UNSIGNED)          -- unsigned
+    return UNRESOLVED_ufixed
+  is
+    constant ARG_LEFT : INTEGER := arg'length-1;
+    alias XARG        : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is arg;
+  begin
+    if arg'length < 1 then
+      return NAUF;
+    end if;
+    return UNRESOLVED_ufixed(XARG);
+  end function to_ufixed;
+
+  function to_sfixed (
+    arg                     : UNRESOLVED_SIGNED;               -- signed
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER                   := 0;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed
+  is
+    constant ARG_LEFT : INTEGER := arg'length-1;
+    alias XARG        : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is arg;
+    variable result   : UNRESOLVED_sfixed (left_index downto right_index);
+  begin
+    if arg'length < 1 or (left_index < right_index) then
+      return NASF;
+    end if;
+    result := resize (arg            => UNRESOLVED_sfixed (XARG),
+                      left_index     => left_index,
+                      right_index    => right_index,
+                      round_style    => round_style,
+                      overflow_style => overflow_style);
+    return result;
+  end function to_sfixed;
+
+  -- converted version
+  function to_sfixed (
+    arg : UNRESOLVED_SIGNED)            -- signed
+    return UNRESOLVED_sfixed
+  is
+    constant ARG_LEFT : INTEGER := arg'length-1;
+    alias XARG        : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is arg;
+  begin
+    if arg'length < 1 then
+      return NASF;
+    end if;
+    return UNRESOLVED_sfixed(XARG);
+  end function to_sfixed;
+
+  function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
+    variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
+  begin
+    if arg'length < 1 then
+      return NASF;
+    end if;
+    result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
+    result (arg'high+1)              := '0';
+    return result;
+  end function to_sfixed;
+
+  -- Because of the fairly complicated sizing rules in the fixed point
+  -- packages these functions are provided to compute the result ranges
+  -- Example:
+  -- signal uf1 : ufixed (3 downto -3);
+  -- signal uf2 : ufixed (4 downto -2);
+  -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
+  --                             ufixed_low (3, -3, '*', 4, -2));
+  -- uf1multuf2 <= uf1 * uf2;
+  -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
+  -- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
+  function ufixed_high (left_index, right_index   : INTEGER;
+                        operation                 : CHARACTER := 'X';
+                        left_index2, right_index2 : INTEGER   := 0)
+    return INTEGER is
+  begin
+    case operation is
+      when '+'| '-' => return maximum (left_index, left_index2) + 1;
+      when '*'      => return left_index + left_index2 + 1;
+      when '/'      => return left_index - right_index2;
+      when '1'      => return -right_index;                    -- reciprocal
+      when 'R'|'r'  => return mins (left_index, left_index2);  -- "rem"
+      when 'M'|'m'  => return mins (left_index, left_index2);  -- "mod"
+      when others   => return left_index;  -- For abs and default
+    end case;
+  end function ufixed_high;
+
+  function ufixed_low (left_index, right_index   : INTEGER;
+                       operation                 : CHARACTER := 'X';
+                       left_index2, right_index2 : INTEGER   := 0)
+    return INTEGER is
+  begin
+    case operation is
+      when '+'| '-' => return mins (right_index, right_index2);
+      when '*'      => return right_index + right_index2;
+      when '/'      => return right_index - left_index2 - 1;
+      when '1'      => return -left_index - 1;                   -- reciprocal
+      when 'R'|'r'  => return mins (right_index, right_index2);  -- "rem"
+      when 'M'|'m'  => return mins (right_index, right_index2);  -- "mod"
+      when others   => return right_index;  -- for abs and default
+    end case;
+  end function ufixed_low;
+
+  function sfixed_high (left_index, right_index   : INTEGER;
+                        operation                 : CHARACTER := 'X';
+                        left_index2, right_index2 : INTEGER   := 0)
+    return INTEGER is
+  begin
+    case operation is
+      when '+'| '-' => return maximum (left_index, left_index2) + 1;
+      when '*'      => return left_index + left_index2 + 1;
+      when '/'      => return left_index - right_index2 + 1;
+      when '1'      => return -right_index + 1;                -- reciprocal
+      when 'R'|'r'  => return mins (left_index, left_index2);  -- "rem"
+      when 'M'|'m'  => return left_index2;                     -- "mod"
+      when 'A'|'a'  => return left_index + 1;                  -- "abs"
+      when 'N'|'n'  => return left_index + 1;                  -- -sfixed
+      when others   => return left_index;
+    end case;
+  end function sfixed_high;
+
+  function sfixed_low (left_index, right_index   : INTEGER;
+                       operation                 : CHARACTER := 'X';
+                       left_index2, right_index2 : INTEGER   := 0)
+    return INTEGER is
+  begin
+    case operation is
+      when '+'| '-' => return mins (right_index, right_index2);
+      when '*'      => return right_index + right_index2;
+      when '/'      => return right_index - left_index2;
+      when '1'      => return -left_index;  -- reciprocal
+      when 'R'|'r'  => return mins (right_index, right_index2);  -- "rem"
+      when 'M'|'m'  => return mins (right_index, right_index2);  -- "mod"
+      when others   => return right_index;  -- default for abs, neg and default
+    end case;
+  end function sfixed_low;
+
+  -- Same as above, but using the "size_res" input only for their ranges:
+  -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
+  --                             ufixed_low (uf1, '*', uf2));
+  -- uf1multuf2 <= uf1 * uf2;
+  function ufixed_high (size_res  : UNRESOLVED_ufixed;
+                        operation : CHARACTER := 'X';
+                        size_res2 : UNRESOLVED_ufixed)
+    return INTEGER is
+  begin
+    return ufixed_high (left_index   => size_res'high,
+                        right_index  => size_res'low,
+                        operation    => operation,
+                        left_index2  => size_res2'high,
+                        right_index2 => size_res2'low);
+  end function ufixed_high;
+
+  function ufixed_low (size_res  : UNRESOLVED_ufixed;
+                       operation : CHARACTER := 'X';
+                       size_res2 : UNRESOLVED_ufixed)
+    return INTEGER is
+  begin
+    return ufixed_low (left_index   => size_res'high,
+                       right_index  => size_res'low,
+                       operation    => operation,
+                       left_index2  => size_res2'high,
+                       right_index2 => size_res2'low);
+  end function ufixed_low;
+
+  function sfixed_high (size_res  : UNRESOLVED_sfixed;
+                        operation : CHARACTER := 'X';
+                        size_res2 : UNRESOLVED_sfixed)
+    return INTEGER is
+  begin
+    return sfixed_high (left_index   => size_res'high,
+                        right_index  => size_res'low,
+                        operation    => operation,
+                        left_index2  => size_res2'high,
+                        right_index2 => size_res2'low);
+  end function sfixed_high;
+
+  function sfixed_low (size_res  : UNRESOLVED_sfixed;
+                       operation : CHARACTER := 'X';
+                       size_res2 : UNRESOLVED_sfixed)
+    return INTEGER is
+  begin
+    return sfixed_low (left_index   => size_res'high,
+                       right_index  => size_res'low,
+                       operation    => operation,
+                       left_index2  => size_res2'high,
+                       right_index2 => size_res2'low);
+  end function sfixed_low;
+
+  -- purpose: returns a saturated number
+  function saturate (
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
+      (others => '1');
+  begin
+    return sat;
+  end function saturate;
+
+  -- purpose: returns a saturated number
+  function saturate (
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
+      (others => '1');
+  begin
+    -- saturate positive, to saturate negative, just do "not saturate()"
+    sat (left_index) := '0';
+    return sat;
+  end function saturate;
+
+  function saturate (
+    size_res : UNRESOLVED_ufixed)       -- only the size of this is used
+    return UNRESOLVED_ufixed is
+  begin
+    return saturate (size_res'high, size_res'low);
+  end function saturate;
+
+  function saturate (
+    size_res : UNRESOLVED_sfixed)       -- only the size of this is used
+    return UNRESOLVED_sfixed is
+  begin
+    return saturate (size_res'high, size_res'low);
+  end function saturate;
+
+  -- As a concession to those who use a graphical DSP environment,
+  -- these functions take parameters in those tools format and create
+  -- fixed point numbers.  These functions are designed to convert from
+  -- a std_logic_vector to the VHDL fixed point format using the conventions
+  -- of these packages.  In a pure VHDL environment you should use the
+  -- "to_ufixed" and "to_sfixed" routines.
+  -- Unsigned fixed point
+  function to_UFix (
+    arg      : STD_ULOGIC_VECTOR;
+    width    : NATURAL;                 -- width of vector
+    fraction : NATURAL)                 -- width of fraction
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
+  begin
+    if (arg'length /= result'length) then
+      report fixed_generic_pkg'instance_name
+        & "TO_UFIX (STD_ULOGIC_VECTOR) "
+        & "Vector lengths do not match.  Input length is "
+        & INTEGER'image(arg'length) & " and output will be "
+        & INTEGER'image(result'length) & " wide."
+        severity error;
+      return NAUF;
+    else
+      result := to_ufixed (arg, result'high, result'low);
+      return result;
+    end if;
+  end function to_UFix;
+
+  -- signed fixed point
+  function to_SFix (
+    arg      : STD_ULOGIC_VECTOR;
+    width    : NATURAL;                 -- width of vector
+    fraction : NATURAL)                 -- width of fraction
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
+  begin
+    if (arg'length /= result'length) then
+      report fixed_generic_pkg'instance_name
+        & "TO_SFIX (STD_ULOGIC_VECTOR) "
+        & "Vector lengths do not match.  Input length is "
+        & INTEGER'image(arg'length) & " and output will be "
+        & INTEGER'image(result'length) & " wide."
+        severity error;
+      return NASF;
+    else
+      result := to_sfixed (arg, result'high, result'low);
+      return result;
+    end if;
+  end function to_SFix;
+
+  -- finding the bounds of a number.  These functions can be used like this:
+  -- signal xxx : ufixed (7 downto -3);
+  -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
+  -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
+  --               downto UFix_low(11, 3, "+", 11, 3));
+  -- Where "11" is the width of xxx (xxx'length),
+  -- and 3 is the lower bound (abs (xxx'low))
+  -- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
+  function ufix_high (
+    width, fraction   : NATURAL;
+    operation         : CHARACTER := 'X';
+    width2, fraction2 : NATURAL   := 0)
+    return INTEGER is
+  begin
+    return ufixed_high (left_index   => width - 1 - fraction,
+                        right_index  => -fraction,
+                        operation    => operation,
+                        left_index2  => width2 - 1 - fraction2,
+                        right_index2 => -fraction2);
+  end function ufix_high;
+
+  function ufix_low (
+    width, fraction   : NATURAL;
+    operation         : CHARACTER := 'X';
+    width2, fraction2 : NATURAL   := 0)
+    return INTEGER is
+  begin
+    return ufixed_low (left_index   => width - 1 - fraction,
+                       right_index  => -fraction,
+                       operation    => operation,
+                       left_index2  => width2 - 1 - fraction2,
+                       right_index2 => -fraction2);
+  end function ufix_low;
+
+  function sfix_high (
+    width, fraction   : NATURAL;
+    operation         : CHARACTER := 'X';
+    width2, fraction2 : NATURAL   := 0)
+    return INTEGER is
+  begin
+    return sfixed_high (left_index   => width - fraction,
+                        right_index  => -fraction,
+                        operation    => operation,
+                        left_index2  => width2 - fraction2,
+                        right_index2 => -fraction2);
+  end function sfix_high;
+
+  function sfix_low (
+    width, fraction   : NATURAL;
+    operation         : CHARACTER := 'X';
+    width2, fraction2 : NATURAL   := 0)
+    return INTEGER is
+  begin
+    return sfixed_low (left_index   => width - fraction,
+                       right_index  => -fraction,
+                       operation    => operation,
+                       left_index2  => width2 - fraction2,
+                       right_index2 => -fraction2);
+  end function sfix_low;
+
+  function to_unsigned (
+    arg                     : UNRESOLVED_ufixed;  -- ufixed point input
+    constant size           : NATURAL;            -- length of output
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_UNSIGNED is
+  begin
+    return to_uns(resize (arg            => arg,
+                          left_index     => size-1,
+                          right_index    => 0,
+                          round_style    => round_style,
+                          overflow_style => overflow_style));
+  end function to_unsigned;
+
+  function to_unsigned (
+    arg                     : UNRESOLVED_ufixed;    -- ufixed point input
+    size_res                : UNRESOLVED_UNSIGNED;  -- length of output
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_UNSIGNED is
+  begin
+    return to_unsigned (arg            => arg,
+                        size           => size_res'length,
+                        round_style    => round_style,
+                        overflow_style => overflow_style);
+  end function to_unsigned;
+
+  function to_signed (
+    arg                     : UNRESOLVED_sfixed;  -- sfixed point input
+    constant size           : NATURAL;            -- length of output
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_SIGNED is
+  begin
+    return to_s(resize (arg            => arg,
+                        left_index     => size-1,
+                        right_index    => 0,
+                        round_style    => round_style,
+                        overflow_style => overflow_style));
+  end function to_signed;
+
+  function to_signed (
+    arg                     : UNRESOLVED_sfixed;  -- sfixed point input
+    size_res                : UNRESOLVED_SIGNED;  -- used for length of output
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_SIGNED is
+  begin
+    return to_signed (arg            => arg,
+                      size           => size_res'length,
+                      round_style    => round_style,
+                      overflow_style => overflow_style);
+  end function to_signed;
+
+  function to_real (
+    arg : UNRESOLVED_ufixed)            -- ufixed point input
+    return REAL
+  is
+    constant left_index  : INTEGER := arg'high;
+    constant right_index : INTEGER := arg'low;
+    variable result      : REAL;        -- result
+    variable arg_int     : UNRESOLVED_ufixed (left_index downto right_index);
+  begin
+    if (arg'length < 1) then
+      return 0.0;
+    end if;
+    arg_int := To_X01(cleanvec(arg));
+    if (Is_X(arg_int)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & "TO_REAL (ufixed): metavalue detected, returning 0.0"
+        severity warning;
+      return 0.0;
+    end if;
+    result := 0.0;
+    for i in arg_int'range loop
+      if (arg_int(i) = '1') then
+        result := result + (2.0**i);
+      end if;
+    end loop;
+    return result;
+  end function to_real;
+
+  function to_real (
+    arg : UNRESOLVED_sfixed)            -- ufixed point input
+    return REAL
+  is
+    constant left_index  : INTEGER := arg'high;
+    constant right_index : INTEGER := arg'low;
+    variable result      : REAL;        -- result
+    variable arg_int     : UNRESOLVED_sfixed (left_index downto right_index);
+    -- unsigned version of argument
+    variable arg_uns     : UNRESOLVED_ufixed (left_index downto right_index);
+    -- absolute of argument
+  begin
+    if (arg'length < 1) then
+      return 0.0;
+    end if;
+    arg_int := to_X01(cleanvec(arg));
+    if (Is_X(arg_int)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & "TO_REAL (sfixed): metavalue detected, returning 0.0"
+        severity warning;
+      return 0.0;
+    end if;
+    arg_uns := to_ufixed (arg_int);
+    result  := to_real (arg_uns);
+    if (arg_int(arg_int'high) = '1') then
+      result := -result;
+    end if;
+    return result;
+  end function to_real;
+
+  function to_integer (
+    arg                     : UNRESOLVED_ufixed;  -- fixed point input
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return NATURAL
+  is
+    constant left_index : INTEGER := arg'high;
+    variable arg_uns    : UNRESOLVED_UNSIGNED (left_index+1 downto 0)
+      := (others => '0');
+  begin
+    if (arg'length < 1) then
+      return 0;
+    end if;
+    if (Is_X (arg)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & "TO_INTEGER (ufixed): metavalue detected, returning 0"
+        severity warning;
+      return 0;
+    end if;
+    if (left_index < -1) then
+      return 0;
+    end if;
+    arg_uns := to_uns(resize (arg            => arg,
+                              left_index     => arg_uns'high,
+                              right_index    => 0,
+                              round_style    => round_style,
+                              overflow_style => overflow_style));
+    return to_integer (arg_uns);
+  end function to_integer;
+
+  function to_integer (
+    arg                     : UNRESOLVED_sfixed;  -- fixed point input
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return INTEGER
+  is
+    constant left_index  : INTEGER := arg'high;
+    variable arg_s       : UNRESOLVED_SIGNED (left_index+1 downto 0);
+  begin
+    if (arg'length < 1) then
+      return 0;
+    end if;
+    if (Is_X (arg)) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & "TO_INTEGER (sfixed): metavalue detected, returning 0"
+        severity warning;
+      return 0;
+    end if;
+    if (left_index < -1) then
+      return 0;
+    end if;
+    arg_s := to_s(resize (arg            => arg,
+                          left_index     => arg_s'high,
+                          right_index    => 0,
+                          round_style    => round_style,
+                          overflow_style => overflow_style));
+    return to_integer (arg_s);
+  end function to_integer;
+
+  function to_01 (
+    s             : UNRESOLVED_ufixed;              -- ufixed point input
+    constant XMAP : STD_ULOGIC := '0')              -- Map x to
+    return UNRESOLVED_ufixed
+  is
+  begin
+    if (s'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & "TO_01(ufixed): null detected, returning NULL"
+        severity warning;
+      return NAUF;
+    end if;
+    return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
+  end function to_01;
+
+  function to_01 (
+    s             : UNRESOLVED_sfixed;  -- sfixed point input
+    constant XMAP : STD_ULOGIC := '0')  -- Map x to
+    return UNRESOLVED_sfixed
+  is
+  begin
+    if (s'length < 1) then
+      assert no_warning
+        report fixed_generic_pkg'instance_name
+        & "TO_01(sfixed): null detected, returning NULL"
+        severity warning;
+      return NASF;
+    end if;
+    return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
+  end function to_01;
+
+  function Is_X (
+    arg : UNRESOLVED_ufixed)
+    return BOOLEAN
+  is
+    variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0);  -- slv
+  begin
+    argslv := to_sulv(arg);
+    return Is_X (argslv);
+  end function Is_X;
+
+  function Is_X (
+    arg : UNRESOLVED_sfixed)
+    return BOOLEAN
+  is
+    variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0);  -- slv
+  begin
+    argslv := to_sulv(arg);
+    return Is_X (argslv);
+  end function Is_X;
+
+  function To_X01 (
+    arg : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed is
+  begin
+    return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
+  end function To_X01;
+
+  function to_X01 (
+    arg : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
+  end function to_X01;
+
+  function To_X01Z (
+    arg : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed is
+  begin
+    return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
+  end function To_X01Z;
+
+  function to_X01Z (
+    arg : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
+  end function to_X01Z;
+
+  function To_UX01 (
+    arg : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed is
+  begin
+    return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
+  end function To_UX01;
+
+  function to_UX01 (
+    arg : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
+  end function to_UX01;
+
+  function resize (
+    arg                     : UNRESOLVED_ufixed;            -- input
+    constant left_index     : INTEGER;  -- integer portion
+    constant right_index    : INTEGER;  -- size of fraction
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed
+  is
+    constant arghigh : INTEGER := maximum (arg'high, arg'low);
+    constant arglow  : INTEGER := mine (arg'high, arg'low);
+    variable invec   : UNRESOLVED_ufixed (arghigh downto arglow);
+    variable result  : UNRESOLVED_ufixed(left_index downto right_index) :=
+      (others => '0');
+    variable needs_rounding : BOOLEAN := false;
+  begin  -- resize
+    if (arg'length < 1) or (result'length < 1) then
+      return NAUF;
+    elsif (invec'length < 1) then
+      return result;                    -- string literal value
+    else
+      invec := cleanvec(arg);
+      if (right_index > arghigh) then   -- return top zeros
+        needs_rounding := (round_style = fixed_round) and
+                          (right_index = arghigh+1);
+      elsif (left_index < arglow) then  -- return overflow
+        if (overflow_style = fixed_saturate) and
+          (or(to_sulv(invec)) = '1') then
+          result := saturate (result'high, result'low);     -- saturate
+        end if;
+      elsif (arghigh > left_index) then
+        -- wrap or saturate?
+        if (overflow_style = fixed_saturate and
+            or (to_sulv(invec(arghigh downto left_index+1))) = '1')
+        then
+          result := saturate (result'high, result'low);     -- saturate
+        else
+          if (arglow >= right_index) then
+            result (left_index downto arglow) :=
+              invec(left_index downto arglow);
+          else
+            result (left_index downto right_index) :=
+              invec (left_index downto right_index);
+            needs_rounding := (round_style = fixed_round);  -- round
+          end if;
+        end if;
+      else                              -- arghigh <= integer width
+        if (arglow >= right_index) then
+          result (arghigh downto arglow) := invec;
+        else
+          result (arghigh downto right_index) :=
+            invec (arghigh downto right_index);
+          needs_rounding := (round_style = fixed_round);    -- round
+        end if;
+      end if;
+      -- Round result
+      if needs_rounding then
+        result := round_fixed (arg            => result,
+                               remainder      => invec (right_index-1
+                                                        downto arglow),
+                               overflow_style => overflow_style);
+      end if;
+      return result;
+    end if;
+  end function resize;
+
+  function resize (
+    arg                     : UNRESOLVED_sfixed;          -- input
+    constant left_index     : INTEGER;  -- integer portion
+    constant right_index    : INTEGER;  -- size of fraction
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed
+  is
+    constant arghigh : INTEGER := maximum (arg'high, arg'low);
+    constant arglow  : INTEGER := mine (arg'high, arg'low);
+    variable invec   : UNRESOLVED_sfixed (arghigh downto arglow);
+    variable result  : UNRESOLVED_sfixed(left_index downto right_index) :=
+      (others => '0');
+    variable reduced        : STD_ULOGIC;
+    variable needs_rounding : BOOLEAN := false;           -- rounding
+  begin  -- resize
+    if (arg'length < 1) or (result'length < 1) then
+      return NASF;
+    elsif (invec'length < 1) then
+      return result;                    -- string literal value
+    else
+      invec := cleanvec(arg);
+      if (right_index > arghigh) then   -- return top zeros
+        if (arg'low /= INTEGER'low) then  -- check for a literal
+          result := (others => arg(arghigh));             -- sign extend
+        end if;
+        needs_rounding := (round_style = fixed_round) and
+                          (right_index = arghigh+1);
+      elsif (left_index < arglow) then  -- return overflow
+        if (overflow_style = fixed_saturate) then
+          reduced := or (to_sulv(invec));
+          if (reduced = '1') then
+            if (invec(arghigh) = '0') then
+              -- saturate POSITIVE
+              result := saturate (result'high, result'low);
+            else
+              -- saturate negative
+              result := not saturate (result'high, result'low);
+            end if;
+            -- else return 0 (input was 0)
+          end if;
+          -- else return 0 (wrap)
+        end if;
+      elsif (arghigh > left_index) then
+        if (invec(arghigh) = '0') then
+          reduced := or (to_sulv(invec(arghigh-1 downto
+                                      left_index)));
+          if overflow_style = fixed_saturate and reduced = '1' then
+            -- saturate positive
+            result := saturate (result'high, result'low);
+          else
+            if (right_index > arglow) then
+              result         := invec (left_index downto right_index);
+              needs_rounding := (round_style = fixed_round);
+            else
+              result (left_index downto arglow) :=
+                invec (left_index downto arglow);
+            end if;
+          end if;
+        else
+          reduced := and (to_sulv(invec(arghigh-1 downto
+                                       left_index)));
+          if overflow_style = fixed_saturate and reduced = '0' then
+            result := not saturate (result'high, result'low);
+          else
+            if (right_index > arglow) then
+              result         := invec (left_index downto right_index);
+              needs_rounding := (round_style = fixed_round);
+            else
+              result (left_index downto arglow) :=
+                invec (left_index downto arglow);
+            end if;
+          end if;
+        end if;
+      else                              -- arghigh <= integer width
+        if (arglow >= right_index) then
+          result (arghigh downto arglow) := invec;
+        else
+          result (arghigh downto right_index) :=
+            invec (arghigh downto right_index);
+          needs_rounding := (round_style = fixed_round);  -- round
+        end if;
+        if (left_index > arghigh) then  -- sign extend
+          result(left_index downto arghigh+1) := (others => invec(arghigh));
+        end if;
+      end if;
+      -- Round result
+      if (needs_rounding) then
+        result := round_fixed (arg            => result,
+                               remainder      => invec (right_index-1
+                                                        downto arglow),
+                               overflow_style => overflow_style);
+      end if;
+      return result;
+    end if;
+  end function resize;
+
+  -- size_res functions
+  -- These functions compute the size from a passed variable named "size_res"
+  -- The only part of this variable used it it's size, it is never passed
+  -- to a lower level routine.
+  function to_ufixed (
+    arg      : STD_ULOGIC_VECTOR;       -- shifted vector
+    size_res : UNRESOLVED_ufixed)       -- for size only
+    return UNRESOLVED_ufixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_ufixed (size_res'left downto fw);
+  begin
+    if (result'length < 1 or arg'length < 1) then
+      return NAUF;
+    else
+      result := to_ufixed (arg         => arg,
+                           left_index  => size_res'high,
+                           right_index => size_res'low);
+      return result;
+    end if;
+  end function to_ufixed;
+
+  function to_sfixed (
+    arg      : STD_ULOGIC_VECTOR;       -- shifted vector
+    size_res : UNRESOLVED_sfixed)       -- for size only
+    return UNRESOLVED_sfixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_sfixed (size_res'left downto fw);
+  begin
+    if (result'length < 1 or arg'length < 1) then
+      return NASF;
+    else
+      result := to_sfixed (arg         => arg,
+                           left_index  => size_res'high,
+                           right_index => size_res'low);
+      return result;
+    end if;
+  end function to_sfixed;
+
+  function to_ufixed (
+    arg                     : NATURAL;            -- integer
+    size_res                : UNRESOLVED_ufixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_ufixed (size_res'left downto fw);
+  begin
+    if (result'length < 1) then
+      return NAUF;
+    else
+      result := to_ufixed (arg            => arg,
+                           left_index     => size_res'high,
+                           right_index    => size_res'low,
+                           round_style    => round_style,
+                           overflow_style => overflow_style);
+      return result;
+    end if;
+  end function to_ufixed;
+
+  function to_sfixed (
+    arg                     : INTEGER;            -- integer
+    size_res                : UNRESOLVED_sfixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_sfixed (size_res'left downto fw);
+  begin
+    if (result'length < 1) then
+      return NASF;
+    else
+      result := to_sfixed (arg            => arg,
+                           left_index     => size_res'high,
+                           right_index    => size_res'low,
+                           round_style    => round_style,
+                           overflow_style => overflow_style);
+      return result;
+    end if;
+  end function to_sfixed;
+
+  function to_ufixed (
+    arg                     : REAL;     -- real
+    size_res                : UNRESOLVED_ufixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)  -- # of guard bits
+    return UNRESOLVED_ufixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_ufixed (size_res'left downto fw);
+  begin
+    if (result'length < 1) then
+      return NAUF;
+    else
+      result := to_ufixed (arg            => arg,
+                           left_index     => size_res'high,
+                           right_index    => size_res'low,
+                           guard_bits     => guard_bits,
+                           round_style    => round_style,
+                           overflow_style => overflow_style);
+      return result;
+    end if;
+  end function to_ufixed;
+
+  function to_sfixed (
+    arg                     : REAL;     -- real
+    size_res                : UNRESOLVED_sfixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)  -- # of guard bits
+    return UNRESOLVED_sfixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_sfixed (size_res'left downto fw);
+  begin
+    if (result'length < 1) then
+      return NASF;
+    else
+      result := to_sfixed (arg            => arg,
+                           left_index     => size_res'high,
+                           right_index    => size_res'low,
+                           guard_bits     => guard_bits,
+                           round_style    => round_style,
+                           overflow_style => overflow_style);
+      return result;
+    end if;
+  end function to_sfixed;
+
+  function to_ufixed (
+    arg                     : UNRESOLVED_UNSIGNED;  -- unsigned
+    size_res                : UNRESOLVED_ufixed;    -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_ufixed (size_res'left downto fw);
+  begin
+    if (result'length < 1 or arg'length < 1) then
+      return NAUF;
+    else
+      result := to_ufixed (arg            => arg,
+                           left_index     => size_res'high,
+                           right_index    => size_res'low,
+                           round_style    => round_style,
+                           overflow_style => overflow_style);
+      return result;
+    end if;
+  end function to_ufixed;
+
+  function to_sfixed (
+    arg                     : UNRESOLVED_SIGNED;  -- signed
+    size_res                : UNRESOLVED_sfixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_sfixed (size_res'left downto fw);
+  begin
+    if (result'length < 1 or arg'length < 1) then
+      return NASF;
+    else
+      result := to_sfixed (arg            => arg,
+                           left_index     => size_res'high,
+                           right_index    => size_res'low,
+                           round_style    => round_style,
+                           overflow_style => overflow_style);
+      return result;
+    end if;
+  end function to_sfixed;
+
+  function resize (
+    arg                     : UNRESOLVED_ufixed;  -- input
+    size_res                : UNRESOLVED_ufixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_ufixed (size_res'high downto fw);
+  begin
+    if (result'length < 1 or arg'length < 1) then
+      return NAUF;
+    else
+      result := resize (arg            => arg,
+                        left_index     => size_res'high,
+                        right_index    => size_res'low,
+                        round_style    => round_style,
+                        overflow_style => overflow_style);
+      return result;
+    end if;
+  end function resize;
+
+  function resize (
+    arg                     : UNRESOLVED_sfixed;  -- input
+    size_res                : UNRESOLVED_sfixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed
+  is
+    constant fw     : INTEGER := mine (size_res'low, size_res'low);  -- catch literals
+    variable result : UNRESOLVED_sfixed (size_res'high downto fw);
+  begin
+    if (result'length < 1 or arg'length < 1) then
+      return NASF;
+    else
+      result := resize (arg            => arg,
+                        left_index     => size_res'high,
+                        right_index    => size_res'low,
+                        round_style    => round_style,
+                        overflow_style => overflow_style);
+      return result;
+    end if;
+  end function resize;
+
+  -- Overloaded math functions for real
+  function "+" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l + to_ufixed (r, l'high, l'low));
+  end function "+";
+
+  function "+" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, r'low) + r);
+  end function "+";
+
+  function "+" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l + to_sfixed (r, l'high, l'low));
+  end function "+";
+
+  function "+" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, r'low) + r);
+  end function "+";
+
+  function "-" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l - to_ufixed (r, l'high, l'low));
+  end function "-";
+
+  function "-" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, r'low) - r);
+  end function "-";
+
+  function "-" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l - to_sfixed (r, l'high, l'low));
+  end function "-";
+
+  function "-" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, r'low) - r);
+  end function "-";
+
+  function "*" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l * to_ufixed (r, l'high, l'low));
+  end function "*";
+
+  function "*" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, r'low) * r);
+  end function "*";
+
+  function "*" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l * to_sfixed (r, l'high, l'low));
+  end function "*";
+
+  function "*" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, r'low) * r);
+  end function "*";
+
+  function "/" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l / to_ufixed (r, l'high, l'low));
+  end function "/";
+
+  function "/" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, r'low) / r);
+  end function "/";
+
+  function "/" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l / to_sfixed (r, l'high, l'low));
+  end function "/";
+
+  function "/" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, r'low) / r);
+  end function "/";
+
+  function "rem" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l rem to_ufixed (r, l'high, l'low));
+  end function "rem";
+
+  function "rem" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, r'low) rem r);
+  end function "rem";
+
+  function "rem" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l rem to_sfixed (r, l'high, l'low));
+  end function "rem";
+
+  function "rem" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, r'low) rem r);
+  end function "rem";
+
+  function "mod" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l mod to_ufixed (r, l'high, l'low));
+  end function "mod";
+
+  function "mod" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, r'low) mod r);
+  end function "mod";
+
+  function "mod" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : REAL)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l mod to_sfixed (r, l'high, l'low));
+  end function "mod";
+
+  function "mod" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, r'low) mod r);
+  end function "mod";
+
+  -- Overloaded math functions for integers
+  function "+" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l + to_ufixed (r, l'high, 0));
+  end function "+";
+
+  function "+" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, 0) + r);
+  end function "+";
+
+  function "+" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : INTEGER)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l + to_sfixed (r, l'high, 0));
+  end function "+";
+
+  function "+" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, 0) + r);
+  end function "+";
+
+  -- Overloaded functions
+  function "-" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l - to_ufixed (r, l'high, 0));
+  end function "-";
+
+  function "-" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, 0) - r);
+  end function "-";
+
+  function "-" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : INTEGER)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l - to_sfixed (r, l'high, 0));
+  end function "-";
+
+  function "-" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, 0) - r);
+  end function "-";
+
+  -- Overloaded functions
+  function "*" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l * to_ufixed (r, l'high, 0));
+  end function "*";
+
+  function "*" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, 0) * r);
+  end function "*";
+
+  function "*" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : INTEGER)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l * to_sfixed (r, l'high, 0));
+  end function "*";
+
+  function "*" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, 0) * r);
+  end function "*";
+
+  -- Overloaded functions
+  function "/" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l / to_ufixed (r, l'high, 0));
+  end function "/";
+
+  function "/" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, 0) / r);
+  end function "/";
+
+  function "/" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : INTEGER)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l / to_sfixed (r, l'high, 0));
+  end function "/";
+
+  function "/" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, 0) / r);
+  end function "/";
+
+  function "rem" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l rem to_ufixed (r, l'high, 0));
+  end function "rem";
+
+  function "rem" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, 0) rem r);
+  end function "rem";
+
+  function "rem" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : INTEGER)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l rem to_sfixed (r, l'high, 0));
+  end function "rem";
+
+  function "rem" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, 0) rem r);
+  end function "rem";
+
+  function "mod" (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return (l mod to_ufixed (r, l'high, 0));
+  end function "mod";
+
+  function "mod" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return (to_ufixed (l, r'high, 0) mod r);
+  end function "mod";
+
+  function "mod" (
+    l : UNRESOLVED_sfixed;              -- fixed point input
+    r : INTEGER)
+    return UNRESOLVED_sfixed is
+  begin
+    return (l mod to_sfixed (r, l'high, 0));
+  end function "mod";
+
+  function "mod" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return UNRESOLVED_sfixed is
+  begin
+    return (to_sfixed (l, r'high, 0) mod r);
+  end function "mod";
+
+  -- overloaded ufixed compare functions with integer
+  function "=" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return BOOLEAN is
+  begin
+    return (l = to_ufixed (r, l'high, l'low));
+  end function "=";
+
+  function "/=" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return BOOLEAN is
+  begin
+    return (l /= to_ufixed (r, l'high, l'low));
+  end function "/=";
+
+  function ">=" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return BOOLEAN is
+  begin
+    return (l >= to_ufixed (r, l'high, l'low));
+  end function ">=";
+
+  function "<=" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return BOOLEAN is
+  begin
+    return (l <= to_ufixed (r, l'high, l'low));
+  end function "<=";
+
+  function ">" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return BOOLEAN is
+  begin
+    return (l > to_ufixed (r, l'high, l'low));
+  end function ">";
+
+  function "<" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return BOOLEAN is
+  begin
+    return (l < to_ufixed (r, l'high, l'low));
+  end function "<";
+
+  function "?=" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (l ?= to_ufixed (r, l'high, l'low));
+  end function "?=";
+
+  function "?/=" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (l ?/= to_ufixed (r, l'high, l'low));
+  end function "?/=";
+
+  function "?>=" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (l ?>= to_ufixed (r, l'high, l'low));
+  end function "?>=";
+
+  function "?<=" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (l ?<= to_ufixed (r, l'high, l'low));
+  end function "?<=";
+
+  function "?>" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (l ?> to_ufixed (r, l'high, l'low));
+  end function "?>";
+
+  function "?<" (
+    l : UNRESOLVED_ufixed;
+    r : NATURAL)                        -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (l ?< to_ufixed (r, l'high, l'low));
+  end function "?<";
+
+  function maximum (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return maximum (l, to_ufixed (r, l'high, l'low));
+  end function maximum;
+
+  function minimum (
+    l : UNRESOLVED_ufixed;              -- fixed point input
+    r : NATURAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return minimum (l, to_ufixed (r, l'high, l'low));
+  end function minimum;
+
+  -- NATURAL to ufixed
+  function "=" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) = r);
+  end function "=";
+
+  function "/=" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) /= r);
+  end function "/=";
+
+  function ">=" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) >= r);
+  end function ">=";
+
+  function "<=" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) <= r);
+  end function "<=";
+
+  function ">" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) > r);
+  end function ">";
+
+  function "<" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) < r);
+  end function "<";
+
+  function "?=" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?= r);
+  end function "?=";
+
+  function "?/=" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?/= r);
+  end function "?/=";
+
+  function "?>=" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?>= r);
+  end function "?>=";
+
+  function "?<=" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?<= r);
+  end function "?<=";
+
+  function "?>" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?> r);
+  end function "?>";
+
+  function "?<" (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?< r);
+  end function "?<";
+
+  function maximum (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return maximum (to_ufixed (l, r'high, r'low), r);
+  end function maximum;
+
+  function minimum (
+    l : NATURAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return minimum (to_ufixed (l, r'high, r'low), r);
+  end function minimum;
+
+  -- overloaded ufixed compare functions with real
+  function "=" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l = to_ufixed (r, l'high, l'low));
+  end function "=";
+
+  function "/=" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l /= to_ufixed (r, l'high, l'low));
+  end function "/=";
+
+  function ">=" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l >= to_ufixed (r, l'high, l'low));
+  end function ">=";
+
+  function "<=" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l <= to_ufixed (r, l'high, l'low));
+  end function "<=";
+
+  function ">" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l > to_ufixed (r, l'high, l'low));
+  end function ">";
+
+  function "<" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l < to_ufixed (r, l'high, l'low));
+  end function "<";
+
+  function "?=" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?= to_ufixed (r, l'high, l'low));
+  end function "?=";
+
+  function "?/=" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?/= to_ufixed (r, l'high, l'low));
+  end function "?/=";
+
+  function "?>=" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?>= to_ufixed (r, l'high, l'low));
+  end function "?>=";
+
+  function "?<=" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?<= to_ufixed (r, l'high, l'low));
+  end function "?<=";
+
+  function "?>" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?> to_ufixed (r, l'high, l'low));
+  end function "?>";
+
+  function "?<" (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?< to_ufixed (r, l'high, l'low));
+  end function "?<";
+
+  function maximum (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return maximum (l, to_ufixed (r, l'high, l'low));
+  end function maximum;
+
+  function minimum (
+    l : UNRESOLVED_ufixed;
+    r : REAL)
+    return UNRESOLVED_ufixed is
+  begin
+    return minimum (l, to_ufixed (r, l'high, l'low));
+  end function minimum;
+
+  -- real and ufixed
+  function "=" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) = r);
+  end function "=";
+
+  function "/=" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) /= r);
+  end function "/=";
+
+  function ">=" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) >= r);
+  end function ">=";
+
+  function "<=" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) <= r);
+  end function "<=";
+
+  function ">" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) > r);
+  end function ">";
+
+  function "<" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_ufixed (l, r'high, r'low) < r);
+  end function "<";
+
+  function "?=" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?= r);
+  end function "?=";
+
+  function "?/=" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?/= r);
+  end function "?/=";
+
+  function "?>=" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?>= r);
+  end function "?>=";
+
+  function "?<=" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?<= r);
+  end function "?<=";
+
+  function "?>" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?> r);
+  end function "?>";
+
+  function "?<" (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_ufixed (l, r'high, r'low) ?< r);
+  end function "?<";
+
+  function maximum (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return maximum (to_ufixed (l, r'high, r'low), r);
+  end function maximum;
+
+  function minimum (
+    l : REAL;
+    r : UNRESOLVED_ufixed)              -- fixed point input
+    return UNRESOLVED_ufixed is
+  begin
+    return minimum (to_ufixed (l, r'high, r'low), r);
+  end function minimum;
+
+  -- overloaded sfixed compare functions with integer
+  function "=" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return BOOLEAN is
+  begin
+    return (l = to_sfixed (r, l'high, l'low));
+  end function "=";
+
+  function "/=" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return BOOLEAN is
+  begin
+    return (l /= to_sfixed (r, l'high, l'low));
+  end function "/=";
+
+  function ">=" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return BOOLEAN is
+  begin
+    return (l >= to_sfixed (r, l'high, l'low));
+  end function ">=";
+
+  function "<=" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return BOOLEAN is
+  begin
+    return (l <= to_sfixed (r, l'high, l'low));
+  end function "<=";
+
+  function ">" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return BOOLEAN is
+  begin
+    return (l > to_sfixed (r, l'high, l'low));
+  end function ">";
+
+  function "<" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return BOOLEAN is
+  begin
+    return (l < to_sfixed (r, l'high, l'low));
+  end function "<";
+
+  function "?=" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return STD_ULOGIC is
+  begin
+    return (l ?= to_sfixed (r, l'high, l'low));
+  end function "?=";
+
+  function "?/=" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return STD_ULOGIC is
+  begin
+    return (l ?/= to_sfixed (r, l'high, l'low));
+  end function "?/=";
+
+  function "?>=" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return STD_ULOGIC is
+  begin
+    return (l ?>= to_sfixed (r, l'high, l'low));
+  end function "?>=";
+
+  function "?<=" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return STD_ULOGIC is
+  begin
+    return (l ?<= to_sfixed (r, l'high, l'low));
+  end function "?<=";
+
+  function "?>" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return STD_ULOGIC is
+  begin
+    return (l ?> to_sfixed (r, l'high, l'low));
+  end function "?>";
+
+  function "?<" (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return STD_ULOGIC is
+  begin
+    return (l ?< to_sfixed (r, l'high, l'low));
+  end function "?<";
+
+  function maximum (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return UNRESOLVED_sfixed is
+  begin
+    return maximum (l, to_sfixed (r, l'high, l'low));
+  end function maximum;
+
+  function minimum (
+    l : UNRESOLVED_sfixed;
+    r : INTEGER)
+    return UNRESOLVED_sfixed is
+  begin
+    return minimum (l, to_sfixed (r, l'high, l'low));
+  end function minimum;
+
+  -- integer and sfixed
+  function "=" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) = r);
+  end function "=";
+
+  function "/=" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) /= r);
+  end function "/=";
+
+  function ">=" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) >= r);
+  end function ">=";
+
+  function "<=" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) <= r);
+  end function "<=";
+
+  function ">" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) > r);
+  end function ">";
+
+  function "<" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) < r);
+  end function "<";
+
+  function "?=" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?= r);
+  end function "?=";
+
+  function "?/=" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?/= r);
+  end function "?/=";
+
+  function "?>=" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?>= r);
+  end function "?>=";
+
+  function "?<=" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?<= r);
+  end function "?<=";
+
+  function "?>" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?> r);
+  end function "?>";
+
+  function "?<" (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?< r);
+  end function "?<";
+
+  function maximum (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return maximum (to_sfixed (l, r'high, r'low), r);
+  end function maximum;
+
+  function minimum (
+    l : INTEGER;
+    r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return minimum (to_sfixed (l, r'high, r'low), r);
+  end function minimum;
+
+  -- overloaded sfixed compare functions with real
+  function "=" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l = to_sfixed (r, l'high, l'low));
+  end function "=";
+
+  function "/=" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l /= to_sfixed (r, l'high, l'low));
+  end function "/=";
+
+  function ">=" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l >= to_sfixed (r, l'high, l'low));
+  end function ">=";
+
+  function "<=" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l <= to_sfixed (r, l'high, l'low));
+  end function "<=";
+
+  function ">" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l > to_sfixed (r, l'high, l'low));
+  end function ">";
+
+  function "<" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return BOOLEAN is
+  begin
+    return (l < to_sfixed (r, l'high, l'low));
+  end function "<";
+
+  function "?=" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?= to_sfixed (r, l'high, l'low));
+  end function "?=";
+
+  function "?/=" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?/= to_sfixed (r, l'high, l'low));
+  end function "?/=";
+
+  function "?>=" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?>= to_sfixed (r, l'high, l'low));
+  end function "?>=";
+
+  function "?<=" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?<= to_sfixed (r, l'high, l'low));
+  end function "?<=";
+
+  function "?>" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?> to_sfixed (r, l'high, l'low));
+  end function "?>";
+
+  function "?<" (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return STD_ULOGIC is
+  begin
+    return (l ?< to_sfixed (r, l'high, l'low));
+  end function "?<";
+
+  function maximum (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return UNRESOLVED_sfixed is
+  begin
+    return maximum (l, to_sfixed (r, l'high, l'low));
+  end function maximum;
+
+  function minimum (
+    l : UNRESOLVED_sfixed;
+    r : REAL)
+    return UNRESOLVED_sfixed is
+  begin
+    return minimum (l, to_sfixed (r, l'high, l'low));
+  end function minimum;
+
+  -- REAL and sfixed
+  function "=" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) = r);
+  end function "=";
+
+  function "/=" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) /= r);
+  end function "/=";
+
+  function ">=" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) >= r);
+  end function ">=";
+
+  function "<=" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) <= r);
+  end function "<=";
+
+  function ">" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) > r);
+  end function ">";
+
+  function "<" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return BOOLEAN is
+  begin
+    return (to_sfixed (l, r'high, r'low) < r);
+  end function "<";
+
+  function "?=" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?= r);
+  end function "?=";
+
+  function "?/=" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?/= r);
+  end function "?/=";
+
+  function "?>=" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?>= r);
+  end function "?>=";
+
+  function "?<=" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?<= r);
+  end function "?<=";
+
+  function "?>" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?> r);
+  end function "?>";
+
+  function "?<" (
+    l : REAL;
+    r : UNRESOLVED_sfixed)              -- fixed point input
+    return STD_ULOGIC is
+  begin
+    return (to_sfixed (l, r'high, r'low) ?< r);
+  end function "?<";
+
+  function maximum (
+    l : REAL;
+    r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return maximum (to_sfixed (l, r'high, r'low), r);
+  end function maximum;
+
+  function minimum (
+    l : REAL;
+    r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return minimum (to_sfixed (l, r'high, r'low), r);
+  end function minimum;
+
+  -- copied from std_logic_textio
+  type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
+  type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
+  type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
+  type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
+
+  constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
+  constant char_to_MVL9 : MVL9_indexed_by_char :=
+    ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
+     'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
+  constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
+    ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
+     'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
+  constant NBSP : CHARACTER      := CHARACTER'val(160);  -- space character
+  constant NUS  : STRING(2 to 1) := (others => ' ');
+
+  -- purpose: Skips white space
+  procedure skip_whitespace (
+    L : inout LINE) is
+    variable c : CHARACTER;
+    variable left : positive;
+  begin
+    while L /= null and L.all'length /= 0 loop
+      left := L.all'left;
+      c := L.all(left);
+      if (c = ' ' or c = NBSP or c = HT) then
+        read (L, c);
+      else
+        exit;
+      end if;
+    end loop;
+  end procedure skip_whitespace;
+
+  -- purpose: writes fixed point into a line
+  procedure write (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_ufixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0) is
+    variable s     : STRING(1 to VALUE'length +1) := (others => ' ');
+    variable sindx : INTEGER;
+  begin  -- function write   Example: 0011.1100
+    sindx := 1;
+    for i in VALUE'high downto VALUE'low loop
+      if i = -1 then
+        s(sindx) := '.';
+        sindx    := sindx + 1;
+      end if;
+      s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
+      sindx    := sindx + 1;
+    end loop;
+    write(L, s, JUSTIFIED, FIELD);
+  end procedure write;
+
+  -- purpose: writes fixed point into a line
+  procedure write (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_sfixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0) is
+    variable s     : STRING(1 to VALUE'length +1);
+    variable sindx : INTEGER;
+  begin  -- function write   Example: 0011.1100
+    sindx := 1;
+    for i in VALUE'high downto VALUE'low loop
+      if i = -1 then
+        s(sindx) := '.';
+        sindx    := sindx + 1;
+      end if;
+      s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
+      sindx    := sindx + 1;
+    end loop;
+    write(L, s, JUSTIFIED, FIELD);
+  end procedure write;
+
+  procedure READ(L     : inout LINE;
+                 VALUE : out   UNRESOLVED_ufixed) is
+    -- Possible data:  00000.0000000
+    --                 000000000000
+    variable c      : CHARACTER;
+    variable readOk : BOOLEAN;
+    variable i      : INTEGER;          -- index variable
+    variable mv : ufixed (VALUE'range);
+    variable lastu  : BOOLEAN := false;       -- last character was an "_"
+    variable founddot : BOOLEAN := false;  -- found a "."
+  begin  -- READ
+    VALUE := (VALUE'range => 'U');
+    skip_whitespace (L);
+    if VALUE'length > 0 then            -- non Null input string
+      read (L, c, readOk);
+      i := VALUE'high;
+      while i >= VALUE'low loop
+        if readOk = false then              -- Bail out if there was a bad read
+          report fixed_generic_pkg'instance_name & "READ(ufixed) "
+            & "End of string encountered"
+            severity error;
+          return;
+        elsif c = '_' then
+          if i = VALUE'high then
+            report fixed_generic_pkg'instance_name & "READ(ufixed) "
+              & "String begins with an ""_""" severity error;
+            return;
+          elsif lastu then
+            report fixed_generic_pkg'instance_name & "READ(ufixed) "
+              & "Two underscores detected in input string ""__"""
+              severity error;
+            return;
+          else
+            lastu := true;
+          end if;
+        elsif c = '.' then                -- binary point
+          if founddot then
+            report fixed_generic_pkg'instance_name & "READ(ufixed) "
+              & "Two binary points found in input string" severity error;
+            return;
+          elsif i /= -1 then                 -- Seperator in the wrong spot
+            report fixed_generic_pkg'instance_name & "READ(ufixed) "
+              & "Decimal point does not match number format "
+              severity error;
+            return;
+          end if;
+          founddot := true;
+          lastu := false;
+        elsif c = ' ' or c = NBSP or c = HT then  -- reading done.
+          report fixed_generic_pkg'instance_name & "READ(ufixed) "
+            & "Short read, Space encounted in input string"
+            severity error;
+          return;
+        elsif char_to_MVL9plus(c) = error then
+          report fixed_generic_pkg'instance_name & "READ(ufixed) "
+            & "Character '" &
+            c & "' read, expected STD_ULOGIC literal."
+            severity error;
+          return;
+        else
+          mv(i) := char_to_MVL9(c);
+          i := i - 1;
+          if i < mv'low then
+            VALUE := mv;
+            return;
+          end if;
+          lastu := false;
+        end if;
+        read(L, c, readOk);
+      end loop;
+    end if;
+  end procedure READ;
+
+  procedure READ(L     : inout LINE;
+                 VALUE : out   UNRESOLVED_ufixed;
+                 GOOD  : out   BOOLEAN) is
+    -- Possible data:  00000.0000000
+    --                 000000000000
+    variable c      : CHARACTER;
+    variable readOk : BOOLEAN;
+    variable mv : ufixed (VALUE'range);
+    variable i      : INTEGER;          -- index variable
+    variable lastu  : BOOLEAN := false;       -- last character was an "_"
+    variable founddot : BOOLEAN := false;  -- found a "."
+  begin  -- READ
+    VALUE := (VALUE'range => 'U');
+    skip_whitespace (L);
+    if VALUE'length > 0 then
+      read (L, c, readOk);
+      i := VALUE'high;
+      GOOD := false;
+      while i >= VALUE'low loop
+        if not readOk then     -- Bail out if there was a bad read
+          return;
+        elsif c = '_' then
+          if i = VALUE'high then          -- Begins with an "_"
+            return;
+          elsif lastu then               -- "__" detected
+            return;
+          else
+            lastu := true;
+          end if;
+        elsif c = '.' then                -- binary point
+          if founddot then
+            return;
+          elsif i /= -1 then                 -- Seperator in the wrong spot
+            return;
+          end if;
+          founddot := true;
+          lastu := false;
+        elsif (char_to_MVL9plus(c) = error) then   -- Illegal character/short read
+          return;
+        else
+          mv(i) := char_to_MVL9(c);
+          i := i - 1;
+          if i < mv'low then             -- reading done
+            GOOD := true;
+            VALUE := mv;
+            return;
+          end if;
+          lastu := false;
+        end if;
+        read(L, c, readOk);
+      end loop;
+    else
+      GOOD := true;                   -- read into a null array
+    end if;
+  end procedure READ;
+
+  procedure READ(L     : inout LINE;
+                 VALUE : out   UNRESOLVED_sfixed) is
+    variable c      : CHARACTER;
+    variable readOk : BOOLEAN;
+    variable i      : INTEGER;          -- index variable
+    variable mv : sfixed (VALUE'range);
+    variable lastu  : BOOLEAN := false;       -- last character was an "_"
+    variable founddot : BOOLEAN := false;  -- found a "."
+  begin  -- READ
+    VALUE := (VALUE'range => 'U');
+    skip_whitespace (L);
+    if VALUE'length > 0 then            -- non Null input string
+      read (L, c, readOk);
+      i := VALUE'high;
+      while i >= VALUE'low loop
+        if readOk = false then              -- Bail out if there was a bad read
+          report fixed_generic_pkg'instance_name & "READ(sfixed) "
+            & "End of string encountered"
+            severity error;
+          return;
+        elsif c = '_' then
+          if i = VALUE'high then
+            report fixed_generic_pkg'instance_name & "READ(sfixed) "
+              & "String begins with an ""_""" severity error;
+            return;
+          elsif lastu then
+            report fixed_generic_pkg'instance_name & "READ(sfixed) "
+              & "Two underscores detected in input string ""__"""
+              severity error;
+            return;
+          else
+            lastu := true;
+          end if;
+        elsif c = '.' then                -- binary point
+          if founddot then
+            report fixed_generic_pkg'instance_name & "READ(sfixed) "
+              & "Two binary points found in input string" severity error;
+            return;
+          elsif i /= -1 then                 -- Seperator in the wrong spot
+            report fixed_generic_pkg'instance_name & "READ(sfixed) "
+              & "Decimal point does not match number format "
+              severity error;
+            return;
+          end if;
+          founddot := true;
+          lastu := false;
+        elsif c = ' ' or c = NBSP or c = HT then  -- reading done.
+          report fixed_generic_pkg'instance_name & "READ(sfixed) "
+            & "Short read, Space encounted in input string"
+            severity error;
+          return;
+        elsif char_to_MVL9plus(c) = error then
+          report fixed_generic_pkg'instance_name & "READ(sfixed) "
+            & "Character '" &
+            c & "' read, expected STD_ULOGIC literal."
+            severity error;
+          return;
+        else
+          mv(i) := char_to_MVL9(c);
+          i := i - 1;
+          if i < mv'low then
+            VALUE := mv;
+            return;
+          end if;
+          lastu := false;
+        end if;
+        read(L, c, readOk);
+      end loop;
+    end if;
+  end procedure READ;
+
+  procedure READ(L     : inout LINE;
+                 VALUE : out   UNRESOLVED_sfixed;
+                 GOOD  : out   BOOLEAN) is
+    variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
+  begin  -- READ
+    READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
+    VALUE := UNRESOLVED_sfixed (value_ufixed);
+  end procedure READ;
+
+  -- octal read and write
+  procedure owrite (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_ufixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0) is
+  begin  -- Example 03.30
+    write (L         => L,
+           VALUE     => TO_OSTRING (VALUE),
+           JUSTIFIED => JUSTIFIED,
+           FIELD     => FIELD);
+  end procedure owrite;
+
+  procedure owrite (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_sfixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0) is
+  begin  -- Example 03.30
+    write (L         => L,
+           VALUE     => TO_OSTRING (VALUE),
+           JUSTIFIED => JUSTIFIED,
+           FIELD     => FIELD);
+  end procedure owrite;
+
+  -- Note that for Octal and Hex read, you can not start with a ".",
+  -- the read is for numbers formatted "A.BC".  These routines go to
+  -- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
+  procedure Char2TriBits (C           :     CHARACTER;
+                          RESULT      : out STD_ULOGIC_VECTOR(2 downto 0);
+                          GOOD        : out BOOLEAN;
+                          ISSUE_ERROR : in  BOOLEAN) is
+  begin
+    case C is
+      when '0' => RESULT := o"0"; GOOD := true;
+      when '1' => RESULT := o"1"; GOOD := true;
+      when '2' => RESULT := o"2"; GOOD := true;
+      when '3' => RESULT := o"3"; GOOD := true;
+      when '4' => RESULT := o"4"; GOOD := true;
+      when '5' => RESULT := o"5"; GOOD := true;
+      when '6' => RESULT := o"6"; GOOD := true;
+      when '7' => RESULT := o"7"; GOOD := true;
+      when 'Z' => RESULT := "ZZZ"; GOOD := true;
+      when 'X' => RESULT := "XXX"; GOOD := true;
+      when others =>
+        assert not ISSUE_ERROR
+          report fixed_generic_pkg'instance_name
+          & "OREAD Error: Read a '" & C &
+          "', expected an Octal character (0-7)."
+          severity error;
+        RESULT := "UUU";
+        GOOD   := false;
+    end case;
+  end procedure Char2TriBits;
+
+  -- purpose: Routines common to the OREAD routines
+  procedure OREAD_common (
+    L                : inout LINE;
+    slv              : out   STD_ULOGIC_VECTOR;
+    igood            : out   BOOLEAN;
+    idex             : out INTEGER;
+    constant bpoint : in INTEGER;       -- binary point
+    constant message : in    BOOLEAN;
+    constant smath   : in    BOOLEAN) is
+
+    -- purpose: error message routine
+    procedure errmes (
+      constant mess : in STRING) is     -- error message
+    begin
+      if message then
+        if smath then
+          report fixed_generic_pkg'instance_name
+            & "OREAD(sfixed) "
+            & mess
+            severity error;
+        else
+          report fixed_generic_pkg'instance_name
+            & "OREAD(ufixed) "
+            & mess
+            severity error;
+        end if;
+      end if;
+    end procedure errmes;
+    variable xgood : BOOLEAN;
+    variable nybble : STD_ULOGIC_VECTOR (2 downto 0);        -- 3 bits
+    variable c : CHARACTER;
+    variable i : INTEGER;
+    variable lastu  : BOOLEAN := false;       -- last character was an "_"
+    variable founddot : BOOLEAN := false;  -- found a dot.
+  begin
+    skip_whitespace (L);
+    if slv'length > 0 then
+      i := slv'high;
+      read (L, c, xgood);
+      while i > 0 loop
+        if xgood = false then
+          errmes ("Error: end of string encountered");
+          exit;
+        elsif c = '_' then
+          if i = slv'length then
+            errmes ("Error: String begins with an ""_""");
+            xgood := false;
+            exit;
+          elsif lastu then
+            errmes ("Error: Two underscores detected in input string ""__""");
+            xgood := false;
+            exit;
+          else
+            lastu := true;
+          end if;
+        elsif (c = '.') then
+          if (i + 1 /= bpoint) then
+            errmes ("encountered ""."" at wrong index");
+            xgood := false;
+            exit;
+          elsif i = slv'length then
+            errmes ("encounted a ""."" at the beginning of the line");
+            xgood := false;
+            exit;
+          elsif founddot then
+            errmes ("Two ""."" encounted in input string");
+            xgood := false;
+            exit;
+          end if;
+          founddot := true;
+          lastu := false;
+        else
+          Char2TriBits(c, nybble, xgood, message);
+          if not xgood then
+            exit;
+          end if;
+          slv (i downto i-2) := nybble;
+          i := i - 3;
+          lastu := false;
+        end if;
+        if i > 0 then
+          read (L, c, xgood);
+        end if;
+      end loop;
+      idex := i;
+      igood := xgood;
+    else
+      igood := true;                  -- read into a null array
+      idex := -1;
+    end if;
+  end procedure OREAD_common;
+
+  -- Note that for Octal and Hex read, you can not start with a ".",
+  -- the read is for numbers formatted "A.BC".  These routines go to
+  -- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
+  procedure OREAD (L     : inout LINE;
+                   VALUE : out   UNRESOLVED_ufixed) is
+    constant hbv    : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
+    constant lbv    : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
+    variable slv    : STD_ULOGIC_VECTOR (hbv-lbv downto 0);  -- high bits
+    variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
+    variable igood  : BOOLEAN;
+    variable i      : INTEGER;
+  begin
+    VALUE := (VALUE'range => 'U');
+    OREAD_common ( L => L,
+                   slv => slv,
+                   igood => igood,
+                   idex => i,
+                   bpoint => -lbv,
+                   message => true,
+                   smath => false);
+    if igood then                       -- We did not get another error
+      if not ((i = -1) and               -- We read everything, and high bits 0
+              (or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
+        report fixed_generic_pkg'instance_name
+          & "OREAD(ufixed): Vector truncated."
+          severity error;
+      else
+        if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
+          assert no_warning
+            report fixed_generic_pkg'instance_name
+            & "OREAD(ufixed): Vector truncated"
+            severity warning;
+        end if;
+        valuex := to_ufixed (slv, hbv, lbv);
+        VALUE  := valuex (VALUE'range);
+      end if;
+    end if;
+  end procedure OREAD;
+
+  procedure OREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_ufixed;
+                  GOOD  : out   BOOLEAN) is
+    constant hbv    : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
+    constant lbv    : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
+    variable slv    : STD_ULOGIC_VECTOR (hbv-lbv downto 0);  -- high bits
+    variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
+    variable igood  : BOOLEAN;
+    variable i      : INTEGER;
+  begin
+    VALUE := (VALUE'range => 'U');
+    OREAD_common ( L => L,
+                   slv => slv,
+                   igood => igood,
+                   idex => i,
+                   bpoint => -lbv,
+                   message => false,
+                   smath => false);
+    if (igood and                   -- We did not get another error
+        (i = -1) and                -- We read everything, and high bits 0
+        (or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
+      valuex := to_ufixed (slv, hbv, lbv);
+      VALUE  := valuex (VALUE'range);
+      GOOD := true;
+    else
+      GOOD := false;
+    end if;
+  end procedure OREAD;
+
+  procedure OREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_sfixed) is
+    constant hbv    : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
+    constant lbv    : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
+    variable slv    : STD_ULOGIC_VECTOR (hbv-lbv downto 0);  -- high bits
+    variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
+    variable igood  : BOOLEAN;
+    variable i      : INTEGER;
+  begin
+    VALUE := (VALUE'range => 'U');
+    OREAD_common ( L => L,
+                   slv => slv,
+                   igood => igood,
+                   idex => i,
+                   bpoint => -lbv,
+                   message => true,
+                   smath => true);
+    if igood then                       -- We did not get another error
+      if not ((i = -1) and               -- We read everything
+              ((slv(VALUE'high-lbv) = '0' and      -- sign bits = extra bits
+                or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
+               (slv(VALUE'high-lbv) = '1' and
+                and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
+        report fixed_generic_pkg'instance_name
+          & "OREAD(sfixed): Vector truncated."
+          severity error;
+      else
+        if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
+          assert no_warning
+            report fixed_generic_pkg'instance_name
+            & "OREAD(sfixed): Vector truncated"
+            severity warning;
+        end if;
+        valuex := to_sfixed (slv, hbv, lbv);
+        VALUE  := valuex (VALUE'range);
+      end if;
+    end if;
+  end procedure OREAD;
+
+  procedure OREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_sfixed;
+                  GOOD  : out   BOOLEAN) is
+    constant hbv    : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
+    constant lbv    : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
+    variable slv    : STD_ULOGIC_VECTOR (hbv-lbv downto 0);  -- high bits
+    variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
+    variable igood  : BOOLEAN;
+    variable i      : INTEGER;
+  begin
+    VALUE := (VALUE'range => 'U');
+    OREAD_common ( L => L,
+                   slv => slv,
+                   igood => igood,
+                   idex => i,
+                   bpoint => -lbv,
+                   message => false,
+                   smath => true);
+    if (igood                       -- We did not get another error
+        and (i = -1)                -- We read everything
+        and ((slv(VALUE'high-lbv) = '0' and  -- sign bits = extra bits
+              or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
+             (slv(VALUE'high-lbv) = '1' and
+              and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
+      valuex := to_sfixed (slv, hbv, lbv);
+      VALUE  := valuex (VALUE'range);
+      GOOD := true;
+    else
+      GOOD := false;
+    end if;
+  end procedure OREAD;
+
+  -- hex read and write
+  procedure hwrite (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_ufixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0) is
+  begin  -- Example 03.30
+    write (L         => L,
+           VALUE     => TO_HSTRING (VALUE),
+           JUSTIFIED => JUSTIFIED,
+           FIELD     => FIELD);
+  end procedure hwrite;
+
+  -- purpose: writes fixed point into a line
+  procedure hwrite (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_sfixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0) is
+  begin  -- Example 03.30
+    write (L         => L,
+           VALUE     => TO_HSTRING (VALUE),
+           JUSTIFIED => JUSTIFIED,
+           FIELD     => FIELD);
+  end procedure hwrite;
+
+  -- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
+  -- Modified from the original to be more forgiving.
+
+  procedure Char2QuadBits (C           :     CHARACTER;
+                           RESULT      : out STD_ULOGIC_VECTOR(3 downto 0);
+                           GOOD        : out BOOLEAN;
+                           ISSUE_ERROR : in  BOOLEAN) is
+  begin
+    case C is
+      when '0'       => RESULT := x"0"; GOOD := true;
+      when '1'       => RESULT := x"1"; GOOD := true;
+      when '2'       => RESULT := x"2"; GOOD := true;
+      when '3'       => RESULT := x"3"; GOOD := true;
+      when '4'       => RESULT := x"4"; GOOD := true;
+      when '5'       => RESULT := x"5"; GOOD := true;
+      when '6'       => RESULT := x"6"; GOOD := true;
+      when '7'       => RESULT := x"7"; GOOD := true;
+      when '8'       => RESULT := x"8"; GOOD := true;
+      when '9'       => RESULT := x"9"; GOOD := true;
+      when 'A' | 'a' => RESULT := x"A"; GOOD := true;
+      when 'B' | 'b' => RESULT := x"B"; GOOD := true;
+      when 'C' | 'c' => RESULT := x"C"; GOOD := true;
+      when 'D' | 'd' => RESULT := x"D"; GOOD := true;
+      when 'E' | 'e' => RESULT := x"E"; GOOD := true;
+      when 'F' | 'f' => RESULT := x"F"; GOOD := true;
+      when 'Z'       => RESULT := "ZZZZ"; GOOD := true;
+      when 'X'       => RESULT := "XXXX"; GOOD := true;
+      when others =>
+        assert not ISSUE_ERROR
+          report fixed_generic_pkg'instance_name
+          & "HREAD Error: Read a '" & C &
+          "', expected a Hex character (0-F)."
+          severity error;
+        RESULT := "UUUU";
+        GOOD   := false;
+    end case;
+  end procedure Char2QuadBits;
+
+  -- purpose: Routines common to the HREAD routines
+  procedure HREAD_common (
+    L                : inout LINE;
+    slv              : out   STD_ULOGIC_VECTOR;
+    igood            : out   BOOLEAN;
+    idex             : out INTEGER;
+    constant bpoint : in INTEGER;       -- binary point
+    constant message : in    BOOLEAN;
+    constant smath   : in    BOOLEAN) is
+
+    -- purpose: error message routine
+    procedure errmes (
+      constant mess : in STRING) is     -- error message
+    begin
+      if message then
+        if smath then
+          report fixed_generic_pkg'instance_name
+            & "HREAD(sfixed) "
+            & mess
+            severity error;
+        else
+          report fixed_generic_pkg'instance_name
+            & "HREAD(ufixed) "
+            & mess
+            severity error;
+        end if;
+      end if;
+    end procedure errmes;
+    variable xgood  : BOOLEAN;
+    variable nybble : STD_ULOGIC_VECTOR (3 downto 0);        -- 4 bits
+    variable c      : CHARACTER;
+    variable i      : INTEGER;
+    variable lastu  : BOOLEAN := false;       -- last character was an "_"
+    variable founddot : BOOLEAN := false;  -- found a dot.
+  begin
+    skip_whitespace (L);
+    if slv'length > 0 then
+      i := slv'high;
+      read (L, c, xgood);
+      while i > 0 loop
+        if xgood = false then
+          errmes ("Error: end of string encountered");
+          exit;
+        elsif c = '_' then
+          if i = slv'length then
+            errmes ("Error: String begins with an ""_""");
+            xgood := false;
+            exit;
+          elsif lastu then
+            errmes ("Error: Two underscores detected in input string ""__""");
+            xgood := false;
+            exit;
+          else
+            lastu := true;
+          end if;
+        elsif (c = '.') then
+          if (i + 1 /= bpoint) then
+            errmes ("encountered ""."" at wrong index");
+            xgood := false;
+            exit;
+          elsif i = slv'length then
+            errmes ("encounted a ""."" at the beginning of the line");
+            xgood := false;
+            exit;
+          elsif founddot then
+            errmes ("Two ""."" encounted in input string");
+            xgood := false;
+            exit;
+          end if;
+          founddot := true;
+          lastu := false;
+        else
+          Char2QuadBits(c, nybble, xgood, message);
+          if not xgood then
+            exit;
+          end if;
+          slv (i downto i-3) := nybble;
+          i := i - 4;
+          lastu := false;
+        end if;
+        if i > 0 then
+          read (L, c, xgood);
+        end if;
+      end loop;
+      idex := i;
+      igood := xgood;
+    else
+      idex := -1;
+      igood := true;                    -- read null string
+    end if;
+  end procedure HREAD_common;
+
+  procedure HREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_ufixed) is
+    constant hbv    : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
+    constant lbv    : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
+    variable slv    : STD_ULOGIC_VECTOR (hbv-lbv downto 0);  -- high bits
+    variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
+    variable igood  : BOOLEAN;
+    variable i      : INTEGER;
+  begin
+    VALUE := (VALUE'range => 'U');
+    HREAD_common ( L => L,
+                   slv => slv,
+                   igood => igood,
+                   idex => i,
+                   bpoint => -lbv,
+                   message => true,
+                   smath => false);
+    if igood then
+      if not ((i = -1) and               -- We read everything, and high bits 0
+              (or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
+        report fixed_generic_pkg'instance_name
+          & "HREAD(ufixed): Vector truncated."
+          severity error;
+      else
+        if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
+          assert no_warning
+            report fixed_generic_pkg'instance_name
+            & "HREAD(ufixed): Vector truncated"
+            severity warning;
+        end if;
+        valuex := to_ufixed (slv, hbv, lbv);
+        VALUE  := valuex (VALUE'range);
+      end if;
+    end if;
+  end procedure HREAD;
+
+  procedure HREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_ufixed;
+                  GOOD  : out   BOOLEAN) is
+    constant hbv    : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
+    constant lbv    : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
+    variable slv    : STD_ULOGIC_VECTOR (hbv-lbv downto 0);  -- high bits
+    variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
+    variable igood  : BOOLEAN;
+    variable i      : INTEGER;
+  begin
+    VALUE := (VALUE'range => 'U');
+    HREAD_common ( L => L,
+                   slv => slv,
+                   igood => igood,
+                   idex => i,
+                   bpoint => -lbv,
+                   message => false,
+                   smath => false);
+    if (igood and                   -- We did not get another error
+        (i = -1) and                -- We read everything, and high bits 0
+        (or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
+      valuex := to_ufixed (slv, hbv, lbv);
+      VALUE  := valuex (VALUE'range);
+      GOOD := true;
+    else
+      GOOD := false;
+    end if;
+  end procedure HREAD;
+
+  procedure HREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_sfixed) is
+    constant hbv    : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
+    constant lbv    : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
+    variable slv    : STD_ULOGIC_VECTOR (hbv-lbv downto 0);  -- high bits
+    variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
+    variable igood  : BOOLEAN;
+    variable i      : INTEGER;
+  begin
+    VALUE := (VALUE'range => 'U');
+    HREAD_common ( L => L,
+                   slv => slv,
+                   igood => igood,
+                   idex => i,
+                   bpoint => -lbv,
+                   message => true,
+                   smath => true);
+    if igood then                       -- We did not get another error
+      if not ((i = -1)                   -- We read everything
+              and ((slv(VALUE'high-lbv) = '0' and  -- sign bits = extra bits
+                    or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
+                   (slv(VALUE'high-lbv) = '1' and
+                    and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
+        report fixed_generic_pkg'instance_name
+          & "HREAD(sfixed): Vector truncated."
+          severity error;
+      else
+        if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
+          assert no_warning
+            report fixed_generic_pkg'instance_name
+            & "HREAD(sfixed): Vector truncated"
+            severity warning;
+        end if;
+        valuex := to_sfixed (slv, hbv, lbv);
+        VALUE  := valuex (VALUE'range);
+      end if;
+    end if;
+  end procedure HREAD;
+
+  procedure HREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_sfixed;
+                  GOOD  : out   BOOLEAN) is
+    constant hbv    : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
+    constant lbv    : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
+    variable slv    : STD_ULOGIC_VECTOR (hbv-lbv downto 0);  -- high bits
+    variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
+    variable igood  : BOOLEAN;
+    variable i      : INTEGER;
+  begin
+    VALUE := (VALUE'range => 'U');
+    HREAD_common ( L => L,
+                   slv => slv,
+                   igood => igood,
+                   idex => i,
+                   bpoint => -lbv,
+                   message => false,
+                   smath => true);
+    if (igood and                   -- We did not get another error
+        (i = -1) and                -- We read everything
+        ((slv(VALUE'high-lbv) = '0' and  -- sign bits = extra bits
+          or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
+         (slv(VALUE'high-lbv) = '1' and
+          and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
+      valuex := to_sfixed (slv, hbv, lbv);
+      VALUE  := valuex (VALUE'range);
+      GOOD := true;
+    else
+      GOOD := false;
+    end if;
+  end procedure HREAD;
+
+  -- TO_STRING functions.  Useful in "report" statements.
+  -- Example:  report "result was " & TO_STRING(result);
+  function TO_STRING (value : UNRESOLVED_ufixed) return STRING is
+    variable s     : STRING(1 to value'length +1) := (others => ' ');
+    variable subval : UNRESOLVED_ufixed (value'high downto -1);
+    variable sindx : INTEGER;
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      if value'high < 0 then
+        if value(value'high) = 'Z' then
+          return TO_STRING (resize (sfixed(value), 0, value'low));
+        else
+          return TO_STRING (resize (value, 0, value'low));
+        end if;
+      elsif value'low >= 0 then
+        if Is_X (value(value'low)) then
+          subval := (others => value(value'low));
+          subval (value'range) := value;
+          return TO_STRING(subval);
+        else
+          return TO_STRING (resize (value, value'high, -1));
+        end if;
+      else
+        sindx := 1;
+        for i in value'high downto value'low loop
+          if i = -1 then
+            s(sindx) := '.';
+            sindx    := sindx + 1;
+          end if;
+          s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
+          sindx    := sindx + 1;
+        end loop;
+        return s;
+      end if;
+    end if;
+  end function TO_STRING;
+
+  function TO_STRING (value : UNRESOLVED_sfixed) return STRING is
+    variable s     : STRING(1 to value'length + 1) := (others => ' ');
+    variable subval : UNRESOLVED_sfixed (value'high downto -1);
+    variable sindx : INTEGER;
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      if value'high < 0 then
+        return TO_STRING (resize (value, 0, value'low));
+      elsif value'low >= 0 then
+        if Is_X (value(value'low)) then
+          subval := (others => value(value'low));
+          subval (value'range) := value;
+          return TO_STRING(subval);
+        else
+          return TO_STRING (resize (value, value'high, -1));
+        end if;
+      else
+        sindx := 1;
+        for i in value'high downto value'low loop
+          if i = -1 then
+            s(sindx) := '.';
+            sindx    := sindx + 1;
+          end if;
+          s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
+          sindx    := sindx + 1;
+        end loop;
+        return s;
+      end if;
+    end if;
+  end function TO_STRING;
+
+  function TO_OSTRING (value : UNRESOLVED_ufixed) return STRING is
+    constant lne  : INTEGER := (-value'low+2)/3;
+    variable subval : UNRESOLVED_ufixed (value'high downto -3);
+    variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + value'low) -1);
+    variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      if value'high < 0 then
+        if value(value'high) = 'Z' then
+          return TO_OSTRING (resize (sfixed(value), 2, value'low));
+        else
+          return TO_OSTRING (resize (value, 2, value'low));
+        end if;
+      elsif value'low >= 0 then
+        if Is_X (value(value'low)) then
+          subval := (others => value(value'low));
+          subval (value'range) := value;
+          return TO_OSTRING(subval);
+        else
+          return TO_OSTRING (resize (value, value'high, -3));
+        end if;
+      else
+        slv := to_sulv (value);
+        if Is_X (value (value'low)) then
+          lpad := (others => value (value'low));
+        else
+          lpad := (others => '0');
+        end if;
+        return TO_OSTRING(slv(slv'high downto slv'high-value'high))
+          & "."
+          & TO_OSTRING(slv(slv'high-value'high-1 downto 0) & lpad);
+      end if;
+    end if;
+  end function TO_OSTRING;
+
+  function TO_HSTRING (value : UNRESOLVED_ufixed) return STRING is
+    constant lne  : INTEGER := (-value'low+3)/4;
+    variable subval : UNRESOLVED_ufixed (value'high downto -4);
+    variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + value'low) -1);
+    variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      if value'high < 0 then
+        if value(value'high) = 'Z' then
+          return TO_HSTRING (resize (sfixed(value), 3, value'low));
+        else
+          return TO_HSTRING (resize (value, 3, value'low));
+        end if;
+      elsif value'low >= 0 then
+        if Is_X (value(value'low)) then
+          subval := (others => value(value'low));
+          subval (value'range) := value;
+          return TO_HSTRING(subval);
+        else
+          return TO_HSTRING (resize (value, value'high, -4));
+        end if;
+      else
+        slv := to_sulv (value);
+        if Is_X (value (value'low)) then
+          lpad := (others => value(value'low));
+        else
+          lpad := (others => '0');
+        end if;
+        return TO_HSTRING(slv(slv'high downto slv'high-value'high))
+          & "."
+          & TO_HSTRING(slv(slv'high-value'high-1 downto 0)&lpad);
+      end if;
+    end if;
+  end function TO_HSTRING;
+
+  function TO_OSTRING (value : UNRESOLVED_sfixed) return STRING is
+    constant ne   : INTEGER := ((value'high+1)+2)/3;
+    variable pad  : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
+    constant lne  : INTEGER := (-value'low+2)/3;
+    variable subval : UNRESOLVED_sfixed (value'high downto -3);
+    variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + value'low) -1);
+    variable slv  : STD_ULOGIC_VECTOR (value'high - value'low downto 0);
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      if value'high < 0 then
+        return TO_OSTRING (resize (value, 2, value'low));
+      elsif value'low >= 0 then
+        if Is_X (value(value'low)) then
+          subval := (others => value(value'low));
+          subval (value'range) := value;
+          return TO_OSTRING(subval);
+        else
+          return TO_OSTRING (resize (value, value'high, -3));
+        end if;
+      else
+        pad := (others => value(value'high));
+        slv := to_sulv (value);
+        if Is_X (value (value'low)) then
+          lpad := (others => value(value'low));
+        else
+          lpad := (others => '0');
+        end if;
+        return TO_OSTRING(pad & slv(slv'high downto slv'high-value'high))
+          & "."
+          & TO_OSTRING(slv(slv'high-value'high-1 downto 0) & lpad);
+      end if;
+    end if;
+  end function TO_OSTRING;
+
+  function TO_HSTRING (value : UNRESOLVED_sfixed) return STRING is
+    constant ne   : INTEGER := ((value'high+1)+3)/4;
+    variable pad  : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
+    constant lne  : INTEGER := (-value'low+3)/4;
+    variable subval : UNRESOLVED_sfixed (value'high downto -4);
+    variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + value'low) -1);
+    variable slv  : STD_ULOGIC_VECTOR (value'length-1 downto 0);
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      if value'high < 0 then
+        return TO_HSTRING (resize (value, 3, value'low));
+      elsif value'low >= 0 then
+        if Is_X (value(value'low)) then
+          subval := (others => value(value'low));
+          subval (value'range) := value;
+          return TO_HSTRING(subval);
+        else
+          return TO_HSTRING (resize (value, value'high, -4));
+        end if;
+      else
+        slv := to_sulv (value);
+        pad := (others => value(value'high));
+        if Is_X (value (value'low)) then
+          lpad := (others => value(value'low));
+        else
+          lpad := (others => '0');
+        end if;
+        return TO_HSTRING(pad & slv(slv'high downto slv'high-value'high))
+          & "."
+          & TO_HSTRING(slv(slv'high-value'high-1 downto 0) & lpad);
+      end if;
+    end if;
+  end function TO_HSTRING;
+
+  -- From string functions allow you to convert a string into a fixed
+  -- point number.  Example:
+  --  signal uf1 : ufixed (3 downto -3);
+  --  uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
+  -- The "." is optional in this syntax, however it exist and is
+  -- in the wrong location an error is produced.  Overflow will
+  -- result in saturation.
+  function from_string (
+    bstring              : STRING;      -- binary string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (left_index downto right_index);
+    variable L      : LINE;
+    variable good   : BOOLEAN;
+  begin
+    L := new STRING'(bstring);
+    READ (L, result, good);
+    deallocate (L);
+    assert (good)
+      report fixed_generic_pkg'instance_name
+      & "from_string: Bad string "& bstring severity error;
+    return result;
+  end function from_string;
+
+  -- Octal and hex conversions work as follows:
+  -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
+  -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
+  function from_ostring (
+    ostring              : STRING;      -- Octal string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (left_index downto right_index);
+    variable L      : LINE;
+    variable good   : BOOLEAN;
+  begin
+    L := new STRING'(ostring);
+    OREAD (L, result, good);
+    deallocate (L);
+    assert (good)
+      report fixed_generic_pkg'instance_name
+      & "from_ostring: Bad string "& ostring severity error;
+    return result;
+  end function from_ostring;
+
+  function from_hstring (
+    hstring              : STRING;      -- hex string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed
+  is
+    variable result : UNRESOLVED_ufixed (left_index downto right_index);
+    variable L      : LINE;
+    variable good   : BOOLEAN;
+  begin
+    L := new STRING'(hstring);
+    HREAD (L, result, good);
+    deallocate (L);
+    assert (good)
+      report fixed_generic_pkg'instance_name
+      & "from_hstring: Bad string "& hstring severity error;
+    return result;
+  end function from_hstring;
+
+  function from_string (
+    bstring              : STRING;      -- binary string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (left_index downto right_index);
+    variable L      : LINE;
+    variable good   : BOOLEAN;
+  begin
+    L := new STRING'(bstring);
+    READ (L, result, good);
+    deallocate (L);
+    assert (good)
+      report fixed_generic_pkg'instance_name
+      & "from_string: Bad string "& bstring severity error;
+    return result;
+  end function from_string;
+
+  function from_ostring (
+    ostring              : STRING;      -- Octal string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (left_index downto right_index);
+    variable L      : LINE;
+    variable good   : BOOLEAN;
+  begin
+    L := new STRING'(ostring);
+    OREAD (L, result, good);
+    deallocate (L);
+    assert (good)
+      report fixed_generic_pkg'instance_name
+      & "from_ostring: Bad string "& ostring severity error;
+    return result;
+  end function from_ostring;
+
+  function from_hstring (
+    hstring              : STRING;      -- hex string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed
+  is
+    variable result : UNRESOLVED_sfixed (left_index downto right_index);
+    variable L      : LINE;
+    variable good   : BOOLEAN;
+  begin
+    L := new STRING'(hstring);
+    HREAD (L, result, good);
+    deallocate (L);
+    assert (good)
+      report fixed_generic_pkg'instance_name
+      & "from_hstring: Bad string "& hstring severity error;
+    return result;
+  end function from_hstring;
+
+  -- Same as above, "size_res" is used for it's range only.
+ function from_string (
+    bstring  : STRING;                  -- binary string
+    size_res : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed is
+  begin
+    return from_string (bstring, size_res'high, size_res'low);
+  end function from_string;
+
+  function from_ostring (
+    ostring  : STRING;                  -- Octal string
+    size_res : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed is
+  begin
+    return from_ostring (ostring, size_res'high, size_res'low);
+  end function from_ostring;
+
+  function from_hstring (
+    hstring  : STRING;                  -- hex string
+    size_res : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed is
+  begin
+    return from_hstring(hstring, size_res'high, size_res'low);
+  end function from_hstring;
+
+  function from_string (
+    bstring  : STRING;                  -- binary string
+    size_res : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return from_string (bstring, size_res'high, size_res'low);
+  end function from_string;
+
+  function from_ostring (
+    ostring  : STRING;                  -- Octal string
+    size_res : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return from_ostring (ostring, size_res'high, size_res'low);
+  end function from_ostring;
+
+  function from_hstring (
+    hstring  : STRING;                  -- hex string
+    size_res : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed is
+  begin
+    return from_hstring (hstring, size_res'high, size_res'low);
+  end function from_hstring;
+
+  -- Direct conversion functions.  Example:
+  --  signal uf1 : ufixed (3 downto -3);
+  --  uf1 <= from_string ("0110.100"); -- 6.5
+  -- In this case the "." is not optional, and the size of
+  -- the output must match exactly.
+  -- purpose: Calculate the string boundaries
+  procedure calculate_string_boundry (
+    arg         : in  STRING;           -- input string
+    left_index  : out INTEGER;          -- left
+    right_index : out INTEGER) is       -- right
+    -- examples "10001.111" would return +4, -3
+    -- "07X.44" would return +2, -2 (then the octal routine would multiply)
+    -- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
+    alias xarg : STRING (arg'length downto 1) is arg;  -- make it downto range
+    variable l, r : INTEGER;            -- internal indexes
+    variable founddot : BOOLEAN := false;
+  begin
+    if arg'length > 0 then
+      l := xarg'high - 1;
+      r := 0;
+      for i in xarg'range loop
+        if xarg(i) = '_' then
+          if r = 0 then
+            l := l - 1;
+          else
+            r := r + 1;
+          end if;
+        elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
+          report fixed_generic_pkg'instance_name
+            & "Found a space in the input STRING " & xarg
+            severity error;
+        elsif xarg(i) = '.' then
+          if founddot then
+            report fixed_generic_pkg'instance_name
+              & "Found two binary points in input string " & xarg
+              severity error;
+          else
+            l := l - i;
+            r := -i + 1;
+            founddot := true;
+          end if;
+        end if;
+      end loop;
+      left_index := l;
+      right_index := r;
+    else
+      left_index := 0;
+      right_index := 0;
+    end if;
+  end procedure calculate_string_boundry;
+
+  -- Direct conversion functions.  Example:
+  --  signal uf1 : ufixed (3 downto -3);
+  --  uf1 <= from_string ("0110.100"); -- 6.5
+  -- In this case the "." is not optional, and the size of
+  -- the output must match exactly.
+  function from_string (
+    bstring : STRING)                      -- binary string
+    return UNRESOLVED_ufixed
+  is
+    variable left_index, right_index : INTEGER;
+  begin
+    calculate_string_boundry (bstring, left_index, right_index);
+    return from_string (bstring, left_index, right_index);
+  end function from_string;
+
+  -- Direct octal and hex conversion functions.  In this case
+  -- the string lengths must match.  Example:
+  -- signal sf1 := sfixed (5 downto -3);
+  -- sf1 <= from_ostring ("71.4") -- -6.5
+  function from_ostring (
+    ostring : STRING)                      -- Octal string
+    return UNRESOLVED_ufixed
+  is
+    variable left_index, right_index : INTEGER;
+  begin
+    calculate_string_boundry (ostring, left_index, right_index);
+    return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
+  end function from_ostring;
+
+  function from_hstring (
+    hstring : STRING)                      -- hex string
+    return UNRESOLVED_ufixed
+  is
+    variable left_index, right_index : INTEGER;
+  begin
+    calculate_string_boundry (hstring, left_index, right_index);
+    return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
+  end function from_hstring;
+
+  function from_string (
+    bstring : STRING)                      -- binary string
+    return UNRESOLVED_sfixed
+  is
+    variable left_index, right_index : INTEGER;
+  begin
+    calculate_string_boundry (bstring, left_index, right_index);
+    return from_string (bstring, left_index, right_index);
+  end function from_string;
+
+  function from_ostring (
+    ostring : STRING)                      -- Octal string
+    return UNRESOLVED_sfixed
+  is
+    variable left_index, right_index : INTEGER;
+  begin
+    calculate_string_boundry (ostring, left_index, right_index);
+    return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
+  end function from_ostring;
+
+  function from_hstring (
+    hstring : STRING)                      -- hex string
+    return UNRESOLVED_sfixed
+  is
+    variable left_index, right_index : INTEGER;
+  begin
+    calculate_string_boundry (hstring, left_index, right_index);
+    return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
+  end function from_hstring;
+
+end package body fixed_generic_pkg;
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl
new file mode 100644
index 0000000..df49433
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl
@@ -0,0 +1,1439 @@
+-- -----------------------------------------------------------------
+-- 
+-- Copyright 2019 IEEE P1076 WG Authors
+-- 
+-- See the LICENSE file distributed with this work for copyright and
+-- licensing information and the AUTHORS file.
+-- 
+-- This file to you under the Apache License, Version 2.0 (the "License").
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+-- implied.  See the License for the specific language governing
+-- permissions and limitations under the License.
+--
+--   Title     :  Fixed-point package (Generic package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This packages defines basic binary fixed point
+--             :  arithmetic functions
+--             :
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+use STD.TEXTIO.all;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use IEEE.fixed_float_types.all;
+
+package fixed_generic_pkg is
+  generic (
+    -- Rounding routine to use in fixed point, fixed_round or fixed_truncate
+    fixed_round_style    : fixed_round_style_type    := fixed_round;
+    -- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
+    fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
+    -- Extra bits used in divide routines
+    fixed_guard_bits     : NATURAL                   := 3;
+    -- If TRUE, then turn off warnings on "X" propagation
+    no_warning           : BOOLEAN                   := false
+    );
+
+  -- Author David Bishop (dbishop@vhdl.org)
+  constant CopyRightNotice : STRING :=
+    "Copyright IEEE P1076 WG. Licensed Apache 2.0";
+
+  -- base Unsigned fixed point type, downto direction assumed
+  type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
+  -- base Signed fixed point type, downto direction assumed
+  type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
+
+  alias U_ufixed is UNRESOLVED_ufixed;
+  alias U_sfixed is UNRESOLVED_sfixed;
+
+  subtype ufixed is (resolved) UNRESOLVED_ufixed;
+  subtype sfixed is (resolved) UNRESOLVED_sfixed;
+
+  --===========================================================================
+  -- Arithmetic Operators:
+  --===========================================================================
+
+  -- Absolute value, 2's complement
+  -- abs sfixed(a downto b) = sfixed(a+1 downto b)
+  function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- Negation, 2's complement
+  -- - sfixed(a downto b) = sfixed(a+1 downto b)
+  function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
+
+  -- Addition
+  -- ufixed(a downto b) + ufixed(c downto d)
+  --   = ufixed(maximum(a,c)+1 downto minimum(b,d))
+  function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- sfixed(a downto b) + sfixed(c downto d)
+  --   = sfixed(maximum(a,c)+1 downto minimum(b,d))
+  function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- Subtraction
+  -- ufixed(a downto b) - ufixed(c downto d)
+  --   = ufixed(maximum(a,c)+1 downto minimum(b,d))
+  function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- sfixed(a downto b) - sfixed(c downto d)
+  --   = sfixed(maximum(a,c)+1 downto minimum(b,d))
+  function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- Multiplication
+  -- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
+  function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
+  function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- Division
+  -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
+  function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
+  function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- Remainder
+  -- ufixed (a downto b) rem ufixed (c downto d)
+  --   = ufixed (minimum(a,c) downto minimum(b,d))
+  function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- sfixed (a downto b) rem sfixed (c downto d)
+  --   = sfixed (minimum(a,c) downto minimum(b,d))
+  function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- Modulo
+  -- ufixed (a downto b) mod ufixed (c downto d)
+  --        = ufixed (minimum(a,c) downto minimum(b, d))
+  function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- sfixed (a downto b) mod sfixed (c downto d)
+  --        = sfixed (c downto minimum(b, d))
+  function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  ----------------------------------------------------------------------------
+  -- In these routines the "real" or "natural" (integer)
+  -- are converted into a fixed point number and then the operation is
+  -- performed.  It is assumed that the array will be large enough.
+  -- If the input is "real" then the real number is converted into a fixed of
+  -- the same size as the fixed point input.  If the number is an "integer"
+  -- then it is converted into fixed with the range (l'high downto 0).
+  ----------------------------------------------------------------------------
+
+  -- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
+  function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
+
+  -- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
+  function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
+  function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
+  function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
+  function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
+
+  -- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
+  function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
+  function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
+  function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
+  function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
+
+  -- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
+  function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
+  function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
+
+  -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
+  function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
+  function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
+  function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
+  function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
+
+  -- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
+  function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
+  function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
+
+  -- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
+  function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
+  function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
+
+  -- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
+  function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
+  function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
+
+  -- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
+  function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
+  function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
+
+  -- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
+  function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+
+  -- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
+  function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
+
+  -- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
+  function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
+  function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
+
+  -- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
+  function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
+  function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
+
+  -- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
+  function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
+  function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
+
+  -- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
+  function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
+  function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
+
+  -- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
+  function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
+  function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
+
+  -- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
+  function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
+  function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
+
+  -- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
+  function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
+  function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
+
+  -- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
+  function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
+  function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
+
+  -- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
+  function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
+  function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
+
+  -- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
+  function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
+  function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
+
+  -- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
+  function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
+  function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
+
+  -- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
+  function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- This version of divide gives the user more control
+  -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
+  function divide (
+    l, r                 : UNRESOLVED_ufixed;
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_ufixed;
+
+  -- This version of divide gives the user more control
+  -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
+  function divide (
+    l, r                 : UNRESOLVED_sfixed;
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_sfixed;
+
+  -- These functions return 1/X
+  -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
+  function reciprocal (
+    arg                  : UNRESOLVED_ufixed;  -- fixed point input
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_ufixed;
+
+  -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
+  function reciprocal (
+    arg                  : UNRESOLVED_sfixed;  -- fixed point input
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_sfixed;
+
+  -- REM function
+  -- ufixed (a downto b) rem ufixed (c downto d)
+  --   = ufixed (minimum(a,c) downto minimum(b,d))
+  function remainder (
+    l, r                 : UNRESOLVED_ufixed;
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_ufixed;
+
+  -- sfixed (a downto b) rem sfixed (c downto d)
+  --   = sfixed (minimum(a,c) downto minimum(b,d))
+  function remainder (
+    l, r                 : UNRESOLVED_sfixed;
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_sfixed;
+
+  -- mod function
+  -- ufixed (a downto b) mod ufixed (c downto d)
+  --        = ufixed (minimum(a,c) downto minimum(b, d))
+  function modulo (
+    l, r                 : UNRESOLVED_ufixed;
+    constant round_style : fixed_round_style_type := fixed_round_style;
+    constant guard_bits  : NATURAL                := fixed_guard_bits)
+    return UNRESOLVED_ufixed;
+
+  -- sfixed (a downto b) mod sfixed (c downto d)
+  --        = sfixed (c downto minimum(b, d))
+  function modulo (
+    l, r                    : UNRESOLVED_sfixed;
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)
+    return UNRESOLVED_sfixed;
+
+  -- Procedure for those who need an "accumulator" function.
+  -- add_carry (ufixed(a downto b), ufixed (c downto d))
+  --         = ufixed (maximum(a,c) downto minimum(b,d))
+  procedure add_carry (
+    L, R   : in  UNRESOLVED_ufixed;
+    c_in   : in  STD_ULOGIC;
+    result : out UNRESOLVED_ufixed;
+    c_out  : out STD_ULOGIC);
+
+  -- add_carry (sfixed(a downto b), sfixed (c downto d))
+  --         = sfixed (maximum(a,c) downto minimum(b,d))
+  procedure add_carry (
+    L, R   : in  UNRESOLVED_sfixed;
+    c_in   : in  STD_ULOGIC;
+    result : out UNRESOLVED_sfixed;
+    c_out  : out STD_ULOGIC);
+
+  -- Scales the result by a power of 2.  Width of input = width of output with
+  -- the binary point moved.
+  function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
+  function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_ufixed;
+  function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
+  function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_sfixed;
+
+  function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
+
+  --===========================================================================
+  -- Comparison Operators
+  --===========================================================================
+
+  function ">"  (l, r : UNRESOLVED_ufixed) return BOOLEAN;
+  function ">"  (l, r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "<"  (l, r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "<"  (l, r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
+  function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
+  function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "="  (l, r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "="  (l, r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
+
+  function "?="  (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?/=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?>"  (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?>=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?<"  (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?<=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?="  (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?/=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?>"  (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?>=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?<"  (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?<=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
+
+  function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
+  function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
+
+  -- Overloads the default "maximum" and "minimum" function
+
+  function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  ----------------------------------------------------------------------------
+  -- In these compare functions a natural is converted into a
+  -- fixed point number of the bounds "maximum(l'high,0) downto 0"
+  ----------------------------------------------------------------------------
+
+  function "="  (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
+  function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
+  function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
+  function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
+  function ">"  (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
+  function "<"  (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
+
+  function "="  (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function ">"  (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "<"  (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+
+  function "?="  (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
+  function "?/=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
+  function "?>=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
+  function "?<=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
+  function "?>"  (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
+  function "?<"  (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
+
+  function "?="  (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?/=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?>=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?<=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?>"  (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?<"  (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+
+  function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
+    return UNRESOLVED_ufixed;
+  function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
+    return UNRESOLVED_ufixed;
+  function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  ----------------------------------------------------------------------------
+  -- In these compare functions a real is converted into a
+  -- fixed point number of the bounds "l'high+1 downto l'low"
+  ----------------------------------------------------------------------------
+
+  function "="  (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
+  function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
+  function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
+  function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
+  function ">"  (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
+  function "<"  (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
+
+  function "="  (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function ">"  (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+  function "<"  (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
+
+  function "?="  (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
+  function "?/=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
+  function "?>=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
+  function "?<=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
+  function "?>"  (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
+  function "?<"  (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
+
+  function "?="  (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?/=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?>=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?<=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?>"  (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "?<"  (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
+
+  function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
+  function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
+  function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  ----------------------------------------------------------------------------
+  -- In these compare functions an integer is converted into a
+  -- fixed point number of the bounds "maximum(l'high,1) downto 0"
+  ----------------------------------------------------------------------------
+
+  function "="  (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
+  function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
+  function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
+  function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
+  function ">"  (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
+  function "<"  (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
+
+  function "="  (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function ">"  (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "<"  (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
+
+  function "?="  (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
+  function "?/=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
+  function "?>=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
+  function "?<=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
+  function "?>"  (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
+  function "?<"  (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
+
+  function "?="  (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?/=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?>=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?<=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?>"  (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?<"  (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+
+  function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
+    return UNRESOLVED_sfixed;
+  function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
+    return UNRESOLVED_sfixed;
+  function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  ----------------------------------------------------------------------------
+  -- In these compare functions a real is converted into a
+  -- fixed point number of the bounds "l'high+1 downto l'low"
+  ----------------------------------------------------------------------------
+
+  function "="  (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
+  function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
+  function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
+  function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
+  function ">"  (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
+  function "<"  (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
+
+  function "="  (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function ">"  (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
+  function "<"  (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
+
+  function "?="  (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
+  function "?/=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
+  function "?>=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
+  function "?<=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
+  function "?>"  (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
+  function "?<"  (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
+
+  function "?="  (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?/=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?>=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?<=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?>"  (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "?<"  (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
+
+  function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
+  function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
+  function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  --===========================================================================
+  -- Shift and Rotate Functions.
+  -- Note that sra and sla are not the same as the BIT_VECTOR version
+  --===========================================================================
+
+  function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed;
+  function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed;
+  function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed;
+  function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed;
+  function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed;
+  function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
+    return UNRESOLVED_ufixed;
+  function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed;
+  function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed;
+  function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed;
+  function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed;
+  function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed;
+  function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
+    return UNRESOLVED_sfixed;
+  function SHIFT_LEFT  (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
+    return UNRESOLVED_ufixed;
+  function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
+    return UNRESOLVED_ufixed;
+  function SHIFT_LEFT  (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
+    return UNRESOLVED_sfixed;
+  function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
+    return UNRESOLVED_sfixed;
+
+  ----------------------------------------------------------------------------
+  -- logical functions
+  ----------------------------------------------------------------------------
+
+  function "not"  (l    : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function "and"  (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function "or"   (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function "nor"  (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function "xor"  (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function "not"  (l    : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function "and"  (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function "or"   (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function "nor"  (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function "xor"  (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- Vector and std_ulogic functions, same as functions in numeric_std
+  function "and"  (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  function "and"  (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
+    return UNRESOLVED_ufixed;
+  function "or"   (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  function "or"   (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
+    return UNRESOLVED_ufixed;
+  function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
+    return UNRESOLVED_ufixed;
+  function "nor"  (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  function "nor"  (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
+    return UNRESOLVED_ufixed;
+  function "xor"  (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  function "xor"  (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
+    return UNRESOLVED_ufixed;
+  function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
+    return UNRESOLVED_ufixed;
+  function "and"  (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  function "and"  (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
+    return UNRESOLVED_sfixed;
+  function "or"   (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  function "or"   (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
+    return UNRESOLVED_sfixed;
+  function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
+    return UNRESOLVED_sfixed;
+  function "nor"  (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  function "nor"  (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
+    return UNRESOLVED_sfixed;
+  function "xor"  (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  function "xor"  (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
+    return UNRESOLVED_sfixed;
+  function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
+    return UNRESOLVED_sfixed;
+
+  -- Reduction operators, same as numeric_std functions
+  function "and"  (l : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "or"   (l : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "nor"  (l : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "xor"  (l : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
+  function "and"  (l : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "or"   (l : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "nor"  (l : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "xor"  (l : UNRESOLVED_sfixed) return STD_ULOGIC;
+  function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
+
+  -- returns arg'low-1 if not found
+  function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
+    return INTEGER;
+  function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
+    return INTEGER;
+
+  -- returns arg'high+1 if not found
+  function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
+    return INTEGER;
+  function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
+    return INTEGER;
+
+  --===========================================================================
+  --   RESIZE Functions
+  --===========================================================================
+  -- resizes the number (larger or smaller)
+  -- The returned result will be ufixed (left_index downto right_index)
+  -- If "round_style" is fixed_round, then the result will be rounded.
+  -- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
+  -- is a '1' or the lower bits of the remainder include a '1' then the result
+  -- will be increased by the smallest representable number for that type.
+  -- "overflow_style" can be fixed_saturate or fixed_wrap.
+  -- In saturate mode, if the number overflows then the largest possible
+  -- representable number is returned.  If wrap mode, then the upper bits
+  -- of the number are truncated.
+
+  function resize (
+    arg                     : UNRESOLVED_ufixed;  -- input
+    constant left_index     : INTEGER;  -- integer portion
+    constant right_index    : INTEGER;  -- size of fraction
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed;
+
+  -- "size_res" functions create the size of the output from the indices
+  -- of the "size_res" input.  The actual value of "size_res" is not used.
+  function resize (
+    arg                     : UNRESOLVED_ufixed;  -- input
+    size_res                : UNRESOLVED_ufixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed;
+
+  -- Note that in "wrap" mode the sign bit is not replicated.  Thus the
+  -- resize of a negative number can have a positive result in wrap mode.
+  function resize (
+    arg                     : UNRESOLVED_sfixed;  -- input
+    constant left_index     : INTEGER;            -- integer portion
+    constant right_index    : INTEGER;            -- size of fraction
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed;
+
+  function resize (
+    arg                     : UNRESOLVED_sfixed;  -- input
+    size_res                : UNRESOLVED_sfixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed;
+
+  --===========================================================================
+  -- Conversion Functions
+  --===========================================================================
+
+  -- integer (natural) to unsigned fixed point.
+  -- arguments are the upper and lower bounds of the number, thus
+  -- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
+  function to_ufixed (
+    arg                     : NATURAL;  -- integer
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER                   := 0;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed;
+
+  function to_ufixed (
+    arg                     : NATURAL;            -- integer
+    size_res                : UNRESOLVED_ufixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed;
+
+  -- real to unsigned fixed point
+  function to_ufixed (
+    arg                     : REAL;     -- real
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)
+    return UNRESOLVED_ufixed;
+
+  function to_ufixed (
+    arg                     : REAL;     -- real
+    size_res                : UNRESOLVED_ufixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)
+    return UNRESOLVED_ufixed;
+
+  -- unsigned to unsigned fixed point
+  function to_ufixed (
+    arg                     : UNRESOLVED_UNSIGNED;             -- unsigned
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER                   := 0;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed;
+
+  function to_ufixed (
+    arg                     : UNRESOLVED_UNSIGNED;           -- unsigned
+    size_res                : UNRESOLVED_ufixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_ufixed;
+
+  -- Performs a conversion.  ufixed (arg'range) is returned
+  function to_ufixed (
+    arg : UNRESOLVED_UNSIGNED)          -- unsigned
+    return UNRESOLVED_ufixed;
+
+  -- unsigned fixed point to unsigned
+  function to_unsigned (
+    arg                     : UNRESOLVED_ufixed;  -- fixed point input
+    constant size           : NATURAL;            -- length of output
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_UNSIGNED;
+
+  -- unsigned fixed point to unsigned
+  function to_unsigned (
+    arg                     : UNRESOLVED_ufixed;    -- fixed point input
+    size_res                : UNRESOLVED_UNSIGNED;  -- used for length of output
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_UNSIGNED;
+
+  -- unsigned fixed point to real
+  function to_real (
+    arg : UNRESOLVED_ufixed)            -- fixed point input
+    return REAL;
+
+  -- unsigned fixed point to integer
+  function to_integer (
+    arg                     : UNRESOLVED_ufixed;  -- fixed point input
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return NATURAL;
+
+  -- Integer to UNRESOLVED_sfixed
+  function to_sfixed (
+    arg                     : INTEGER;   -- integer
+    constant left_index     : INTEGER;   -- left index (high index)
+    constant right_index    : INTEGER                   := 0;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed;
+
+  function to_sfixed (
+    arg                     : INTEGER;            -- integer
+    size_res                : UNRESOLVED_sfixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed;
+
+  -- Real to sfixed
+  function to_sfixed (
+    arg                     : REAL;     -- real
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)
+    return UNRESOLVED_sfixed;
+
+  function to_sfixed (
+    arg                     : REAL;     -- real
+    size_res                : UNRESOLVED_sfixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style;
+    constant guard_bits     : NATURAL                   := fixed_guard_bits)
+    return UNRESOLVED_sfixed;
+
+  -- signed to sfixed
+  function to_sfixed (
+    arg                     : UNRESOLVED_SIGNED;               -- signed
+    constant left_index     : INTEGER;  -- left index (high index)
+    constant right_index    : INTEGER                   := 0;  -- right index
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed;
+
+  function to_sfixed (
+    arg                     : UNRESOLVED_SIGNED;  -- signed
+    size_res                : UNRESOLVED_sfixed;  -- for size only
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_sfixed;
+
+  -- signed to sfixed (output assumed to be size of signed input)
+  function to_sfixed (
+    arg : UNRESOLVED_SIGNED)            -- signed
+    return UNRESOLVED_sfixed;
+
+  -- Conversion from ufixed to sfixed
+  function to_sfixed (
+    arg : UNRESOLVED_ufixed)
+    return UNRESOLVED_sfixed;
+
+  -- signed fixed point to signed
+  function to_signed (
+    arg                     : UNRESOLVED_sfixed;  -- fixed point input
+    constant size           : NATURAL;            -- length of output
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_SIGNED;
+
+  -- signed fixed point to signed
+  function to_signed (
+    arg                     : UNRESOLVED_sfixed;  -- fixed point input
+    size_res                : UNRESOLVED_SIGNED;  -- used for length of output
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return UNRESOLVED_SIGNED;
+
+  -- signed fixed point to real
+  function to_real (
+    arg : UNRESOLVED_sfixed)            -- fixed point input
+    return REAL;
+
+  -- signed fixed point to integer
+  function to_integer (
+    arg                     : UNRESOLVED_sfixed;  -- fixed point input
+    constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
+    constant round_style    : fixed_round_style_type    := fixed_round_style)
+    return INTEGER;
+
+  -- Because of the fairly complicated sizing rules in the fixed point
+  -- packages these functions are provided to compute the result ranges
+  -- Example:
+  -- signal uf1 : ufixed (3 downto -3);
+  -- signal uf2 : ufixed (4 downto -2);
+  -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
+  --                             ufixed_low (3, -3, '*', 4, -2));
+  -- uf1multuf2 <= uf1 * uf2;
+  -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
+  --                   '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
+  function ufixed_high (left_index, right_index   : INTEGER;
+                        operation                 : CHARACTER := 'X';
+                        left_index2, right_index2 : INTEGER   := 0)
+    return INTEGER;
+
+  function ufixed_low (left_index, right_index   : INTEGER;
+                       operation                 : CHARACTER := 'X';
+                       left_index2, right_index2 : INTEGER   := 0)
+    return INTEGER;
+
+  function sfixed_high (left_index, right_index   : INTEGER;
+                        operation                 : CHARACTER := 'X';
+                        left_index2, right_index2 : INTEGER   := 0)
+    return INTEGER;
+
+  function sfixed_low (left_index, right_index   : INTEGER;
+                       operation                 : CHARACTER := 'X';
+                       left_index2, right_index2 : INTEGER   := 0)
+    return INTEGER;
+
+  -- Same as above, but using the "size_res" input only for their ranges:
+  -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
+  --                             ufixed_low (uf1, '*', uf2));
+  -- uf1multuf2 <= uf1 * uf2;
+  --
+  function ufixed_high (size_res  : UNRESOLVED_ufixed;
+                        operation : CHARACTER := 'X';
+                        size_res2 : UNRESOLVED_ufixed)
+    return INTEGER;
+
+  function ufixed_low (size_res  : UNRESOLVED_ufixed;
+                       operation : CHARACTER := 'X';
+                       size_res2 : UNRESOLVED_ufixed)
+    return INTEGER;
+
+  function sfixed_high (size_res  : UNRESOLVED_sfixed;
+                        operation : CHARACTER := 'X';
+                        size_res2 : UNRESOLVED_sfixed)
+    return INTEGER;
+
+  function sfixed_low (size_res  : UNRESOLVED_sfixed;
+                       operation : CHARACTER := 'X';
+                       size_res2 : UNRESOLVED_sfixed)
+    return INTEGER;
+
+  -- purpose: returns a saturated number
+  function saturate (
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed;
+
+  -- purpose: returns a saturated number
+  function saturate (
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed;
+
+  function saturate (
+    size_res : UNRESOLVED_ufixed)       -- only the size of this is used
+    return UNRESOLVED_ufixed;
+
+  function saturate (
+    size_res : UNRESOLVED_sfixed)       -- only the size of this is used
+    return UNRESOLVED_sfixed;
+
+  --===========================================================================
+  -- Translation Functions
+  --===========================================================================
+
+  -- maps meta-logical values
+  function to_01 (
+    s             : UNRESOLVED_ufixed;  -- fixed point input
+    constant XMAP : STD_ULOGIC := '0')  -- Map x to
+    return UNRESOLVED_ufixed;
+
+  -- maps meta-logical values
+  function to_01 (
+    s             : UNRESOLVED_sfixed;  -- fixed point input
+    constant XMAP : STD_ULOGIC := '0')  -- Map x to
+    return UNRESOLVED_sfixed;
+
+  function Is_X    (arg : UNRESOLVED_ufixed) return BOOLEAN;
+  function Is_X    (arg : UNRESOLVED_sfixed) return BOOLEAN;
+  function to_X01  (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function to_X01  (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+  function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
+  function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
+
+  -- straight vector conversion routines, needed for synthesis.
+  -- These functions are here so that a std_logic_vector can be
+  -- converted to and from sfixed and ufixed.  Note that you can
+  -- not convert these vectors because of their negative index.
+
+  function to_slv (
+    arg : UNRESOLVED_ufixed)            -- fixed point vector
+    return STD_LOGIC_VECTOR;
+  alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
+                                     return STD_LOGIC_VECTOR];
+  alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
+                                       return STD_LOGIC_VECTOR];
+
+  function to_slv (
+    arg : UNRESOLVED_sfixed)            -- fixed point vector
+    return STD_LOGIC_VECTOR;
+  alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
+                                     return STD_LOGIC_VECTOR];
+  alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
+                                       return STD_LOGIC_VECTOR];
+
+  function to_sulv (
+    arg : UNRESOLVED_ufixed)            -- fixed point vector
+    return STD_ULOGIC_VECTOR;
+  alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
+                                      return STD_ULOGIC_VECTOR];
+  alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
+                                        return STD_ULOGIC_VECTOR];
+
+  function to_sulv (
+    arg : UNRESOLVED_sfixed)            -- fixed point vector
+    return STD_ULOGIC_VECTOR;
+  alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
+                                      return STD_ULOGIC_VECTOR];
+  alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
+                                        return STD_ULOGIC_VECTOR];
+
+  function to_ufixed (
+    arg                  : STD_ULOGIC_VECTOR;  -- shifted vector
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed;
+
+  function to_ufixed (
+    arg      : STD_ULOGIC_VECTOR;       -- shifted vector
+    size_res : UNRESOLVED_ufixed)       -- for size only
+    return UNRESOLVED_ufixed;
+
+  function to_sfixed (
+    arg                  : STD_ULOGIC_VECTOR;  -- shifted vector
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed;
+
+  function to_sfixed (
+    arg      : STD_ULOGIC_VECTOR;       -- shifted vector
+    size_res : UNRESOLVED_sfixed)       -- for size only
+    return UNRESOLVED_sfixed;
+
+  -- As a concession to those who use a graphical DSP environment,
+  -- these functions take parameters in those tools format and create
+  -- fixed point numbers.  These functions are designed to convert from
+  -- a std_logic_vector to the VHDL fixed point format using the conventions
+  -- of these packages.  In a pure VHDL environment you should use the
+  -- "to_ufixed" and "to_sfixed" routines.
+
+  -- unsigned fixed point
+  function to_UFix (
+    arg      : STD_ULOGIC_VECTOR;
+    width    : NATURAL;                 -- width of vector
+    fraction : NATURAL)                 -- width of fraction
+    return UNRESOLVED_ufixed;
+
+  -- signed fixed point
+  function to_SFix (
+    arg      : STD_ULOGIC_VECTOR;
+    width    : NATURAL;                 -- width of vector
+    fraction : NATURAL)                 -- width of fraction
+    return UNRESOLVED_sfixed;
+
+  -- finding the bounds of a number.  These functions can be used like this:
+  -- signal xxx : ufixed (7 downto -3);
+  -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
+  -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
+  --               downto UFix_low(11, 3, "+", 11, 3));
+  -- Where "11" is the width of xxx (xxx'length),
+  -- and 3 is the lower bound (abs (xxx'low))
+  -- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
+
+  function UFix_high (width, fraction   : NATURAL;
+                      operation         : CHARACTER := 'X';
+                      width2, fraction2 : NATURAL   := 0)
+    return INTEGER;
+
+  function UFix_low (width, fraction   : NATURAL;
+                     operation         : CHARACTER := 'X';
+                     width2, fraction2 : NATURAL   := 0)
+    return INTEGER;
+
+  -- Same as above but for signed fixed point.  Note that the width
+  -- of a signed fixed point number ignores the sign bit, thus
+  -- width = sxxx'length-1
+
+  function SFix_high (width, fraction   : NATURAL;
+                      operation         : CHARACTER := 'X';
+                      width2, fraction2 : NATURAL   := 0)
+    return INTEGER;
+
+  function SFix_low (width, fraction   : NATURAL;
+                     operation         : CHARACTER := 'X';
+                     width2, fraction2 : NATURAL   := 0)
+    return INTEGER;
+
+  --===========================================================================
+  -- string and textio Functions
+  --===========================================================================
+
+  -- purpose: writes fixed point into a line
+  procedure WRITE (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_ufixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0);
+
+  -- purpose: writes fixed point into a line
+  procedure WRITE (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_sfixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0);
+
+  procedure READ(L     : inout LINE;
+                 VALUE : out   UNRESOLVED_ufixed);
+
+  procedure READ(L     : inout LINE;
+                 VALUE : out   UNRESOLVED_ufixed;
+                 GOOD  : out   BOOLEAN);
+
+  procedure READ(L     : inout LINE;
+                 VALUE : out   UNRESOLVED_sfixed);
+
+  procedure READ(L     : inout LINE;
+                 VALUE : out   UNRESOLVED_sfixed;
+                 GOOD  : out   BOOLEAN);
+
+  alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
+  alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
+  alias bread is READ [LINE, UNRESOLVED_ufixed];
+  alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
+  alias bread is READ [LINE, UNRESOLVED_sfixed];
+  alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
+  alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
+  alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
+  alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
+  alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
+  alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
+  alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
+
+  -- octal read and write
+  procedure OWRITE (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_ufixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0);
+
+  procedure OWRITE (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_sfixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0);
+
+  procedure OREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_ufixed);
+
+  procedure OREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_ufixed;
+                  GOOD  : out   BOOLEAN);
+
+  procedure OREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_sfixed);
+
+  procedure OREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_sfixed;
+                  GOOD  : out   BOOLEAN);
+  alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
+  alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
+  alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
+  alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
+  alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
+  alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
+
+  -- hex read and write
+  procedure HWRITE (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_ufixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0);
+
+  -- purpose: writes fixed point into a line
+  procedure HWRITE (
+    L         : inout LINE;               -- input line
+    VALUE     : in    UNRESOLVED_sfixed;  -- fixed point input
+    JUSTIFIED : in    SIDE  := right;
+    FIELD     : in    WIDTH := 0);
+
+  procedure HREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_ufixed);
+
+  procedure HREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_ufixed;
+                  GOOD  : out   BOOLEAN);
+
+  procedure HREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_sfixed);
+
+  procedure HREAD(L     : inout LINE;
+                  VALUE : out   UNRESOLVED_sfixed;
+                  GOOD  : out   BOOLEAN);
+  alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
+  alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
+  alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
+  alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
+  alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
+  alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
+
+  -- returns a string, useful for:
+  -- assert (x = y) report "error found " & TO_STRING(x) severity error;
+  function TO_STRING (value : UNRESOLVED_ufixed) return STRING;
+
+  alias TO_BSTRING is TO_STRING [UNRESOLVED_ufixed return STRING];
+  alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
+
+  function TO_OSTRING (value : UNRESOLVED_ufixed) return STRING;
+  alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
+
+  function TO_HSTRING (value : UNRESOLVED_ufixed) return STRING;
+  alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
+
+  function TO_STRING (value : UNRESOLVED_sfixed) return STRING;
+  alias TO_BSTRING is TO_STRING [UNRESOLVED_sfixed return STRING];
+  alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
+
+  function TO_OSTRING (value : UNRESOLVED_sfixed) return STRING;
+  alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
+
+  function TO_HSTRING (value : UNRESOLVED_sfixed) return STRING;
+  alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
+
+  -- From string functions allow you to convert a string into a fixed
+  -- point number.  Example:
+  --  signal uf1 : ufixed (3 downto -3);
+  --  uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
+  -- The "." is optional in this syntax, however it exist and is
+  -- in the wrong location an error is produced.  Overflow will
+  -- result in saturation.
+
+  function from_string (
+    bstring              : STRING;      -- binary string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed;
+  alias from_bstring is from_string [STRING, INTEGER, INTEGER
+                                     return UNRESOLVED_ufixed];
+  alias from_binary_string is from_string [STRING, INTEGER, INTEGER
+                                           return UNRESOLVED_ufixed];
+
+  -- Octal and hex conversions work as follows:
+  -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
+  -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
+
+  function from_ostring (
+    ostring              : STRING;      -- Octal string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed;
+  alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
+                                           return UNRESOLVED_ufixed];
+
+  function from_hstring (
+    hstring              : STRING;      -- hex string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_ufixed;
+  alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
+                                         return UNRESOLVED_ufixed];
+
+  function from_string (
+    bstring              : STRING;      -- binary string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed;
+  alias from_bstring is from_string [STRING, INTEGER, INTEGER
+                                     return UNRESOLVED_sfixed];
+  alias from_binary_string is from_string [STRING, INTEGER, INTEGER
+                                           return UNRESOLVED_sfixed];
+
+  function from_ostring (
+    ostring              : STRING;      -- Octal string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed;
+  alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
+                                           return UNRESOLVED_sfixed];
+
+  function from_hstring (
+    hstring              : STRING;      -- hex string
+    constant left_index  : INTEGER;
+    constant right_index : INTEGER)
+    return UNRESOLVED_sfixed;
+  alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
+                                         return UNRESOLVED_sfixed];
+
+  -- Same as above, "size_res" is used for it's range only.
+  function from_string (
+    bstring  : STRING;                  -- binary string
+    size_res : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
+                                     return UNRESOLVED_ufixed];
+  alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
+                                           return UNRESOLVED_ufixed];
+
+  function from_ostring (
+    ostring  : STRING;                  -- Octal string
+    size_res : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
+                                           return UNRESOLVED_ufixed];
+
+  function from_hstring (
+    hstring  : STRING;                  -- hex string
+    size_res : UNRESOLVED_ufixed)
+    return UNRESOLVED_ufixed;
+  alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
+                                         return UNRESOLVED_ufixed];
+
+  function from_string (
+    bstring  : STRING;                  -- binary string
+    size_res : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
+                                     return UNRESOLVED_sfixed];
+  alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
+                                           return UNRESOLVED_sfixed];
+
+  function from_ostring (
+    ostring  : STRING;                  -- Octal string
+    size_res : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
+                                           return UNRESOLVED_sfixed];
+
+  function from_hstring (
+    hstring  : STRING;                  -- hex string
+    size_res : UNRESOLVED_sfixed)
+    return UNRESOLVED_sfixed;
+  alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
+                                         return UNRESOLVED_sfixed];
+
+  -- Direct conversion functions.  Example:
+  --  signal uf1 : ufixed (3 downto -3);
+  --  uf1 <= from_string ("0110.100"); -- 6.5
+  -- In this case the "." is not optional, and the size of
+  -- the output must match exactly.
+
+  function from_string (
+    bstring : STRING)                   -- binary string
+    return UNRESOLVED_ufixed;
+  alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
+  alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
+
+  -- Direct octal and hex conversion functions.  In this case
+  -- the string lengths must match.  Example:
+  -- signal sf1 := sfixed (5 downto -3);
+  -- sf1 <= from_ostring ("71.4") -- -6.5
+
+  function from_ostring (
+    ostring : STRING)                   -- Octal string
+    return UNRESOLVED_ufixed;
+  alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
+
+  function from_hstring (
+    hstring : STRING)                   -- hex string
+    return UNRESOLVED_ufixed;
+  alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
+
+  function from_string (
+    bstring : STRING)                   -- binary string
+    return UNRESOLVED_sfixed;
+  alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
+  alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
+
+  function from_ostring (
+    ostring : STRING)                   -- Octal string
+    return UNRESOLVED_sfixed;
+  alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
+
+  function from_hstring (
+    hstring : STRING)                   -- hex string
+    return UNRESOLVED_sfixed;
+  alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
+
+end package fixed_generic_pkg;
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl
new file mode 100644
index 0000000..1436432
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl
@@ -0,0 +1,52 @@
+-- -----------------------------------------------------------------
+-- 
+-- Copyright 2019 IEEE P1076 WG Authors
+-- 
+-- See the LICENSE file distributed with this work for copyright and
+-- licensing information and the AUTHORS file.
+-- 
+-- This file to you under the Apache License, Version 2.0 (the "License").
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+-- implied.  See the License for the specific language governing
+-- permissions and limitations under the License.
+-- 
+--
+--   Title     :  Fixed-point package (Instantiated package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This packages defines basic binary fixed point
+--             :  arithmetic functions
+--             :
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+library IEEE;
+
+package fixed_pkg is new IEEE.fixed_generic_pkg
+  generic map (
+    fixed_round_style    => IEEE.fixed_float_types.fixed_round,
+    fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
+    fixed_guard_bits     => 3,
+    no_warning           => false
+    );
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd
new file mode 100644
index 0000000..b771ed2
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 13.05.2022 14:01:29
+-- Design Name: 
+-- Module Name: fixedPointTest - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+library ieee_proposed;
+use ieee_proposed.fixed_pkg.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fixedPointTest is
+    Port ( a : in sfixed (7 downto -6);
+           b : in sfixed (7 downto -6);
+           c : out sfixed (8 downto -6));
+end fixedPointTest;
+
+architecture Behavioral of fixedPointTest is
+
+begin
+
+process(a, b)
+    begin
+
+    c <= a + b;
+        
+end process;
+
+
+end Behavioral;
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp
new file mode 100644
index 0000000..0eed252
Binary files /dev/null and b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp differ
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.xpr b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.xpr
new file mode 100644
index 0000000..cbac5dd
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.xpr
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="56" Path="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="fe9f01c3de714c74922630b435e922b1"/>
+    <Option Name="Part" Val="xc7z010clg400-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2021.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2020.4"/>
+    <Option Name="SimulatorVersionQuesta" Val="2020.4"/>
+    <Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
+    <Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
+    <Option Name="SimulatorVersionRiviera" Val="2020.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
+    <Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
+    <Option Name="BoardPart" Val="digilentinc.com:cora-z7-10:part0:1.1"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../../../../../AppData/Roaming/Xilinx/Vivado/2021.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="cora-z7-10"/>
+    <Option Name="WTXSimLaunchSim" Val="4"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_float_types.vhdl">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="Library" Val="ieee_proposed"/>
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_float_types.vhdl"/>
+          <Attr Name="ImportTime" Val="1652436395"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="Library" Val="ieee_proposed"/>
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl"/>
+          <Attr Name="ImportTime" Val="1652436398"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="Library" Val="ieee_proposed"/>
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl"/>
+          <Attr Name="ImportTime" Val="1652436400"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_pkg.vhdl">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="Library" Val="ieee_proposed"/>
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_pkg.vhdl"/>
+          <Attr Name="ImportTime" Val="1652436402"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/fixedPointTest.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="fixedPointTest"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc"/>
+          <Attr Name="ImportTime" Val="1648802911"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <File Path="$PSRCDIR/sim_1/new/fixedPointTest_db.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/fixedPointTest_db_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="fixedPointTest_db"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/fixedPointTest_db_behav.wcfg"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/fixedPointTest.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="15">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/fixedPointTest.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/StreckenSim_mitRegler/fixedPointTest/fixedPointTest_db_behav.wcfg b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest_db_behav.wcfg
new file mode 100644
index 0000000..77f9322
--- /dev/null
+++ b/StreckenSim_mitRegler/fixedPointTest/fixedPointTest_db_behav.wcfg
@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="fixedPointTest_db_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="fixedPointTest_db" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0 ps"></ZoomStartTime>
+      <ZoomEndTime time="350 ps"></ZoomEndTime>
+      <Cursor1Time time="19 ps"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="173"></NameColumnWidth>
+      <ValueColumnWidth column_width="79"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="3" />
+   <wvobject fp_name="/fixedPointTest_db/a" type="array">
+      <obj_property name="ElementShortName">a[7:-6]</obj_property>
+      <obj_property name="ObjectShortName">a[7:-6]</obj_property>
+      <obj_property name="Radix">REALRADIX</obj_property>
+      <obj_property name="radix_realType">SIGNEDFIXEDPOINTRADIX</obj_property>
+      <obj_property name="radix_fractionWidth">7</obj_property>
+      <obj_property name="radix_otherWidth">0</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject fp_name="/fixedPointTest_db/b" type="array">
+      <obj_property name="ElementShortName">b[7:-6]</obj_property>
+      <obj_property name="ObjectShortName">b[7:-6]</obj_property>
+      <obj_property name="Radix">REALRADIX</obj_property>
+      <obj_property name="radix_realType">SIGNEDFIXEDPOINTRADIX</obj_property>
+      <obj_property name="radix_fractionWidth">7</obj_property>
+      <obj_property name="radix_otherWidth">0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/fixedPointTest_db/c" type="array">
+      <obj_property name="ElementShortName">c[8:-6]</obj_property>
+      <obj_property name="ObjectShortName">c[8:-6]</obj_property>
+      <obj_property name="Radix">REALRADIX</obj_property>
+      <obj_property name="radix_realType">SIGNEDFIXEDPOINTRADIX</obj_property>
+      <obj_property name="radix_fractionWidth">8</obj_property>
+      <obj_property name="radix_otherWidth">0</obj_property>
+   </wvobject>
+</wave_config>