diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/sim/ssm.db b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/sim/ssm.db new file mode 100644 index 0000000..7cec227 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/sim/ssm.db @@ -0,0 +1,10 @@ +################################################################################ +# DONOT REMOVE THIS FILE +# Unified simulation database file for selected simulation model for IP +# +# File: ssm.db (Wed Mar 16 19:55:41 2022) +# +# This file is generated by the unified simulation automation and contains the +# selected simulation model information for the IP/BD instances. +# DONOT REMOVE THIS FILE +################################################################################ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc new file mode 100644 index 0000000..7fe7d7c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:13 +6d6f64655f636f756e7465727c4755494d6f6465:20 +eof: diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf new file mode 100644 index 0000000..3393c09 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf @@ -0,0 +1,44 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303130636c673430302d31:00:00 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a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/webtalk_pa.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..dfce549 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/webtalk_pa.xml @@ -0,0 +1,21 @@ + + + + +
+ + +
+
+ + + + + + + +
+ + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/xsim.wdf b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.hw/Coraz7_Test.lpr b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.hw/Coraz7_Test.lpr new file mode 100644 index 0000000..9280233 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.hw/Coraz7_Test.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.hw/hw_1/hw.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.hw/hw_1/hw.xml new file mode 100644 index 0000000..64982ec --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.ip_user_files/README.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_1.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_10.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..1ad25b8 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_11.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_12.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..7d87bda --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_13.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_14.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_15.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_16.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_17.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_18.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_19.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_2.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_20.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_21.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_22.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_22.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_23.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_23.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_23.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_24.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_24.xml new file mode 100644 index 0000000..516336f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_24.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_25.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_25.xml new file mode 100644 index 0000000..7d87bda --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_25.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_26.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_26.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null 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--git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_29.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_29.xml new file mode 100644 index 0000000..e7e8c6f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_29.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_3.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..822b88f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_30.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_30.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_31.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_31.xml new file mode 100644 index 0000000..1ad25b8 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_32.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_32.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_33.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_33.xml new file mode 100644 index 0000000..822b88f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_34.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_34.xml new file mode 100644 index 0000000..7d87bda --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_34.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_35.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_35.xml new file mode 100644 index 0000000..48a47dd --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_35.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_36.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_36.xml new file mode 100644 index 0000000..48a47dd --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_36.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_37.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_37.xml new file mode 100644 index 0000000..48a47dd --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_37.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_38.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_38.xml new file mode 100644 index 0000000..48a47dd --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_38.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_39.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_39.xml new file mode 100644 index 0000000..cf24cd7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_39.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_4.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_40.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_40.xml new file mode 100644 index 0000000..cf24cd7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_40.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_41.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_41.xml new file mode 100644 index 0000000..cf24cd7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_41.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_42.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_42.xml new file mode 100644 index 0000000..cf24cd7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_42.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_43.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_43.xml new file mode 100644 index 0000000..cf24cd7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_43.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_44.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_44.xml new file mode 100644 index 0000000..cf24cd7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_44.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_45.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_45.xml new file mode 100644 index 0000000..cf24cd7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_45.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_46.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_46.xml new file mode 100644 index 0000000..cf24cd7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_46.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_47.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_47.xml new file mode 100644 index 0000000..7634aca --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_47.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_48.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_48.xml new file mode 100644 index 0000000..7634aca --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_48.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_49.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_49.xml new file mode 100644 index 0000000..7634aca --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_49.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_5.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..822b88f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_50.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_50.xml new file mode 100644 index 0000000..5f2034e --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_50.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_51.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_51.xml new file mode 100644 index 0000000..5f2034e --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_51.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_52.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_52.xml new file mode 100644 index 0000000..5f2034e --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_52.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_53.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_53.xml new file mode 100644 index 0000000..5f2034e --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_53.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_54.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_54.xml new file mode 100644 index 0000000..abb1755 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_54.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_55.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_55.xml new file mode 100644 index 0000000..abb1755 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_55.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_56.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_56.xml new file mode 100644 index 0000000..abb1755 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_56.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_57.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_57.xml new file mode 100644 index 0000000..abb1755 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_57.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_58.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_58.xml new file mode 100644 index 0000000..abb1755 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_58.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_59.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_59.xml new file mode 100644 index 0000000..abb1755 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_59.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_6.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_60.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_60.xml new file mode 100644 index 0000000..abb1755 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_60.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_61.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_61.xml new file mode 100644 index 0000000..abb1755 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_61.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_7.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_8.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..334a93f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_9.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..822b88f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.Vivado_Synthesis.queue.rst b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.Xil/regler_propImpl.xdc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.Xil/regler_propImpl.xdc new file mode 100644 index 0000000..8696049 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.Xil/regler_propImpl.xdc @@ -0,0 +1,3 @@ +set_property SRC_FILE_INFO {cfile:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc rfile:../../../Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..18a1a72 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.end.rst b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/ISEWrap.js b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..db0a510 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/ISEWrap.js @@ -0,0 +1,269 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/ISEWrap.sh b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..c2fbbb6 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/ISEWrap.sh @@ -0,0 +1,84 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/__synthesis_is_complete__ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..0c8bfdc --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml @@ -0,0 +1,89 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/htr.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/htr.txt new file mode 100644 index 0000000..ffcbae6 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log regler.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf new file mode 100644 index 0000000..9eb2a5f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3035343861623234333065633433623139386531656634383534326531333964:506172656e742050412070726f6a656374204944:00 +eof:4289439755 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp new file mode 100644 index 0000000..54d0bf7 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.tcl b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.tcl new file mode 100644 index 0000000..a14b412 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.tcl @@ -0,0 +1,123 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "synth_1" START { ROLLUP_AUTO } +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7z010clg400-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt [current_project] +set_property parent.project_path C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_vhdl -library xil_defaultlib C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc +set_property used_in_implementation false [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] + +set_param ips.enableIPCacheLiteLoad 1 + +read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top regler -part xc7z010clg400-1 +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef regler.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "synth_1_synth_report_utilization_0" "report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb" +OPTRACE "synth reports" END { } +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "synth_1" END { } diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds new file mode 100644 index 0000000..7418c7b --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds @@ -0,0 +1,233 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Wed May 11 14:51:23 2022 +# Process ID: 15124 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 +# Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +source regler.tcl -notrace +create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.617 ; gain = 8.895 +Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top regler -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' +INFO: [Device 21-403] Loading part xc7z010clg400-1 +WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 12736 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43] +WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:95] +WARNING: [Synth 8-6014] Unused sequential element e_k2_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:96] +INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1261.617 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] +Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/regler_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.617 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1261.617 ; gain = 0.000 +WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 3 Input 32 Bit Adders := 2 + 2 Input 32 Bit Adders := 1 + 2 Input 31 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Multipliers : + 1x32 Multipliers := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1262.070 ; gain = 0.453 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 104| +|3 |LUT1 | 66| +|4 |LUT2 | 59| +|5 |LUT3 | 182| +|6 |LUT4 | 138| +|7 |LUT5 | 49| +|8 |LUT6 | 186| +|9 |FDRE | 64| +|10 |IBUF | 65| +|11 |OBUF | 32| ++------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:38 . Memory (MB): peak = 1275.852 ; gain = 14.234 +Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1284.461 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1294.609 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete, checksum: 235c9ea4 +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 1294.609 ; gain = 32.992 +INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed May 11 14:52:19 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.pb new file mode 100644 index 0000000..e00eb9a Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt new file mode 100644 index 0000000..ea00cea --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt @@ -0,0 +1,179 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 +| Date : Wed May 11 14:52:19 2022 +| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) +| Command : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb +| Design : regler +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 538 | 0 | 0 | 17600 | 3.06 | +| LUT as Logic | 538 | 0 | 0 | 17600 | 3.06 | +| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 64 | 0 | 0 | 35200 | 0.18 | +| Register as Flip Flop | 64 | 0 | 0 | 35200 | 0.18 | +| Register as Latch | 0 | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 64 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 97 | 0 | 0 | 100 | 97.00 | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 0 | 8 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT6 | 186 | LUT | +| LUT3 | 182 | LUT | +| LUT4 | 138 | LUT | +| CARRY4 | 104 | CarryLogic | +| LUT1 | 66 | LUT | +| IBUF | 65 | IO | +| FDRE | 64 | Flop & Latch | +| LUT2 | 59 | LUT | +| LUT5 | 49 | LUT | +| OBUF | 32 | IO | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/rundef.js b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/rundef.js new file mode 100644 index 0000000..6f279c8 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;"; +} else { + PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log regler.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.bat new file mode 100644 index 0000000..6c4f290 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log new file mode 100644 index 0000000..8dff16d --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log @@ -0,0 +1,232 @@ + +*** Running vivado + with args -log regler.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl + + + +****** Vivado v2021.2 (64-bit) + **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 + **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 + ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. + +source regler.tcl -notrace +create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.617 ; gain = 8.895 +Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top regler -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' +INFO: [Device 21-403] Loading part xc7z010clg400-1 +WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 12736 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43] +WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:95] +WARNING: [Synth 8-6014] Unused sequential element e_k2_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:96] +INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1261.617 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] +Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/regler_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.617 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1261.617 ; gain = 0.000 +WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 3 Input 32 Bit Adders := 2 + 2 Input 32 Bit Adders := 1 + 2 Input 31 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Multipliers : + 1x32 Multipliers := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1261.617 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1262.070 ; gain = 0.453 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 104| +|3 |LUT1 | 66| +|4 |LUT2 | 59| +|5 |LUT3 | 182| +|6 |LUT4 | 138| +|7 |LUT5 | 49| +|8 |LUT6 | 186| +|9 |FDRE | 64| +|10 |IBUF | 65| +|11 |OBUF | 32| ++------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:38 . Memory (MB): peak = 1275.852 ; gain = 14.234 +Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1275.852 ; gain = 14.234 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1284.461 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1294.609 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete, checksum: 235c9ea4 +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 1294.609 ; gain = 32.992 +INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed May 11 14:52:19 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.sh b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.sh new file mode 100644 index 0000000..7fd56a5 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin +else + PATH=C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log regler.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou new file mode 100644 index 0000000..02f5e15 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Wed May 11 14:51:23 2022 +# Process ID: 15124 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 +# Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +source regler.tcl -notrace diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb new file mode 100644 index 0000000..b98674d Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..80fd303 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,26 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Wed May 11 14:53:11 +0200 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: compile.bat +REM +REM **************************************************************************** +REM compile VHDL design sources +echo "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +call xvhdl --incr --relax -prj pwm_test_db_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log new file mode 100644 index 0000000..067b6b7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..f64e503 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Wed May 11 14:53:14 +0200 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +REM elaborate design +echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..7e75ef2 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,19 @@ +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb new file mode 100644 index 0000000..6fa9743 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl new file mode 100644 index 0000000..f6215eb --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 5 s diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb new file mode 100644 index 0000000..2c05b86 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..7d49c16 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Wed May 11 14:53:17 +0200 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +REM simulate design +echo "xsim pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch pwm_test_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg -log simulate.log" +call xsim pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch pwm_test_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..3a14ee6 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1 @@ +Time resolution is 1 ps diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..2d4b18e Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg new file mode 100644 index 0000000..1d8cc0b Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimSettings.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimSettings.ini new file mode 100644 index 0000000..56ff420 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimcrash.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe new file mode 100644 index 0000000..bb81b98 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log new file mode 100644 index 0000000..7bfe923 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/pwm_test_behav/xsimk.exe -simmode gui -wdb pwm_test_behav.wdb -simrunnum 0 -socket 65496 +Design successfully loaded +Design Loading Memory Usage: 8396 KB (Peak: 8396 KB) +Design Loading CPU Usage: 15 ms +Simulation completed +Simulation Memory Usage: 8892 KB (Peak: 8892 KB) +Simulation CPU Usage: 78 ms diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt new file mode 100644 index 0000000..e2d8861 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "pwm_test_db_behav" "xil_defaultlib.pwm_test_db" -log "elaborate.log" diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/TempBreakPointFile.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..9d4ecc7 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c new file mode 100644 index 0000000..3dffdc5 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.c @@ -0,0 +1,111 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_13(char*, char *); +IKI_DLLESPEC extern void execute_14(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_12(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[6] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_10, (funcp)execute_12, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 6; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 6); + iki_vhdl_file_variable_register(dp + 5864); + iki_vhdl_file_variable_register(dp + 5920); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/pwm_test_db_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/pwm_test_db_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/pwm_test_db_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..57cae11 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg new file mode 100644 index 0000000..c620899 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.dbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem new file mode 100644 index 0000000..f675cfd Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.mem differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc new file mode 100644 index 0000000..49c332a Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.reloc differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx new file mode 100644 index 0000000..3835e3d --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 4299248977330252882 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , + buildDate : "Oct 19 2021" , + buildTime : "03:16:22" , + linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_behav/xsimk.exe\" \"xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti new file mode 100644 index 0000000..4d7e29a Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rtti differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.svtype b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.svtype differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type new file mode 100644 index 0000000..962d77f Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.type differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg new file mode 100644 index 0000000..a931a0a Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.xdbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini new file mode 100644 index 0000000..33023c2 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini @@ -0,0 +1,52 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=157 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=156 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=156 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 +[Object Radixes] +RADIX_0=hex /pwm_test_db/cnt; diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimcrash.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe new file mode 100644 index 0000000..59c97d7 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimk.exe differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log new file mode 100644 index 0000000..586b470 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 61498 +Design successfully loaded +Design Loading Memory Usage: 7260 KB (Peak: 7260 KB) +Design Loading CPU Usage: 62 ms +Simulation completed +Simulation Memory Usage: 15764 KB (Peak: 15764 KB) +Simulation CPU Usage: 1281 ms diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb new file mode 100644 index 0000000..4c2072c Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pt1.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test.vdb new file mode 100644 index 0000000..0bb4f2f Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb new file mode 100644 index 0000000..0c730e1 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb new file mode 100644 index 0000000..9ffe93c Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regler.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..fda9d9d --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,7 @@ +0.7 +2020.2 +Oct 19 2021 +03:16:22 +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652272655,vhdl,,,,pwm_test_db,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1651498208,vhdl,,,,pt1,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652273474,vhdl,,,,regler,,,,,,,, diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..d5b3dc7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1,476 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +uvm=$RDI_DATADIR/xsim/system_verilog/uvm +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +hdmi_acr_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_0 +compact_gt_v1_0_11=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_11 +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +oran_radio_if_v2_1_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v2_1_0 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +tmr_comparator_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_4 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0 +mrmac_v1_3_3=$RDI_DATADIR/xsim/ip/mrmac_v1_3_3 +ernic_v3_1_1=$RDI_DATADIR/xsim/ip/ernic_v3_1_1 +axi_uartlite_v2_0_29=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_29 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +pcie_qdma_mailbox_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_0 +axi_crossbar_v2_1_26=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_26 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +dcmac_v1_2_0=$RDI_DATADIR/xsim/ip/dcmac_v1_2_0 +axi_emc_v3_0_25=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_25 +axi_register_slice_v2_1_25=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_25 +xdfe_equalizer_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_1 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +xdfe_cc_mixer_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v1_0_1 +fast_adapter_v1_0_2=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_2 +mem_tg_v1_0_7=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_7 +cpm5_v1_0_5=$RDI_DATADIR/xsim/ip/cpm5_v1_0_5 +mult_gen_v12_0_17=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_17 +qdma_v4_0_8=$RDI_DATADIR/xsim/ip/qdma_v4_0_8 +xfft_v9_1_7=$RDI_DATADIR/xsim/ip/xfft_v9_1_7 +noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0 +axi_pcie3_v3_0_19=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_19 +dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf +system_cache_v5_0_7=$RDI_DATADIR/xsim/ip/system_cache_v5_0_7 +axi_tft_v2_0_24=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_24 +rs_toolbox_v9_0_8=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_8 +v_csc_v1_1_4=$RDI_DATADIR/xsim/ip/v_csc_v1_1_4 +axi_sideband_util_v1_0_9=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_9 +axis_combiner_v1_1_23=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_23 +sim_trig_v1_0_7=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_7 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +emb_mem_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_5 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +axi_timebase_wdt_v3_0_17=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_17 +roe_framer_v3_0_2=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_2 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +lte_3gpp_channel_estimator_v2_0_19=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_19 +axi_epc_v2_0_28=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_28 +noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0 +v_hdmi_rx1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_2 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0 +axis_clock_converter_v1_1_26=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_26 +processing_system7_vip_v1_0_13=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_13 +c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14 +mailbox_v2_1_15=$RDI_DATADIR/xsim/ip/mailbox_v2_1_15 +ten_gig_eth_mac_v15_1_10=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_10 +floating_point_v7_0_19=$RDI_DATADIR/xsim/ip/floating_point_v7_0_19 +v_smpte_uhdsdi_tx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_1 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +xdfe_cc_filter_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_0_1 +audio_formatter_v1_0_7=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_7 +gtwizard_ultrascale_v1_6_13=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_13 +qdriv_pl_v1_0_6=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_6 +audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0 +versal_cips_ps_vip_v1_0_3=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_3 +axi_perf_mon_v5_0_27=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_27 +dfx_controller_v1_0_2=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_2 +lib_bmg_v1_0_14=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_14 +amm_axi_bridge_v1_0_11=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_11 +sem_ultra_v3_1_21=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_21 +processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6 +axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +i2s_transmitter_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_5 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +v_axi4s_remap_v1_1_4=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_4 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0 +tri_mode_ethernet_mac_v9_0_20=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_20 +etrnic_v1_1_4=$RDI_DATADIR/xsim/ip/etrnic_v1_1_4 +ieee802d3_400g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_6 +tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4 +sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0 +sim_clk_gen_v1_0_3=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_3 +flexo_100g_rs_fec_v1_0_20=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_20 +axi_dma_v7_1_26=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_26 +g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +mrmac_v1_5_0=$RDI_DATADIR/xsim/ip/mrmac_v1_5_0 +emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0 +axi_usb2_device_v5_0_26=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_26 +clk_gen_sim_v1_0_2=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_2 +pcie_dma_versal_v2_0_7=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_7 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +ieee802d3_25g_rs_fec_v1_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_22 +v_hdmi_tx1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_2 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +axis_vio_v1_0_6=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_6 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +noc_nmu_phydir_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_phydir_v1_0_0 +pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1 +axi_chip2chip_v5_0_14=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_14 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +ethernet_1_10_25g_v2_7_2=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_2 +mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +ptp_1588_timer_syncer_v2_0_1=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_1 +vby1hs_v1_0_1=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_1 +axis_subset_converter_v1_1_25=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_25 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0 +switch_core_top_v1_0_10=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_10 +noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0 +pr_decoupler_v1_0_10=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_10 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +v_tpg_v8_0_8=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_8 +mpegtsmux_v1_1_3=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_3 +ptp_1588_timer_syncer_v1_0_2=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_2 +ieee802d3_rs_fec_v2_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_14 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +axi_clock_converter_v2_1_24=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_24 +v_smpte_uhdsdi_rx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_1 +axi_datamover_v5_1_27=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_27 +axis_data_fifo_v2_0_7=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_7 +tcc_decoder_3gppmm_v2_0_22=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_22 +tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0 +lte_pucch_receiver_v2_0_20=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_20 +lmb_bram_if_cntlr_v4_0_20=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_20 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +jesd204_v7_2_14=$RDI_DATADIR/xsim/ip/jesd204_v7_2_14 +vfb_v1_0_19=$RDI_DATADIR/xsim/ip/vfb_v1_0_19 +lte_3gpp_mimo_encoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_16 +uhdsdi_gt_v2_0_7=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_7 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +v_mix_v5_1_4=$RDI_DATADIR/xsim/ip/v_mix_v5_1_4 +dfx_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_1 +trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0 +g709_fec_v2_4_4=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_4 +gmii_to_rgmii_v4_1_3=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_3 +viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12 +lmb_v10_v3_0_11=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_11 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +axi_traffic_gen_v3_0_11=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_11 +v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9 +polar_v1_0_9=$RDI_DATADIR/xsim/ip/polar_v1_0_9 +lte_ul_channel_decoder_v4_0_18=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_18 +soft_ecc_proxy_v1_0_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_1 +axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17 +ldpc_v2_0_9=$RDI_DATADIR/xsim/ip/ldpc_v2_0_9 +axi_fifo_mm_s_v4_2_7=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_7 +axis_interconnect_v1_1_19=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_19 +sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0 +v_axi4s_remap_v1_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_18 +gig_ethernet_pcs_pma_v16_2_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_6 +xfft_v7_2_12=$RDI_DATADIR/xsim/ip/xfft_v7_2_12 +axi_ethernetlite_v3_0_24=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_24 +axi_sg_v4_1_14=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_14 +xdfe_resampler_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_1 +qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +axi_bram_ctrl_v4_1_6=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_6 +lte_rach_detector_v3_1_10=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_10 +axis_protocol_checker_v2_0_9=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_9 +vitis_deadlock_detector_v1_0_0=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_0 +v_uhdsdi_audio_v2_0_5=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_5 +cmac_v2_6_6=$RDI_DATADIR/xsim/ip/cmac_v2_6_6 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +ieee802d3_200g_rs_fec_v2_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_4 +cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15 +tsn_endpoint_ethernet_mac_block_v1_0_10=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_10 +av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1 +axi_c2c_v1_0_2=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_2 +axi_mcdma_v1_1_6=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_6 +dfx_decoupler_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_3 +axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1 +axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1 +axi4svideo_bridge_v1_0_13=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_13 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +l_ethernet_v3_2_4=$RDI_DATADIR/xsim/ip/l_ethernet_v3_2_4 +dds_compiler_v6_0_21=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_21 +v_frmbuf_wr_v2_3_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_3_0 +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +fc32_rs_fec_v1_0_20=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_20 +v_mix_v5_2_2=$RDI_DATADIR/xsim/ip/v_mix_v5_2_2 +pc_cfr_v7_0_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_0_0 +axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0 +xdma_v4_1_14=$RDI_DATADIR/xsim/ip/xdma_v4_1_14 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +axi_firewall_v1_2_0=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_0 +spdif_v2_0_25=$RDI_DATADIR/xsim/ip/spdif_v2_0_25 +ahblite_axi_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_20 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0 +axi_iic_v2_1_1=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_1 +displayport_v8_1_4=$RDI_DATADIR/xsim/ip/displayport_v8_1_4 +dft_v4_2_2=$RDI_DATADIR/xsim/ip/dft_v4_2_2 +video_frame_crc_v1_0_4=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_4 +v_vid_gt_bridge_v1_0_4=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_4 +div_gen_v5_1_18=$RDI_DATADIR/xsim/ip/div_gen_v5_1_18 +axi_pcie_v2_9_6=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_6 +axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0 +axi_ahblite_bridge_v3_0_22=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_22 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0 +v_vid_in_axi4s_v5_0_0=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_0 +g709_rs_decoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_9 +axi_protocol_converter_v2_1_25=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_25 +rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17 +hdmi_gt_controller_v1_0_6=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_6 +cordic_v6_0_17=$RDI_DATADIR/xsim/ip/cordic_v6_0_17 +axi_memory_init_v1_0_6=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_6 +axi_cdma_v4_1_25=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_25 +pc_cfr_v6_4_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_2 +ten_gig_eth_pcs_pma_v6_0_21=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_21 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +axi_msg_v1_0_7=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_7 +nvme_tc_v3_0_0=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_0 +v_frmbuf_rd_v2_2_4=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_4 +trace_s2mm_v1_2_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_2_0 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +mipi_dphy_v4_3_3=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_3 +ats_switch_v1_0_4=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_4 +axi_vfifo_ctrl_v2_0_27=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_27 +cpm4_v1_0_5=$RDI_DATADIR/xsim/ip/cpm4_v1_0_5 +v_tc_v6_2_3=$RDI_DATADIR/xsim/ip/v_tc_v6_2_3 +v_dp_axi4s_vid_out_v1_0_3=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_3 +axis_switch_v1_1_25=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_25 +axis_dwidth_converter_v1_1_24=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_24 +lte_3gpp_mimo_decoder_v3_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_17 +multi_channel_25g_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_15 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +convolution_v9_0_15=$RDI_DATADIR/xsim/ip/convolution_v9_0_15 +v_axi4s_vid_out_v4_0_13=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_13 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0 +axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0 +v_warp_filter_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_0_2 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +axis_register_slice_v1_1_25=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_25 +blk_mem_gen_v8_4_5=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_5 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +v_vscaler_v1_1_4=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_4 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +aurora_8b10b_versal_v1_0_1=$RDI_DATADIR/xsim/ip/aurora_8b10b_versal_v1_0_1 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +tmr_sem_v1_0_20=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_20 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2 +mdm_v3_2_22=$RDI_DATADIR/xsim/ip/mdm_v3_2_22 +noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0 +an_lt_v1_0_5=$RDI_DATADIR/xsim/ip/an_lt_v1_0_5 +v_frmbuf_rd_v2_3_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_3_0 +axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0 +vid_phy_controller_v2_2_12=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_12 +dsp_macro_v1_0_2=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_2 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +lte_fft_v2_1_5=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_5 +can_v5_0_28=$RDI_DATADIR/xsim/ip/can_v5_0_28 +axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0 +c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14 +axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0 +usxgmii_v1_2_4=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_4 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14 +v_vcresampler_v1_1_4=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_4 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +zynq_ultra_ps_e_vip_v1_0_11=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_11 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +v_demosaic_v1_1_4=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_4 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +xpm_cdc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_0 +axi_data_fifo_v2_1_24=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_24 +ilknf_v1_0_0=$RDI_DATADIR/xsim/ip/ilknf_v1_0_0 +axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4 +versal_cips_v3_1_0=$RDI_DATADIR/xsim/ip/versal_cips_v3_1_0 +adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0 +i2s_receiver_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_5 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4 +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +axis_broadcaster_v1_1_24=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_24 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0 +axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0 +icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0 +dcmac_v1_1_0=$RDI_DATADIR/xsim/ip/dcmac_v1_1_0 +interlaken_v2_4_10=$RDI_DATADIR/xsim/ip/interlaken_v2_4_10 +axi_mm2s_mapper_v1_1_24=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_24 +v_frmbuf_wr_v2_2_4=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_4 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +cmpy_v6_0_20=$RDI_DATADIR/xsim/ip/cmpy_v6_0_20 +axi_protocol_checker_v2_0_11=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_11 +shell_utils_addr_remap_v1_0_4=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_4 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +axi_firewall_v1_1_4=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_4 +xxv_ethernet_v4_0_2=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_0_2 +axi_vip_v1_1_11=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_11 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +xpm=$RDI_DATADIR/xsim/ip/xpm +perf_axi_tg_v1_0_7=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_7 +ieee802d3_50g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_18 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0 +lte_dl_channel_encoder_v4_0_3=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_3 +axi_timer_v2_0_27=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_27 +tmr_manager_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_8 +axi_gpio_v2_0_27=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_27 +displayport_v9_0_4=$RDI_DATADIR/xsim/ip/displayport_v9_0_4 +xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0 +picxo=$RDI_DATADIR/xsim/ip/picxo +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +srio_gen2_v4_1_13=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_13 +av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0 +lte_fft_v2_0_21=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_21 +sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13 +axis_data_fifo_v1_1_26=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_26 +axi4stream_vip_v1_1_11=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_11 +vid_phy_controller_v2_1_12=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_12 +axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0 +microblaze_v11_0_8=$RDI_DATADIR/xsim/ip/microblaze_v11_0_8 +v_gamma_lut_v1_1_4=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_4 +axi_amm_bridge_v1_0_15=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_15 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +advanced_io_wizard_v1_0_6=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_6 +sid_v8_0_16=$RDI_DATADIR/xsim/ip/sid_v8_0_16 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +axi_hwicap_v3_0_29=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_29 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +v_smpte_uhdsdi_v1_0_9=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_9 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +tcc_encoder_3gpp_v5_0_17=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_17 +v_tpg_v8_2_0=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_0 +fir_compiler_v7_2_17=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_17 +cpri_v8_11_9=$RDI_DATADIR/xsim/ip/cpri_v8_11_9 +fifo_generator_v13_2_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_6 +v_letterbox_v1_1_4=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_4 +in_system_ibert_v1_0_15=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_15 +ieee802d3_clause74_fec_v1_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_12 +xscl=$RDI_DATADIR/xsim/ip/xscl +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +iomodule_v3_1_7=$RDI_DATADIR/xsim/ip/iomodule_v3_1_7 +xdfe_fft_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_1 +axi_interconnect_v1_7_19=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_19 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +axi_dwidth_converter_v2_1_25=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_25 +ddr4_pl_v1_0_7=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_7 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +hbm_phyio_control_v1_0_0=$RDI_DATADIR/xsim/ip/hbm_phyio_control_v1_0_0 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7 +v_multi_scaler_v1_2_2=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_2 +axi_mmu_v2_1_23=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_23 +axi_hbicap_v1_0_4=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_4 +quadsgmii_v3_5_5=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_5 +tsn_temac_v1_0_6=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_6 +gtwizard_ultrascale_v1_7_12=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_12 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +v_hscaler_v1_1_4=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_4 +ll_compress_v2_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v2_0_0 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +v_warp_init_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_init_v1_0_2 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +high_speed_selectio_wiz_v3_6_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_2 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14 +sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0 +axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0 +axi_quad_spi_v3_2_24=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_24 +v_scenechange_v1_1_3=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_3 +ieee802d3_50g_rs_fec_v2_0_10=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_10 +axi_intc_v4_1_16=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_16 +canfd_v3_0_4=$RDI_DATADIR/xsim/ip/canfd_v3_0_4 +sd_fec_v1_1_8=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_8 +uram_rd_back_v1_0_2=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_2 +axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +cam_v2_2_2=$RDI_DATADIR/xsim/ip/cam_v2_2_2 +zynq_ultra_ps_e_v3_3_6=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_6 +duc_ddc_compiler_v3_0_16=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_16 +emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_vdma_v6_3_13=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_13 +dprx_fec_8b10b_v1_0_1=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_1 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +xbip_multadd_v3_0_16=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_16 +lib_fifo_v1_0_15=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_15 +xdfe_common_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_0 +axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16 +jesd204c_v4_2_7=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_7 +cmac_usplus_v3_1_6=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_6 +axi_ethernet_buffer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_24 +v_hcresampler_v1_1_4=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_4 +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +rld3_pl_v1_0_8=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_8 +v_tpg_v8_1_4=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_4 +vitis_net_p4_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_net_p4_v1_0_2 +rama_v1_1_11_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_11_lib +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1 +nvmeha_v1_0_6=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_6 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +xdfe_nr_prach_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v1_0_1 +v_hdmi_phy1_v1_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_5 +axi_uart16550_v2_0_27=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_27 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +floating_point_v7_1_13=$RDI_DATADIR/xsim/ip/floating_point_v7_1_13 +oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2 +rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16 +ta_dma_v1_0_9=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_9 +ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini.bak b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini.bak new file mode 100644 index 0000000..d5b3dc7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.ini.bak @@ -0,0 +1,476 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +uvm=$RDI_DATADIR/xsim/system_verilog/uvm +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +hdmi_acr_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_0 +compact_gt_v1_0_11=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_11 +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +oran_radio_if_v2_1_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v2_1_0 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +tmr_comparator_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_4 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0 +mrmac_v1_3_3=$RDI_DATADIR/xsim/ip/mrmac_v1_3_3 +ernic_v3_1_1=$RDI_DATADIR/xsim/ip/ernic_v3_1_1 +axi_uartlite_v2_0_29=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_29 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +pcie_qdma_mailbox_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_0 +axi_crossbar_v2_1_26=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_26 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +dcmac_v1_2_0=$RDI_DATADIR/xsim/ip/dcmac_v1_2_0 +axi_emc_v3_0_25=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_25 +axi_register_slice_v2_1_25=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_25 +xdfe_equalizer_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_1 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +xdfe_cc_mixer_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v1_0_1 +fast_adapter_v1_0_2=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_2 +mem_tg_v1_0_7=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_7 +cpm5_v1_0_5=$RDI_DATADIR/xsim/ip/cpm5_v1_0_5 +mult_gen_v12_0_17=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_17 +qdma_v4_0_8=$RDI_DATADIR/xsim/ip/qdma_v4_0_8 +xfft_v9_1_7=$RDI_DATADIR/xsim/ip/xfft_v9_1_7 +noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0 +axi_pcie3_v3_0_19=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_19 +dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf +system_cache_v5_0_7=$RDI_DATADIR/xsim/ip/system_cache_v5_0_7 +axi_tft_v2_0_24=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_24 +rs_toolbox_v9_0_8=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_8 +v_csc_v1_1_4=$RDI_DATADIR/xsim/ip/v_csc_v1_1_4 +axi_sideband_util_v1_0_9=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_9 +axis_combiner_v1_1_23=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_23 +sim_trig_v1_0_7=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_7 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +emb_mem_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_5 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +axi_timebase_wdt_v3_0_17=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_17 +roe_framer_v3_0_2=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_2 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +lte_3gpp_channel_estimator_v2_0_19=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_19 +axi_epc_v2_0_28=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_28 +noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0 +v_hdmi_rx1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_2 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0 +axis_clock_converter_v1_1_26=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_26 +processing_system7_vip_v1_0_13=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_13 +c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14 +mailbox_v2_1_15=$RDI_DATADIR/xsim/ip/mailbox_v2_1_15 +ten_gig_eth_mac_v15_1_10=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_10 +floating_point_v7_0_19=$RDI_DATADIR/xsim/ip/floating_point_v7_0_19 +v_smpte_uhdsdi_tx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_1 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +xdfe_cc_filter_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_0_1 +audio_formatter_v1_0_7=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_7 +gtwizard_ultrascale_v1_6_13=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_13 +qdriv_pl_v1_0_6=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_6 +audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0 +versal_cips_ps_vip_v1_0_3=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_3 +axi_perf_mon_v5_0_27=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_27 +dfx_controller_v1_0_2=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_2 +lib_bmg_v1_0_14=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_14 +amm_axi_bridge_v1_0_11=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_11 +sem_ultra_v3_1_21=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_21 +processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6 +axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +i2s_transmitter_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_5 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +v_axi4s_remap_v1_1_4=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_4 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0 +tri_mode_ethernet_mac_v9_0_20=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_20 +etrnic_v1_1_4=$RDI_DATADIR/xsim/ip/etrnic_v1_1_4 +ieee802d3_400g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_6 +tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4 +sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0 +sim_clk_gen_v1_0_3=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_3 +flexo_100g_rs_fec_v1_0_20=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_20 +axi_dma_v7_1_26=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_26 +g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +mrmac_v1_5_0=$RDI_DATADIR/xsim/ip/mrmac_v1_5_0 +emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0 +axi_usb2_device_v5_0_26=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_26 +clk_gen_sim_v1_0_2=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_2 +pcie_dma_versal_v2_0_7=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_7 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +ieee802d3_25g_rs_fec_v1_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_22 +v_hdmi_tx1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_2 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +axis_vio_v1_0_6=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_6 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +noc_nmu_phydir_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_phydir_v1_0_0 +pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1 +axi_chip2chip_v5_0_14=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_14 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +ethernet_1_10_25g_v2_7_2=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_2 +mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +ptp_1588_timer_syncer_v2_0_1=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_1 +vby1hs_v1_0_1=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_1 +axis_subset_converter_v1_1_25=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_25 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0 +switch_core_top_v1_0_10=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_10 +noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0 +pr_decoupler_v1_0_10=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_10 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +v_tpg_v8_0_8=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_8 +mpegtsmux_v1_1_3=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_3 +ptp_1588_timer_syncer_v1_0_2=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_2 +ieee802d3_rs_fec_v2_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_14 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +axi_clock_converter_v2_1_24=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_24 +v_smpte_uhdsdi_rx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_1 +axi_datamover_v5_1_27=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_27 +axis_data_fifo_v2_0_7=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_7 +tcc_decoder_3gppmm_v2_0_22=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_22 +tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0 +lte_pucch_receiver_v2_0_20=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_20 +lmb_bram_if_cntlr_v4_0_20=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_20 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +jesd204_v7_2_14=$RDI_DATADIR/xsim/ip/jesd204_v7_2_14 +vfb_v1_0_19=$RDI_DATADIR/xsim/ip/vfb_v1_0_19 +lte_3gpp_mimo_encoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_16 +uhdsdi_gt_v2_0_7=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_7 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +v_mix_v5_1_4=$RDI_DATADIR/xsim/ip/v_mix_v5_1_4 +dfx_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_1 +trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0 +g709_fec_v2_4_4=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_4 +gmii_to_rgmii_v4_1_3=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_3 +viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12 +lmb_v10_v3_0_11=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_11 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +axi_traffic_gen_v3_0_11=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_11 +v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9 +polar_v1_0_9=$RDI_DATADIR/xsim/ip/polar_v1_0_9 +lte_ul_channel_decoder_v4_0_18=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_18 +soft_ecc_proxy_v1_0_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_1 +axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17 +ldpc_v2_0_9=$RDI_DATADIR/xsim/ip/ldpc_v2_0_9 +axi_fifo_mm_s_v4_2_7=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_7 +axis_interconnect_v1_1_19=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_19 +sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0 +v_axi4s_remap_v1_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_18 +gig_ethernet_pcs_pma_v16_2_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_6 +xfft_v7_2_12=$RDI_DATADIR/xsim/ip/xfft_v7_2_12 +axi_ethernetlite_v3_0_24=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_24 +axi_sg_v4_1_14=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_14 +xdfe_resampler_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_1 +qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +axi_bram_ctrl_v4_1_6=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_6 +lte_rach_detector_v3_1_10=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_10 +axis_protocol_checker_v2_0_9=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_9 +vitis_deadlock_detector_v1_0_0=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_0 +v_uhdsdi_audio_v2_0_5=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_5 +cmac_v2_6_6=$RDI_DATADIR/xsim/ip/cmac_v2_6_6 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +ieee802d3_200g_rs_fec_v2_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_4 +cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15 +tsn_endpoint_ethernet_mac_block_v1_0_10=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_10 +av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1 +axi_c2c_v1_0_2=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_2 +axi_mcdma_v1_1_6=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_6 +dfx_decoupler_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_3 +axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1 +axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1 +axi4svideo_bridge_v1_0_13=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_13 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +l_ethernet_v3_2_4=$RDI_DATADIR/xsim/ip/l_ethernet_v3_2_4 +dds_compiler_v6_0_21=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_21 +v_frmbuf_wr_v2_3_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_3_0 +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +fc32_rs_fec_v1_0_20=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_20 +v_mix_v5_2_2=$RDI_DATADIR/xsim/ip/v_mix_v5_2_2 +pc_cfr_v7_0_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_0_0 +axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0 +xdma_v4_1_14=$RDI_DATADIR/xsim/ip/xdma_v4_1_14 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +axi_firewall_v1_2_0=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_0 +spdif_v2_0_25=$RDI_DATADIR/xsim/ip/spdif_v2_0_25 +ahblite_axi_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_20 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0 +axi_iic_v2_1_1=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_1 +displayport_v8_1_4=$RDI_DATADIR/xsim/ip/displayport_v8_1_4 +dft_v4_2_2=$RDI_DATADIR/xsim/ip/dft_v4_2_2 +video_frame_crc_v1_0_4=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_4 +v_vid_gt_bridge_v1_0_4=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_4 +div_gen_v5_1_18=$RDI_DATADIR/xsim/ip/div_gen_v5_1_18 +axi_pcie_v2_9_6=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_6 +axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0 +axi_ahblite_bridge_v3_0_22=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_22 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0 +v_vid_in_axi4s_v5_0_0=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_0 +g709_rs_decoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_9 +axi_protocol_converter_v2_1_25=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_25 +rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17 +hdmi_gt_controller_v1_0_6=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_6 +cordic_v6_0_17=$RDI_DATADIR/xsim/ip/cordic_v6_0_17 +axi_memory_init_v1_0_6=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_6 +axi_cdma_v4_1_25=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_25 +pc_cfr_v6_4_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_2 +ten_gig_eth_pcs_pma_v6_0_21=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_21 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +axi_msg_v1_0_7=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_7 +nvme_tc_v3_0_0=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_0 +v_frmbuf_rd_v2_2_4=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_4 +trace_s2mm_v1_2_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_2_0 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +mipi_dphy_v4_3_3=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_3 +ats_switch_v1_0_4=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_4 +axi_vfifo_ctrl_v2_0_27=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_27 +cpm4_v1_0_5=$RDI_DATADIR/xsim/ip/cpm4_v1_0_5 +v_tc_v6_2_3=$RDI_DATADIR/xsim/ip/v_tc_v6_2_3 +v_dp_axi4s_vid_out_v1_0_3=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_3 +axis_switch_v1_1_25=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_25 +axis_dwidth_converter_v1_1_24=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_24 +lte_3gpp_mimo_decoder_v3_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_17 +multi_channel_25g_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_15 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +convolution_v9_0_15=$RDI_DATADIR/xsim/ip/convolution_v9_0_15 +v_axi4s_vid_out_v4_0_13=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_13 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0 +axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0 +v_warp_filter_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_0_2 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +axis_register_slice_v1_1_25=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_25 +blk_mem_gen_v8_4_5=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_5 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +v_vscaler_v1_1_4=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_4 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +aurora_8b10b_versal_v1_0_1=$RDI_DATADIR/xsim/ip/aurora_8b10b_versal_v1_0_1 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +tmr_sem_v1_0_20=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_20 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2 +mdm_v3_2_22=$RDI_DATADIR/xsim/ip/mdm_v3_2_22 +noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0 +an_lt_v1_0_5=$RDI_DATADIR/xsim/ip/an_lt_v1_0_5 +v_frmbuf_rd_v2_3_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_3_0 +axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0 +vid_phy_controller_v2_2_12=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_12 +dsp_macro_v1_0_2=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_2 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +lte_fft_v2_1_5=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_5 +can_v5_0_28=$RDI_DATADIR/xsim/ip/can_v5_0_28 +axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0 +c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14 +axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0 +usxgmii_v1_2_4=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_4 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14 +v_vcresampler_v1_1_4=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_4 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +zynq_ultra_ps_e_vip_v1_0_11=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_11 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +v_demosaic_v1_1_4=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_4 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +xpm_cdc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_0 +axi_data_fifo_v2_1_24=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_24 +ilknf_v1_0_0=$RDI_DATADIR/xsim/ip/ilknf_v1_0_0 +axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4 +versal_cips_v3_1_0=$RDI_DATADIR/xsim/ip/versal_cips_v3_1_0 +adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0 +i2s_receiver_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_5 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4 +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +axis_broadcaster_v1_1_24=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_24 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0 +axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0 +icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0 +dcmac_v1_1_0=$RDI_DATADIR/xsim/ip/dcmac_v1_1_0 +interlaken_v2_4_10=$RDI_DATADIR/xsim/ip/interlaken_v2_4_10 +axi_mm2s_mapper_v1_1_24=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_24 +v_frmbuf_wr_v2_2_4=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_4 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +cmpy_v6_0_20=$RDI_DATADIR/xsim/ip/cmpy_v6_0_20 +axi_protocol_checker_v2_0_11=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_11 +shell_utils_addr_remap_v1_0_4=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_4 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +axi_firewall_v1_1_4=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_4 +xxv_ethernet_v4_0_2=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_0_2 +axi_vip_v1_1_11=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_11 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +xpm=$RDI_DATADIR/xsim/ip/xpm +perf_axi_tg_v1_0_7=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_7 +ieee802d3_50g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_18 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0 +lte_dl_channel_encoder_v4_0_3=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_3 +axi_timer_v2_0_27=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_27 +tmr_manager_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_8 +axi_gpio_v2_0_27=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_27 +displayport_v9_0_4=$RDI_DATADIR/xsim/ip/displayport_v9_0_4 +xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0 +picxo=$RDI_DATADIR/xsim/ip/picxo +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +srio_gen2_v4_1_13=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_13 +av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0 +lte_fft_v2_0_21=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_21 +sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13 +axis_data_fifo_v1_1_26=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_26 +axi4stream_vip_v1_1_11=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_11 +vid_phy_controller_v2_1_12=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_12 +axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0 +microblaze_v11_0_8=$RDI_DATADIR/xsim/ip/microblaze_v11_0_8 +v_gamma_lut_v1_1_4=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_4 +axi_amm_bridge_v1_0_15=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_15 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +advanced_io_wizard_v1_0_6=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_6 +sid_v8_0_16=$RDI_DATADIR/xsim/ip/sid_v8_0_16 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +axi_hwicap_v3_0_29=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_29 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +v_smpte_uhdsdi_v1_0_9=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_9 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +tcc_encoder_3gpp_v5_0_17=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_17 +v_tpg_v8_2_0=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_0 +fir_compiler_v7_2_17=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_17 +cpri_v8_11_9=$RDI_DATADIR/xsim/ip/cpri_v8_11_9 +fifo_generator_v13_2_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_6 +v_letterbox_v1_1_4=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_4 +in_system_ibert_v1_0_15=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_15 +ieee802d3_clause74_fec_v1_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_12 +xscl=$RDI_DATADIR/xsim/ip/xscl +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +iomodule_v3_1_7=$RDI_DATADIR/xsim/ip/iomodule_v3_1_7 +xdfe_fft_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_1 +axi_interconnect_v1_7_19=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_19 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +axi_dwidth_converter_v2_1_25=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_25 +ddr4_pl_v1_0_7=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_7 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +hbm_phyio_control_v1_0_0=$RDI_DATADIR/xsim/ip/hbm_phyio_control_v1_0_0 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7 +v_multi_scaler_v1_2_2=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_2 +axi_mmu_v2_1_23=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_23 +axi_hbicap_v1_0_4=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_4 +quadsgmii_v3_5_5=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_5 +tsn_temac_v1_0_6=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_6 +gtwizard_ultrascale_v1_7_12=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_12 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +v_hscaler_v1_1_4=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_4 +ll_compress_v2_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v2_0_0 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +v_warp_init_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_init_v1_0_2 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +high_speed_selectio_wiz_v3_6_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_2 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14 +sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0 +axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0 +axi_quad_spi_v3_2_24=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_24 +v_scenechange_v1_1_3=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_3 +ieee802d3_50g_rs_fec_v2_0_10=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_10 +axi_intc_v4_1_16=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_16 +canfd_v3_0_4=$RDI_DATADIR/xsim/ip/canfd_v3_0_4 +sd_fec_v1_1_8=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_8 +uram_rd_back_v1_0_2=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_2 +axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +cam_v2_2_2=$RDI_DATADIR/xsim/ip/cam_v2_2_2 +zynq_ultra_ps_e_v3_3_6=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_6 +duc_ddc_compiler_v3_0_16=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_16 +emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_vdma_v6_3_13=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_13 +dprx_fec_8b10b_v1_0_1=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_1 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +xbip_multadd_v3_0_16=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_16 +lib_fifo_v1_0_15=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_15 +xdfe_common_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_0 +axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16 +jesd204c_v4_2_7=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_7 +cmac_usplus_v3_1_6=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_6 +axi_ethernet_buffer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_24 +v_hcresampler_v1_1_4=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_4 +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +rld3_pl_v1_0_8=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_8 +v_tpg_v8_1_4=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_4 +vitis_net_p4_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_net_p4_v1_0_2 +rama_v1_1_11_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_11_lib +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1 +nvmeha_v1_0_6=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_6 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +xdfe_nr_prach_v1_0_1=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v1_0_1 +v_hdmi_phy1_v1_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_5 +axi_uart16550_v2_0_27=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_27 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +floating_point_v7_1_13=$RDI_DATADIR/xsim/ip/floating_point_v7_1_13 +oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2 +rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16 +ta_dma_v1_0_9=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_9 +ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log new file mode 100644 index 0000000..067b6b7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..c13ee82 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/compile.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/compile.bat new file mode 100644 index 0000000..cfca2da --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/compile.bat @@ -0,0 +1,30 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Wed Mar 16 20:51:33 +0100 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: compile.bat +REM +REM **************************************************************************** +REM compile Verilog/System Verilog design sources +echo "xvlog --incr --relax -prj pwm_test_db_vlog.prj" +call xvlog --incr --relax -prj pwm_test_db_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +REM compile VHDL design sources +echo "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +call xvhdl --incr --relax -prj pwm_test_db_vhdl.prj -log xvhdl.log +call type xvhdl.log >> compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.bat new file mode 100644 index 0000000..66b4e36 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Wed Mar 16 20:51:37 +0100 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +REM elaborate design +echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" +call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.log new file mode 100644 index 0000000..edf13b1 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/elaborate.log @@ -0,0 +1,8 @@ +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Pass Through NonSizing Optimizer +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db.tcl b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v new file mode 100644 index 0000000..aefc624 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v @@ -0,0 +1,1024 @@ +// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 +// Date : Wed Mar 16 20:26:05 2022 +// Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) +// Command : write_verilog -mode funcsim -nolib -force -file +// C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v +// Design : pwm_test +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module pwm_test + (clk, + led); + input clk; + output led; + + wire clk; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire \count[0]_i_2_n_0 ; + wire [31:0]count_reg; + wire \count_reg[0]_i_1_n_0 ; + wire \count_reg[0]_i_1_n_1 ; + wire \count_reg[0]_i_1_n_2 ; + wire \count_reg[0]_i_1_n_3 ; + wire \count_reg[0]_i_1_n_4 ; + wire \count_reg[0]_i_1_n_5 ; + wire \count_reg[0]_i_1_n_6 ; + wire \count_reg[0]_i_1_n_7 ; + wire \count_reg[12]_i_1_n_0 ; + wire \count_reg[12]_i_1_n_1 ; + wire \count_reg[12]_i_1_n_2 ; + wire \count_reg[12]_i_1_n_3 ; + wire \count_reg[12]_i_1_n_4 ; + wire \count_reg[12]_i_1_n_5 ; + wire \count_reg[12]_i_1_n_6 ; + wire \count_reg[12]_i_1_n_7 ; + wire \count_reg[16]_i_1_n_0 ; + wire \count_reg[16]_i_1_n_1 ; + wire \count_reg[16]_i_1_n_2 ; + wire \count_reg[16]_i_1_n_3 ; + wire \count_reg[16]_i_1_n_4 ; + wire \count_reg[16]_i_1_n_5 ; + wire \count_reg[16]_i_1_n_6 ; + wire \count_reg[16]_i_1_n_7 ; + wire \count_reg[20]_i_1_n_0 ; + wire \count_reg[20]_i_1_n_1 ; + wire \count_reg[20]_i_1_n_2 ; + wire \count_reg[20]_i_1_n_3 ; + wire \count_reg[20]_i_1_n_4 ; + wire \count_reg[20]_i_1_n_5 ; + wire \count_reg[20]_i_1_n_6 ; + wire \count_reg[20]_i_1_n_7 ; + wire \count_reg[24]_i_1_n_0 ; + wire \count_reg[24]_i_1_n_1 ; + wire \count_reg[24]_i_1_n_2 ; + wire \count_reg[24]_i_1_n_3 ; + wire \count_reg[24]_i_1_n_4 ; + wire \count_reg[24]_i_1_n_5 ; + wire \count_reg[24]_i_1_n_6 ; + wire \count_reg[24]_i_1_n_7 ; + wire \count_reg[28]_i_1_n_1 ; + wire \count_reg[28]_i_1_n_2 ; + wire \count_reg[28]_i_1_n_3 ; + wire \count_reg[28]_i_1_n_4 ; + wire \count_reg[28]_i_1_n_5 ; + wire \count_reg[28]_i_1_n_6 ; + wire \count_reg[28]_i_1_n_7 ; + wire \count_reg[4]_i_1_n_0 ; + wire \count_reg[4]_i_1_n_1 ; + wire \count_reg[4]_i_1_n_2 ; + wire \count_reg[4]_i_1_n_3 ; + wire \count_reg[4]_i_1_n_4 ; + wire \count_reg[4]_i_1_n_5 ; + wire \count_reg[4]_i_1_n_6 ; + wire \count_reg[4]_i_1_n_7 ; + wire \count_reg[8]_i_1_n_0 ; + wire \count_reg[8]_i_1_n_1 ; + wire \count_reg[8]_i_1_n_2 ; + wire \count_reg[8]_i_1_n_3 ; + wire \count_reg[8]_i_1_n_4 ; + wire \count_reg[8]_i_1_n_5 ; + wire \count_reg[8]_i_1_n_6 ; + wire \count_reg[8]_i_1_n_7 ; + wire led; + wire led_OBUF; + wire led_reg_i_10_n_0; + wire led_reg_i_11_n_0; + wire led_reg_i_12_n_0; + wire led_reg_i_12_n_1; + wire led_reg_i_12_n_2; + wire led_reg_i_12_n_3; + wire led_reg_i_13_n_0; + wire led_reg_i_14_n_0; + wire led_reg_i_15_n_0; + wire led_reg_i_16_n_0; + wire led_reg_i_17_n_0; + wire led_reg_i_18_n_0; + wire led_reg_i_19_n_0; + wire led_reg_i_1_n_0; + wire led_reg_i_1_n_1; + wire led_reg_i_1_n_2; + wire led_reg_i_1_n_3; + wire led_reg_i_20_n_0; + wire led_reg_i_21_n_0; + wire led_reg_i_21_n_1; + wire led_reg_i_21_n_2; + wire led_reg_i_21_n_3; + wire led_reg_i_22_n_0; + wire led_reg_i_23_n_0; + wire led_reg_i_24_n_0; + wire led_reg_i_25_n_0; + wire led_reg_i_26_n_0; + wire led_reg_i_27_n_0; + wire led_reg_i_28_n_0; + wire led_reg_i_28_n_1; + wire led_reg_i_28_n_2; + wire led_reg_i_28_n_3; + wire led_reg_i_29_n_0; + wire led_reg_i_2_n_0; + wire led_reg_i_2_n_1; + wire led_reg_i_2_n_2; + wire led_reg_i_2_n_3; + wire led_reg_i_30_n_0; + wire led_reg_i_31_n_0; + wire led_reg_i_32_n_0; + wire led_reg_i_33_n_0; + wire led_reg_i_34_n_0; + wire led_reg_i_35_n_0; + wire led_reg_i_35_n_1; + wire led_reg_i_35_n_2; + wire led_reg_i_35_n_3; + wire led_reg_i_36_n_0; + wire led_reg_i_37_n_0; + wire led_reg_i_38_n_0; + wire led_reg_i_39_n_0; + wire led_reg_i_3_n_0; + wire led_reg_i_3_n_1; + wire led_reg_i_3_n_2; + wire led_reg_i_3_n_3; + wire led_reg_i_40_n_0; + wire led_reg_i_41_n_0; + wire led_reg_i_42_n_0; + wire led_reg_i_43_n_0; + wire led_reg_i_43_n_1; + wire led_reg_i_43_n_2; + wire led_reg_i_43_n_3; + wire led_reg_i_44_n_0; + wire led_reg_i_45_n_0; + wire led_reg_i_46_n_0; + wire led_reg_i_47_n_0; + wire led_reg_i_48_n_0; + wire led_reg_i_49_n_0; + wire led_reg_i_4_n_0; + wire led_reg_i_50_n_0; + wire led_reg_i_51_n_0; + wire led_reg_i_52_n_0; + wire led_reg_i_53_n_0; + wire led_reg_i_54_n_0; + wire led_reg_i_55_n_0; + wire led_reg_i_56_n_0; + wire led_reg_i_57_n_0; + wire led_reg_i_58_n_0; + wire led_reg_i_59_n_0; + wire led_reg_i_5_n_0; + wire led_reg_i_60_n_0; + wire led_reg_i_61_n_0; + wire led_reg_i_62_n_0; + wire led_reg_i_63_n_0; + wire led_reg_i_64_n_0; + wire led_reg_i_65_n_0; + wire led_reg_i_6_n_0; + wire led_reg_i_7_n_0; + wire led_reg_i_8_n_0; + wire led_reg_i_9_n_0; + wire [3:3]\NLW_count_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_led_reg_i_1_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_12_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_2_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_21_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_28_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_3_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_35_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_43_O_UNCONNECTED; + + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + LUT1 #( + .INIT(2'h1)) + \count[0]_i_2 + (.I0(count_reg[0]), + .O(\count[0]_i_2_n_0 )); + FDCE #( + .INIT(1'b0)) + \count_reg[0] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[0]_i_1_n_7 ), + .Q(count_reg[0])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[0]_i_1 + (.CI(1'b0), + .CO({\count_reg[0]_i_1_n_0 ,\count_reg[0]_i_1_n_1 ,\count_reg[0]_i_1_n_2 ,\count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\count_reg[0]_i_1_n_4 ,\count_reg[0]_i_1_n_5 ,\count_reg[0]_i_1_n_6 ,\count_reg[0]_i_1_n_7 }), + .S({count_reg[3:1],\count[0]_i_2_n_0 })); + FDCE #( + .INIT(1'b0)) + \count_reg[10] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[8]_i_1_n_5 ), + .Q(count_reg[10])); + FDCE #( + .INIT(1'b0)) + \count_reg[11] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[8]_i_1_n_4 ), + .Q(count_reg[11])); + FDCE #( + .INIT(1'b0)) + \count_reg[12] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[12]_i_1_n_7 ), + .Q(count_reg[12])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[12]_i_1 + (.CI(\count_reg[8]_i_1_n_0 ), + .CO({\count_reg[12]_i_1_n_0 ,\count_reg[12]_i_1_n_1 ,\count_reg[12]_i_1_n_2 ,\count_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[12]_i_1_n_4 ,\count_reg[12]_i_1_n_5 ,\count_reg[12]_i_1_n_6 ,\count_reg[12]_i_1_n_7 }), + .S(count_reg[15:12])); + FDCE #( + .INIT(1'b0)) + \count_reg[13] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[12]_i_1_n_6 ), + .Q(count_reg[13])); + FDCE #( + .INIT(1'b0)) + \count_reg[14] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[12]_i_1_n_5 ), + .Q(count_reg[14])); + FDCE #( + .INIT(1'b0)) + \count_reg[15] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[12]_i_1_n_4 ), + .Q(count_reg[15])); + FDCE #( + .INIT(1'b0)) + \count_reg[16] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[16]_i_1_n_7 ), + .Q(count_reg[16])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[16]_i_1 + (.CI(\count_reg[12]_i_1_n_0 ), + .CO({\count_reg[16]_i_1_n_0 ,\count_reg[16]_i_1_n_1 ,\count_reg[16]_i_1_n_2 ,\count_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[16]_i_1_n_4 ,\count_reg[16]_i_1_n_5 ,\count_reg[16]_i_1_n_6 ,\count_reg[16]_i_1_n_7 }), + .S(count_reg[19:16])); + FDCE #( + .INIT(1'b0)) + \count_reg[17] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[16]_i_1_n_6 ), + .Q(count_reg[17])); + FDCE #( + .INIT(1'b0)) + \count_reg[18] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[16]_i_1_n_5 ), + .Q(count_reg[18])); + FDCE #( + .INIT(1'b0)) + \count_reg[19] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[16]_i_1_n_4 ), + .Q(count_reg[19])); + FDCE #( + .INIT(1'b0)) + \count_reg[1] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[0]_i_1_n_6 ), + .Q(count_reg[1])); + FDCE #( + .INIT(1'b0)) + \count_reg[20] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[20]_i_1_n_7 ), + .Q(count_reg[20])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[20]_i_1 + (.CI(\count_reg[16]_i_1_n_0 ), + .CO({\count_reg[20]_i_1_n_0 ,\count_reg[20]_i_1_n_1 ,\count_reg[20]_i_1_n_2 ,\count_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[20]_i_1_n_4 ,\count_reg[20]_i_1_n_5 ,\count_reg[20]_i_1_n_6 ,\count_reg[20]_i_1_n_7 }), + .S(count_reg[23:20])); + FDCE #( + .INIT(1'b0)) + \count_reg[21] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[20]_i_1_n_6 ), + .Q(count_reg[21])); + FDCE #( + .INIT(1'b0)) + \count_reg[22] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[20]_i_1_n_5 ), + .Q(count_reg[22])); + FDCE #( + .INIT(1'b0)) + \count_reg[23] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[20]_i_1_n_4 ), + .Q(count_reg[23])); + FDCE #( + .INIT(1'b0)) + \count_reg[24] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[24]_i_1_n_7 ), + .Q(count_reg[24])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[24]_i_1 + (.CI(\count_reg[20]_i_1_n_0 ), + .CO({\count_reg[24]_i_1_n_0 ,\count_reg[24]_i_1_n_1 ,\count_reg[24]_i_1_n_2 ,\count_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[24]_i_1_n_4 ,\count_reg[24]_i_1_n_5 ,\count_reg[24]_i_1_n_6 ,\count_reg[24]_i_1_n_7 }), + .S(count_reg[27:24])); + FDCE #( + .INIT(1'b0)) + \count_reg[25] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[24]_i_1_n_6 ), + .Q(count_reg[25])); + FDCE #( + .INIT(1'b0)) + \count_reg[26] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[24]_i_1_n_5 ), + .Q(count_reg[26])); + FDCE #( + .INIT(1'b0)) + \count_reg[27] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[24]_i_1_n_4 ), + .Q(count_reg[27])); + FDCE #( + .INIT(1'b0)) + \count_reg[28] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[28]_i_1_n_7 ), + .Q(count_reg[28])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[28]_i_1 + (.CI(\count_reg[24]_i_1_n_0 ), + .CO({\NLW_count_reg[28]_i_1_CO_UNCONNECTED [3],\count_reg[28]_i_1_n_1 ,\count_reg[28]_i_1_n_2 ,\count_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[28]_i_1_n_4 ,\count_reg[28]_i_1_n_5 ,\count_reg[28]_i_1_n_6 ,\count_reg[28]_i_1_n_7 }), + .S(count_reg[31:28])); + FDCE #( + .INIT(1'b0)) + \count_reg[29] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[28]_i_1_n_6 ), + .Q(count_reg[29])); + FDCE #( + .INIT(1'b0)) + \count_reg[2] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[0]_i_1_n_5 ), + .Q(count_reg[2])); + FDCE #( + .INIT(1'b0)) + \count_reg[30] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[28]_i_1_n_5 ), + .Q(count_reg[30])); + FDCE #( + .INIT(1'b0)) + \count_reg[31] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[28]_i_1_n_4 ), + .Q(count_reg[31])); + FDCE #( + .INIT(1'b0)) + \count_reg[3] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[0]_i_1_n_4 ), + .Q(count_reg[3])); + FDCE #( + .INIT(1'b0)) + \count_reg[4] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[4]_i_1_n_7 ), + .Q(count_reg[4])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[4]_i_1 + (.CI(\count_reg[0]_i_1_n_0 ), + .CO({\count_reg[4]_i_1_n_0 ,\count_reg[4]_i_1_n_1 ,\count_reg[4]_i_1_n_2 ,\count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[4]_i_1_n_4 ,\count_reg[4]_i_1_n_5 ,\count_reg[4]_i_1_n_6 ,\count_reg[4]_i_1_n_7 }), + .S(count_reg[7:4])); + FDCE #( + .INIT(1'b0)) + \count_reg[5] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[4]_i_1_n_6 ), + .Q(count_reg[5])); + FDCE #( + .INIT(1'b0)) + \count_reg[6] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[4]_i_1_n_5 ), + .Q(count_reg[6])); + FDCE #( + .INIT(1'b0)) + \count_reg[7] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[4]_i_1_n_4 ), + .Q(count_reg[7])); + FDCE #( + .INIT(1'b0)) + \count_reg[8] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[8]_i_1_n_7 ), + .Q(count_reg[8])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[8]_i_1 + (.CI(\count_reg[4]_i_1_n_0 ), + .CO({\count_reg[8]_i_1_n_0 ,\count_reg[8]_i_1_n_1 ,\count_reg[8]_i_1_n_2 ,\count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[8]_i_1_n_4 ,\count_reg[8]_i_1_n_5 ,\count_reg[8]_i_1_n_6 ,\count_reg[8]_i_1_n_7 }), + .S(count_reg[11:8])); + FDCE #( + .INIT(1'b0)) + \count_reg[9] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[8]_i_1_n_6 ), + .Q(count_reg[9])); + OBUF led_OBUF_inst + (.I(led_OBUF), + .O(led)); + (* XILINX_LEGACY_PRIM = "LDC" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:GE" *) + LDCE #( + .INIT(1'b0)) + led_reg + (.CLR(led_reg_i_2_n_0), + .D(led_reg_i_1_n_0), + .G(led_reg_i_1_n_0), + .GE(1'b1), + .Q(led_OBUF)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_1 + (.CI(led_reg_i_3_n_0), + .CO({led_reg_i_1_n_0,led_reg_i_1_n_1,led_reg_i_1_n_2,led_reg_i_1_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_4_n_0,led_reg_i_5_n_0,led_reg_i_6_n_0,led_reg_i_7_n_0}), + .O(NLW_led_reg_i_1_O_UNCONNECTED[3:0]), + .S({led_reg_i_8_n_0,led_reg_i_9_n_0,led_reg_i_10_n_0,led_reg_i_11_n_0})); + LUT2 #( + .INIT(4'h1)) + led_reg_i_10 + (.I0(count_reg[26]), + .I1(count_reg[27]), + .O(led_reg_i_10_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_11 + (.I0(count_reg[24]), + .I1(count_reg[25]), + .O(led_reg_i_11_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_12 + (.CI(led_reg_i_28_n_0), + .CO({led_reg_i_12_n_0,led_reg_i_12_n_1,led_reg_i_12_n_2,led_reg_i_12_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_29_n_0,led_reg_i_30_n_0,1'b0,1'b0}), + .O(NLW_led_reg_i_12_O_UNCONNECTED[3:0]), + .S({led_reg_i_31_n_0,led_reg_i_32_n_0,led_reg_i_33_n_0,led_reg_i_34_n_0})); + LUT2 #( + .INIT(4'h2)) + led_reg_i_13 + (.I0(count_reg[30]), + .I1(count_reg[31]), + .O(led_reg_i_13_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_14 + (.I0(count_reg[28]), + .I1(count_reg[29]), + .O(led_reg_i_14_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_15 + (.I0(count_reg[26]), + .I1(count_reg[27]), + .O(led_reg_i_15_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_16 + (.I0(count_reg[24]), + .I1(count_reg[25]), + .O(led_reg_i_16_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_17 + (.I0(count_reg[30]), + .I1(count_reg[31]), + .O(led_reg_i_17_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_18 + (.I0(count_reg[28]), + .I1(count_reg[29]), + .O(led_reg_i_18_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_19 + (.I0(count_reg[26]), + .I1(count_reg[27]), + .O(led_reg_i_19_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_2 + (.CI(led_reg_i_12_n_0), + .CO({led_reg_i_2_n_0,led_reg_i_2_n_1,led_reg_i_2_n_2,led_reg_i_2_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_13_n_0,led_reg_i_14_n_0,led_reg_i_15_n_0,led_reg_i_16_n_0}), + .O(NLW_led_reg_i_2_O_UNCONNECTED[3:0]), + .S({led_reg_i_17_n_0,led_reg_i_18_n_0,led_reg_i_19_n_0,led_reg_i_20_n_0})); + LUT2 #( + .INIT(4'h1)) + led_reg_i_20 + (.I0(count_reg[24]), + .I1(count_reg[25]), + .O(led_reg_i_20_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_21 + (.CI(led_reg_i_35_n_0), + .CO({led_reg_i_21_n_0,led_reg_i_21_n_1,led_reg_i_21_n_2,led_reg_i_21_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_36_n_0,led_reg_i_37_n_0,count_reg[11],led_reg_i_38_n_0}), + .O(NLW_led_reg_i_21_O_UNCONNECTED[3:0]), + .S({led_reg_i_39_n_0,led_reg_i_40_n_0,led_reg_i_41_n_0,led_reg_i_42_n_0})); + LUT2 #( + .INIT(4'hE)) + led_reg_i_22 + (.I0(count_reg[22]), + .I1(count_reg[23]), + .O(led_reg_i_22_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_23 + (.I0(count_reg[16]), + .I1(count_reg[17]), + .O(led_reg_i_23_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_24 + (.I0(count_reg[22]), + .I1(count_reg[23]), + .O(led_reg_i_24_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_25 + (.I0(count_reg[20]), + .I1(count_reg[21]), + .O(led_reg_i_25_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_26 + (.I0(count_reg[18]), + .I1(count_reg[19]), + .O(led_reg_i_26_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_27 + (.I0(count_reg[17]), + .I1(count_reg[16]), + .O(led_reg_i_27_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_28 + (.CI(led_reg_i_43_n_0), + .CO({led_reg_i_28_n_0,led_reg_i_28_n_1,led_reg_i_28_n_2,led_reg_i_28_n_3}), + .CYINIT(1'b0), + .DI({count_reg[15],led_reg_i_44_n_0,led_reg_i_45_n_0,led_reg_i_46_n_0}), + .O(NLW_led_reg_i_28_O_UNCONNECTED[3:0]), + .S({led_reg_i_47_n_0,led_reg_i_48_n_0,led_reg_i_49_n_0,led_reg_i_50_n_0})); + LUT2 #( + .INIT(4'hE)) + led_reg_i_29 + (.I0(count_reg[22]), + .I1(count_reg[23]), + .O(led_reg_i_29_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_3 + (.CI(led_reg_i_21_n_0), + .CO({led_reg_i_3_n_0,led_reg_i_3_n_1,led_reg_i_3_n_2,led_reg_i_3_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_22_n_0,count_reg[21],1'b0,led_reg_i_23_n_0}), + .O(NLW_led_reg_i_3_O_UNCONNECTED[3:0]), + .S({led_reg_i_24_n_0,led_reg_i_25_n_0,led_reg_i_26_n_0,led_reg_i_27_n_0})); + LUT2 #( + .INIT(4'hE)) + led_reg_i_30 + (.I0(count_reg[20]), + .I1(count_reg[21]), + .O(led_reg_i_30_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_31 + (.I0(count_reg[22]), + .I1(count_reg[23]), + .O(led_reg_i_31_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_32 + (.I0(count_reg[20]), + .I1(count_reg[21]), + .O(led_reg_i_32_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_33 + (.I0(count_reg[18]), + .I1(count_reg[19]), + .O(led_reg_i_33_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_34 + (.I0(count_reg[16]), + .I1(count_reg[17]), + .O(led_reg_i_34_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_35 + (.CI(1'b0), + .CO({led_reg_i_35_n_0,led_reg_i_35_n_1,led_reg_i_35_n_2,led_reg_i_35_n_3}), + .CYINIT(1'b1), + .DI({led_reg_i_51_n_0,led_reg_i_52_n_0,led_reg_i_53_n_0,led_reg_i_54_n_0}), + .O(NLW_led_reg_i_35_O_UNCONNECTED[3:0]), + .S({led_reg_i_55_n_0,led_reg_i_56_n_0,led_reg_i_57_n_0,led_reg_i_58_n_0})); + LUT2 #( + .INIT(4'h8)) + led_reg_i_36 + (.I0(count_reg[14]), + .I1(count_reg[15]), + .O(led_reg_i_36_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_37 + (.I0(count_reg[12]), + .I1(count_reg[13]), + .O(led_reg_i_37_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_38 + (.I0(count_reg[8]), + .I1(count_reg[9]), + .O(led_reg_i_38_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_39 + (.I0(count_reg[15]), + .I1(count_reg[14]), + .O(led_reg_i_39_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_4 + (.I0(count_reg[30]), + .I1(count_reg[31]), + .O(led_reg_i_4_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_40 + (.I0(count_reg[12]), + .I1(count_reg[13]), + .O(led_reg_i_40_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_41 + (.I0(count_reg[10]), + .I1(count_reg[11]), + .O(led_reg_i_41_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_42 + (.I0(count_reg[8]), + .I1(count_reg[9]), + .O(led_reg_i_42_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_43 + (.CI(1'b0), + .CO({led_reg_i_43_n_0,led_reg_i_43_n_1,led_reg_i_43_n_2,led_reg_i_43_n_3}), + .CYINIT(1'b1), + .DI({count_reg[7],led_reg_i_59_n_0,led_reg_i_60_n_0,led_reg_i_61_n_0}), + .O(NLW_led_reg_i_43_O_UNCONNECTED[3:0]), + .S({led_reg_i_62_n_0,led_reg_i_63_n_0,led_reg_i_64_n_0,led_reg_i_65_n_0})); + LUT2 #( + .INIT(4'hE)) + led_reg_i_44 + (.I0(count_reg[12]), + .I1(count_reg[13]), + .O(led_reg_i_44_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_45 + (.I0(count_reg[10]), + .I1(count_reg[11]), + .O(led_reg_i_45_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_46 + (.I0(count_reg[8]), + .I1(count_reg[9]), + .O(led_reg_i_46_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_47 + (.I0(count_reg[14]), + .I1(count_reg[15]), + .O(led_reg_i_47_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_48 + (.I0(count_reg[12]), + .I1(count_reg[13]), + .O(led_reg_i_48_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_49 + (.I0(count_reg[10]), + .I1(count_reg[11]), + .O(led_reg_i_49_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_5 + (.I0(count_reg[28]), + .I1(count_reg[29]), + .O(led_reg_i_5_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_50 + (.I0(count_reg[9]), + .I1(count_reg[8]), + .O(led_reg_i_50_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_51 + (.I0(count_reg[6]), + .I1(count_reg[7]), + .O(led_reg_i_51_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_52 + (.I0(count_reg[4]), + .I1(count_reg[5]), + .O(led_reg_i_52_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_53 + (.I0(count_reg[2]), + .I1(count_reg[3]), + .O(led_reg_i_53_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_54 + (.I0(count_reg[0]), + .I1(count_reg[1]), + .O(led_reg_i_54_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_55 + (.I0(count_reg[7]), + .I1(count_reg[6]), + .O(led_reg_i_55_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_56 + (.I0(count_reg[4]), + .I1(count_reg[5]), + .O(led_reg_i_56_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_57 + (.I0(count_reg[2]), + .I1(count_reg[3]), + .O(led_reg_i_57_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_58 + (.I0(count_reg[0]), + .I1(count_reg[1]), + .O(led_reg_i_58_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_59 + (.I0(count_reg[4]), + .I1(count_reg[5]), + .O(led_reg_i_59_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_6 + (.I0(count_reg[26]), + .I1(count_reg[27]), + .O(led_reg_i_6_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_60 + (.I0(count_reg[2]), + .I1(count_reg[3]), + .O(led_reg_i_60_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_61 + (.I0(count_reg[0]), + .I1(count_reg[1]), + .O(led_reg_i_61_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_62 + (.I0(count_reg[6]), + .I1(count_reg[7]), + .O(led_reg_i_62_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_63 + (.I0(count_reg[4]), + .I1(count_reg[5]), + .O(led_reg_i_63_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_64 + (.I0(count_reg[2]), + .I1(count_reg[3]), + .O(led_reg_i_64_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_65 + (.I0(count_reg[0]), + .I1(count_reg[1]), + .O(led_reg_i_65_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_7 + (.I0(count_reg[24]), + .I1(count_reg[25]), + .O(led_reg_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_8 + (.I0(count_reg[30]), + .I1(count_reg[31]), + .O(led_reg_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_9 + (.I0(count_reg[28]), + .I1(count_reg[29]), + .O(led_reg_i_9_n_0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.wdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.wdb new file mode 100644 index 0000000..d8f570c Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.wdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.bat new file mode 100644 index 0000000..ba5eaf4 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Wed Mar 16 20:17:55 +0100 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +REM simulate design +echo "xsim pwm_test_db_func_synth -key {Post-Synthesis:sim_1:Functional:pwm_test_db} -tclbatch pwm_test_db.tcl -log simulate.log" +call xsim pwm_test_db_func_synth -key {Post-Synthesis:sim_1:Functional:pwm_test_db} -tclbatch pwm_test_db.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.log new file mode 100644 index 0000000..3a14ee6 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/simulate.log @@ -0,0 +1 @@ +Time resolution is 1 ps diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xelab.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xelab.pb new file mode 100644 index 0000000..f7d526c Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xelab.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/Compile_Options.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/Compile_Options.txt new file mode 100644 index 0000000..7da51e8 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "pwm_test_db_func_synth" "xil_defaultlib.pwm_test_db" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/TempBreakPointFile.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_0.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_0.win64.obj new file mode 100644 index 0000000..1c0621d Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_0.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.c b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.c new file mode 100644 index 0000000..587a597 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.c @@ -0,0 +1,376 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_2(char*, char *); +IKI_DLLESPEC extern void execute_3(char*, char *); +IKI_DLLESPEC extern void execute_4(char*, char *); +IKI_DLLESPEC extern void execute_5(char*, char *); +IKI_DLLESPEC extern void execute_6(char*, char *); +IKI_DLLESPEC extern void execute_7(char*, char *); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_347(char*, char *); +IKI_DLLESPEC extern void execute_348(char*, char *); +IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_933(char*, char *); +IKI_DLLESPEC extern void execute_938(char*, char *); +IKI_DLLESPEC extern void execute_944(char*, char *); +IKI_DLLESPEC extern void execute_951(char*, char *); +IKI_DLLESPEC extern void execute_957(char*, char *); +IKI_DLLESPEC extern void execute_963(char*, char *); +IKI_DLLESPEC extern void execute_971(char*, char *); +IKI_DLLESPEC extern void execute_977(char*, char *); +IKI_DLLESPEC extern void execute_982(char*, char *); +IKI_DLLESPEC extern void execute_987(char*, char *); +IKI_DLLESPEC extern void execute_351(char*, char *); +IKI_DLLESPEC extern void execute_21(char*, char *); +IKI_DLLESPEC extern void execute_352(char*, char *); +IKI_DLLESPEC extern void execute_24(char*, char *); +IKI_DLLESPEC extern void execute_354(char*, char *); +IKI_DLLESPEC extern void execute_355(char*, char *); +IKI_DLLESPEC extern void execute_353(char*, char *); +IKI_DLLESPEC extern void execute_26(char*, char *); +IKI_DLLESPEC extern void execute_27(char*, char *); +IKI_DLLESPEC extern void execute_28(char*, char *); +IKI_DLLESPEC extern void execute_356(char*, char *); +IKI_DLLESPEC extern void execute_357(char*, char *); +IKI_DLLESPEC extern void execute_358(char*, char *); +IKI_DLLESPEC extern void execute_359(char*, char *); +IKI_DLLESPEC extern void execute_360(char*, char *); +IKI_DLLESPEC extern void execute_361(char*, char *); +IKI_DLLESPEC extern void execute_362(char*, char *); +IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_365(char*, char *); +IKI_DLLESPEC extern void execute_366(char*, char *); +IKI_DLLESPEC extern void execute_367(char*, char *); +IKI_DLLESPEC extern void execute_368(char*, char *); +IKI_DLLESPEC extern void execute_162(char*, char *); +IKI_DLLESPEC extern void execute_556(char*, char *); +IKI_DLLESPEC extern void execute_557(char*, char *); +IKI_DLLESPEC extern void execute_558(char*, char *); +IKI_DLLESPEC extern void execute_164(char*, char *); +IKI_DLLESPEC extern void execute_166(char*, char *); +IKI_DLLESPEC extern void execute_167(char*, char *); +IKI_DLLESPEC extern void execute_559(char*, char *); +IKI_DLLESPEC extern void execute_560(char*, char *); +IKI_DLLESPEC extern void execute_561(char*, char *); +IKI_DLLESPEC extern void execute_562(char*, char *); +IKI_DLLESPEC extern void execute_564(char*, char *); +IKI_DLLESPEC extern void execute_565(char*, char *); +IKI_DLLESPEC extern void execute_566(char*, char *); +IKI_DLLESPEC extern void execute_569(char*, char *); +IKI_DLLESPEC extern void execute_570(char*, char *); +IKI_DLLESPEC extern void execute_571(char*, char *); +IKI_DLLESPEC extern void execute_572(char*, char *); +IKI_DLLESPEC extern void execute_568(char*, char *); +IKI_DLLESPEC extern void execute_171(char*, char *); +IKI_DLLESPEC extern void execute_583(char*, char *); +IKI_DLLESPEC extern void execute_584(char*, char *); +IKI_DLLESPEC extern void execute_585(char*, char *); +IKI_DLLESPEC extern void execute_586(char*, char *); +IKI_DLLESPEC extern void execute_582(char*, char *); +IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_47(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_48(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_49(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_50(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_53(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_55(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_56(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_70(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_71(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_73(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_74(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_75(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_76(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_84(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_85(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_86(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_87(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_88(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_89(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_90(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_91(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_92(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_93(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_94(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_95(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_96(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_97(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_98(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_99(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_100(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_101(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_102(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_103(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_104(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_105(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_106(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_107(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_108(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_109(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_110(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_111(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_112(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_113(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_114(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_115(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_116(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_123(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_124(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_125(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_126(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_127(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_130(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_131(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_132(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_133(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_134(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_135(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_136(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_137(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_139(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_140(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_141(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_142(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_144(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_145(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_146(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_147(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_148(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_149(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_150(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_151(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_152(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_153(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_154(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_155(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_156(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_157(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_158(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_159(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_160(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_161(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_162(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_163(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_164(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_166(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_167(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_168(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_169(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_173(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_174(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_175(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_176(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_177(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_178(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_179(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_180(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_181(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_182(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_183(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_184(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_185(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_186(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_187(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_188(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_189(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_190(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_191(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_216(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_334(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_348(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_354(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_366(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_372(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_386(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_392(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_398(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_418(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_424(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_430(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_436(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_450(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_456(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_462(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_468(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_474(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_480(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_494(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_500(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_506(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_512(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_526(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[260] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_347, (funcp)execute_348, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_933, (funcp)execute_938, (funcp)execute_944, (funcp)execute_951, (funcp)execute_957, (funcp)execute_963, (funcp)execute_971, (funcp)execute_977, (funcp)execute_982, (funcp)execute_987, (funcp)execute_351, (funcp)execute_21, (funcp)execute_352, (funcp)execute_24, (funcp)execute_354, (funcp)execute_355, (funcp)execute_353, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_356, (funcp)execute_357, (funcp)execute_358, (funcp)execute_359, (funcp)execute_360, (funcp)execute_361, (funcp)execute_362, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_365, (funcp)execute_366, (funcp)execute_367, (funcp)execute_368, (funcp)execute_162, (funcp)execute_556, (funcp)execute_557, (funcp)execute_558, (funcp)execute_164, (funcp)execute_166, (funcp)execute_167, (funcp)execute_559, (funcp)execute_560, (funcp)execute_561, (funcp)execute_562, (funcp)execute_564, (funcp)execute_565, (funcp)execute_566, (funcp)execute_569, (funcp)execute_570, (funcp)execute_571, (funcp)execute_572, (funcp)execute_568, (funcp)execute_171, (funcp)execute_583, (funcp)execute_584, (funcp)execute_585, (funcp)execute_586, (funcp)execute_582, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)transaction_46, (funcp)transaction_47, (funcp)transaction_48, (funcp)transaction_49, (funcp)transaction_50, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_53, (funcp)transaction_54, (funcp)transaction_55, (funcp)transaction_56, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_70, (funcp)transaction_71, (funcp)transaction_72, (funcp)transaction_73, (funcp)transaction_74, (funcp)transaction_75, (funcp)transaction_76, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_84, (funcp)transaction_85, (funcp)transaction_86, (funcp)transaction_87, (funcp)transaction_88, (funcp)transaction_89, (funcp)transaction_90, (funcp)transaction_91, (funcp)transaction_92, (funcp)transaction_93, (funcp)transaction_94, (funcp)transaction_95, (funcp)transaction_96, (funcp)transaction_97, (funcp)transaction_98, (funcp)transaction_99, (funcp)transaction_100, (funcp)transaction_101, (funcp)transaction_102, (funcp)transaction_103, (funcp)transaction_104, (funcp)transaction_105, (funcp)transaction_106, (funcp)transaction_107, (funcp)transaction_108, (funcp)transaction_109, (funcp)transaction_110, (funcp)transaction_111, (funcp)transaction_112, (funcp)transaction_113, (funcp)transaction_114, (funcp)transaction_115, (funcp)transaction_116, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_123, (funcp)transaction_124, (funcp)transaction_125, (funcp)transaction_126, (funcp)transaction_127, (funcp)transaction_130, (funcp)transaction_131, (funcp)transaction_132, (funcp)transaction_133, (funcp)transaction_134, (funcp)transaction_135, (funcp)transaction_136, (funcp)transaction_137, (funcp)transaction_139, (funcp)transaction_140, (funcp)transaction_141, (funcp)transaction_142, (funcp)transaction_144, (funcp)transaction_145, (funcp)transaction_146, (funcp)transaction_147, (funcp)transaction_148, (funcp)transaction_149, (funcp)transaction_150, (funcp)transaction_151, (funcp)transaction_152, (funcp)transaction_153, (funcp)transaction_154, (funcp)transaction_155, (funcp)transaction_156, (funcp)transaction_157, (funcp)transaction_158, (funcp)transaction_159, (funcp)transaction_160, (funcp)transaction_161, (funcp)transaction_162, (funcp)transaction_163, (funcp)transaction_164, (funcp)transaction_165, (funcp)transaction_166, (funcp)transaction_167, (funcp)transaction_168, (funcp)transaction_169, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_173, (funcp)transaction_174, (funcp)transaction_175, (funcp)transaction_176, (funcp)transaction_177, (funcp)transaction_178, (funcp)transaction_179, (funcp)transaction_180, (funcp)transaction_181, (funcp)transaction_182, (funcp)transaction_183, (funcp)transaction_184, (funcp)transaction_185, (funcp)transaction_186, (funcp)transaction_187, (funcp)transaction_188, (funcp)transaction_189, (funcp)transaction_190, (funcp)transaction_191, (funcp)transaction_192, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_216, (funcp)transaction_275, (funcp)transaction_290, (funcp)transaction_296, (funcp)transaction_302, (funcp)transaction_316, (funcp)transaction_322, (funcp)transaction_328, (funcp)transaction_334, (funcp)transaction_348, (funcp)transaction_354, (funcp)transaction_360, (funcp)transaction_366, (funcp)transaction_372, (funcp)transaction_386, (funcp)transaction_392, (funcp)transaction_398, (funcp)transaction_404, (funcp)transaction_418, (funcp)transaction_424, (funcp)transaction_430, (funcp)transaction_436, (funcp)transaction_450, (funcp)transaction_456, (funcp)transaction_462, (funcp)transaction_468, (funcp)transaction_474, (funcp)transaction_480, (funcp)transaction_494, (funcp)transaction_500, (funcp)transaction_506, (funcp)transaction_512, (funcp)transaction_526}; +const int NumRelocateId= 260; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/pwm_test_db_func_synth/xsim.reloc", (void **)funcTab, 260); + iki_vhdl_file_variable_register(dp + 201296); + iki_vhdl_file_variable_register(dp + 201352); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/pwm_test_db_func_synth/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 206376, dp + 206832, 0, 0, 0, 0, 1, 1); + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/pwm_test_db_func_synth/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/pwm_test_db_func_synth/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/pwm_test_db_func_synth/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/pwm_test_db_func_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.win64.obj new file mode 100644 index 0000000..7c5181d Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/obj/xsim_1.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.dbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.dbg new file mode 100644 index 0000000..e242c94 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.dbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.mem b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.mem new file mode 100644 index 0000000..a72c31e Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.mem differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.reloc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.reloc new file mode 100644 index 0000000..b7ff7ca Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.reloc differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rlx new file mode 100644 index 0000000..09683a8 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 9113727300305093394 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl" , + buildDate : "Oct 19 2021" , + buildTime : "03:16:22" , + linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_func_synth/xsimk.exe\" \"xsim.dir/pwm_test_db_func_synth/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_func_synth/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rtti b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rtti new file mode 100644 index 0000000..265f971 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.rtti differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.svtype b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.svtype new file mode 100644 index 0000000..99e2679 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.svtype differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.type b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.type new file mode 100644 index 0000000..2eb74e4 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.type differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.xdbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.xdbg new file mode 100644 index 0000000..91656bd Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsim.xdbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimSettings.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimSettings.ini new file mode 100644 index 0000000..bfb3c44 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=512 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=2147483647 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=210 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimcrash.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimk.exe b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimk.exe new file mode 100644 index 0000000..bbe8b79 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimk.exe differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimkernel.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimkernel.log new file mode 100644 index 0000000..e166472 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/pwm_test_db_func_synth/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/pwm_test_db_func_synth/xsimk.exe -simmode gui -wdb pwm_test_db_func_synth.wdb -simrunnum 0 -socket 49911 +Design successfully loaded +Design Loading Memory Usage: 8300 KB (Peak: 8300 KB) +Design Loading CPU Usage: 0 ms +Simulation completed +Simulation Memory Usage: 9176 KB (Peak: 9176 KB) +Simulation CPU Usage: 15 ms diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb new file mode 100644 index 0000000..663ff15 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb new file mode 100644 index 0000000..10ea637 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb new file mode 100644 index 0000000..3ac8021 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..2731f62 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,6 @@ +0.7 +2020.2 +Oct 19 2021 +03:16:22 +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v,1647458765,verilog,,,,glbl;pwm_test,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1647459068,vhdl,,,,pwm_test_db,,,,,,,, diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.log new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvhdl.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.log new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/func/xsim/xvlog.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/.usf.tcl_error.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/.usf.tcl_error.log new file mode 100644 index 0000000..30e81d1 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/.usf.tcl_error.log @@ -0,0 +1,15 @@ +******************************************************************************** +* Unified simulation Tcl App stack trace dump +* +* File: .usf.tcl_error.log (Wed Mar 16 21:02:12 2022) +* +* This file is generated by the unified simulation automation and contains the +* tcl stack trace of error returned by the simulator App for the current run. +* +******************************************************************************** +1 + while executing +"catch {eval "xsim $cmd_args"} err_msg" + (procedure "tclapp::xilinx::xsim::simulate" line 178) + invoked from within +"tclapp::xilinx::xsim::simulate { -simset sim_1 -mode post-synthesis -type timing -run_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/..." diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.bat new file mode 100644 index 0000000..9642207 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.bat @@ -0,0 +1,30 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Wed Mar 16 20:54:19 +0100 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: compile.bat +REM +REM **************************************************************************** +REM compile Verilog/System Verilog design sources +echo "xvlog --incr --relax -prj pwm_test_db_vlog.prj" +call xvlog --incr --relax -prj pwm_test_db_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +REM compile VHDL design sources +echo "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +call xvhdl --incr --relax -prj pwm_test_db_vhdl.prj -log xvhdl.log +call type xvhdl.log >> compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.log new file mode 100644 index 0000000..d427ec6 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/compile.log @@ -0,0 +1,5 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module pwm_test +INFO: [VRFC 10-311] analyzing module glbl +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.bat new file mode 100644 index 0000000..f6ec502 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Wed Mar 16 20:54:23 +0100 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +REM elaborate design +echo "xelab --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log" +call xelab --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.log new file mode 100644 index 0000000..d3c6e77 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/elaborate.log @@ -0,0 +1,31 @@ +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Pass Through NonSizing Optimizer +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut". +INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut". +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package vl.vl_types +Compiling module xil_defaultlib.glbl +Compiling module simprims_ver.BUFG +Compiling module simprims_ver.IBUF +Compiling module simprims_ver.x_lut1_mux2 +Compiling module simprims_ver.LUT1(INIT=2'b01) +Compiling module simprims_ver.FDCE_default +Compiling module simprims_ver.CARRY4 +Compiling module simprims_ver.OBUF +Compiling module simprims_ver.latchsre_ldce +Compiling module simprims_ver.LDCE +Compiling module simprims_ver.x_lut2_mux4 +Compiling module simprims_ver.LUT2 +Compiling module xil_defaultlib.pwm_test +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_time_synth diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db.tcl b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db.tcl new file mode 100644 index 0000000..35691cf --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 5000 ms diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf new file mode 100644 index 0000000..d4abca3 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf @@ -0,0 +1,2344 @@ +(DELAYFILE +(SDFVERSION "3.0" ) +(DESIGN "pwm_test") +(DATE "Wed Mar 16 20:54:19 2022") +(VENDOR "XILINX") +(PROGRAM "Vivado") +(VERSION "2021.2") +(DIVIDER /) +(TIMESCALE 1ps) +(CELL + (CELLTYPE "BUFG") + (INSTANCE clk_IBUF_BUFG_inst) + (DELAY + (PATHPULSE (50.0)) + (ABSOLUTE + (IOPATH I O (91.0:101.0:101.0) (91.0:101.0:101.0)) + ) + ) +) +(CELL + (CELLTYPE "IBUF") + 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(439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[11\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[12\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[13\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[14\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[15\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[16\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[17\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[18\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[19\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[1\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[20\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[21\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[22\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[23\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[24\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[25\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[26\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[27\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[28\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[29\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[2\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[30\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[31\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[3\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[4\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[5\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[6\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[7\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[8\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_BUFG_inst/O count_reg\[9\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT clk_IBUF_inst/O clk_IBUF_BUFG_inst/I (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT count\[0\]_i_2/O count_reg\[0\]_i_1/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT count_reg\[0\]/Q count\[0\]_i_2/I0 (282.1:297.0:297.0) (282.1:297.0:297.0)) + (INTERCONNECT count_reg\[0\]/Q led_reg_i_54/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[0\]/Q led_reg_i_58/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[0\]/Q led_reg_i_61/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[0\]/Q led_reg_i_65/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[0\]_i_1/CO[3] count_reg\[4\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT count_reg\[0\]_i_1/O[3] count_reg\[3\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[0\]_i_1/O[2] count_reg\[2\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[0\]_i_1/O[1] count_reg\[1\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[0\]_i_1/O[0] count_reg\[0\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[10\]/Q led_reg_i_41/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[10\]/Q led_reg_i_45/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[10\]/Q led_reg_i_49/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[10\]/Q count_reg\[8\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0)) + (INTERCONNECT count_reg\[11\]/Q led_reg_i_21/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT count_reg\[11\]/Q led_reg_i_41/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[11\]/Q led_reg_i_45/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[11\]/Q led_reg_i_49/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[11\]/Q count_reg\[8\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0)) + (INTERCONNECT count_reg\[12\]/Q led_reg_i_37/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[12\]/Q led_reg_i_40/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[12\]/Q led_reg_i_44/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[12\]/Q led_reg_i_48/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[12\]/Q count_reg\[12\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0)) + (INTERCONNECT count_reg\[12\]_i_1/CO[3] count_reg\[16\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT count_reg\[12\]_i_1/O[3] count_reg\[15\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[12\]_i_1/O[2] count_reg\[14\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[12\]_i_1/O[1] count_reg\[13\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[12\]_i_1/O[0] count_reg\[12\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[13\]/Q led_reg_i_37/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[13\]/Q led_reg_i_40/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[13\]/Q led_reg_i_44/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[13\]/Q led_reg_i_48/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[13\]/Q count_reg\[12\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0)) + (INTERCONNECT count_reg\[14\]/Q led_reg_i_36/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[14\]/Q led_reg_i_47/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[14\]/Q led_reg_i_39/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[14\]/Q count_reg\[12\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0)) + (INTERCONNECT count_reg\[15\]/Q led_reg_i_28/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0)) + (INTERCONNECT count_reg\[15\]/Q led_reg_i_39/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[15\]/Q led_reg_i_36/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[15\]/Q led_reg_i_47/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[15\]/Q count_reg\[12\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0)) + (INTERCONNECT count_reg\[16\]/Q led_reg_i_23/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[16\]/Q led_reg_i_34/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[16\]/Q led_reg_i_27/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[16\]/Q count_reg\[16\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0)) + (INTERCONNECT count_reg\[16\]_i_1/CO[3] count_reg\[20\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT count_reg\[16\]_i_1/O[3] count_reg\[19\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[16\]_i_1/O[2] count_reg\[18\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[16\]_i_1/O[1] count_reg\[17\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[16\]_i_1/O[0] count_reg\[16\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[17\]/Q led_reg_i_27/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[17\]/Q led_reg_i_23/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[17\]/Q led_reg_i_34/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[17\]/Q count_reg\[16\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0)) + (INTERCONNECT count_reg\[18\]/Q led_reg_i_26/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[18\]/Q led_reg_i_33/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[18\]/Q count_reg\[16\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0)) + (INTERCONNECT count_reg\[19\]/Q led_reg_i_26/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[19\]/Q led_reg_i_33/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[19\]/Q count_reg\[16\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0)) + (INTERCONNECT count_reg\[1\]/Q led_reg_i_54/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[1\]/Q led_reg_i_58/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[1\]/Q led_reg_i_61/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[1\]/Q led_reg_i_65/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[1\]/Q count_reg\[0\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0)) + (INTERCONNECT count_reg\[20\]/Q led_reg_i_25/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[20\]/Q led_reg_i_30/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[20\]/Q led_reg_i_32/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[20\]/Q count_reg\[20\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0)) + (INTERCONNECT count_reg\[20\]_i_1/CO[3] count_reg\[24\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT count_reg\[20\]_i_1/O[3] count_reg\[23\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[20\]_i_1/O[2] count_reg\[22\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[20\]_i_1/O[1] count_reg\[21\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[20\]_i_1/O[0] count_reg\[20\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[21\]/Q led_reg_i_3/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0)) + (INTERCONNECT count_reg\[21\]/Q led_reg_i_25/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[21\]/Q led_reg_i_30/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[21\]/Q led_reg_i_32/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[21\]/Q count_reg\[20\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0)) + (INTERCONNECT count_reg\[22\]/Q led_reg_i_22/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[22\]/Q led_reg_i_24/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[22\]/Q led_reg_i_29/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[22\]/Q led_reg_i_31/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[22\]/Q count_reg\[20\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0)) + (INTERCONNECT count_reg\[23\]/Q led_reg_i_22/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[23\]/Q led_reg_i_24/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[23\]/Q led_reg_i_29/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[23\]/Q led_reg_i_31/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[23\]/Q count_reg\[20\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0)) + (INTERCONNECT count_reg\[24\]/Q led_reg_i_11/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[24\]/Q led_reg_i_16/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[24\]/Q led_reg_i_20/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[24\]/Q led_reg_i_7/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[24\]/Q count_reg\[24\]_i_1/S[0] (590.2:644.0:644.0) (590.2:644.0:644.0)) + (INTERCONNECT count_reg\[24\]_i_1/CO[3] count_reg\[28\]_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT count_reg\[24\]_i_1/O[3] count_reg\[27\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[24\]_i_1/O[2] count_reg\[26\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[24\]_i_1/O[1] count_reg\[25\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[24\]_i_1/O[0] count_reg\[24\]/D (62.0:76.0:76.0) (62.0:76.0:76.0)) + (INTERCONNECT count_reg\[25\]/Q led_reg_i_11/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[25\]/Q led_reg_i_16/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[25\]/Q led_reg_i_20/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[25\]/Q led_reg_i_7/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[25\]/Q count_reg\[24\]_i_1/S[1] (915.0:985.0:985.0) (915.0:985.0:985.0)) + (INTERCONNECT count_reg\[26\]/Q led_reg_i_10/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[26\]/Q led_reg_i_15/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[26\]/Q led_reg_i_19/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[26\]/Q led_reg_i_6/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT count_reg\[26\]/Q count_reg\[24\]_i_1/S[2] (907.5:977.0:977.0) (907.5:977.0:977.0)) + (INTERCONNECT count_reg\[27\]/Q led_reg_i_10/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[27\]/Q led_reg_i_15/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[27\]/Q led_reg_i_19/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[27\]/Q led_reg_i_6/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT count_reg\[27\]/Q count_reg\[24\]_i_1/S[3] (590.1:643.0:643.0) (590.1:643.0:643.0)) + (INTERCONNECT count_reg\[28\]/Q led_reg_i_14/I0 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(981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[2\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[30\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[31\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[3\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[4\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[5\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[6\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[7\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[8\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] count_reg\[9\]/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_2/CO[3] led_reg/CLR (981.5:1048.0:1048.0) (981.5:1048.0:1048.0)) + (INTERCONNECT led_reg_i_20/O led_reg_i_2/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT led_reg_i_21/CO[3] led_reg_i_3/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT led_reg_i_22/O led_reg_i_3/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0)) + (INTERCONNECT led_reg_i_23/O led_reg_i_3/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_24/O led_reg_i_3/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0)) + (INTERCONNECT led_reg_i_25/O led_reg_i_3/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_26/O led_reg_i_3/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_27/O led_reg_i_3/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT led_reg_i_28/CO[3] led_reg_i_12/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT led_reg_i_29/O led_reg_i_12/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0)) + (INTERCONNECT led_reg_i_3/CO[3] led_reg_i_1/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT led_reg_i_30/O led_reg_i_12/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0)) + (INTERCONNECT led_reg_i_31/O led_reg_i_12/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0)) + (INTERCONNECT led_reg_i_32/O led_reg_i_12/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_33/O led_reg_i_12/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_34/O led_reg_i_12/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT led_reg_i_35/CO[3] led_reg_i_21/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT led_reg_i_36/O led_reg_i_21/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0)) + (INTERCONNECT led_reg_i_37/O led_reg_i_21/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0)) + (INTERCONNECT led_reg_i_38/O led_reg_i_21/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_39/O led_reg_i_21/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0)) + (INTERCONNECT led_reg_i_4/O led_reg_i_1/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0)) + (INTERCONNECT led_reg_i_40/O led_reg_i_21/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_41/O led_reg_i_21/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_42/O led_reg_i_21/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT led_reg_i_43/CO[3] led_reg_i_28/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT led_reg_i_44/O led_reg_i_28/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0)) + (INTERCONNECT led_reg_i_45/O led_reg_i_28/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_46/O led_reg_i_28/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_47/O led_reg_i_28/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0)) + (INTERCONNECT led_reg_i_48/O led_reg_i_28/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_49/O led_reg_i_28/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_5/O led_reg_i_1/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0)) + (INTERCONNECT led_reg_i_50/O led_reg_i_28/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT led_reg_i_51/O led_reg_i_35/DI[3] (21.0:26.0:26.0) (21.0:26.0:26.0)) + (INTERCONNECT led_reg_i_52/O led_reg_i_35/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0)) + (INTERCONNECT led_reg_i_53/O led_reg_i_35/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_54/O led_reg_i_35/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_55/O led_reg_i_35/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0)) + (INTERCONNECT led_reg_i_56/O led_reg_i_35/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_57/O led_reg_i_35/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_58/O led_reg_i_35/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT led_reg_i_59/O led_reg_i_43/DI[2] (24.0:29.0:29.0) (24.0:29.0:29.0)) + (INTERCONNECT led_reg_i_6/O led_reg_i_1/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_60/O led_reg_i_43/DI[1] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_61/O led_reg_i_43/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_62/O led_reg_i_43/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0)) + (INTERCONNECT led_reg_i_63/O led_reg_i_43/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_64/O led_reg_i_43/S[1] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT led_reg_i_65/O led_reg_i_43/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT led_reg_i_7/O led_reg_i_1/DI[0] (22.0:27.0:27.0) (22.0:27.0:27.0)) + (INTERCONNECT led_reg_i_8/O led_reg_i_1/S[3] (17.0:21.0:21.0) (17.0:21.0:21.0)) + (INTERCONNECT led_reg_i_9/O led_reg_i_1/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + ) + ) +) +) diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v new file mode 100644 index 0000000..0d4fd63 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v @@ -0,0 +1,1028 @@ +// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 +// Date : Wed Mar 16 20:54:19 2022 +// Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) +// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file +// C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v +// Design : pwm_test +// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or +// synthesized. Please ensure that this netlist is used with the corresponding SDF file. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps +`define XIL_TIMING + +(* NotValidForBitStream *) +module pwm_test + (clk, + led); + input clk; + output led; + + wire clk; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire \count[0]_i_2_n_0 ; + wire [31:0]count_reg; + wire \count_reg[0]_i_1_n_0 ; + wire \count_reg[0]_i_1_n_1 ; + wire \count_reg[0]_i_1_n_2 ; + wire \count_reg[0]_i_1_n_3 ; + wire \count_reg[0]_i_1_n_4 ; + wire \count_reg[0]_i_1_n_5 ; + wire \count_reg[0]_i_1_n_6 ; + wire \count_reg[0]_i_1_n_7 ; + wire \count_reg[12]_i_1_n_0 ; + wire \count_reg[12]_i_1_n_1 ; + wire \count_reg[12]_i_1_n_2 ; + wire \count_reg[12]_i_1_n_3 ; + wire \count_reg[12]_i_1_n_4 ; + wire \count_reg[12]_i_1_n_5 ; + wire \count_reg[12]_i_1_n_6 ; + wire \count_reg[12]_i_1_n_7 ; + wire \count_reg[16]_i_1_n_0 ; + wire \count_reg[16]_i_1_n_1 ; + wire \count_reg[16]_i_1_n_2 ; + wire \count_reg[16]_i_1_n_3 ; + wire \count_reg[16]_i_1_n_4 ; + wire \count_reg[16]_i_1_n_5 ; + wire \count_reg[16]_i_1_n_6 ; + wire \count_reg[16]_i_1_n_7 ; + wire \count_reg[20]_i_1_n_0 ; + wire \count_reg[20]_i_1_n_1 ; + wire \count_reg[20]_i_1_n_2 ; + wire \count_reg[20]_i_1_n_3 ; + wire \count_reg[20]_i_1_n_4 ; + wire \count_reg[20]_i_1_n_5 ; + wire \count_reg[20]_i_1_n_6 ; + wire \count_reg[20]_i_1_n_7 ; + wire \count_reg[24]_i_1_n_0 ; + wire \count_reg[24]_i_1_n_1 ; + wire \count_reg[24]_i_1_n_2 ; + wire \count_reg[24]_i_1_n_3 ; + wire \count_reg[24]_i_1_n_4 ; + wire \count_reg[24]_i_1_n_5 ; + wire \count_reg[24]_i_1_n_6 ; + wire \count_reg[24]_i_1_n_7 ; + wire \count_reg[28]_i_1_n_1 ; + wire \count_reg[28]_i_1_n_2 ; + wire \count_reg[28]_i_1_n_3 ; + wire \count_reg[28]_i_1_n_4 ; + wire \count_reg[28]_i_1_n_5 ; + wire \count_reg[28]_i_1_n_6 ; + wire \count_reg[28]_i_1_n_7 ; + wire \count_reg[4]_i_1_n_0 ; + wire \count_reg[4]_i_1_n_1 ; + wire \count_reg[4]_i_1_n_2 ; + wire \count_reg[4]_i_1_n_3 ; + wire \count_reg[4]_i_1_n_4 ; + wire \count_reg[4]_i_1_n_5 ; + wire \count_reg[4]_i_1_n_6 ; + wire \count_reg[4]_i_1_n_7 ; + wire \count_reg[8]_i_1_n_0 ; + wire \count_reg[8]_i_1_n_1 ; + wire \count_reg[8]_i_1_n_2 ; + wire \count_reg[8]_i_1_n_3 ; + wire \count_reg[8]_i_1_n_4 ; + wire \count_reg[8]_i_1_n_5 ; + wire \count_reg[8]_i_1_n_6 ; + wire \count_reg[8]_i_1_n_7 ; + wire led; + wire led_OBUF; + wire led_reg_i_10_n_0; + wire led_reg_i_11_n_0; + wire led_reg_i_12_n_0; + wire led_reg_i_12_n_1; + wire led_reg_i_12_n_2; + wire led_reg_i_12_n_3; + wire led_reg_i_13_n_0; + wire led_reg_i_14_n_0; + wire led_reg_i_15_n_0; + wire led_reg_i_16_n_0; + wire led_reg_i_17_n_0; + wire led_reg_i_18_n_0; + wire led_reg_i_19_n_0; + wire led_reg_i_1_n_0; + wire led_reg_i_1_n_1; + wire led_reg_i_1_n_2; + wire led_reg_i_1_n_3; + wire led_reg_i_20_n_0; + wire led_reg_i_21_n_0; + wire led_reg_i_21_n_1; + wire led_reg_i_21_n_2; + wire led_reg_i_21_n_3; + wire led_reg_i_22_n_0; + wire led_reg_i_23_n_0; + wire led_reg_i_24_n_0; + wire led_reg_i_25_n_0; + wire led_reg_i_26_n_0; + wire led_reg_i_27_n_0; + wire led_reg_i_28_n_0; + wire led_reg_i_28_n_1; + wire led_reg_i_28_n_2; + wire led_reg_i_28_n_3; + wire led_reg_i_29_n_0; + wire led_reg_i_2_n_0; + wire led_reg_i_2_n_1; + wire led_reg_i_2_n_2; + wire led_reg_i_2_n_3; + wire led_reg_i_30_n_0; + wire led_reg_i_31_n_0; + wire led_reg_i_32_n_0; + wire led_reg_i_33_n_0; + wire led_reg_i_34_n_0; + wire led_reg_i_35_n_0; + wire led_reg_i_35_n_1; + wire led_reg_i_35_n_2; + wire led_reg_i_35_n_3; + wire led_reg_i_36_n_0; + wire led_reg_i_37_n_0; + wire led_reg_i_38_n_0; + wire led_reg_i_39_n_0; + wire led_reg_i_3_n_0; + wire led_reg_i_3_n_1; + wire led_reg_i_3_n_2; + wire led_reg_i_3_n_3; + wire led_reg_i_40_n_0; + wire led_reg_i_41_n_0; + wire led_reg_i_42_n_0; + wire led_reg_i_43_n_0; + wire led_reg_i_43_n_1; + wire led_reg_i_43_n_2; + wire led_reg_i_43_n_3; + wire led_reg_i_44_n_0; + wire led_reg_i_45_n_0; + wire led_reg_i_46_n_0; + wire led_reg_i_47_n_0; + wire led_reg_i_48_n_0; + wire led_reg_i_49_n_0; + wire led_reg_i_4_n_0; + wire led_reg_i_50_n_0; + wire led_reg_i_51_n_0; + wire led_reg_i_52_n_0; + wire led_reg_i_53_n_0; + wire led_reg_i_54_n_0; + wire led_reg_i_55_n_0; + wire led_reg_i_56_n_0; + wire led_reg_i_57_n_0; + wire led_reg_i_58_n_0; + wire led_reg_i_59_n_0; + wire led_reg_i_5_n_0; + wire led_reg_i_60_n_0; + wire led_reg_i_61_n_0; + wire led_reg_i_62_n_0; + wire led_reg_i_63_n_0; + wire led_reg_i_64_n_0; + wire led_reg_i_65_n_0; + wire led_reg_i_6_n_0; + wire led_reg_i_7_n_0; + wire led_reg_i_8_n_0; + wire led_reg_i_9_n_0; + wire [3:3]\NLW_count_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_led_reg_i_1_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_12_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_2_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_21_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_28_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_3_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_35_O_UNCONNECTED; + wire [3:0]NLW_led_reg_i_43_O_UNCONNECTED; + +initial begin + $sdf_annotate("pwm_test_db_time_synth.sdf",,,,"tool_control"); +end + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + LUT1 #( + .INIT(2'h1)) + \count[0]_i_2 + (.I0(count_reg[0]), + .O(\count[0]_i_2_n_0 )); + FDCE #( + .INIT(1'b0)) + \count_reg[0] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[0]_i_1_n_7 ), + .Q(count_reg[0])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[0]_i_1 + (.CI(1'b0), + .CO({\count_reg[0]_i_1_n_0 ,\count_reg[0]_i_1_n_1 ,\count_reg[0]_i_1_n_2 ,\count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\count_reg[0]_i_1_n_4 ,\count_reg[0]_i_1_n_5 ,\count_reg[0]_i_1_n_6 ,\count_reg[0]_i_1_n_7 }), + .S({count_reg[3:1],\count[0]_i_2_n_0 })); + FDCE #( + .INIT(1'b0)) + \count_reg[10] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[8]_i_1_n_5 ), + .Q(count_reg[10])); + FDCE #( + .INIT(1'b0)) + \count_reg[11] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[8]_i_1_n_4 ), + .Q(count_reg[11])); + FDCE #( + .INIT(1'b0)) + \count_reg[12] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[12]_i_1_n_7 ), + .Q(count_reg[12])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[12]_i_1 + (.CI(\count_reg[8]_i_1_n_0 ), + .CO({\count_reg[12]_i_1_n_0 ,\count_reg[12]_i_1_n_1 ,\count_reg[12]_i_1_n_2 ,\count_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[12]_i_1_n_4 ,\count_reg[12]_i_1_n_5 ,\count_reg[12]_i_1_n_6 ,\count_reg[12]_i_1_n_7 }), + .S(count_reg[15:12])); + FDCE #( + .INIT(1'b0)) + \count_reg[13] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[12]_i_1_n_6 ), + .Q(count_reg[13])); + FDCE #( + .INIT(1'b0)) + \count_reg[14] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[12]_i_1_n_5 ), + .Q(count_reg[14])); + FDCE #( + .INIT(1'b0)) + \count_reg[15] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[12]_i_1_n_4 ), + .Q(count_reg[15])); + FDCE #( + .INIT(1'b0)) + \count_reg[16] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[16]_i_1_n_7 ), + .Q(count_reg[16])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[16]_i_1 + (.CI(\count_reg[12]_i_1_n_0 ), + .CO({\count_reg[16]_i_1_n_0 ,\count_reg[16]_i_1_n_1 ,\count_reg[16]_i_1_n_2 ,\count_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[16]_i_1_n_4 ,\count_reg[16]_i_1_n_5 ,\count_reg[16]_i_1_n_6 ,\count_reg[16]_i_1_n_7 }), + .S(count_reg[19:16])); + FDCE #( + .INIT(1'b0)) + \count_reg[17] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[16]_i_1_n_6 ), + .Q(count_reg[17])); + FDCE #( + .INIT(1'b0)) + \count_reg[18] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[16]_i_1_n_5 ), + .Q(count_reg[18])); + FDCE #( + .INIT(1'b0)) + \count_reg[19] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[16]_i_1_n_4 ), + .Q(count_reg[19])); + FDCE #( + .INIT(1'b0)) + \count_reg[1] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[0]_i_1_n_6 ), + .Q(count_reg[1])); + FDCE #( + .INIT(1'b0)) + \count_reg[20] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[20]_i_1_n_7 ), + .Q(count_reg[20])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[20]_i_1 + (.CI(\count_reg[16]_i_1_n_0 ), + .CO({\count_reg[20]_i_1_n_0 ,\count_reg[20]_i_1_n_1 ,\count_reg[20]_i_1_n_2 ,\count_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[20]_i_1_n_4 ,\count_reg[20]_i_1_n_5 ,\count_reg[20]_i_1_n_6 ,\count_reg[20]_i_1_n_7 }), + .S(count_reg[23:20])); + FDCE #( + .INIT(1'b0)) + \count_reg[21] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[20]_i_1_n_6 ), + .Q(count_reg[21])); + FDCE #( + .INIT(1'b0)) + \count_reg[22] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[20]_i_1_n_5 ), + .Q(count_reg[22])); + FDCE #( + .INIT(1'b0)) + \count_reg[23] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[20]_i_1_n_4 ), + .Q(count_reg[23])); + FDCE #( + .INIT(1'b0)) + \count_reg[24] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[24]_i_1_n_7 ), + .Q(count_reg[24])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[24]_i_1 + (.CI(\count_reg[20]_i_1_n_0 ), + .CO({\count_reg[24]_i_1_n_0 ,\count_reg[24]_i_1_n_1 ,\count_reg[24]_i_1_n_2 ,\count_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[24]_i_1_n_4 ,\count_reg[24]_i_1_n_5 ,\count_reg[24]_i_1_n_6 ,\count_reg[24]_i_1_n_7 }), + .S(count_reg[27:24])); + FDCE #( + .INIT(1'b0)) + \count_reg[25] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[24]_i_1_n_6 ), + .Q(count_reg[25])); + FDCE #( + .INIT(1'b0)) + \count_reg[26] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[24]_i_1_n_5 ), + .Q(count_reg[26])); + FDCE #( + .INIT(1'b0)) + \count_reg[27] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[24]_i_1_n_4 ), + .Q(count_reg[27])); + FDCE #( + .INIT(1'b0)) + \count_reg[28] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[28]_i_1_n_7 ), + .Q(count_reg[28])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[28]_i_1 + (.CI(\count_reg[24]_i_1_n_0 ), + .CO({\NLW_count_reg[28]_i_1_CO_UNCONNECTED [3],\count_reg[28]_i_1_n_1 ,\count_reg[28]_i_1_n_2 ,\count_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[28]_i_1_n_4 ,\count_reg[28]_i_1_n_5 ,\count_reg[28]_i_1_n_6 ,\count_reg[28]_i_1_n_7 }), + .S(count_reg[31:28])); + FDCE #( + .INIT(1'b0)) + \count_reg[29] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[28]_i_1_n_6 ), + .Q(count_reg[29])); + FDCE #( + .INIT(1'b0)) + \count_reg[2] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[0]_i_1_n_5 ), + .Q(count_reg[2])); + FDCE #( + .INIT(1'b0)) + \count_reg[30] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[28]_i_1_n_5 ), + .Q(count_reg[30])); + FDCE #( + .INIT(1'b0)) + \count_reg[31] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[28]_i_1_n_4 ), + .Q(count_reg[31])); + FDCE #( + .INIT(1'b0)) + \count_reg[3] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[0]_i_1_n_4 ), + .Q(count_reg[3])); + FDCE #( + .INIT(1'b0)) + \count_reg[4] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[4]_i_1_n_7 ), + .Q(count_reg[4])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[4]_i_1 + (.CI(\count_reg[0]_i_1_n_0 ), + .CO({\count_reg[4]_i_1_n_0 ,\count_reg[4]_i_1_n_1 ,\count_reg[4]_i_1_n_2 ,\count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[4]_i_1_n_4 ,\count_reg[4]_i_1_n_5 ,\count_reg[4]_i_1_n_6 ,\count_reg[4]_i_1_n_7 }), + .S(count_reg[7:4])); + FDCE #( + .INIT(1'b0)) + \count_reg[5] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[4]_i_1_n_6 ), + .Q(count_reg[5])); + FDCE #( + .INIT(1'b0)) + \count_reg[6] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[4]_i_1_n_5 ), + .Q(count_reg[6])); + FDCE #( + .INIT(1'b0)) + \count_reg[7] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[4]_i_1_n_4 ), + .Q(count_reg[7])); + FDCE #( + .INIT(1'b0)) + \count_reg[8] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[8]_i_1_n_7 ), + .Q(count_reg[8])); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \count_reg[8]_i_1 + (.CI(\count_reg[4]_i_1_n_0 ), + .CO({\count_reg[8]_i_1_n_0 ,\count_reg[8]_i_1_n_1 ,\count_reg[8]_i_1_n_2 ,\count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\count_reg[8]_i_1_n_4 ,\count_reg[8]_i_1_n_5 ,\count_reg[8]_i_1_n_6 ,\count_reg[8]_i_1_n_7 }), + .S(count_reg[11:8])); + FDCE #( + .INIT(1'b0)) + \count_reg[9] + (.C(clk_IBUF_BUFG), + .CE(1'b1), + .CLR(led_reg_i_2_n_0), + .D(\count_reg[8]_i_1_n_6 ), + .Q(count_reg[9])); + OBUF led_OBUF_inst + (.I(led_OBUF), + .O(led)); + (* XILINX_LEGACY_PRIM = "LDC" *) + (* XILINX_TRANSFORM_PINMAP = "VCC:GE" *) + LDCE #( + .INIT(1'b0)) + led_reg + (.CLR(led_reg_i_2_n_0), + .D(led_reg_i_1_n_0), + .G(led_reg_i_1_n_0), + .GE(1'b1), + .Q(led_OBUF)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_1 + (.CI(led_reg_i_3_n_0), + .CO({led_reg_i_1_n_0,led_reg_i_1_n_1,led_reg_i_1_n_2,led_reg_i_1_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_4_n_0,led_reg_i_5_n_0,led_reg_i_6_n_0,led_reg_i_7_n_0}), + .O(NLW_led_reg_i_1_O_UNCONNECTED[3:0]), + .S({led_reg_i_8_n_0,led_reg_i_9_n_0,led_reg_i_10_n_0,led_reg_i_11_n_0})); + LUT2 #( + .INIT(4'h1)) + led_reg_i_10 + (.I0(count_reg[26]), + .I1(count_reg[27]), + .O(led_reg_i_10_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_11 + (.I0(count_reg[24]), + .I1(count_reg[25]), + .O(led_reg_i_11_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_12 + (.CI(led_reg_i_28_n_0), + .CO({led_reg_i_12_n_0,led_reg_i_12_n_1,led_reg_i_12_n_2,led_reg_i_12_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_29_n_0,led_reg_i_30_n_0,1'b0,1'b0}), + .O(NLW_led_reg_i_12_O_UNCONNECTED[3:0]), + .S({led_reg_i_31_n_0,led_reg_i_32_n_0,led_reg_i_33_n_0,led_reg_i_34_n_0})); + LUT2 #( + .INIT(4'h2)) + led_reg_i_13 + (.I0(count_reg[30]), + .I1(count_reg[31]), + .O(led_reg_i_13_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_14 + (.I0(count_reg[28]), + .I1(count_reg[29]), + .O(led_reg_i_14_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_15 + (.I0(count_reg[26]), + .I1(count_reg[27]), + .O(led_reg_i_15_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_16 + (.I0(count_reg[24]), + .I1(count_reg[25]), + .O(led_reg_i_16_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_17 + (.I0(count_reg[30]), + .I1(count_reg[31]), + .O(led_reg_i_17_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_18 + (.I0(count_reg[28]), + .I1(count_reg[29]), + .O(led_reg_i_18_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_19 + (.I0(count_reg[26]), + .I1(count_reg[27]), + .O(led_reg_i_19_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_2 + (.CI(led_reg_i_12_n_0), + .CO({led_reg_i_2_n_0,led_reg_i_2_n_1,led_reg_i_2_n_2,led_reg_i_2_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_13_n_0,led_reg_i_14_n_0,led_reg_i_15_n_0,led_reg_i_16_n_0}), + .O(NLW_led_reg_i_2_O_UNCONNECTED[3:0]), + .S({led_reg_i_17_n_0,led_reg_i_18_n_0,led_reg_i_19_n_0,led_reg_i_20_n_0})); + LUT2 #( + .INIT(4'h1)) + led_reg_i_20 + (.I0(count_reg[24]), + .I1(count_reg[25]), + .O(led_reg_i_20_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_21 + (.CI(led_reg_i_35_n_0), + .CO({led_reg_i_21_n_0,led_reg_i_21_n_1,led_reg_i_21_n_2,led_reg_i_21_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_36_n_0,led_reg_i_37_n_0,count_reg[11],led_reg_i_38_n_0}), + .O(NLW_led_reg_i_21_O_UNCONNECTED[3:0]), + .S({led_reg_i_39_n_0,led_reg_i_40_n_0,led_reg_i_41_n_0,led_reg_i_42_n_0})); + LUT2 #( + .INIT(4'hE)) + led_reg_i_22 + (.I0(count_reg[22]), + .I1(count_reg[23]), + .O(led_reg_i_22_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_23 + (.I0(count_reg[16]), + .I1(count_reg[17]), + .O(led_reg_i_23_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_24 + (.I0(count_reg[22]), + .I1(count_reg[23]), + .O(led_reg_i_24_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_25 + (.I0(count_reg[20]), + .I1(count_reg[21]), + .O(led_reg_i_25_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_26 + (.I0(count_reg[18]), + .I1(count_reg[19]), + .O(led_reg_i_26_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_27 + (.I0(count_reg[17]), + .I1(count_reg[16]), + .O(led_reg_i_27_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_28 + (.CI(led_reg_i_43_n_0), + .CO({led_reg_i_28_n_0,led_reg_i_28_n_1,led_reg_i_28_n_2,led_reg_i_28_n_3}), + .CYINIT(1'b0), + .DI({count_reg[15],led_reg_i_44_n_0,led_reg_i_45_n_0,led_reg_i_46_n_0}), + .O(NLW_led_reg_i_28_O_UNCONNECTED[3:0]), + .S({led_reg_i_47_n_0,led_reg_i_48_n_0,led_reg_i_49_n_0,led_reg_i_50_n_0})); + LUT2 #( + .INIT(4'hE)) + led_reg_i_29 + (.I0(count_reg[22]), + .I1(count_reg[23]), + .O(led_reg_i_29_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_3 + (.CI(led_reg_i_21_n_0), + .CO({led_reg_i_3_n_0,led_reg_i_3_n_1,led_reg_i_3_n_2,led_reg_i_3_n_3}), + .CYINIT(1'b0), + .DI({led_reg_i_22_n_0,count_reg[21],1'b0,led_reg_i_23_n_0}), + .O(NLW_led_reg_i_3_O_UNCONNECTED[3:0]), + .S({led_reg_i_24_n_0,led_reg_i_25_n_0,led_reg_i_26_n_0,led_reg_i_27_n_0})); + LUT2 #( + .INIT(4'hE)) + led_reg_i_30 + (.I0(count_reg[20]), + .I1(count_reg[21]), + .O(led_reg_i_30_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_31 + (.I0(count_reg[22]), + .I1(count_reg[23]), + .O(led_reg_i_31_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_32 + (.I0(count_reg[20]), + .I1(count_reg[21]), + .O(led_reg_i_32_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_33 + (.I0(count_reg[18]), + .I1(count_reg[19]), + .O(led_reg_i_33_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_34 + (.I0(count_reg[16]), + .I1(count_reg[17]), + .O(led_reg_i_34_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_35 + (.CI(1'b0), + .CO({led_reg_i_35_n_0,led_reg_i_35_n_1,led_reg_i_35_n_2,led_reg_i_35_n_3}), + .CYINIT(1'b1), + .DI({led_reg_i_51_n_0,led_reg_i_52_n_0,led_reg_i_53_n_0,led_reg_i_54_n_0}), + .O(NLW_led_reg_i_35_O_UNCONNECTED[3:0]), + .S({led_reg_i_55_n_0,led_reg_i_56_n_0,led_reg_i_57_n_0,led_reg_i_58_n_0})); + LUT2 #( + .INIT(4'h8)) + led_reg_i_36 + (.I0(count_reg[14]), + .I1(count_reg[15]), + .O(led_reg_i_36_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_37 + (.I0(count_reg[12]), + .I1(count_reg[13]), + .O(led_reg_i_37_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_38 + (.I0(count_reg[8]), + .I1(count_reg[9]), + .O(led_reg_i_38_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_39 + (.I0(count_reg[15]), + .I1(count_reg[14]), + .O(led_reg_i_39_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_4 + (.I0(count_reg[30]), + .I1(count_reg[31]), + .O(led_reg_i_4_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_40 + (.I0(count_reg[12]), + .I1(count_reg[13]), + .O(led_reg_i_40_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_41 + (.I0(count_reg[10]), + .I1(count_reg[11]), + .O(led_reg_i_41_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_42 + (.I0(count_reg[8]), + .I1(count_reg[9]), + .O(led_reg_i_42_n_0)); + (* COMPARATOR_THRESHOLD = "11" *) + CARRY4 led_reg_i_43 + (.CI(1'b0), + .CO({led_reg_i_43_n_0,led_reg_i_43_n_1,led_reg_i_43_n_2,led_reg_i_43_n_3}), + .CYINIT(1'b1), + .DI({count_reg[7],led_reg_i_59_n_0,led_reg_i_60_n_0,led_reg_i_61_n_0}), + .O(NLW_led_reg_i_43_O_UNCONNECTED[3:0]), + .S({led_reg_i_62_n_0,led_reg_i_63_n_0,led_reg_i_64_n_0,led_reg_i_65_n_0})); + LUT2 #( + .INIT(4'hE)) + led_reg_i_44 + (.I0(count_reg[12]), + .I1(count_reg[13]), + .O(led_reg_i_44_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_45 + (.I0(count_reg[10]), + .I1(count_reg[11]), + .O(led_reg_i_45_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_46 + (.I0(count_reg[8]), + .I1(count_reg[9]), + .O(led_reg_i_46_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_47 + (.I0(count_reg[14]), + .I1(count_reg[15]), + .O(led_reg_i_47_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_48 + (.I0(count_reg[12]), + .I1(count_reg[13]), + .O(led_reg_i_48_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_49 + (.I0(count_reg[10]), + .I1(count_reg[11]), + .O(led_reg_i_49_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_5 + (.I0(count_reg[28]), + .I1(count_reg[29]), + .O(led_reg_i_5_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_50 + (.I0(count_reg[9]), + .I1(count_reg[8]), + .O(led_reg_i_50_n_0)); + LUT2 #( + .INIT(4'h8)) + led_reg_i_51 + (.I0(count_reg[6]), + .I1(count_reg[7]), + .O(led_reg_i_51_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_52 + (.I0(count_reg[4]), + .I1(count_reg[5]), + .O(led_reg_i_52_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_53 + (.I0(count_reg[2]), + .I1(count_reg[3]), + .O(led_reg_i_53_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_54 + (.I0(count_reg[0]), + .I1(count_reg[1]), + .O(led_reg_i_54_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_55 + (.I0(count_reg[7]), + .I1(count_reg[6]), + .O(led_reg_i_55_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_56 + (.I0(count_reg[4]), + .I1(count_reg[5]), + .O(led_reg_i_56_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_57 + (.I0(count_reg[2]), + .I1(count_reg[3]), + .O(led_reg_i_57_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_58 + (.I0(count_reg[0]), + .I1(count_reg[1]), + .O(led_reg_i_58_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_59 + (.I0(count_reg[4]), + .I1(count_reg[5]), + .O(led_reg_i_59_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_6 + (.I0(count_reg[26]), + .I1(count_reg[27]), + .O(led_reg_i_6_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_60 + (.I0(count_reg[2]), + .I1(count_reg[3]), + .O(led_reg_i_60_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_61 + (.I0(count_reg[0]), + .I1(count_reg[1]), + .O(led_reg_i_61_n_0)); + LUT2 #( + .INIT(4'h2)) + led_reg_i_62 + (.I0(count_reg[6]), + .I1(count_reg[7]), + .O(led_reg_i_62_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_63 + (.I0(count_reg[4]), + .I1(count_reg[5]), + .O(led_reg_i_63_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_64 + (.I0(count_reg[2]), + .I1(count_reg[3]), + .O(led_reg_i_64_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_65 + (.I0(count_reg[0]), + .I1(count_reg[1]), + .O(led_reg_i_65_n_0)); + LUT2 #( + .INIT(4'hE)) + led_reg_i_7 + (.I0(count_reg[24]), + .I1(count_reg[25]), + .O(led_reg_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_8 + (.I0(count_reg[30]), + .I1(count_reg[31]), + .O(led_reg_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + led_reg_i_9 + (.I0(count_reg[28]), + .I1(count_reg[29]), + .O(led_reg_i_9_n_0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.bat b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.bat new file mode 100644 index 0000000..de13086 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2021.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Wed Mar 16 20:54:28 +0100 2022 +REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +REM +REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +REM simulate design +echo "xsim pwm_test_db_time_synth -key {Post-Synthesis:sim_1:Timing:pwm_test_db} -tclbatch pwm_test_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg -log simulate.log" +call xsim pwm_test_db_time_synth -key {Post-Synthesis:sim_1:Timing:pwm_test_db} -tclbatch pwm_test_db.tcl -view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.log new file mode 100644 index 0000000..8f8d1ed --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/simulate.log @@ -0,0 +1,2 @@ +Time resolution is 1 ps +INFO: xsimkernel Simulation Memory Usage: 20776 KB (Peak: 20776 KB), Simulation CPU Usage: 461827 ms diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xelab.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xelab.pb new file mode 100644 index 0000000..3da06a8 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xelab.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/Compile_Options.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/Compile_Options.txt new file mode 100644 index 0000000..f5cc3de --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "2" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "pwm_test_db_time_synth" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.pwm_test_db" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/TempBreakPointFile.txt b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_0.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_0.win64.obj new file mode 100644 index 0000000..6ea05cd Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_0.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.c b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.c new file mode 100644 index 0000000..51840eb --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.c @@ -0,0 +1,1016 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_2(char*, char *); +IKI_DLLESPEC extern void execute_3(char*, char *); +IKI_DLLESPEC extern void execute_4(char*, char *); +IKI_DLLESPEC extern void execute_5(char*, char *); +IKI_DLLESPEC extern void execute_6(char*, char *); +IKI_DLLESPEC extern void execute_7(char*, char *); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_380(char*, char *); +IKI_DLLESPEC extern void execute_381(char*, char *); +IKI_DLLESPEC extern void execute_19(char*, char *); +IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_2296(char*, char *); +IKI_DLLESPEC extern void execute_2301(char*, char *); +IKI_DLLESPEC extern void execute_2307(char*, char *); +IKI_DLLESPEC extern void execute_2314(char*, char *); +IKI_DLLESPEC extern void execute_2320(char*, char *); +IKI_DLLESPEC extern void execute_2326(char*, char *); +IKI_DLLESPEC extern void execute_2334(char*, char *); +IKI_DLLESPEC extern void execute_2340(char*, char *); +IKI_DLLESPEC extern void execute_2345(char*, char *); +IKI_DLLESPEC extern void execute_2350(char*, char *); +IKI_DLLESPEC extern void execute_2355(char*, char *); +IKI_DLLESPEC extern void execute_2356(char*, char *); +IKI_DLLESPEC extern void execute_2357(char*, char *); +IKI_DLLESPEC extern void execute_2358(char*, char *); +IKI_DLLESPEC extern void execute_2359(char*, char *); +IKI_DLLESPEC extern void execute_2360(char*, char *); +IKI_DLLESPEC extern void execute_2361(char*, char *); +IKI_DLLESPEC extern void execute_2362(char*, char *); +IKI_DLLESPEC extern void execute_2363(char*, char *); +IKI_DLLESPEC extern void execute_2364(char*, char *); +IKI_DLLESPEC extern void execute_2365(char*, char *); +IKI_DLLESPEC extern void execute_2366(char*, char *); +IKI_DLLESPEC extern void execute_2367(char*, char *); +IKI_DLLESPEC extern void execute_2368(char*, char *); +IKI_DLLESPEC extern void execute_2369(char*, char *); +IKI_DLLESPEC extern void execute_2370(char*, char *); +IKI_DLLESPEC extern void execute_2371(char*, char *); +IKI_DLLESPEC extern void execute_2372(char*, char *); +IKI_DLLESPEC extern void execute_2373(char*, char *); +IKI_DLLESPEC extern void execute_2374(char*, char *); +IKI_DLLESPEC extern void execute_2375(char*, char *); +IKI_DLLESPEC extern void execute_2376(char*, char *); +IKI_DLLESPEC extern void execute_2377(char*, char *); +IKI_DLLESPEC extern void execute_2378(char*, char *); +IKI_DLLESPEC extern void execute_2379(char*, char *); +IKI_DLLESPEC extern void execute_2380(char*, char *); +IKI_DLLESPEC extern void execute_2381(char*, char *); +IKI_DLLESPEC extern void execute_2382(char*, char *); +IKI_DLLESPEC extern void execute_2383(char*, char *); +IKI_DLLESPEC extern void execute_2384(char*, char *); +IKI_DLLESPEC extern void execute_2385(char*, char *); +IKI_DLLESPEC extern void execute_2386(char*, char *); +IKI_DLLESPEC extern void execute_2387(char*, char *); +IKI_DLLESPEC extern void execute_2388(char*, char *); +IKI_DLLESPEC extern void execute_2389(char*, char *); +IKI_DLLESPEC extern void execute_2390(char*, char *); +IKI_DLLESPEC extern void execute_2391(char*, char *); +IKI_DLLESPEC extern void execute_2392(char*, char *); +IKI_DLLESPEC extern void execute_2393(char*, char *); +IKI_DLLESPEC extern void execute_2394(char*, char *); +IKI_DLLESPEC extern void execute_2395(char*, char *); +IKI_DLLESPEC extern void execute_2396(char*, char *); +IKI_DLLESPEC extern void execute_2397(char*, char *); +IKI_DLLESPEC extern void execute_2398(char*, char *); +IKI_DLLESPEC extern void execute_2399(char*, char *); +IKI_DLLESPEC extern void execute_2400(char*, char *); +IKI_DLLESPEC extern void execute_2401(char*, char *); +IKI_DLLESPEC extern void execute_2402(char*, char *); +IKI_DLLESPEC extern void execute_2403(char*, char *); +IKI_DLLESPEC extern void execute_2404(char*, char *); +IKI_DLLESPEC extern void execute_2405(char*, char *); +IKI_DLLESPEC extern void execute_2406(char*, char *); +IKI_DLLESPEC extern void execute_2407(char*, char *); +IKI_DLLESPEC extern void execute_2408(char*, char *); +IKI_DLLESPEC extern void execute_2409(char*, char *); +IKI_DLLESPEC extern void execute_2410(char*, char *); +IKI_DLLESPEC extern void execute_2411(char*, char *); +IKI_DLLESPEC extern void execute_2412(char*, char *); +IKI_DLLESPEC extern void execute_2413(char*, char *); +IKI_DLLESPEC extern void execute_2414(char*, char *); +IKI_DLLESPEC extern void execute_2415(char*, char *); +IKI_DLLESPEC extern void execute_2416(char*, char *); +IKI_DLLESPEC extern void execute_2417(char*, char *); +IKI_DLLESPEC extern void execute_2418(char*, char *); +IKI_DLLESPEC extern void execute_2419(char*, char *); +IKI_DLLESPEC extern void execute_2420(char*, char *); +IKI_DLLESPEC extern void execute_2421(char*, char *); +IKI_DLLESPEC extern void execute_2422(char*, char *); +IKI_DLLESPEC extern void execute_2423(char*, char *); +IKI_DLLESPEC extern void execute_2424(char*, char *); +IKI_DLLESPEC extern void execute_2425(char*, char *); +IKI_DLLESPEC extern void execute_2426(char*, char *); +IKI_DLLESPEC extern void execute_2427(char*, char *); +IKI_DLLESPEC extern void execute_2428(char*, char *); +IKI_DLLESPEC extern void execute_2429(char*, char *); +IKI_DLLESPEC extern void execute_2430(char*, char *); +IKI_DLLESPEC extern void execute_2431(char*, char *); +IKI_DLLESPEC extern void execute_2432(char*, char *); +IKI_DLLESPEC extern void execute_2433(char*, char *); +IKI_DLLESPEC extern void execute_2434(char*, char *); +IKI_DLLESPEC extern void execute_2435(char*, char *); +IKI_DLLESPEC extern void execute_2436(char*, char *); +IKI_DLLESPEC extern void execute_2437(char*, char *); +IKI_DLLESPEC extern void execute_2438(char*, char *); +IKI_DLLESPEC extern void execute_2439(char*, char *); +IKI_DLLESPEC extern void execute_2440(char*, char *); +IKI_DLLESPEC extern void execute_2441(char*, char *); +IKI_DLLESPEC extern void execute_2442(char*, char *); +IKI_DLLESPEC extern void execute_2443(char*, char *); +IKI_DLLESPEC extern void execute_2444(char*, char *); +IKI_DLLESPEC extern void execute_2445(char*, char *); +IKI_DLLESPEC extern void execute_2446(char*, char *); +IKI_DLLESPEC extern void execute_2447(char*, char *); +IKI_DLLESPEC extern void execute_2448(char*, char *); +IKI_DLLESPEC extern void execute_2449(char*, char *); +IKI_DLLESPEC extern void execute_2450(char*, char *); +IKI_DLLESPEC extern void execute_2451(char*, char *); +IKI_DLLESPEC extern void execute_2452(char*, char *); +IKI_DLLESPEC extern void execute_2453(char*, char *); +IKI_DLLESPEC extern void execute_2454(char*, char *); +IKI_DLLESPEC extern void execute_2455(char*, char *); +IKI_DLLESPEC extern void execute_2456(char*, char *); +IKI_DLLESPEC extern void execute_2457(char*, char *); +IKI_DLLESPEC extern void execute_2458(char*, char *); +IKI_DLLESPEC extern void execute_2459(char*, char *); +IKI_DLLESPEC extern void execute_2460(char*, char *); +IKI_DLLESPEC extern void execute_2461(char*, char *); +IKI_DLLESPEC extern void execute_2462(char*, char *); +IKI_DLLESPEC extern void execute_2463(char*, char *); +IKI_DLLESPEC extern void execute_2464(char*, char *); +IKI_DLLESPEC extern void execute_2465(char*, char *); +IKI_DLLESPEC extern void execute_2466(char*, char *); +IKI_DLLESPEC extern void execute_2467(char*, char *); +IKI_DLLESPEC extern void execute_2468(char*, char *); +IKI_DLLESPEC extern void execute_2469(char*, char *); +IKI_DLLESPEC extern void execute_2470(char*, char *); +IKI_DLLESPEC extern void execute_2471(char*, char *); +IKI_DLLESPEC extern void execute_2472(char*, char *); +IKI_DLLESPEC extern void execute_2473(char*, char *); +IKI_DLLESPEC extern void execute_2474(char*, char *); +IKI_DLLESPEC extern void execute_2475(char*, char *); +IKI_DLLESPEC extern void execute_2476(char*, char *); +IKI_DLLESPEC extern void execute_2477(char*, char *); +IKI_DLLESPEC extern void execute_2478(char*, char *); +IKI_DLLESPEC extern void execute_2479(char*, char *); +IKI_DLLESPEC extern void execute_2480(char*, char *); +IKI_DLLESPEC extern void execute_2481(char*, char *); +IKI_DLLESPEC extern void execute_2482(char*, char *); +IKI_DLLESPEC extern void execute_2483(char*, char *); +IKI_DLLESPEC extern void execute_2484(char*, char *); +IKI_DLLESPEC extern void execute_2485(char*, char *); +IKI_DLLESPEC extern void execute_2486(char*, char *); +IKI_DLLESPEC extern void execute_2487(char*, char *); +IKI_DLLESPEC extern void execute_2488(char*, char *); +IKI_DLLESPEC extern void execute_2489(char*, char *); +IKI_DLLESPEC extern void execute_2490(char*, char *); +IKI_DLLESPEC extern void execute_2491(char*, char *); +IKI_DLLESPEC extern void execute_2492(char*, char *); +IKI_DLLESPEC extern void execute_2493(char*, char *); +IKI_DLLESPEC extern void execute_2494(char*, char *); +IKI_DLLESPEC extern void execute_2495(char*, char *); +IKI_DLLESPEC extern void execute_2496(char*, char *); +IKI_DLLESPEC extern void execute_2497(char*, char *); +IKI_DLLESPEC extern void execute_2498(char*, char *); +IKI_DLLESPEC extern void execute_2499(char*, char *); +IKI_DLLESPEC extern void execute_2500(char*, char *); +IKI_DLLESPEC extern void execute_2501(char*, char *); +IKI_DLLESPEC extern void execute_2502(char*, char *); +IKI_DLLESPEC extern void execute_2503(char*, char *); +IKI_DLLESPEC extern void execute_2504(char*, char *); +IKI_DLLESPEC extern void execute_2505(char*, char *); +IKI_DLLESPEC extern void execute_2506(char*, char *); +IKI_DLLESPEC extern void execute_2507(char*, char *); +IKI_DLLESPEC extern void execute_2508(char*, char *); +IKI_DLLESPEC extern void execute_2509(char*, char *); +IKI_DLLESPEC extern void execute_2510(char*, char *); +IKI_DLLESPEC extern void execute_2511(char*, char *); +IKI_DLLESPEC extern void execute_2512(char*, char *); +IKI_DLLESPEC extern void execute_2513(char*, char *); +IKI_DLLESPEC extern void execute_2514(char*, char *); +IKI_DLLESPEC extern void execute_2515(char*, char *); +IKI_DLLESPEC extern void execute_2516(char*, char *); +IKI_DLLESPEC extern void execute_2517(char*, char *); +IKI_DLLESPEC extern void execute_2518(char*, char *); +IKI_DLLESPEC extern void execute_2519(char*, char *); +IKI_DLLESPEC extern void execute_2520(char*, char *); +IKI_DLLESPEC extern void execute_2521(char*, char *); +IKI_DLLESPEC extern void execute_2522(char*, char *); +IKI_DLLESPEC extern void execute_2523(char*, char *); +IKI_DLLESPEC extern void execute_2524(char*, char *); +IKI_DLLESPEC extern void execute_2525(char*, char *); +IKI_DLLESPEC extern void execute_2526(char*, char *); +IKI_DLLESPEC extern void execute_2527(char*, char *); +IKI_DLLESPEC extern void execute_2528(char*, char *); +IKI_DLLESPEC extern void execute_2529(char*, char *); +IKI_DLLESPEC extern void execute_2530(char*, char *); +IKI_DLLESPEC extern void execute_2531(char*, char *); +IKI_DLLESPEC extern void execute_2532(char*, char *); +IKI_DLLESPEC extern void execute_2533(char*, char *); +IKI_DLLESPEC extern void execute_2534(char*, char *); +IKI_DLLESPEC extern void execute_2535(char*, char *); +IKI_DLLESPEC extern void execute_2536(char*, char *); +IKI_DLLESPEC extern void execute_2537(char*, char *); +IKI_DLLESPEC extern void execute_2538(char*, char *); +IKI_DLLESPEC extern void execute_2539(char*, char *); +IKI_DLLESPEC extern void execute_2540(char*, char *); +IKI_DLLESPEC extern void execute_2541(char*, char *); +IKI_DLLESPEC extern void execute_2542(char*, char *); +IKI_DLLESPEC extern void execute_2543(char*, char *); +IKI_DLLESPEC extern void execute_2544(char*, char *); +IKI_DLLESPEC extern void execute_2545(char*, char *); +IKI_DLLESPEC extern void execute_2546(char*, char *); +IKI_DLLESPEC extern void execute_2547(char*, char *); +IKI_DLLESPEC extern void execute_2548(char*, char *); +IKI_DLLESPEC extern void execute_2549(char*, char *); +IKI_DLLESPEC extern void execute_2550(char*, char *); +IKI_DLLESPEC extern void execute_2551(char*, char *); +IKI_DLLESPEC extern void execute_2552(char*, char *); +IKI_DLLESPEC extern void execute_2553(char*, char *); +IKI_DLLESPEC extern void execute_2554(char*, char *); +IKI_DLLESPEC extern void execute_2555(char*, char *); +IKI_DLLESPEC extern void execute_2556(char*, char *); +IKI_DLLESPEC extern void execute_2557(char*, char *); +IKI_DLLESPEC extern void execute_2558(char*, char *); +IKI_DLLESPEC extern void execute_2559(char*, char *); +IKI_DLLESPEC extern void execute_2560(char*, char *); +IKI_DLLESPEC extern void execute_2561(char*, char *); +IKI_DLLESPEC extern void execute_2562(char*, char *); +IKI_DLLESPEC extern void execute_2563(char*, char *); +IKI_DLLESPEC extern void execute_2564(char*, char *); +IKI_DLLESPEC extern void execute_2565(char*, char *); +IKI_DLLESPEC extern void execute_2566(char*, char *); +IKI_DLLESPEC extern void execute_2567(char*, char *); +IKI_DLLESPEC extern void execute_2568(char*, char *); +IKI_DLLESPEC extern void execute_2569(char*, char *); +IKI_DLLESPEC extern void execute_2570(char*, char *); +IKI_DLLESPEC extern void execute_2571(char*, char *); +IKI_DLLESPEC extern void execute_2572(char*, char *); +IKI_DLLESPEC extern void execute_2573(char*, char *); +IKI_DLLESPEC extern void execute_2574(char*, char *); +IKI_DLLESPEC extern void execute_2575(char*, char *); +IKI_DLLESPEC extern void execute_2576(char*, char *); +IKI_DLLESPEC extern void execute_2577(char*, char *); +IKI_DLLESPEC extern void execute_2578(char*, char *); +IKI_DLLESPEC extern void execute_2579(char*, char *); +IKI_DLLESPEC extern void execute_2580(char*, char *); +IKI_DLLESPEC extern void execute_2581(char*, char *); +IKI_DLLESPEC extern void execute_2582(char*, char *); +IKI_DLLESPEC extern void execute_2583(char*, char *); +IKI_DLLESPEC extern void execute_384(char*, char *); +IKI_DLLESPEC extern void vlog_timingcheck_execute_0(char*, char*, char*); +IKI_DLLESPEC extern void execute_22(char*, char *); +IKI_DLLESPEC extern void execute_387(char*, char *); +IKI_DLLESPEC extern void execute_25(char*, char *); +IKI_DLLESPEC extern void execute_389(char*, char *); +IKI_DLLESPEC extern void execute_390(char*, char *); +IKI_DLLESPEC extern void execute_388(char*, char *); +IKI_DLLESPEC extern void execute_27(char*, char *); +IKI_DLLESPEC extern void execute_28(char*, char *); +IKI_DLLESPEC extern void execute_29(char*, char *); +IKI_DLLESPEC extern void execute_30(char*, char *); +IKI_DLLESPEC extern void execute_391(char*, char *); +IKI_DLLESPEC extern void execute_392(char*, char *); +IKI_DLLESPEC extern void execute_393(char*, char *); +IKI_DLLESPEC extern void execute_394(char*, char *); +IKI_DLLESPEC extern void execute_395(char*, char *); +IKI_DLLESPEC extern void execute_396(char*, char *); +IKI_DLLESPEC extern void execute_397(char*, char *); +IKI_DLLESPEC extern void execute_398(char*, char *); +IKI_DLLESPEC extern void execute_399(char*, char *); +IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_401(char*, char *); +IKI_DLLESPEC extern void execute_402(char*, char *); +IKI_DLLESPEC extern void execute_403(char*, char *); +IKI_DLLESPEC extern void execute_404(char*, char *); +IKI_DLLESPEC extern void execute_405(char*, char *); +IKI_DLLESPEC extern void execute_406(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_1(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_2(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_751(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_752(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_753(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_754(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_755(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_756(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_757(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_758(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_759(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_760(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_761(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_762(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_763(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_764(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_765(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_766(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_767(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_768(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_769(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_770(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_771(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_772(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_773(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_774(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_27(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_28(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_29(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_1899c67f_af79f1dc_30(char*, char *); +IKI_DLLESPEC extern void execute_425(char*, char *); +IKI_DLLESPEC extern void execute_431(char*, char *); +IKI_DLLESPEC extern void execute_432(char*, char *); +IKI_DLLESPEC extern void execute_433(char*, char *); +IKI_DLLESPEC extern void execute_434(char*, char *); +IKI_DLLESPEC extern void execute_435(char*, char *); +IKI_DLLESPEC extern void execute_436(char*, char *); +IKI_DLLESPEC extern void execute_437(char*, char *); +IKI_DLLESPEC extern void execute_440(char*, char *); +IKI_DLLESPEC extern void execute_441(char*, char *); +IKI_DLLESPEC extern void execute_442(char*, char *); +IKI_DLLESPEC extern void execute_443(char*, char *); +IKI_DLLESPEC extern void execute_195(char*, char *); +IKI_DLLESPEC extern void execute_1871(char*, char *); +IKI_DLLESPEC extern void execute_1872(char*, char *); +IKI_DLLESPEC extern void execute_1873(char*, char *); +IKI_DLLESPEC extern void execute_197(char*, char *); +IKI_DLLESPEC extern void execute_199(char*, char *); +IKI_DLLESPEC extern void execute_200(char*, char *); +IKI_DLLESPEC extern void execute_1874(char*, char *); +IKI_DLLESPEC extern void execute_1875(char*, char *); +IKI_DLLESPEC extern void execute_1876(char*, char *); +IKI_DLLESPEC extern void execute_1877(char*, char *); +IKI_DLLESPEC extern void execute_1879(char*, char *); +IKI_DLLESPEC extern void execute_1880(char*, char *); +IKI_DLLESPEC extern void execute_1881(char*, char *); +IKI_DLLESPEC extern void execute_1882(char*, char *); +IKI_DLLESPEC extern void execute_1883(char*, char *); +IKI_DLLESPEC extern void execute_1884(char*, char *); +IKI_DLLESPEC extern void execute_1885(char*, char *); +IKI_DLLESPEC extern void execute_1886(char*, char *); +IKI_DLLESPEC extern void execute_1887(char*, char *); +IKI_DLLESPEC extern void execute_1888(char*, char *); +IKI_DLLESPEC extern void execute_1890(char*, char *); +IKI_DLLESPEC extern void execute_1891(char*, char *); +IKI_DLLESPEC extern void execute_1892(char*, char *); +IKI_DLLESPEC extern void execute_1893(char*, char *); +IKI_DLLESPEC extern void execute_1895(char*, char *); +IKI_DLLESPEC extern void execute_1896(char*, char *); +IKI_DLLESPEC extern void execute_1897(char*, char *); +IKI_DLLESPEC extern void execute_1898(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_775(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_776(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_777(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_778(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_779(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_780(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_781(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_782(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_783(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_784(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_785(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_786(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_787(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_788(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_789(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_790(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_791(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_792(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_793(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_794(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_795(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_796(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_797(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_798(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_799(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_800(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_801(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_802(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_803(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_804(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_805(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_806(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_807(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_808(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_809(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_a0cd4192_f4d1fc17_810(char*, char *); +IKI_DLLESPEC extern void execute_1925(char*, char *); +IKI_DLLESPEC extern void execute_1933(char*, char *); +IKI_DLLESPEC extern void execute_1934(char*, char *); +IKI_DLLESPEC extern void execute_1935(char*, char *); +IKI_DLLESPEC extern void execute_1899(char*, char *); +IKI_DLLESPEC extern void execute_204(char*, char *); +IKI_DLLESPEC extern void execute_1946(char*, char *); +IKI_DLLESPEC extern void execute_1947(char*, char *); +IKI_DLLESPEC extern void execute_1948(char*, char *); +IKI_DLLESPEC extern void execute_1949(char*, char *); +IKI_DLLESPEC extern void execute_1945(char*, char *); +IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_39(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_47(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_48(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_49(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_50(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_53(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_55(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_56(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_70(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_71(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_73(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_74(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_75(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_76(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_84(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_85(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_86(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_87(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_88(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_89(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_90(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_91(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_92(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_93(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_94(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_95(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_96(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_97(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_98(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_99(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_100(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_101(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_102(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_103(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_104(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_105(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_106(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_107(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_108(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_109(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_110(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_111(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_112(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_113(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_114(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_115(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_116(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_123(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_124(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_125(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_126(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_127(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_128(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_129(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_130(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_131(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_132(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_133(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_134(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_135(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_136(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_137(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_138(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_139(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_140(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_141(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_142(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_143(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_144(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_145(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_146(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_147(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_148(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_149(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_150(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_151(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_152(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_153(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_154(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_155(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_156(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_157(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_158(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_159(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_160(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_161(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_162(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_163(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_164(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_166(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_167(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_168(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_169(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_173(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_174(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_175(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_176(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_177(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_178(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_179(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_180(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_181(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_182(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_183(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_184(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_185(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_186(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_187(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_188(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_189(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_190(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_191(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_196(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_199(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_202(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_203(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_204(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_205(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_206(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_207(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_208(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_209(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_210(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_211(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_212(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_213(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_214(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_215(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_216(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_217(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_218(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_219(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_220(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_221(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_222(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_223(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_224(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_225(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_226(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_227(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_228(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_229(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_230(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_231(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_233(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_234(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_235(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_236(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_237(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_238(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_239(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_240(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_241(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_242(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_243(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_244(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_245(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_246(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_247(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_248(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_249(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_250(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_251(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_252(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_253(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_254(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_255(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_256(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_257(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_258(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_259(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_260(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_261(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_262(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_263(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_264(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_265(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_266(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_267(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_268(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_269(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_270(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_271(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_272(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_324(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_325(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_326(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_327(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_329(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_330(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_331(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_332(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_333(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_334(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_335(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_336(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_337(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_338(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_339(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_340(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_341(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_342(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_343(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_344(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_345(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_346(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_347(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_348(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_349(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_350(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_351(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_352(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_353(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_354(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_355(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_356(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_357(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_359(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_361(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_362(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_363(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_364(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_365(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_366(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_367(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_368(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_369(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_370(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_371(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_372(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_373(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_374(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_375(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_376(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_377(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_378(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_379(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_380(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_381(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_382(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_383(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_384(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_385(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_386(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_387(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_388(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_389(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_390(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_391(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_392(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_393(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_394(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_395(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_396(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_397(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_398(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_399(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_400(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_401(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_402(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_403(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_405(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_406(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_407(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_408(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_409(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_410(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_411(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_412(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_413(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_414(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_415(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_416(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_417(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_418(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_419(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_420(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_421(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_422(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_423(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_424(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_425(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_426(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_427(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_428(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_429(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_430(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_431(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_432(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_433(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_434(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_435(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_436(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_437(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_438(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_439(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_440(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_441(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_442(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_443(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_444(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_445(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_447(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_448(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_453(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_454(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_461(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_462(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_467(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_468(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_473(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_474(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_480(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_481(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_486(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_487(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_491(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_492(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_493(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_529(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_530(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_531(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_625(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_626(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_749(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_750(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_902(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_903(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1026(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1027(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1150(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1151(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1332(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1333(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1456(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1457(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1530(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1531(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1532(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1551(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1552(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1601(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1602(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1603(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1616(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1617(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1618(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1661(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1662(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1663(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1676(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1677(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1714(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1715(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1716(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1771(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1772(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1773(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_509(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_547(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_576(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_605(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_642(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_671(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_700(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_729(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_766(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_795(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_824(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_853(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_882(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_919(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_948(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_977(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1006(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1043(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1072(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1101(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1130(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1167(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1196(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1225(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1254(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1349(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1378(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1407(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1436(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1473(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[900] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_380, (funcp)execute_381, (funcp)execute_19, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_2296, (funcp)execute_2301, (funcp)execute_2307, (funcp)execute_2314, (funcp)execute_2320, (funcp)execute_2326, (funcp)execute_2334, (funcp)execute_2340, (funcp)execute_2345, (funcp)execute_2350, (funcp)execute_2355, (funcp)execute_2356, (funcp)execute_2357, (funcp)execute_2358, (funcp)execute_2359, (funcp)execute_2360, (funcp)execute_2361, (funcp)execute_2362, (funcp)execute_2363, (funcp)execute_2364, (funcp)execute_2365, (funcp)execute_2366, (funcp)execute_2367, (funcp)execute_2368, (funcp)execute_2369, (funcp)execute_2370, (funcp)execute_2371, (funcp)execute_2372, (funcp)execute_2373, (funcp)execute_2374, (funcp)execute_2375, (funcp)execute_2376, (funcp)execute_2377, (funcp)execute_2378, (funcp)execute_2379, (funcp)execute_2380, (funcp)execute_2381, (funcp)execute_2382, (funcp)execute_2383, (funcp)execute_2384, (funcp)execute_2385, (funcp)execute_2386, (funcp)execute_2387, (funcp)execute_2388, (funcp)execute_2389, (funcp)execute_2390, (funcp)execute_2391, (funcp)execute_2392, (funcp)execute_2393, (funcp)execute_2394, (funcp)execute_2395, (funcp)execute_2396, (funcp)execute_2397, (funcp)execute_2398, (funcp)execute_2399, (funcp)execute_2400, (funcp)execute_2401, (funcp)execute_2402, (funcp)execute_2403, (funcp)execute_2404, (funcp)execute_2405, (funcp)execute_2406, (funcp)execute_2407, (funcp)execute_2408, (funcp)execute_2409, (funcp)execute_2410, (funcp)execute_2411, (funcp)execute_2412, (funcp)execute_2413, (funcp)execute_2414, (funcp)execute_2415, (funcp)execute_2416, (funcp)execute_2417, (funcp)execute_2418, (funcp)execute_2419, (funcp)execute_2420, (funcp)execute_2421, (funcp)execute_2422, (funcp)execute_2423, (funcp)execute_2424, (funcp)execute_2425, (funcp)execute_2426, (funcp)execute_2427, (funcp)execute_2428, (funcp)execute_2429, (funcp)execute_2430, (funcp)execute_2431, (funcp)execute_2432, (funcp)execute_2433, (funcp)execute_2434, (funcp)execute_2435, (funcp)execute_2436, (funcp)execute_2437, (funcp)execute_2438, (funcp)execute_2439, (funcp)execute_2440, (funcp)execute_2441, (funcp)execute_2442, (funcp)execute_2443, (funcp)execute_2444, (funcp)execute_2445, (funcp)execute_2446, (funcp)execute_2447, (funcp)execute_2448, (funcp)execute_2449, (funcp)execute_2450, (funcp)execute_2451, (funcp)execute_2452, (funcp)execute_2453, (funcp)execute_2454, (funcp)execute_2455, (funcp)execute_2456, (funcp)execute_2457, (funcp)execute_2458, (funcp)execute_2459, (funcp)execute_2460, (funcp)execute_2461, (funcp)execute_2462, (funcp)execute_2463, (funcp)execute_2464, (funcp)execute_2465, (funcp)execute_2466, (funcp)execute_2467, (funcp)execute_2468, (funcp)execute_2469, (funcp)execute_2470, (funcp)execute_2471, (funcp)execute_2472, (funcp)execute_2473, (funcp)execute_2474, (funcp)execute_2475, (funcp)execute_2476, (funcp)execute_2477, (funcp)execute_2478, (funcp)execute_2479, (funcp)execute_2480, (funcp)execute_2481, (funcp)execute_2482, (funcp)execute_2483, (funcp)execute_2484, (funcp)execute_2485, (funcp)execute_2486, (funcp)execute_2487, (funcp)execute_2488, (funcp)execute_2489, (funcp)execute_2490, (funcp)execute_2491, (funcp)execute_2492, (funcp)execute_2493, (funcp)execute_2494, (funcp)execute_2495, (funcp)execute_2496, (funcp)execute_2497, (funcp)execute_2498, (funcp)execute_2499, (funcp)execute_2500, (funcp)execute_2501, (funcp)execute_2502, (funcp)execute_2503, (funcp)execute_2504, (funcp)execute_2505, (funcp)execute_2506, (funcp)execute_2507, (funcp)execute_2508, (funcp)execute_2509, (funcp)execute_2510, (funcp)execute_2511, (funcp)execute_2512, (funcp)execute_2513, (funcp)execute_2514, (funcp)execute_2515, (funcp)execute_2516, (funcp)execute_2517, (funcp)execute_2518, (funcp)execute_2519, (funcp)execute_2520, (funcp)execute_2521, (funcp)execute_2522, (funcp)execute_2523, (funcp)execute_2524, (funcp)execute_2525, (funcp)execute_2526, (funcp)execute_2527, (funcp)execute_2528, (funcp)execute_2529, (funcp)execute_2530, (funcp)execute_2531, (funcp)execute_2532, (funcp)execute_2533, (funcp)execute_2534, (funcp)execute_2535, (funcp)execute_2536, (funcp)execute_2537, (funcp)execute_2538, (funcp)execute_2539, (funcp)execute_2540, (funcp)execute_2541, (funcp)execute_2542, (funcp)execute_2543, (funcp)execute_2544, (funcp)execute_2545, (funcp)execute_2546, (funcp)execute_2547, (funcp)execute_2548, (funcp)execute_2549, (funcp)execute_2550, (funcp)execute_2551, (funcp)execute_2552, (funcp)execute_2553, (funcp)execute_2554, (funcp)execute_2555, (funcp)execute_2556, (funcp)execute_2557, (funcp)execute_2558, (funcp)execute_2559, (funcp)execute_2560, (funcp)execute_2561, (funcp)execute_2562, (funcp)execute_2563, (funcp)execute_2564, (funcp)execute_2565, (funcp)execute_2566, (funcp)execute_2567, (funcp)execute_2568, (funcp)execute_2569, (funcp)execute_2570, (funcp)execute_2571, (funcp)execute_2572, (funcp)execute_2573, (funcp)execute_2574, (funcp)execute_2575, (funcp)execute_2576, (funcp)execute_2577, (funcp)execute_2578, (funcp)execute_2579, (funcp)execute_2580, (funcp)execute_2581, (funcp)execute_2582, (funcp)execute_2583, (funcp)execute_384, (funcp)vlog_timingcheck_execute_0, (funcp)execute_22, (funcp)execute_387, (funcp)execute_25, (funcp)execute_389, (funcp)execute_390, (funcp)execute_388, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_391, (funcp)execute_392, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_397, (funcp)execute_398, (funcp)execute_399, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_401, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)execute_406, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_1, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_2, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_751, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_752, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_753, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_754, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_755, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_756, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_757, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_758, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_759, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_760, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_761, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_762, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_763, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_764, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_765, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_766, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_767, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_768, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_769, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_770, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_771, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_772, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_773, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_774, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_27, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_28, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_29, (funcp)timing_checker_condition_m_1899c67f_af79f1dc_30, (funcp)execute_425, (funcp)execute_431, (funcp)execute_432, (funcp)execute_433, (funcp)execute_434, (funcp)execute_435, (funcp)execute_436, (funcp)execute_437, (funcp)execute_440, (funcp)execute_441, (funcp)execute_442, (funcp)execute_443, (funcp)execute_195, (funcp)execute_1871, (funcp)execute_1872, (funcp)execute_1873, (funcp)execute_197, (funcp)execute_199, (funcp)execute_200, (funcp)execute_1874, (funcp)execute_1875, (funcp)execute_1876, (funcp)execute_1877, (funcp)execute_1879, (funcp)execute_1880, (funcp)execute_1881, (funcp)execute_1882, (funcp)execute_1883, (funcp)execute_1884, (funcp)execute_1885, (funcp)execute_1886, (funcp)execute_1887, (funcp)execute_1888, (funcp)execute_1890, (funcp)execute_1891, (funcp)execute_1892, (funcp)execute_1893, (funcp)execute_1895, (funcp)execute_1896, (funcp)execute_1897, (funcp)execute_1898, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_775, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_776, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_777, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_778, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_779, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_780, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_781, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_782, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_783, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_784, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_785, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_786, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_787, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_788, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_789, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_790, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_791, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_792, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_793, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_794, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_795, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_796, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_797, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_798, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_799, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_800, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_801, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_802, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_803, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_804, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_805, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_806, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_807, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_808, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_809, (funcp)timing_checker_condition_m_a0cd4192_f4d1fc17_810, (funcp)execute_1925, (funcp)execute_1933, (funcp)execute_1934, (funcp)execute_1935, (funcp)execute_1899, (funcp)execute_204, (funcp)execute_1946, (funcp)execute_1947, (funcp)execute_1948, (funcp)execute_1949, (funcp)execute_1945, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)transaction_46, (funcp)transaction_47, (funcp)transaction_48, (funcp)transaction_49, (funcp)transaction_50, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_53, (funcp)transaction_54, (funcp)transaction_55, (funcp)transaction_56, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_70, (funcp)transaction_71, (funcp)transaction_72, (funcp)transaction_73, (funcp)transaction_74, (funcp)transaction_75, (funcp)transaction_76, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_84, (funcp)transaction_85, (funcp)transaction_86, (funcp)transaction_87, (funcp)transaction_88, (funcp)transaction_89, (funcp)transaction_90, (funcp)transaction_91, (funcp)transaction_92, (funcp)transaction_93, (funcp)transaction_94, (funcp)transaction_95, (funcp)transaction_96, (funcp)transaction_97, (funcp)transaction_98, (funcp)transaction_99, (funcp)transaction_100, (funcp)transaction_101, (funcp)transaction_102, (funcp)transaction_103, (funcp)transaction_104, (funcp)transaction_105, (funcp)transaction_106, (funcp)transaction_107, (funcp)transaction_108, (funcp)transaction_109, (funcp)transaction_110, (funcp)transaction_111, (funcp)transaction_112, (funcp)transaction_113, (funcp)transaction_114, (funcp)transaction_115, (funcp)transaction_116, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_123, (funcp)transaction_124, (funcp)transaction_125, (funcp)transaction_126, (funcp)transaction_127, (funcp)transaction_128, (funcp)transaction_129, (funcp)transaction_130, (funcp)transaction_131, (funcp)transaction_132, (funcp)transaction_133, (funcp)transaction_134, (funcp)transaction_135, (funcp)transaction_136, (funcp)transaction_137, (funcp)transaction_138, (funcp)transaction_139, (funcp)transaction_140, (funcp)transaction_141, (funcp)transaction_142, (funcp)transaction_143, (funcp)transaction_144, (funcp)transaction_145, (funcp)transaction_146, (funcp)transaction_147, (funcp)transaction_148, (funcp)transaction_149, (funcp)transaction_150, (funcp)transaction_151, (funcp)transaction_152, (funcp)transaction_153, (funcp)transaction_154, (funcp)transaction_155, (funcp)transaction_156, (funcp)transaction_157, (funcp)transaction_158, (funcp)transaction_159, (funcp)transaction_160, (funcp)transaction_161, (funcp)transaction_162, (funcp)transaction_163, (funcp)transaction_164, (funcp)transaction_165, (funcp)transaction_166, (funcp)transaction_167, (funcp)transaction_168, (funcp)transaction_169, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_173, (funcp)transaction_174, (funcp)transaction_175, (funcp)transaction_176, (funcp)transaction_177, (funcp)transaction_178, (funcp)transaction_179, (funcp)transaction_180, (funcp)transaction_181, (funcp)transaction_182, (funcp)transaction_183, (funcp)transaction_184, (funcp)transaction_185, (funcp)transaction_186, (funcp)transaction_187, (funcp)transaction_188, (funcp)transaction_189, (funcp)transaction_190, (funcp)transaction_191, (funcp)transaction_192, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_196, (funcp)transaction_197, (funcp)transaction_198, (funcp)transaction_199, (funcp)transaction_200, (funcp)transaction_201, (funcp)transaction_202, (funcp)transaction_203, (funcp)transaction_204, (funcp)transaction_205, (funcp)transaction_206, (funcp)transaction_207, (funcp)transaction_208, (funcp)transaction_209, (funcp)transaction_210, (funcp)transaction_211, (funcp)transaction_212, (funcp)transaction_213, (funcp)transaction_214, (funcp)transaction_215, (funcp)transaction_216, (funcp)transaction_217, (funcp)transaction_218, (funcp)transaction_219, (funcp)transaction_220, (funcp)transaction_221, (funcp)transaction_222, (funcp)transaction_223, (funcp)transaction_224, (funcp)transaction_225, (funcp)transaction_226, (funcp)transaction_227, (funcp)transaction_228, (funcp)transaction_229, (funcp)transaction_230, (funcp)transaction_231, (funcp)transaction_232, (funcp)transaction_233, (funcp)transaction_234, (funcp)transaction_235, (funcp)transaction_236, (funcp)transaction_237, (funcp)transaction_238, (funcp)transaction_239, (funcp)transaction_240, (funcp)transaction_241, (funcp)transaction_242, (funcp)transaction_243, (funcp)transaction_244, (funcp)transaction_245, (funcp)transaction_246, (funcp)transaction_247, (funcp)transaction_248, (funcp)transaction_249, (funcp)transaction_250, (funcp)transaction_251, (funcp)transaction_252, (funcp)transaction_253, (funcp)transaction_254, (funcp)transaction_255, (funcp)transaction_256, (funcp)transaction_257, (funcp)transaction_258, (funcp)transaction_259, (funcp)transaction_260, (funcp)transaction_261, (funcp)transaction_262, (funcp)transaction_263, (funcp)transaction_264, (funcp)transaction_265, (funcp)transaction_266, (funcp)transaction_267, (funcp)transaction_268, (funcp)transaction_269, (funcp)transaction_270, (funcp)transaction_271, (funcp)transaction_272, (funcp)transaction_273, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_324, (funcp)transaction_325, (funcp)transaction_326, (funcp)transaction_327, (funcp)transaction_328, (funcp)transaction_329, (funcp)transaction_330, (funcp)transaction_331, (funcp)transaction_332, (funcp)transaction_333, (funcp)transaction_334, (funcp)transaction_335, (funcp)transaction_336, (funcp)transaction_337, (funcp)transaction_338, (funcp)transaction_339, (funcp)transaction_340, (funcp)transaction_341, (funcp)transaction_342, (funcp)transaction_343, (funcp)transaction_344, (funcp)transaction_345, (funcp)transaction_346, (funcp)transaction_347, (funcp)transaction_348, (funcp)transaction_349, (funcp)transaction_350, (funcp)transaction_351, (funcp)transaction_352, (funcp)transaction_353, (funcp)transaction_354, (funcp)transaction_355, (funcp)transaction_356, (funcp)transaction_357, (funcp)transaction_358, (funcp)transaction_359, (funcp)transaction_360, (funcp)transaction_361, (funcp)transaction_362, (funcp)transaction_363, (funcp)transaction_364, (funcp)transaction_365, (funcp)transaction_366, (funcp)transaction_367, (funcp)transaction_368, (funcp)transaction_369, (funcp)transaction_370, (funcp)transaction_371, (funcp)transaction_372, (funcp)transaction_373, (funcp)transaction_374, (funcp)transaction_375, (funcp)transaction_376, (funcp)transaction_377, (funcp)transaction_378, (funcp)transaction_379, (funcp)transaction_380, (funcp)transaction_381, (funcp)transaction_382, (funcp)transaction_383, (funcp)transaction_384, (funcp)transaction_385, (funcp)transaction_386, (funcp)transaction_387, (funcp)transaction_388, (funcp)transaction_389, (funcp)transaction_390, (funcp)transaction_391, (funcp)transaction_392, (funcp)transaction_393, (funcp)transaction_394, (funcp)transaction_395, (funcp)transaction_396, (funcp)transaction_397, (funcp)transaction_398, (funcp)transaction_399, (funcp)transaction_400, (funcp)transaction_401, (funcp)transaction_402, (funcp)transaction_403, (funcp)transaction_404, (funcp)transaction_405, (funcp)transaction_406, (funcp)transaction_407, (funcp)transaction_408, (funcp)transaction_409, (funcp)transaction_410, (funcp)transaction_411, (funcp)transaction_412, (funcp)transaction_413, (funcp)transaction_414, (funcp)transaction_415, (funcp)transaction_416, (funcp)transaction_417, (funcp)transaction_418, (funcp)transaction_419, (funcp)transaction_420, (funcp)transaction_421, (funcp)transaction_422, (funcp)transaction_423, (funcp)transaction_424, (funcp)transaction_425, (funcp)transaction_426, (funcp)transaction_427, (funcp)transaction_428, (funcp)transaction_429, (funcp)transaction_430, (funcp)transaction_431, (funcp)transaction_432, (funcp)transaction_433, (funcp)transaction_434, (funcp)transaction_435, (funcp)transaction_436, (funcp)transaction_437, (funcp)transaction_438, (funcp)transaction_439, (funcp)transaction_440, (funcp)transaction_441, (funcp)transaction_442, (funcp)transaction_443, (funcp)transaction_444, (funcp)transaction_445, (funcp)transaction_447, (funcp)transaction_448, (funcp)transaction_453, (funcp)transaction_454, (funcp)transaction_461, (funcp)transaction_462, (funcp)transaction_467, (funcp)transaction_468, (funcp)transaction_473, (funcp)transaction_474, (funcp)transaction_480, (funcp)transaction_481, (funcp)transaction_486, (funcp)transaction_487, (funcp)transaction_491, (funcp)transaction_492, (funcp)transaction_493, (funcp)transaction_529, (funcp)transaction_530, (funcp)transaction_531, (funcp)transaction_625, (funcp)transaction_626, (funcp)transaction_749, (funcp)transaction_750, (funcp)transaction_902, (funcp)transaction_903, (funcp)transaction_1026, (funcp)transaction_1027, (funcp)transaction_1150, (funcp)transaction_1151, (funcp)transaction_1332, (funcp)transaction_1333, (funcp)transaction_1456, (funcp)transaction_1457, (funcp)transaction_1530, (funcp)transaction_1531, (funcp)transaction_1532, (funcp)transaction_1551, (funcp)transaction_1552, (funcp)transaction_1601, (funcp)transaction_1602, (funcp)transaction_1603, (funcp)transaction_1616, (funcp)transaction_1617, (funcp)transaction_1618, (funcp)transaction_1661, (funcp)transaction_1662, (funcp)transaction_1663, (funcp)transaction_1676, (funcp)transaction_1677, (funcp)transaction_1714, (funcp)transaction_1715, (funcp)transaction_1716, (funcp)transaction_1771, (funcp)transaction_1772, (funcp)transaction_1773, (funcp)transaction_509, (funcp)transaction_547, (funcp)transaction_576, (funcp)transaction_605, (funcp)transaction_642, (funcp)transaction_671, (funcp)transaction_700, (funcp)transaction_729, (funcp)transaction_766, (funcp)transaction_795, (funcp)transaction_824, (funcp)transaction_853, (funcp)transaction_882, (funcp)transaction_919, (funcp)transaction_948, (funcp)transaction_977, (funcp)transaction_1006, (funcp)transaction_1043, (funcp)transaction_1072, (funcp)transaction_1101, (funcp)transaction_1130, (funcp)transaction_1167, (funcp)transaction_1196, (funcp)transaction_1225, (funcp)transaction_1254, (funcp)transaction_1283, (funcp)transaction_1312, (funcp)transaction_1349, (funcp)transaction_1378, (funcp)transaction_1407, (funcp)transaction_1436, (funcp)transaction_1473}; +const int NumRelocateId= 900; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/pwm_test_db_time_synth/xsim.reloc", (void **)funcTab, 900); + iki_vhdl_file_variable_register(dp + 1321952); + iki_vhdl_file_variable_register(dp + 1322008); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/pwm_test_db_time_synth/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1327032, dp + 1327488, 0, 0, 0, 0, 1, 1); + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/pwm_test_db_time_synth/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/pwm_test_db_time_synth/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/pwm_test_db_time_synth/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/pwm_test_db_time_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.win64.obj b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.win64.obj new file mode 100644 index 0000000..4ab6d50 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/obj/xsim_1.win64.obj differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.dbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.dbg new file mode 100644 index 0000000..b4a8dfc Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.dbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.mem b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.mem new file mode 100644 index 0000000..99f00d2 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.mem differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.reloc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.reloc new file mode 100644 index 0000000..66264ce Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.reloc differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rlx new file mode 100644 index 0000000..6795fbb --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 4084566433590232689 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl" , + buildDate : "Oct 19 2021" , + buildTime : "03:16:22" , + linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_time_synth/xsimk.exe\" \"xsim.dir/pwm_test_db_time_synth/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_time_synth/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rtti b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rtti new file mode 100644 index 0000000..4168c98 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.rtti differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.svtype b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.svtype new file mode 100644 index 0000000..5315270 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.svtype differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.type b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.type new file mode 100644 index 0000000..4185d6e Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.type differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.xdbg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.xdbg new file mode 100644 index 0000000..1ecabf7 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsim.xdbg differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimSettings.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimSettings.ini new file mode 100644 index 0000000..fabf023 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=210 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=210 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimcrash.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimk.exe b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimk.exe new file mode 100644 index 0000000..dde0172 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimk.exe differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimkernel.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimkernel.log new file mode 100644 index 0000000..104868a --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/pwm_test_db_time_synth/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/pwm_test_db_time_synth/xsimk.exe -simmode gui -wdb pwm_test_db_time_synth.wdb -simrunnum 0 -socket 49950 +Design successfully loaded +Design Loading Memory Usage: 10480 KB (Peak: 10480 KB) +Design Loading CPU Usage: 31 ms +Simulation completed +Simulation Memory Usage: 20776 KB (Peak: 20776 KB) +Simulation CPU Usage: 461827 ms diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb new file mode 100644 index 0000000..755c375 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb new file mode 100644 index 0000000..c12c6f1 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test.sdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb new file mode 100644 index 0000000..7f2244b Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..302f1e1 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,6 @@ +0.7 +2020.2 +Oct 19 2021 +03:16:22 +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v,1647460459,verilog,,,,glbl;pwm_test,,,,,,,, +C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1647459068,vhdl,,,,pwm_test_db,,,,,,,, diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.ini b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.log new file mode 100644 index 0000000..a0e1ca7 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.pb new file mode 100644 index 0000000..f4c8b8e Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvhdl.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.log new file mode 100644 index 0000000..086a5ad --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.log @@ -0,0 +1,3 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module pwm_test +INFO: [VRFC 10-311] analyzing module glbl diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.pb b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.pb new file mode 100644 index 0000000..465ffe8 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/synth/timing/xsim/xvlog.pb differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc new file mode 100644 index 0000000..cc4d01f --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc @@ -0,0 +1,150 @@ +## This file is a general .xdc for the Cora Z7-10 Rev. B +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## PL System Clock +set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk +#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set + +## RGB LEDs +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_0_35 Sch=led1_b +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g +#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r + +## Buttons +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1] + +## Pmod Header JA +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L17P_T2_34 Sch=ja_p[1] +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L17N_T2_34 Sch=ja_n[1] +#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L7P_T1_34 Sch=ja_p[2] +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L7N_T1_34 Sch=ja_n[2] +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4] + +## Pmod Header JB +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1] +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1] +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2] +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3] +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4] + +## Crypto SDA +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; + +## Dedicated Analog Inputs +#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p +#set_property -dict { PACKAGE_PIN L10 IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n + +## ChipKit Outer Analog Header - as Single-Ended Analog Inputs +## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O. +## WARNING: Do not use both sets of constraints at the same time! +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1] +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2] +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3] +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3] +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4] +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4] +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5] +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5] +## ChipKit Outer Analog Header - as Digital I/O +## NOTE: The following constraints should be used when using these ports as digital I/O. +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[0] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L10N_T1_AD11N_35 Sch=ck_a[1] +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L12P_T1_MRCC_35 Sch=ck_a[2] +#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[3] +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=ck_a[4] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L6P_T0_34 Sch=ck_a[5] + +## ChipKit Inner Analog Header - as Differential Analog Inputs +## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O. +## WARNING: Do not use both sets of constraints at the same time! +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0] +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0] +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12] +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12] +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8] +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8] +## ChipKit Inner Analog Header - as Digital I/O +## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O. +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0] +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0] +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12] +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12] +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8] +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8] + +## ChipKit Outer Digital Header +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L5P_T0_34 Sch=ck_io[2] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L5N_T0_34 Sch=ck_io[3] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L21P_T3_DQS_34 Sch=ck_io[4] +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L21N_T3_DQS_34 Sch=ck_io[5] +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19N_T3_VREF_34 Sch=ck_io[6] +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L6N_T0_VREF_34 Sch=ck_io[7] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L13P_T2_MRCC_34 Sch=ck_io[8] +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L11N_T1_SRCC_34 Sch=ck_io[10] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L12N_T1_MRCC_35 Sch=ck_io[11] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12] +#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L19N_T3_VREF_35 Sch=ck_io[13] + +## ChipKit Inner Digital Header +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19P_T3_34 Sch=ck_io[26] +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L2N_T0_34 Sch=ck_io[27] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[28] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L10P_T1_34 Sch=ck_io[29] +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L9P_T1_DQS_34 Sch=ck_io[30] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L9N_T1_DQS_34 Sch=ck_io[31] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L20P_T3_34 Sch=ck_io[32] +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_34 Sch=ck_io[33] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L23N_T3_34 Sch=ck_io[34] +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L23P_T3_34 Sch=ck_io[35] +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_AD10P_35 Sch=ck_io[36] +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L11N_T1_SRCC_35 Sch=ck_io[37] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L13N_T2_MRCC_35 Sch=ck_io[38] +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=ck_io[39] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_35 Sch=ck_io[40] +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9N_T1_DQS_AD3N_35 Sch=ck_io[41] + +## ChipKit SPI +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss + +## ChipKit I2C +#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda + +##Misc. ChipKit signals +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L7N_T1_AD2N_35 Sch=ck_ioa + +## User Digital I/O Header J1 +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[1] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=user_dio[1] +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[2] }]; #IO_L7P_T1_AD2P_35 Sch=user_dio[2] +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[3] }]; #IO_L14P_T2_SRCC_34 Sch=user_dio[3] +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[4] }]; #IO_L14N_T2_SRCC_34 Sch=user_dio[4] +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[5] }]; #IO_L13N_T2_MRCC_34 Sch=user_dio[5] +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[6] }]; #IO_0_34 Sch=user_dio[6] +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[7] }]; #IO_L15P_T2_DQS_34 Sch=user_dio[7] +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[8] }]; #IO_25_34 Sch=user_dio[8] +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[9] }]; #IO_L15N_T2_DQS_34 Sch=user_dio[9] +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[10] }]; #IO_L16P_T2_34 Sch=user_dio[10] +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[11] }]; #IO_L16N_T2_34 Sch=user_dio[11] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[12] }]; #IO_L10P_T1_AD11P_35 Sch=user_dio[12] diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd new file mode 100644 index 0000000..dc07118 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd @@ -0,0 +1,111 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16.03.2022 20:07:22 +-- Design Name: +-- Module Name: pwm_test_db - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity pwm_test_db is +-- Port ( ); +end pwm_test_db; + +architecture Behavioral of pwm_test_db is + +component regler is + Port ( clk : in STD_LOGIC; --Clk -> Gibt Abtastzeit vor + w : in integer := 0; --Sollwert + y : in integer := 0; --Istwert + u : inout integer := 0); --Stellgöße +end component; + +component pt1 is + Port ( clk : in STD_LOGIC; + u : in integer; + y : inout integer); +end component; + +signal clk : std_logic := '0'; +signal clk_100 : std_logic := '0'; + +signal w : integer := 1000000; +signal u : integer := 0; +signal y : integer := 0; +signal cnt : integer := 0; +signal risingEdge : std_logic := '0'; + +begin + +uut_regler: regler PORT MAP ( + clk => clk, + w => w, + y => y, + u => u +); + +uut_pt1: pt1 PORT MAP ( + clk => clk, + u => u, + y => y +); + +--generate clock +clk <= not clk after 5 us; + + +process +begin + w <= 1000000; + +-- if rising_edge(clk) and ( cnt >= 100) then +-- clk_100 <= not clk_100; +-- cnt <= 0; +-- end if; + + if clk = '1' and risingEdge = '0' then + cnt <= cnt+1; + risingEdge <= '1'; + clk_100 <= '0'; + end if; + + if clk = '0' then + risingEdge <= '0'; + end if; + + if cnt >= 99 then + clk_100 <= '1'; + cnt <= 0; + end if; + + wait for 1 us; +-- cnt <= cnt+1; + +end process; + + +end Behavioral; diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd new file mode 100644 index 0000000..bbc5a75 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd @@ -0,0 +1,13 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x0", + "gen_directory": "../../../../Coraz7_Test.gen/sources_1/bd/IO_Test", + "name": "IO_Test", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2021.2" + }, + "design_tree": {} + } +} \ No newline at end of file diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/IO_Test/ui/bd_316ac62b.ui b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/IO_Test/ui/bd_316ac62b.ui new file mode 100644 index 0000000..b6d7bc6 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/IO_Test/ui/bd_316ac62b.ui @@ -0,0 +1,12 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-600,-236", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS +# -string -flagsOSRD +levelinfo -pg 1 0 10 +pagesize -pg 1 -db -bbox -sgen 0 0 10 10 +" +} + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd new file mode 100644 index 0000000..f4a0235 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd @@ -0,0 +1,13 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x0", + "gen_directory": "../../../../Coraz7_Test.gen/sources_1/bd/design_1", + "name": "design_1", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2021.2" + }, + "design_tree": {} + } +} \ No newline at end of file diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/IO_Test.v b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/IO_Test.v new file mode 100644 index 0000000..402d187 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/IO_Test.v @@ -0,0 +1,27 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16.03.2022 18:50:02 +// Design Name: +// Module Name: IO_Test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module IO_Test( + input clk, + output led + ); +endmodule diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd new file mode 100644 index 0000000..1e754df --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd @@ -0,0 +1,62 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/25/2022 01:45:24 PM +-- Design Name: +-- Module Name: pt1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity pt1 is + Port ( + clk : in STD_LOGIC; + u : in integer := 0; + y : inout integer := 0); -- muss vielleicht initalisiert werden vorher!? +end pt1; + +architecture Behavioral of pt1 is + +signal stepWidth : integer := 10000; -- in ns -> 10 us später berechnet aus Clk und Prescaler + +-- Konstanten Streckenparameter +signal a : integer := 1; +signal k : integer := 2; + + +-- signal u : integer := 100000; -- Eingangswert Strecke jetzt u aus port +-- signal x : integer := 0; -- Ausgangssignal Strecke -> Stellgröße jetzt y aus port + +begin + +process(clk) + begin + if rising_edge(clk) then + y <= y + stepWidth*(k*u-a*y)/1000; -- durch 1000 wg. milisekunden abtastzeit + end if; + +end process; +end Behavioral; diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd new file mode 100644 index 0000000..74dc924 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd @@ -0,0 +1,105 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16.03.2022 19:12:30 +-- Design Name: +-- Module Name: pwm_test - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.MATH_REAL.ALL; +--use IEEE.float_pkg.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity regler is + Port ( clk : in STD_LOGIC; --Clk -> Gibt abtastzeit vor + w : in integer := 0; --Sollwert + y : in integer := 0; --Istwert + u : inout integer := 0); --Stellgöße +end regler; + +architecture Behavioral of regler is + + +--signal stepWidth : integer := 1; -- 10 us später berechnet aus Clk und Prescaler + + +-- Parameter aus Sprungantwort etc. +signal KR : integer := 1; -- Verstärkung +signal T : integer := 1; -- Abtastzeit in ns = 1ms = 1000000ns +signal TV : integer := 0; -- Vorhaltezeit für Differenzierer interesannt +signal TN : integer := 10; -- Nachstellzeit + +-- Konstanten Reglerparameter +--signal a1 : integer ; +--signal b0 : integer; +--signal b1 : integer; +--signal b2 : integer; + +signal a1 : integer := 1; +signal b0 : integer := KR*(1+TV/T); +signal b1 : integer := -KR *(1 - T / TN + 2 * TV / T ); +signal b2 : integer := KR * TV/T; + + +--interne Signale signal +--signal u_k1 : integer := 0; -- = uk-1 = u (wurde nicht geändert) +--signal e_k : integer := 0; -- aktuelle Reglerdiffferenz +signal e_k1 : integer := 0; -- letzte "" +signal e_k2 : integer := 0; -- vorletzte "" + + +-- signal u : integer := 100000; -- Eingangswert Strecke + +--signal x : integer := 0; -- Ausgangssignal Strecke -> Stellgröße + +begin + + +process(clk) + variable e_k : integer; + + begin + + if rising_edge(clk) then + + -- Konstanten Reglerparameter +-- a1 <= 1; +-- b0 <= KR*(1+TV/T); +-- b1 <= -KR *(1 - T / TN + 2 * TV / T ); +-- b2 <= KR * TV/T; + + --u <= e; -- Regler überbrücken! + e_k := w - y; --Reglerdifferenzbilden + u <= (a1*u+b0*e_k+b1*e_k1+b2*e_k2)/1000; --Stellgröße u berechnen + e_k2 <= e_k1; + e_k1 <= e_k; + end if; + +end process; + +--test + +end Behavioral; diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp new file mode 100644 index 0000000..bd4c7e0 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp new file mode 100644 index 0000000..2645c57 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr new file mode 100644 index 0000000..e0954f5 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr @@ -0,0 +1,268 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/hs_err_pid1564.dmp b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/hs_err_pid1564.dmp new file mode 100644 index 0000000..614a0a2 Binary files /dev/null and b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/hs_err_pid1564.dmp differ diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/hs_err_pid1564.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/hs_err_pid1564.log new file mode 100644 index 0000000..ea7dd1e --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/hs_err_pid1564.log @@ -0,0 +1,5 @@ +# +# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION) +# +Stack: +no stack trace available, please use hs_err_.dmp instead. diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg new file mode 100644 index 0000000..bd2d9f5 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + clk + clk + + + u + u + STYLE_ANALOG + 100 + + + y + y + STYLE_ANALOG + ANALOG_YRANGETYPE_AUTO + 2951310000.000000 + 3249430000.000000 + #00FF00 + true + 150 + SIGNEDDECRADIX + ANALOG_INTERPOLATION_LINEAR + ANALOG_OFFSCALE_HIDE + 0.000000 + + + clk_100 + clk_100 + + + cnt + cnt + + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou new file mode 100644 index 0000000..950778c --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou @@ -0,0 +1,40 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Wed May 11 13:29:39 2022 +# Process ID: 16520 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13076 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +r +update_compile_order -fileset sources_1 +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +close_sim +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +close_sim +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +close_sim +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +close_sim diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log new file mode 100644 index 0000000..2523552 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log @@ -0,0 +1,356 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Wed May 11 13:29:39 2022 +# Process ID: 16520 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13076 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. +Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' +' +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. +INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. +open_project: Time (s): cpu = 00:00:43 ; elapsed = 00:00:21 . Memory (MB): peak = 1254.160 ; gain = 0.000 +update_compile_order -fileset sources_1 +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [USF-XSim-69] 'compile' step finished in '3' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1254.160 ; gain = 0.000 +INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 s +xsim: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1254.160 ; gain = 0.000 +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 s +launch_simulation: Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1254.160 ; gain = 0.000 +reset_run synth_1 +INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp +WARNING: [Vivado 12-1017] Problems encountered: +1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 + +launch_runs synth_1 -jobs 6 +[Wed May 11 14:33:13 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [USF-XSim-69] 'compile' step finished in '3' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 s +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 s +launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1254.160 ; gain = 0.000 +reset_run synth_1 +INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp +WARNING: [Vivado 12-1017] Problems encountered: +1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 + +launch_runs synth_1 -jobs 6 +[Wed May 11 14:37:39 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' +INFO: [USF-XSim-69] 'compile' step finished in '3' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 s +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 s +launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1254.160 ; gain = 0.000 +reset_run synth_1 +INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp +WARNING: [Vivado 12-1017] Problems encountered: +1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 + +launch_runs synth_1 -jobs 6 +[Wed May 11 14:51:19 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [USF-XSim-69] 'compile' step finished in '3' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 s +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 s +launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 1254.160 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +exit +INFO: [Common 17-206] Exiting Vivado at Wed May 11 14:59:27 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_10280.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_10280.backup.jou new file mode 100644 index 0000000..d00703b --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_10280.backup.jou @@ -0,0 +1,42 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Tue Mar 29 10:43:14 2022 +# Process ID: 10280 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18072 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr +update_compile_order -fileset sources_1 +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +open_run synth_1 -name synth_1 +set_property IOSTANDARD LVCMOS33 [get_ports [list clk]] +save_constraints +launch_runs impl_1 -jobs 6 +wait_on_run impl_1 +launch_runs impl_1 -to_step write_bitstream -jobs 6 +wait_on_run impl_1 +close_design +open_run impl_1 +open_hw_manager +connect_hw_server -allow_non_jtag +open_hw_target +set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1] +current_hw_device [get_hw_devices xc7z010_1] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0] +set_property PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1] +program_hw_devices [get_hw_devices xc7z010_1] +refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0] +close_sim diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_10280.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_10280.backup.log new file mode 100644 index 0000000..8b0a5f0 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_10280.backup.log @@ -0,0 +1,245 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Tue Mar 29 10:43:14 2022 +# Process ID: 10280 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18072 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. +open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 1251.211 ; gain = 0.000 +update_compile_order -fileset sources_1 +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test' +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.pwm_test [pwm_test_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 ms +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 ms +launch_simulation: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1251.211 ; gain = 0.000 +reset_run synth_1 +INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp +WARNING: [Vivado 12-1017] Problems encountered: +1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1 + +launch_runs synth_1 -jobs 6 +[Tue Mar 29 11:00:35 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log +open_run synth_1 -name synth_1 +Design is defaulting to impl run constrset: constrs_1 +Design is defaulting to synth run part: xc7z010clg400-1 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1532.922 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2021.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1627.844 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +open_run: Time (s): cpu = 00:00:16 ; elapsed = 00:00:08 . Memory (MB): peak = 1746.418 ; gain = 495.207 +set_property IOSTANDARD LVCMOS33 [get_ports [list clk]] +save_constraints +launch_runs impl_1 -jobs 6 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2221.637 ; gain = 0.000 +[Tue Mar 29 11:09:22 2022] Launched impl_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log +launch_runs impl_1 -to_step write_bitstream -jobs 6 +[Tue Mar 29 11:10:24 2022] Launched impl_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log +close_design +open_run impl_1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2222.562 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2021.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 2253.348 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 2253.348 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2253.348 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +open_hw_manager +connect_hw_server -allow_non_jtag +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2021.2 + **** Build date : Oct 19 2021 at 03:13:30 + ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2021.2.0 + ****** Build date : Sep 27 2021-23:44:20 + **** Build number : 2021.2.1632779060 + ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. + + + +connect_hw_server: Time (s): cpu = 00:00:08 ; elapsed = 00:00:29 . Memory (MB): peak = 2403.906 ; gain = 14.949 +open_hw_target +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210370A9326CA +open_hw_target: Time (s): cpu = 00:00:22 ; elapsed = 00:00:58 . Memory (MB): peak = 4174.812 ; gain = 1770.906 +set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1] +current_hw_device [get_hw_devices xc7z010_1] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0] +INFO: [Labtools 27-1435] Device xc7z010 (JTAG device index = 1) is not programmed (DONE status = 0). +refresh_hw_device: Time (s): cpu = 00:00:06 ; elapsed = 00:00:19 . Memory (MB): peak = 4201.266 ; gain = 24.125 +set_property PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1] +program_hw_devices [get_hw_devices xc7z010_1] +INFO: [Labtools 27-3164] End of startup status: HIGH +program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 4201.266 ; gain = 0.000 +refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0] +INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it. +refresh_hw_device: Time (s): cpu = 00:00:07 ; elapsed = 00:00:26 . Memory (MB): peak = 4201.598 ; gain = 0.332 +ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210370A9326CA +close_sim +INFO: [Simtcl 6-16] Simulation closed +exit +INFO: [Common 17-206] Exiting Vivado at Tue Mar 29 12:45:07 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_11748.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_11748.backup.jou new file mode 100644 index 0000000..51c1cfa --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_11748.backup.jou @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Mon May 2 13:46:02 2022 +# Process ID: 11748 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6660 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +update_compile_order -fileset sources_1 +reset_run synth_1 +launch_runs synth_1 -jobs 6 diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_11748.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_11748.backup.log new file mode 100644 index 0000000..e8a42d0 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_11748.backup.log @@ -0,0 +1,84 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Mon May 2 13:46:02 2022 +# Process ID: 11748 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6660 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. +Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +INFO: [Project 1-313] Project file moved from 'C:/Users/jt/Downloads/FPGA_Projekt/StreckeSim_PT1_working/StreckeSim' since last save. +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/jt/Downloads/FPGA_Projekt/StreckeSim_PT1_working/StreckeSim/Coraz7_Test.gen/sources_1'. +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. +Scanning sources... +Finished scanning sources +INFO: [Project 1-1877] Auto incremental dir location 'C:/Users/jt/Downloads/FPGA_Projekt/StreckeSim/StreckeSim/Coraz7_Test.srcs/utils_1/imports/impl_1' of run 'impl_1' is not writable, setting it to default location 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/impl_1'. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. +open_project: Time (s): cpu = 00:00:38 ; elapsed = 00:00:18 . Memory (MB): peak = 1253.570 ; gain = 0.000 +update_compile_order -fileset sources_1 +WARNING: [Common 17-9] Error reading message records. +WARNING: [Common 17-9] Error reading message records. +WARNING: [Common 17-9] Error reading message records. +exit +INFO: [Common 17-206] Exiting Vivado at Mon May 2 13:48:24 2022... +rive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp +WARNING: [Vivado 12-1017] Problems encountered: +1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 + +launch_runs synth_1 -jobs 6 +[Mon May 2 13:46:53 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_14848.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_14848.backup.jou new file mode 100644 index 0000000..c11aaef --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_14848.backup.jou @@ -0,0 +1,34 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Wed May 4 17:59:18 2022 +# Process ID: 14848 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18128 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +update_compile_order -fileset sources_1 +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +close_sim diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_14848.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_14848.backup.log new file mode 100644 index 0000000..3462643 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_14848.backup.log @@ -0,0 +1,170 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Wed May 4 17:59:18 2022 +# Process ID: 14848 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18128 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. +Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' since last save. +INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. +INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. +open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 1576.867 ; gain = 0.000 +update_compile_order -fileset sources_1 +reset_run synth_1 +INFO: [Project 1-1160] Copying file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp to C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1 and adding it to utils fileset +launch_runs synth_1 -jobs 6 +CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:58] +[Wed May 4 18:03:05 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 6 +CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:58] +[Wed May 4 18:04:54 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 6 +CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:83] +[Wed May 4 18:10:10 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +reset_run synth_1 +WARNING: [Vivado 12-1017] Problems encountered: +1. PID not specified + +launch_runs synth_1 -jobs 6 +CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:83] +[Wed May 4 18:10:19 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 6 +[Wed May 4 18:26:30 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pt1' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] +WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 s +xsim: Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 1576.867 ; gain = 0.000 +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 s +launch_simulation: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1576.867 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +exit +INFO: [Common 17-206] Exiting Vivado at Wed May 4 19:29:14 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.jou new file mode 100644 index 0000000..4a1ebb9 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Wed May 4 17:41:44 2022 +# Process ID: 17388 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22812 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#-----------------------------------------------------------sstart_guiopen_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +update_compile_order -fileset sources_1 + diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.log new file mode 100644 index 0000000..be43c05 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.log @@ -0,0 +1,67 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Wed May 4 17:41:44 2022 +# Process ID: 17388 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22812 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#-----------------------------------------------------------sstart_guiopen_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. +Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' +WWARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not availableIINFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' since last save.INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. +IINFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +IINFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.open_project: Time (s): cpu = 00:00:36 ; elapsed = 00:00:19 . Memory (MB): peak = 1250.172 ; gain = 0.000 +update_compile_order -fileset sources_1 +exit +INFO: [Common 17-206] Exiting Vivado at Wed May 4 17:58:54 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.jou b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.jou new file mode 100644 index 0000000..a8fcf30 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.jou @@ -0,0 +1,43 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Mon May 2 13:48:39 2022 +# Process ID: 3460 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9928 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +update_compile_order -fileset sources_1 +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 +add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 61 +remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 61 +remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 +add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 +remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 +add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +close_sim +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +reset_run synth_1 +launch_runs synth_1 -jobs 6 +wait_on_run synth_1 +close_sim +launch_simulation +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +close_sim diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.log b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.log new file mode 100644 index 0000000..85d3d27 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.log @@ -0,0 +1,295 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Mon May 2 13:48:39 2022 +# Process ID: 3460 +# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9928 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr +# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log +# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou +# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB +#----------------------------------------------------------- +start_gui +open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. +Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. +INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. +open_project: Time (s): cpu = 00:00:31 ; elapsed = 00:00:12 . Memory (MB): peak = 1254.516 ; gain = 0.000 +update_compile_order -fileset sources_1 +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pt1' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 s +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 s +launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1271.582 ; gain = 17.066 +reset_run synth_1 +INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp +WARNING: [Vivado 12-1017] Problems encountered: +1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 + +launch_runs synth_1 -jobs 6 +[Mon May 2 13:54:34 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 +add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 61 +remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 61 +remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 +add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 +remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 +add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 +reset_run synth_1 +INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp +WARNING: [Vivado 12-1017] Problems encountered: +1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 + +launch_runs synth_1 -jobs 6 +[Mon May 2 14:46:17 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +WARNING: [Simulator 45-24] Previous breakpoint at line 62 in file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd' not restored because it is no longer a breakable line. +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 s +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 s +launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1271.582 ; gain = 0.000 +reset_run synth_1 +INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp +WARNING: [Vivado 12-1017] Problems encountered: +1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 + +launch_runs synth_1 -jobs 6 +[Mon May 2 14:59:49 2022] Launched synth_1... +Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' +WARNING: [Vivado 12-12986] Compiled library path does not exist: '' +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'pt1' +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'regler' +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" +Vivado Simulator v2021.2 +Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] +Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] +Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db +Built simulation snapshot pwm_test_db_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg +source pwm_test_db.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 5 s +INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 5 s +launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1271.582 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +exit +INFO: [Common 17-206] Exiting Vivado at Mon May 2 15:30:20 2022... diff --git a/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid17388.str b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid17388.str new file mode 100644 index 0000000..f37a284 --- /dev/null +++ b/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid17388.str @@ -0,0 +1,126 @@ +/* + +Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2] +SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021 +IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021 + +Process ID (PID): 17388 +License: Customer +Mode: GUI Mode + +Current time: Wed May 04 17:42:02 CEST 2022 +Time zone: Central European Standard Time (Europe/Berlin) + +OS: Windows 10 +OS Version: 10.0 +OS Architecture: amd64 +Available processors (cores): 12 + +Screen size: 1920x1080 +Screen resolution (DPI): 100 +Available screens: 2 +Default font: family=Dialog,name=Dialog,style=plain,size=12 +Scale size: 12 + +Java version: 11.0.11 64-bit +Java home: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9 +Java executable: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe +Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m] +Java initial memory (-Xms): 256 MB +Java maximum memory (-Xmx): 3 GB + + +User name: Felix +User home directory: C:/Users/Felix +User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim +User country: DE +User language: de +User locale: de_DE + +RDI_BASEROOT: C:/Xilinx/Vivado +HDI_APPROOT: C:/Xilinx/Vivado/2021.2 +RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data +RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin + +Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml +Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/ +Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts +PlanAhead jar file: C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar +Vivado log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log +Vivado journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou +Engine tmp dir: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-17388-DESKTOP-PAACOM8 + +Xilinx Environment Variables +---------------------------- +TWINCATSDK: C:\TwinCAT\3.1\SDK\ +XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE +XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE +XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2 +XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2 +XILINX_VIVADO: C:/Xilinx/Vivado/2021.2 +XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2 + + +GUI allocated memory: 256 MB +GUI max memory: 3,072 MB +Engine allocated memory: 1,306 MB + +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. + +*/ + +// TclEventType: START_GUI +// Tcl Message: start_gui +// TclEventType: PROJECT_OPEN_DIALOG +// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: FLOW_ADDED +// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' +// HMemoryUtils.trashcanNow. Engine heap size: 1,306 MB. GUI used memory: 55 MB. Current time: 5/4/22, 5:42:03 PM CEST +// TclEventType: MSGMGR_MOVEMSG +// TclEventType: FILE_SET_CHANGE +// TclEventType: FILE_SET_NEW +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_CURRENT +// TclEventType: PROJECT_DASHBOARD_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_NEW +// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr +// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' +// Tcl Message: Scanning sources... Finished scanning sources +// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified +// TclEventType: PROJECT_NEW +// [GUI Memory]: 77 MB (+77767kb) [00:00:24] +// [Engine Memory]: 1,306 MB (+1218476kb) [00:00:24] +// WARNING: HEventQueue.dispatchEvent() is taking 4570 ms. +// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. +// [GUI Memory]: 103 MB (+23495kb) [00:00:28] +// Tcl Message: open_project: Time (s): cpu = 00:00:39 ; elapsed = 00:00:17 . Memory (MB): peak = 1578.641 ; gain = 0.000 +// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1 +dismissDialog("Open Project"); // bA +// Tcl Message: update_compile_order -fileset sources_1 +// Elapsed time: 105 seconds +selectTreeTable(PAResourceEtoH.ExpRunTreePanel_EXP_RUN_TREE_TABLE, "synth_1 ; constrs_1 ; Synthesis Out-of-date ; ; ; ; ; ; ; ; ; 671 ; 63 ; 0.0 ; 0 ; 0 ; Mon May 02 14:59:56 CEST 2022 ; 00:00:43 ; Vivado Synthesis Defaults (Vivado Synthesis 2021) ; Vivado Synthesis Default Reports (Vivado Synthesis 2021) ; xc7z010clg400-1 ; Vivado Synthesis Defaults", 0, (String) null, 10, true); // az - Node +// PAPropertyPanels.initPanels (synth_1) elapsed time: 0.5s +// [GUI Memory]: 116 MB (+8558kb) [00:02:33] +// Elapsed time: 591 seconds +expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1); // D +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, pwm_test.vhd]", 2, false); // D +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, pwm_test.vhd]", 2, false, false, false, false, false, true); // D - Double Click +// HMemoryUtils.trashcanNow. Engine heap size: 1,306 MB. GUI used memory: 65 MB. Current time: 5/4/22, 5:54:26 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 1,306 MB. GUI used memory: 65 MB. Current time: 5/4/22, 5:54:56 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 1,306 MB. GUI used memory: 65 MB. Current time: 5/4/22, 5:55:26 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 1,306 MB. GUI used memory: 65 MB. Current time: 5/4/22, 5:55:56 PM CEST