/* Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2] SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021 IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021 Process ID (PID): 10504 License: Customer Mode: GUI Mode Current time: Mon May 23 20:31:24 CEST 2022 Time zone: Central European Standard Time (Europe/Berlin) OS: Windows 10 OS Version: 10.0 OS Architecture: amd64 Available processors (cores): 12 Screen size: 1920x1080 Screen resolution (DPI): 100 Available screens: 2 Default font: family=Dialog,name=Dialog,style=plain,size=12 Scale size: 12 Java version: 11.0.11 64-bit Java home: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9 Java executable: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m] Java initial memory (-Xms): 256 MB Java maximum memory (-Xmx): 3 GB User name: Felix User home directory: C:/Users/Felix User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim User country: DE User language: de User locale: de_DE RDI_BASEROOT: C:/Xilinx/Vivado HDI_APPROOT: C:/Xilinx/Vivado/2021.2 RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/ Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts PlanAhead jar file: C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar Vivado log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log Vivado journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou Engine tmp dir: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-10504-DESKTOP-PAACOM8 Xilinx Environment Variables ---------------------------- TWINCATSDK: C:\TwinCAT\3.1\SDK\ XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2 XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2 XILINX_VIVADO: C:/Xilinx/Vivado/2021.2 XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2 GUI allocated memory: 319 MB GUI max memory: 3,072 MB Engine allocated memory: 1,307 MB Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. */ // TclEventType: START_GUI // Tcl Message: start_gui // TclEventType: PROJECT_OPEN_DIALOG // Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 // TclEventType: DEBUG_PROBE_SET_CHANGE // TclEventType: FLOW_ADDED // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 55 MB. Current time: 5/23/22, 8:31:25 PM CEST // TclEventType: MSGMGR_MOVEMSG // TclEventType: FILE_SET_CHANGE // TclEventType: FILE_SET_NEW // TclEventType: RUN_CURRENT // TclEventType: PROJECT_DASHBOARD_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_NEW // [GUI Memory]: 70 MB (+71283kb) [00:00:14] // [Engine Memory]: 1,307 MB (+1219381kb) [00:00:14] // [GUI Memory]: 109 MB (+37180kb) [00:00:15] // WARNING: HEventQueue.dispatchEvent() is taking 2465 ms. // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' // Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. // Tcl Message: Scanning sources... Finished scanning sources // Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. // [GUI Memory]: 117 MB (+2679kb) [00:00:16] // Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1 // Tcl Message: open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000 dismissDialog("Open Project"); // bA // Tcl Message: update_compile_order -fileset sources_1