/* Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2] SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021 IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021 Process ID (PID): 3672 License: Customer Mode: GUI Mode Current time: Fri May 13 11:28:40 CEST 2022 Time zone: Central European Standard Time (Europe/Berlin) OS: Windows 10 OS Version: 10.0 OS Architecture: amd64 Available processors (cores): 12 Screen size: 1920x1080 Screen resolution (DPI): 100 Available screens: 2 Default font: family=Dialog,name=Dialog,style=plain,size=12 Scale size: 12 Java version: 11.0.11 64-bit Java home: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9 Java executable: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m] Java initial memory (-Xms): 256 MB Java maximum memory (-Xmx): 3 GB User name: Felix User home directory: C:/Users/Felix User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim User country: DE User language: de User locale: de_DE RDI_BASEROOT: C:/Xilinx/Vivado HDI_APPROOT: C:/Xilinx/Vivado/2021.2 RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/ Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts PlanAhead jar file: C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar Vivado log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log Vivado journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou Engine tmp dir: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-3672-DESKTOP-PAACOM8 Xilinx Environment Variables ---------------------------- TWINCATSDK: C:\TwinCAT\3.1\SDK\ XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2 XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2 XILINX_VIVADO: C:/Xilinx/Vivado/2021.2 XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2 GUI allocated memory: 256 MB GUI max memory: 3,072 MB Engine allocated memory: 1,300 MB Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. */ // TclEventType: START_GUI // Tcl Message: start_gui // TclEventType: PROJECT_OPEN_DIALOG // Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 // TclEventType: DEBUG_PROBE_SET_CHANGE // TclEventType: FLOW_ADDED // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 57 MB. Current time: 5/13/22, 11:28:41 AM CEST // TclEventType: MSGMGR_MOVEMSG // TclEventType: FILE_SET_CHANGE // TclEventType: FILE_SET_NEW // TclEventType: RUN_COMPLETED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_CURRENT // TclEventType: PROJECT_DASHBOARD_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_NEW // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' // Tcl Message: INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save. // Tcl Message: INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. // Tcl Message: Scanning sources... Finished scanning sources // Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified // TclEventType: PROJECT_NEW // [GUI Memory]: 79 MB (+80353kb) [00:00:27] // [Engine Memory]: 1,300 MB (+1211828kb) [00:00:27] // WARNING: HEventQueue.dispatchEvent() is taking 7148 ms. // WARNING: HEventQueue.dispatchEvent() is taking 1355 ms. // Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. // [GUI Memory]: 107 MB (+24993kb) [00:00:34] // Tcl Message: open_project: Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 1576.332 ; gain = 0.000 // Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1 dismissDialog("Open Project"); // bA // Tcl Message: update_compile_order -fileset sources_1 // Elapsed time: 10 seconds selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n // Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS selectButton("OptionPane.button", "OK"); // JButton // TclEventType: RUN_MODIFY // TclEventType: RUN_RESET // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_RESET // TclEventType: RUN_MODIFY // Tcl Message: reset_run synth_1 // Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp // TclEventType: FILE_SET_CHANGE selectButton(RDIResource.BaseDialog_OK, "OK"); // a dismissDialog("Launch Runs"); // f // TclEventType: RUN_LAUNCH // TclEventType: RUN_MODIFY // TclEventType: RUN_STATUS_CHANGE // Tcl Message: launch_runs synth_1 -jobs 6 // Tcl Message: [Fri May 13 11:29:15 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log // TclEventType: RUN_STATUS_CHANGE // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:29:44 AM CEST // TclEventType: RUN_COMPLETED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:30:15 AM CEST // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:30:45 AM CEST // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:32:14 AM CEST // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:32:45 AM CEST // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:33:15 AM CEST // Elapsed time: 245 seconds selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a // 'k' command handler elapsed time: 249 seconds closeMainWindow("Coraz7_Test - [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr] - Vivado 2021.2"); // bb // HOptionPane Warning: 'A background task is running. Please wait until it completes to exit Vivado. If you choose to abort background task and exit immediately, you will lose all unsaved changes to project. (Background Task)'