/* Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2] SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021 IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021 Process ID (PID): 5492 License: Customer Mode: GUI Mode Current time: Fri May 13 11:33:46 CEST 2022 Time zone: Central European Standard Time (Europe/Berlin) OS: Windows 10 OS Version: 10.0 OS Architecture: amd64 Available processors (cores): 12 Screen size: 1920x1080 Screen resolution (DPI): 100 Available screens: 2 Default font: family=Dialog,name=Dialog,style=plain,size=12 Scale size: 12 Java version: 11.0.11 64-bit Java home: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9 Java executable: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m] Java initial memory (-Xms): 256 MB Java maximum memory (-Xmx): 3 GB User name: Felix User home directory: C:/Users/Felix User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim User country: DE User language: de User locale: de_DE RDI_BASEROOT: C:/Xilinx/Vivado HDI_APPROOT: C:/Xilinx/Vivado/2021.2 RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/ Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts PlanAhead jar file: C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar Vivado log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log Vivado journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou Engine tmp dir: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-5492-DESKTOP-PAACOM8 Xilinx Environment Variables ---------------------------- TWINCATSDK: C:\TwinCAT\3.1\SDK\ XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2 XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2 XILINX_VIVADO: C:/Xilinx/Vivado/2021.2 XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2 GUI allocated memory: 324 MB GUI max memory: 3,072 MB Engine allocated memory: 1,307 MB Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. */ // TclEventType: START_GUI // Tcl Message: start_gui // TclEventType: PROJECT_OPEN_DIALOG // Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 // TclEventType: DEBUG_PROBE_SET_CHANGE // TclEventType: FLOW_ADDED // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 57 MB. Current time: 5/13/22, 11:33:47 AM CEST // TclEventType: MSGMGR_MOVEMSG // TclEventType: FILE_SET_CHANGE // TclEventType: FILE_SET_NEW // TclEventType: RUN_COMPLETED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_FAILED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_CURRENT // TclEventType: PROJECT_DASHBOARD_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_DASHBOARD_GADGET_NEW // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE // TclEventType: PROJECT_NEW // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' // Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. // Tcl Message: Scanning sources... Finished scanning sources // TclEventType: PROJECT_NEW // [GUI Memory]: 81 MB (+82453kb) [00:00:14] // [Engine Memory]: 1,307 MB (+1218722kb) [00:00:14] // WARNING: HEventQueue.dispatchEvent() is taking 2855 ms. // Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. // Tcl Message: open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000 // Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1 dismissDialog("Open Project"); // bA // [GUI Memory]: 115 MB (+31765kb) [00:00:19] selectButton(PAResourceQtoS.RunGadget_SHOW_ERROR, "5 errors"); // g // Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW // Tcl Message: update_compile_order -fileset sources_1 expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints]", 4); // D // PAPropertyPanels.initPanels (Cora-Z7-10-Master.xdc) elapsed time: 0.2s selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Cora-Z7-10-Master.xdc]", 6, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Cora-Z7-10-Master.xdc]", 6, false, false, false, false, false, true); // D - Double Click // [GUI Memory]: 128 MB (+7607kb) [00:00:27] // WARNING: HEventQueue.dispatchEvent() is taking 1562 ms. dismissDialog("Opening Editor"); // bA selectCodeEditor("Cora-Z7-10-Master.xdc", 78, 103); // be selectMenuItem(RDIResourceCommand.RDICommands_COPY, "Copy"); // ao // Elapsed time: 21 seconds selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n // Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS // TclEventType: RUN_MODIFY // TclEventType: RUN_RESET // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_RESET // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_RESET // TclEventType: RUN_MODIFY // Tcl Message: reset_run synth_1 // Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp // TclEventType: FILE_SET_CHANGE selectButton(RDIResource.BaseDialog_OK, "OK"); // a dismissDialog("Launch Runs"); // f // TclEventType: RUN_LAUNCH // TclEventType: RUN_MODIFY // TclEventType: RUN_STATUS_CHANGE // Tcl Message: launch_runs synth_1 -jobs 6 // Tcl Message: [Fri May 13 11:34:46 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log dismissDialog("Starting Design Runs"); // bA // TclEventType: RUN_STATUS_CHANGE // [GUI Memory]: 136 MB (+1534kb) [00:02:03] // TclEventType: RUN_COMPLETED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // Elapsed time: 74 seconds selectButton(RDIResource.BaseDialog_OK, "OK"); // a // Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION selectButton(RDIResource.BaseDialog_OK, "OK"); // a dismissDialog("Launch Runs"); // f // TclEventType: RUN_LAUNCH // TclEventType: RUN_MODIFY // TclEventType: RUN_STATUS_CHANGE // Tcl Message: launch_runs impl_1 -jobs 6 // Tcl Message: [Fri May 13 11:36:03 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log dismissDialog("Starting Design Runs"); // bA // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // TclEventType: RUN_FAILED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // Elapsed time: 56 seconds selectButton(RDIResource.BaseDialog_OK, "OK"); // a // Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW dismissDialog("Implementation Failed"); // ag // TclEventType: FILE_SET_CHANGE // Elapsed time: 218 seconds selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // m // Elapsed time: 41 seconds selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false, false, false, false, false, true); // D - Double Click // WARNING: HEventQueue.dispatchEvent() is taking 1116 ms. dismissDialog("Opening Editor"); // bA // Elapsed time: 190 seconds selectCodeEditor("pwm_test.vhd", 212, 280); // be selectCodeEditor("pwm_test.vhd", 47, 263); // be selectCodeEditor("pwm_test.vhd", 474, 312); // be selectCodeEditor("pwm_test.vhd", 58, 355); // be typeControlKey((HResource) null, "pwm_test.vhd", 'v'); // be selectCodeEditor("pwm_test.vhd", 184, 376); // be selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 3, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true, false, false, false, true, false); // D - Popup Trigger - Node selectMenu(PAResourceCommand.PACommandNames_AUTO_UPDATE_HIER, "Hierarchy Update"); // al selectMenu(PAResourceQtoS.SrcMenu_IP_HIERARCHY, "IP Hierarchy"); // al selectMenuItem(PAResourceCommand.PACommandNames_ADD_SOURCES, "Add Sources..."); // ao // Run Command: PAResourceCommand.PACommandNames_ADD_SOURCES selectButton("NEXT", "Next >"); // JButton selectButton(PAResourceQtoS.SrcChooserPanel_CREATE_FILE, "Create File"); // a selectComboBox(PAResourceAtoD.CreateSrcFileDialog_FILE_TYPE, "VHDL", 3); // cm // Elapsed time: 33 seconds setText(PAResourceAtoD.CreateSrcFileDialog_FILE_NAME, "wendeTangente"); // aa selectButton(RDIResource.BaseDialog_OK, "OK"); // a dismissDialog("Create Source File"); // F selectButton("FINISH", "Finish"); // JButton // 'g' command handler elapsed time: 48 seconds dismissDialog("Add Sources"); // c // Tcl Message: close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // Tcl Message: add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, " ; in ; false ; 0 ; 0", 0, "in", 1); // ab selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, " ; in ; false ; 0 ; 0", 0, (String) null, 0); // ab selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, null, -1, null, -1); // ab editTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, "value", 0, "Port Name", 0); // ab selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, " ; in ; false ; 0 ; 0", 1, "in", 1); // ab editTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, "out", 1, "Direction", 1); // ab selectTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, " ; out ; false ; 0 ; 0", 1, (String) null, 0); // ab selectButton(RDIResource.BaseDialog_OK, "OK"); // a editTable(PAResourceAtoD.DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS, "param1", 1, "Port Name", 0); // ab // TclEventType: FILE_SET_CHANGE dismissDialog("Define Module"); // I selectCodeEditor("pwm_test.vhd", 607, 348); // be // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // [GUI Memory]: 144 MB (+960kb) [00:12:40] // Tcl Message: update_compile_order -fileset sources_1 selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 3, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 4, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 4, false, false, false, false, false, true); // D - Double Click // WARNING: HEventQueue.dispatchEvent() is taking 1093 ms. dismissDialog("Opening Editor"); // bA selectCodeEditor("wendeTangente.vhd", 79, 426); // be selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 4, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false); // D selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m // Elapsed time: 18 seconds selectCodeEditor("wendeTangente.vhd", 59, 446); // be selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Cora-Z7-10-Master.xdc", 1); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectCodeEditor("wendeTangente.vhd", 62, 314); // be selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectCodeEditor("wendeTangente.vhd", 28, 285); // be selectCodeEditor("wendeTangente.vhd", 26, 300); // be selectCodeEditor("wendeTangente.vhd", 28, 331); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be selectCodeEditor("wendeTangente.vhd", 108, 351); // be selectCodeEditor("wendeTangente.vhd", 80, 403); // be selectCodeEditor("wendeTangente.vhd", 208, 149); // be // Elapsed time: 17 seconds selectCodeEditor("wendeTangente.vhd", 245, 193); // be selectCodeEditor("wendeTangente.vhd", 116, 301); // be // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE selectCodeEditor("wendeTangente.vhd", 124, 324); // be // Elapsed time: 16 seconds selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m // [GUI Memory]: 152 MB (+678kb) [00:14:45] selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectCodeEditor("wendeTangente.vhd", 122, 375); // be selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectCodeEditor("wendeTangente.vhd", 102, 413); // be selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectCodeEditor("wendeTangente.vhd", 369, 205); // be selectCodeEditor("wendeTangente.vhd", 121, 277); // be selectCodeEditor("wendeTangente.vhd", 69, 214); // be // Elapsed time: 264 seconds selectCodeEditor("wendeTangente.vhd", 141, 255); // be selectCodeEditor("wendeTangente.vhd", 140, 241); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be selectCodeEditor("wendeTangente.vhd", 391, 297); // be // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 81 MB. Current time: 5/13/22, 12:03:47 PM CEST // Elapsed time: 931 seconds selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true, false, false, false, true, false); // D - Popup Trigger - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D selectCodeEditor("wendeTangente.vhd", 2, 251); // be selectCodeEditor("wendeTangente.vhd", 243, 261); // be selectCodeEditor("wendeTangente.vhd", 0, 239); // be selectCodeEditor("wendeTangente.vhd", 0, 229); // be selectCodeEditor("wendeTangente.vhd", 215, 325); // be // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, design_1 (design_1.bd)]", 1, false, false, false, false, false, true); // D - Double Click // TclEventType: LOAD_FEATURE // TclEventType: RSB_SCRIPT_TASK // Tcl Message: open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} // Tcl Message: Reading block design file ... selectButton(RDIResource.ProgressDialog_CANCEL, "Cancel"); // a // Tcl Message: INFO: [Common 17-41] Interrupt caught. Command should exit soon. INFO: [Common 17-344] 'source' was cancelled // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // Tcl Message: ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] - while executing "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" ERROR: [Ip 78-89] Error in evaluating command source init.tcl - while executing "source init.tcl" // Tcl Message: 1 // TclEventType: RSB_CHANGE_CURRENT_DIAGRAM // TclEventType: RSB_SCRIPT_TASK // TclEventType: RSB_CHANGE_CURRENT_DIAGRAM // Tcl Message: INFO: [BD 41-1808] Open Block Design has been cancelled. INFO: [Common 17-344] 'open_bd_design' was cancelled // CommandFailedException: ERROR: [Common 17-69] Command failed: dismissDialog("Open Block Design"); // bA selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f dismissDialog("Critical Messages"); // a selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 2, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources]", 0, true, false, false, false, true, false); // D - Popup Trigger - Node selectButton(PAResourceCommand.PACommandNames_ADD_SOURCES, "Sources_add_sources"); // D // Run Command: PAResourceCommand.PACommandNames_ADD_SOURCES // Elapsed time: 12 seconds selectButton("NEXT", "Next >"); // JButton selectButton(PAResourceQtoS.SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE, "Add"); // D selectMenuItem(PAResourceQtoS.SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT, "Add Files..."); // ao // Elapsed time: 12 seconds String[] filenames31467 = {"C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl", "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl", "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl", "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl"}; setFileChooser(filenames31467); // Elapsed time: 28 seconds selectCheckBox(PAResourceQtoS.SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO, "Copy sources into project", true); // g: TRUE selectButton("FINISH", "Finish"); // JButton // 'g' command handler elapsed time: 65 seconds dismissDialog("Add Sources"); // c // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // Tcl Message: import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // Tcl Message: update_compile_order -fileset sources_1 selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // D - Node expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, fixed_generic_pkg-body.vhdl]", 2, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, design_1 (design_1.bd)]", 4, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, fixed_generic_pkg-body.vhdl]", 2, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, fixed_generic_pkg-body.vhdl]", 2, false, false, false, false, false, true); // D - Double Click // WARNING: HEventQueue.dispatchEvent() is taking 1943 ms. dismissDialog("Opening Editor"); // bA // Elapsed time: 38 seconds selectTab(RDIResource.PropertiesView_TABBED_PANE, (HResource) null, "Properties", 1); // i selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i // Elapsed time: 19 seconds selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced]", 4); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_float_types.vhdl]", 8, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_pkg.vhdl]", 7, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_pkg.vhdl]", 7, false); // D // Elapsed time: 10 seconds selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_pkg.vhdl]", 7, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_float_types.vhdl]", 8, false); // D selectTab(RDIResource.PropertiesView_TABBED_PANE, (HResource) null, "General", 0); // i selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] dismissDialog("Set Type"); // ac selectButton(PAResourceQtoS.SrcFilePropPanels_LIBRARY, (String) null); // s setText(PAResourceQtoS.SpecifyLibraryDialog_LIBRARY_NAME, "ieee_proposed"); // k selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] dismissDialog("Set Library"); // ad expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008]", 10); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg-body.vhdl]", 9, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_pkg.vhdl]", 7, false, true, true, false, false, false); // D - Shift Key - Control Key selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg.vhdl]", 8, false, false, true, false, false, false); // D - Control Key selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg-body.vhdl]", 9, false, false, true, false, false, false); // D - Control Key selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] dismissDialog("Set Type"); // ac selectButton(PAResourceQtoS.SrcFilePropPanels_LIBRARY, (String) null); // s selectComboBox(PAResourceQtoS.SpecifyLibraryDialog_LIBRARY_NAME, "ieee_proposed", 0); // K selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] dismissDialog("Set Library"); // ad selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, ieee_proposed, Unreferenced, fixed_float_types.vhdl]", 13, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, ieee_proposed, Unreferenced, fixed_pkg.vhdl]", 12, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, ieee_proposed, Unreferenced, fixed_float_types.vhdl]", 13, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg-body.vhdl]", 8, false); // D selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] dismissDialog("Set Type"); // ac selectButton(PAResourceQtoS.SrcFilePropPanels_LIBRARY, (String) null); // s selectComboBox(PAResourceQtoS.SpecifyLibraryDialog_LIBRARY_NAME, "ieee_proposed", 0); // K selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] dismissDialog("Set Library"); // ad selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg.vhdl]", 7, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL, xil_defaultlib, Unreferenced, fixed_generic_pkg.vhdl]", 7, false); // D selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] dismissDialog("Set Type"); // ac selectButton(PAResourceQtoS.SrcFilePropPanels_LIBRARY, (String) null); // s selectComboBox(PAResourceQtoS.SpecifyLibraryDialog_LIBRARY_NAME, "ieee_proposed", 0); // K selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] dismissDialog("Set Library"); // ad // Elapsed time: 63 seconds selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false, false, false, false, false, true); // D - Double Click dismissDialog("Opening Editor"); // bA selectCodeEditor("wendeTangente.vhd", 464, 183); // be selectCodeEditor("wendeTangente.vhd", 17, 226); // be selectCodeEditor("wendeTangente.vhd", 185, 265); // be selectCodeEditor("wendeTangente.vhd", 244, 194); // be // Elapsed time: 44 seconds selectCodeEditor("wendeTangente.vhd", 248, 258); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be selectCodeEditor("wendeTangente.vhd", 558, 347); // be // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE selectCodeEditor("wendeTangente.vhd", 70, 366); // be selectCodeEditor("wendeTangente.vhd", 78, 227); // be selectCodeEditor("wendeTangente.vhd", 28, 384); // be // Elapsed time: 16 seconds selectCodeEditor("wendeTangente.vhd", 360, 336); // be selectCodeEditor("wendeTangente.vhd", 2, 384); // be selectCodeEditor("wendeTangente.vhd", 134, 428); // be selectCodeEditor("wendeTangente.vhd", 101, 87); // be selectCodeEditor("wendeTangente.vhd", 95, 98); // be selectCodeEditor("wendeTangente.vhd", 95, 98, false, false, false, false, true); // be - Double Click selectCodeEditor("wendeTangente.vhd", 102, 108); // be selectCodeEditor("wendeTangente.vhd", 102, 108, false, false, false, false, true); // be - Double Click selectCodeEditor("wendeTangente.vhd", 200, 90); // be selectCodeEditor("wendeTangente.vhd", 210, 90); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be selectCodeEditor("wendeTangente.vhd", 217, 82); // be selectCodeEditor("wendeTangente.vhd", 204, 95); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be selectCodeEditor("wendeTangente.vhd", 27, 112); // be selectCodeEditor("wendeTangente.vhd", 82, 110); // be selectCodeEditor("wendeTangente.vhd", 140, 229); // be selectCodeEditor("wendeTangente.vhd", 140, 229, false, false, false, false, true); // be - Double Click selectCodeEditor("wendeTangente.vhd", 261, 228); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be selectCodeEditor("wendeTangente.vhd", 150, 87); // be selectCodeEditor("wendeTangente.vhd", 150, 85, false, false, false, false, true); // be - Double Click typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be selectCodeEditor("wendeTangente.vhd", 168, 98); // be selectCodeEditor("wendeTangente.vhd", 168, 98, false, false, false, false, true); // be - Double Click selectCodeEditor("wendeTangente.vhd", 171, 111); // be selectCodeEditor("wendeTangente.vhd", 171, 111, false, false, false, false, true); // be - Double Click typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be selectCodeEditor("wendeTangente.vhd", 179, 121); // be selectCodeEditor("wendeTangente.vhd", 103, 200); // be selectCodeEditor("wendeTangente.vhd", 149, 132); // be selectCodeEditor("wendeTangente.vhd", 149, 132, false, false, false, false, true); // be - Double Click typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be selectCodeEditor("wendeTangente.vhd", 263, 288); // be // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE selectCodeEditor("wendeTangente.vhd", 250, 368); // be selectCodeEditor("wendeTangente.vhd", 0, 230); // be selectCodeEditor("wendeTangente.vhd", 334, 337); // be // [GUI Memory]: 163 MB (+3607kb) [00:43:11] selectCodeEditor("wendeTangente.vhd", 67, 312); // be selectCodeEditor("wendeTangente.vhd", 67, 312, false, false, false, false, true); // be - Double Click selectCodeEditor("wendeTangente.vhd", 321, 364); // be selectCodeEditor("wendeTangente.vhd", 562, 220); // be selectCodeEditor("wendeTangente.vhd", 333, 229); // be selectCodeEditor("wendeTangente.vhd", 287, 237); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be selectCodeEditor("wendeTangente.vhd", 313, 95); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'v'); // be selectCodeEditor("wendeTangente.vhd", 302, 273); // be // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "fixed_generic_pkg-body.vhdl", 4); // m closeView(PAResourceOtoP.PAViews_CODE, "Code"); // D selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n // Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a // TclEventType: DG_GRAPH_STALE dismissDialog("Save Project"); // al // TclEventType: RUN_MODIFY // TclEventType: DG_GRAPH_STALE // TclEventType: RUN_MODIFY // TclEventType: FILE_SET_CHANGE // TclEventType: RUN_RESET // TclEventType: FILE_SET_CHANGE // TclEventType: RUN_RESET // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_RESET // Tcl Message: reset_run synth_1 // TclEventType: RUN_RESET // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_RESET // TclEventType: RUN_MODIFY // Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp // TclEventType: FILE_SET_CHANGE selectButton(RDIResource.BaseDialog_OK, "OK"); // a dismissDialog("Launch Runs"); // f // TclEventType: RUN_LAUNCH // Tcl Message: launch_runs synth_1 -jobs 6 // TclEventType: RUN_MODIFY // Tcl Message: [Fri May 13 12:17:21 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log // 'k' command handler elapsed time: 4 seconds dismissDialog("Starting Design Runs"); // bA // TclEventType: RUN_STATUS_CHANGE selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node // TclEventType: RUN_COMPLETED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // Elapsed time: 69 seconds selectButton(RDIResource.BaseDialog_OK, "OK"); // a // Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION selectButton(RDIResource.BaseDialog_OK, "OK"); // a dismissDialog("Launch Runs"); // f // TclEventType: RUN_LAUNCH // TclEventType: RUN_MODIFY // Tcl Message: launch_runs impl_1 -jobs 6 // Tcl Message: [Fri May 13 12:18:35 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log dismissDialog("Starting Design Runs"); // bA // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // Elapsed time: 28 seconds selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl. - . while executing. source init.tcl. ]", 3, false, false, false, false, false, true); // ah - Double Click selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl. - . while executing. source init.tcl. ]", 3, false); // ah selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl. - . while executing. source init.tcl. ]", 3, false, false, false, false, false, true); // ah - Double Click selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl. - . while executing. source init.tcl. ]", 3, false); // ah // TclEventType: RUN_FAILED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // Elapsed time: 138 seconds selectButton(RDIResource.BaseDialog_OK, "OK"); // a // Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW dismissDialog("Implementation Failed"); // ag // Elapsed time: 14 seconds selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, (String) null, 5, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, (String) null, 5, true, false, false, false, false, true); // ah - Double Click - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, (String) null, 5, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, (String) null, 5, true, false, false, false, false, true); // ah - Double Click - Node selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, design_1 (design_1.bd)]", 2, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, design_1 (design_1.bd)]", 2, false, false, false, false, false, true); // D - Double Click // TclEventType: RSB_SCRIPT_TASK // TclEventType: RSB_CHANGE_CURRENT_DIAGRAM // TclEventType: RSB_LOCK_CHANGE // TclEventType: RSB_SCRIPT_TASK // TclEventType: RSB_OPEN_DIAGRAM // Tcl Message: open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} // Tcl Message: Reading block design file ... Successfully read diagram from block design file closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v dismissDialog("Open Block Design"); // bA selectTree(PAResourceQtoS.SystemTreeView_SYSTEM_TREE, "[design_1]", 0, false); // a selectTree(PAResourceQtoS.SystemTreeView_SYSTEM_TREE, "[design_1]", 0, false, false, false, false, false, true); // a - Double Click selectTab((HResource) null, (HResource) null, "Sources", 0); // aL selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false, false, false, false, false, true); // D - Double Click dismissDialog("Opening Editor"); // bA // Elapsed time: 10 seconds selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false, false, false, false, false, true); // D - Double Click // WARNING: HEventQueue.dispatchEvent() is taking 1097 ms. dismissDialog("Opening Editor"); // bA selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false, false, false, false, false, true); // D - Double Click dismissDialog("Opening Editor"); // bA selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 2); // m expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 9); // D expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 10); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true, false, false, false, false, true); // D - Double Click - Node // WARNING: HEventQueue.dispatchEvent() is taking 1102 ms. dismissDialog("Opening Editor"); // bA // Elapsed time: 10 seconds selectCodeEditor("pwm_test_db.vhd", 267, 259); // be selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectCodeEditor("wendeTangente.vhd", 1, 112); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 4); // m // Elapsed time: 12 seconds selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 5); // m selectCodeEditor("pwm_test_db.vhd", 28, 264); // be selectCodeEditor("pwm_test_db.vhd", 10, 292); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 20, 242); // be selectCodeEditor("pwm_test_db.vhd", 20, 242, false, false, false, false, true); // be - Double Click selectCodeEditor("pwm_test_db.vhd", 91, 322); // be selectCodeEditor("pwm_test_db.vhd", 74, 316); // be selectCodeEditor("pwm_test_db.vhd", 74, 316, false, false, false, false, true); // be - Double Click selectCodeEditor("pwm_test_db.vhd", 247, 299); // be selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 3); // m selectCodeEditor("wendeTangente.vhd", 193, 216); // be selectCodeEditor("wendeTangente.vhd", 245, 128); // be typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 5); // m selectCodeEditor("pwm_test_db.vhd", 229, 126); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 380, 150); // be // Elapsed time: 11 seconds selectCodeEditor("pwm_test_db.vhd", 306, 90); // be selectCodeEditor("pwm_test_db.vhd", 76, 54); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be selectCodeEditor("pwm_test_db.vhd", 295, 221); // be selectCodeEditor("pwm_test_db.vhd", 24, 267); // be selectCodeEditor("pwm_test_db.vhd", 20, 265, false, false, false, false, true); // be - Double Click selectCodeEditor("pwm_test_db.vhd", 20, 265); // be typeControlKey(null, null, 'z'); typeControlKey(null, null, 'z'); // Elapsed time: 12 seconds selectCodeEditor("pwm_test_db.vhd", 176, 19); // be selectCodeEditor("pwm_test_db.vhd", 115, 302); // be selectCodeEditor("pwm_test_db.vhd", 176, 245); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be selectCodeEditor("pwm_test_db.vhd", 141, 268); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be // Elapsed time: 32 seconds selectCodeEditor("pwm_test_db.vhd", 359, 285); // be selectCodeEditor("pwm_test_db.vhd", 210, 205); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 328, 212); // be selectCodeEditor("pwm_test_db.vhd", 329, 210, false, false, false, false, true); // be - Double Click selectCodeEditor("pwm_test_db.vhd", 378, 252); // be selectCodeEditor("pwm_test_db.vhd", 435, 213); // be selectCodeEditor("pwm_test_db.vhd", 444, 207); // be selectCodeEditor("pwm_test_db.vhd", 448, 208); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be selectCodeEditor("pwm_test_db.vhd", 425, 218); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 450, 249); // be selectCodeEditor("pwm_test_db.vhd", 52, 246); // be selectCodeEditor("pwm_test_db.vhd", 223, 252); // be selectCodeEditor("pwm_test_db.vhd", 325, 231); // be selectCodeEditor("pwm_test_db.vhd", 325, 231, false, false, false, false, true); // be - Double Click selectCodeEditor("pwm_test_db.vhd", 357, 226); // be selectCodeEditor("pwm_test_db.vhd", 318, 279); // be selectCodeEditor("pwm_test_db.vhd", 325, 273); // be selectCodeEditor("pwm_test_db.vhd", 52, 206); // be selectCodeEditor("pwm_test_db.vhd", 56, 201); // be // Elapsed time: 25 seconds selectCodeEditor("pwm_test_db.vhd", 135, 223); // be selectCodeEditor("pwm_test_db.vhd", 135, 223, false, false, false, false, true); // be - Double Click // Elapsed time: 46 seconds selectCodeEditor("pwm_test_db.vhd", 249, 352); // be selectCodeEditor("pwm_test_db.vhd", 190, 413); // be selectCodeEditor("pwm_test_db.vhd", 121, 77); // be selectCodeEditor("pwm_test_db.vhd", 121, 77, false, false, false, false, true); // be - Double Click typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be selectCodeEditor("pwm_test_db.vhd", 172, 280); // be selectCodeEditor("pwm_test_db.vhd", 172, 280, false, false, false, false, true); // be - Double Click typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 142, 318); // be // Elapsed time: 11 seconds selectCodeEditor("pwm_test_db.vhd", 56, 181); // be selectCodeEditor("pwm_test_db.vhd", 102, 197); // be selectCodeEditor("pwm_test_db.vhd", 138, 247); // be // Elapsed time: 39 seconds selectCodeEditor("pwm_test_db.vhd", 222, 193); // be selectCodeEditor("pwm_test_db.vhd", 221, 293); // be selectCodeEditor("pwm_test_db.vhd", 57, 247); // be selectCodeEditor("pwm_test_db.vhd", 208, 212); // be // Elapsed time: 20 seconds selectCodeEditor("pwm_test_db.vhd", 289, 129); // be // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n // Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS selectButton("OptionPane.button", "OK"); // JButton // TclEventType: RUN_MODIFY // TclEventType: RUN_RESET // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_RESET // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_RESET // TclEventType: RUN_MODIFY // Tcl Message: reset_run synth_1 // Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp // TclEventType: FILE_SET_CHANGE selectButton(RDIResource.BaseDialog_OK, "OK"); // a dismissDialog("Launch Runs"); // f // TclEventType: RUN_LAUNCH // TclEventType: RUN_MODIFY // Tcl Message: launch_runs synth_1 -jobs 6 // Tcl Message: [Fri May 13 12:28:24 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log // 'k' command handler elapsed time: 4 seconds dismissDialog("Starting Design Runs"); // bA // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_COMPLETED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // Elapsed time: 59 seconds selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a dismissDialog("Synthesis Completed"); // ag selectCodeEditor("pwm_test_db.vhd", 332, 290); // be selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL // TclEventType: LAUNCH_SIM // TclEventType: FILE_SET_OPTIONS_CHANGE // Tcl Message: launch_simulation // Tcl Message: Command: launch_simulation // Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' // Tcl Message: INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' // Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" // TclEventType: LAUNCH_SIM_LOG // Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' // Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" // TclEventType: LAUNCH_SIM // Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' // Tcl Message: ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. // Tcl Message: launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 // Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. // CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. // HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. (Run Simulation)' // 'd' command handler elapsed time: 13 seconds // Elapsed time: 13 seconds selectButton("OptionPane.button", "OK"); // JButton selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f dismissDialog("Critical Messages"); // a selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 620, 122); // dT selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 621, 122, false, false, false, false, true); // dT - Double Click // Elapsed time: 125 seconds selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 365, 91); // dT selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 389, 88); // dT selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 659, 97); // dT selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 174, 111); // dT selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 289, 113); // dT selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 275, 172); // dT selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 275, 172, false, false, false, false, true); // dT - Double Click // Elapsed time: 26 seconds selectButton(RDIResource.TclConsoleView_CLEAR_ALL_OUTPUT_IN_TCL_CONSOLE, "Tcl Console_remove"); // D selectButton("OptionPane.button", "Yes"); // JButton selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 554, 99); // dT selectCodeEditor("pwm_test_db.vhd", 222, 436); // be selectCodeEditor("pwm_test_db.vhd", 249, 331); // be selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL // TclEventType: LAUNCH_SIM // TclEventType: FILE_SET_OPTIONS_CHANGE // Tcl Message: launch_simulation // Tcl Message: Command: launch_simulation // Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' // Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" // TclEventType: LAUNCH_SIM_LOG // Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' // Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" // TclEventType: LAUNCH_SIM // Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' // Tcl Message: ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. // Tcl Message: launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.359 ; gain = 0.000 // Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. // CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. // HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. (Run Simulation)' // 'd' command handler elapsed time: 34 seconds // Elapsed time: 34 seconds selectButton("OptionPane.button", "OK"); // JButton // Elapsed time: 10 seconds selectButton(PAResourceAtoD.CmdMsgDialog_OPEN_MESSAGES_VIEW, "Open Messages View"); // a // Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW dismissDialog("Critical Messages"); // a selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node // Elapsed time: 14 seconds expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Utility Sources]", 18); // D expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Waveform Configuration File]", 17); // D selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 85 MB. Current time: 5/13/22, 12:33:48 PM CEST selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Compile Order", 3); // i selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true, false, false, false, true, false); // D - Popup Trigger - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true); // D - Node selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 12, true); // D - Node selectTab(RDIResource.PropertiesView_TABBED_PANE, (HResource) null, "Properties", 1); // i selectTab(RDIResource.PropertiesView_TABBED_PANE, (HResource) null, "General", 0); // i selectButton(PAResourceQtoS.SrcFilePropPanels_TYPE, (String) null); // s selectComboBox(PAResourceQtoS.SrcFileTypeComboBox_SOURCE_FILE_TYPE, "VHDL 2008", 4); // cj selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: FILE_SET_CHANGE // Tcl Message: set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] dismissDialog("Set Type"); // ac // Elapsed time: 15 seconds selectCodeEditor("pwm_test_db.vhd", 488, 154); // be selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n // Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS selectButton("OptionPane.button", "Cancel"); // JButton selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL // TclEventType: LAUNCH_SIM // TclEventType: FILE_SET_OPTIONS_CHANGE // Tcl Message: launch_simulation // Tcl Message: Command: launch_simulation // Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' // Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" // TclEventType: LAUNCH_SIM_LOG // Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' // Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' // Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" // TclEventType: LAUNCH_SIM // TclEventType: LOAD_FEATURE // Tcl Message: Built simulation snapshot pwm_test_db_behav // Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim // Tcl Message: with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" // Tcl Message: INFO: [USF-XSim-8] Loading simulator feature // TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_UPDATE_TITLE // TclEventType: WAVEFORM_OPEN_WCFG // Tcl Message: Time resolution is 1 ps // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: WAVEFORM_DELAYED_MODEL_EVENT // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: SIMULATION_OBJECT_TREE_RESTORED // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 94 MB. Current time: 5/13/22, 12:34:41 PM CEST // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED // TclEventType: SIMULATION_CURRENT_STACK_CHANGED // TclEventType: SIMULATION_UPDATE_STACK_FRAMES // TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED // TclEventType: SIMULATION_UPDATE_LOCALS // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_STOPPED // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg // Tcl Message: source pwm_test_db.tcl // Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 5 s // Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 // Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s // Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1580.359 ; gain = 0.000 // 'd' command handler elapsed time: 8 seconds dismissDialog("Run Simulation"); // e // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_MODEL_EVENT selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 147, 182); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, clk_100]", 3, false); // l // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, cnt]", 4, false); // l // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 99, 124); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: SIMULATION_UPDATE_OBJECT_TREE selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true); // c - Node selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "b[7:-6] ; 0147 ; Array", 1, "b[7:-6]", 0, true); // c - Node selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "a[7:-6] ; 3f38 ; Array", 0, "a[7:-6]", 0, true); // c - Node selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "a[7:-6] ; 3f38 ; Array", 0, "a[7:-6]", 0, true, false, false, false, false, true); // c - Double Click - Node // TclEventType: SIMULATION_OPEN_SOURCE // TclEventType: SIMULATION_UPDATE_OBJECT_TREE selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "b[7:-6] ; 0147 ; Array", 1, "b[7:-6]", 0, true); // c - Node selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 158, 204); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, cnt]", 4, false, false, false, false, true, false); // l - Popup Trigger // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: SIMULATION_UPDATE_OBJECT_TREE selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true); // c - Node selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true, false, false, false, true, false); // c - Popup Trigger - Node selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "a[7:-6] ; 3f38 ; Array", 0, "a[7:-6]", 0, true); // c - Node selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "a[7:-6] ; 3f38 ; Array", 0, "a[7:-6]", 0, true, false, false, false, true, false); // c - Popup Trigger - Node selectMenuItem((HResource) null, "Add to Wave Window"); // ao // Tcl Command: 'current_wave_config {pwm_test_db_func_synth.wcfg}' // Tcl Message: current_wave_config {pwm_test_db_func_synth.wcfg} // Tcl Message: pwm_test_db_func_synth.wcfg // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_TITLE // TclEventType: WAVEFORM_DELAYED_MODEL_EVENT // Tcl Message: add_wave {{/pwm_test_db/uutWendeTangente/a}} selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "b[7:-6] ; 0147 ; Array", 1, "b[7:-6]", 0, true); // c - Node // TclEventType: SIMULATION_UPDATE_OBJECT_TREE selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "b[7:-6] ; 0147 ; Array", 1, "b[7:-6]", 0, true, false, false, false, true, false); // c - Popup Trigger - Node selectMenuItem((HResource) null, "Add to Wave Window"); // ao // Tcl Command: 'current_wave_config {pwm_test_db_func_synth.wcfg}' // Tcl Message: current_wave_config {pwm_test_db_func_synth.wcfg} // Tcl Message: pwm_test_db_func_synth.wcfg // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_TITLE // Tcl Message: add_wave {{/pwm_test_db/uutWendeTangente/b}} selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true); // c - Node // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_MODEL_EVENT selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "c[7:-6] ; UUUU ; Array", 2, "c[7:-6]", 0, true, false, false, false, true, false); // c - Popup Trigger - Node selectMenuItem((HResource) null, "Add to Wave Window"); // ao // Tcl Command: 'current_wave_config {pwm_test_db_func_synth.wcfg}' // Tcl Message: current_wave_config {pwm_test_db_func_synth.wcfg} // Tcl Message: pwm_test_db_func_synth.wcfg // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_TITLE // TclEventType: WAVEFORM_DELAYED_MODEL_EVENT // Tcl Message: add_wave {{/pwm_test_db/uutWendeTangente/c}} // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_MODEL_EVENT selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL selectButton("OptionPane.button", "Yes"); // JButton // TclEventType: WAVEFORM_UPDATE_TITLE selectButton("OptionPane.button", "Save"); // JButton // Tcl Message: save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} // TclEventType: WAVEFORM_CLOSE_WCFG // TclEventType: SIMULATION_CLOSE_SIMULATION // Tcl Message: close_sim // Tcl Message: INFO: [Simtcl 6-16] Simulation closed dismissDialog("Close"); // bA // TclEventType: LAUNCH_SIM // TclEventType: FILE_SET_OPTIONS_CHANGE // Tcl Message: launch_simulation // Tcl Message: Command: launch_simulation // Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' // Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" // TclEventType: LAUNCH_SIM_LOG // Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' // Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" // TclEventType: LAUNCH_SIM // Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim // Tcl Message: with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" // Tcl Message: INFO: [USF-XSim-8] Loading simulator feature // TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // Tcl Message: Time resolution is 1 ps // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_UPDATE_TITLE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_DELAYED_MODEL_EVENT // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: SIMULATION_OBJECT_TREE_RESTORED // TclEventType: WAVEFORM_MODEL_EVENT // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 106 MB. Current time: 5/13/22, 12:35:22 PM CEST // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED // TclEventType: SIMULATION_CURRENT_STACK_CHANGED // TclEventType: SIMULATION_UPDATE_STACK_FRAMES // TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED // TclEventType: SIMULATION_UPDATE_LOCALS // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_STOPPED // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg // Tcl Message: source pwm_test_db.tcl // Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 5 s // Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 // Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s // Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 // 'd' command handler elapsed time: 10 seconds dismissDialog("Run Simulation"); // e // TclEventType: FILE_SET_CHANGE // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: SIMULATION_ADD_BREAKPOINT // Tcl Message: add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 // TclEventType: SIMULATION_DELETE_BREAKPOINT // Tcl Message: remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 87, 183); // b // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 87, 183, false, false, false, false, true); // b - Double Click // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 96 MB. Current time: 5/13/22, 12:35:42 PM CEST // Elapsed time: 12 seconds selectButton(RDIResource.TclConsoleView_CLEAR_ALL_OUTPUT_IN_TCL_CONSOLE, "Tcl Console_remove"); // D selectButton("OptionPane.button", "Yes"); // JButton selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL selectButton("OptionPane.button", "Yes"); // JButton // TclEventType: WAVEFORM_CLOSE_WCFG // TclEventType: SIMULATION_CLOSE_SIMULATION // Tcl Message: close_sim // Tcl Message: INFO: [Simtcl 6-16] Simulation closed dismissDialog("Close"); // bA // TclEventType: LAUNCH_SIM // TclEventType: FILE_SET_OPTIONS_CHANGE // Tcl Message: launch_simulation // Tcl Message: Command: launch_simulation // Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' // Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" // TclEventType: LAUNCH_SIM_LOG // Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' // Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" // TclEventType: LAUNCH_SIM // Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim // Tcl Message: with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" // Tcl Message: INFO: [USF-XSim-8] Loading simulator feature // TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // Tcl Message: Time resolution is 1 ps // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_UPDATE_TITLE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_DELAYED_MODEL_EVENT // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: SIMULATION_OBJECT_TREE_RESTORED // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 100 MB. Current time: 5/13/22, 12:36:02 PM CEST // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED // TclEventType: SIMULATION_CURRENT_STACK_CHANGED // TclEventType: SIMULATION_UPDATE_STACK_FRAMES // TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED // TclEventType: SIMULATION_UPDATE_LOCALS // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_STOPPED // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg // Tcl Message: source pwm_test_db.tcl // Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 5 s // Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 // Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s // Tcl Message: launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 // 'd' command handler elapsed time: 8 seconds dismissDialog("Run Simulation"); // e // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // Elapsed time: 17 seconds selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 99 MB. Current time: 5/13/22, 12:36:21 PM CEST // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, b[7:-6]]", 5); // l // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 4); // l // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 4); // l // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, c[7:-6]]", 13); // l // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, c[7:-6]]", 11); // l // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 100 MB. Current time: 5/13/22, 12:36:31 PM CEST collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, b[7:-6]]", 4); // l // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 3); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Cora-Z7-10-Master.xdc", 0); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 1); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m // Elapsed time: 25 seconds selectCodeEditor("pwm_test_db.vhd", 71, 124); // be selectCodeEditor("pwm_test_db.vhd", 356, 188); // be selectCodeEditor("pwm_test_db.vhd", 72, 128); // be selectCodeEditor("pwm_test_db.vhd", 72, 128, false, false, false, false, true); // be - Double Click selectCodeEditor("pwm_test_db.vhd", 240, 229); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be selectCodeEditor("pwm_test_db.vhd", 61, 232); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 167, 227); // be selectCodeEditor("pwm_test_db.vhd", 167, 227, false, false, false, false, true); // be - Double Click selectCodeEditor("pwm_test_db.vhd", 171, 329); // be // Elapsed time: 47 seconds selectCodeEditor("pwm_test_db.vhd", 64, 224); // be selectCodeEditor("pwm_test_db.vhd", 304, 254); // be selectCodeEditor("pwm_test_db.vhd", 191, 326); // be selectCodeEditor("pwm_test_db.vhd", 90, 234); // be selectCodeEditor("pwm_test_db.vhd", 113, 281); // be // Elapsed time: 147 seconds selectCodeEditor("pwm_test_db.vhd", 193, 310); // be // Elapsed time: 11 seconds typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 407, 21); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be selectCodeEditor("pwm_test_db.vhd", 187, 229); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 215, 223); // be selectCodeEditor("pwm_test_db.vhd", 215, 223, false, false, false, false, true); // be - Double Click selectCodeEditor("pwm_test_db.vhd", 204, 289); // be selectCodeEditor("pwm_test_db.vhd", 361, 229); // be selectCodeEditor("pwm_test_db.vhd", 118, 257); // be selectButton(RDIResourceCommand.RDICommands_SAVE_FILE, (String) null); // D // TclEventType: DG_GRAPH_STALE // WARNING: HEventQueue.dispatchEvent() is taking 1774 ms. // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL selectButton("OptionPane.button", "Yes"); // JButton // TclEventType: WAVEFORM_CLOSE_WCFG // TclEventType: SIMULATION_CLOSE_SIMULATION // Tcl Message: close_sim // Tcl Message: INFO: [Simtcl 6-16] Simulation closed dismissDialog("Close"); // bA // TclEventType: LAUNCH_SIM // TclEventType: FILE_SET_OPTIONS_CHANGE // Tcl Message: launch_simulation // Tcl Message: Command: launch_simulation // Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' // Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" // TclEventType: LAUNCH_SIM_LOG // Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' // Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' // Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" // TclEventType: LAUNCH_SIM // Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim // Tcl Message: with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" // Tcl Message: INFO: [USF-XSim-8] Loading simulator feature // TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_UPDATE_TITLE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_DELAYED_MODEL_EVENT // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: SIMULATION_OBJECT_TREE_RESTORED // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 103 MB. Current time: 5/13/22, 12:41:46 PM CEST // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED // TclEventType: SIMULATION_CURRENT_STACK_CHANGED // TclEventType: SIMULATION_UPDATE_STACK_FRAMES // TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED // TclEventType: SIMULATION_UPDATE_LOCALS // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_STOPPED // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // Tcl Message: Time resolution is 1 ps // Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg // Tcl Message: source pwm_test_db.tcl // Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 5 s // Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 // Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s // Tcl Message: launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 // 'd' command handler elapsed time: 9 seconds dismissDialog("Run Simulation"); // e // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_MODEL_EVENT selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 25, 286); // b // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 42, 302); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 103 MB. Current time: 5/13/22, 12:41:51 PM CEST // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 40, 326); // b // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 31, 359); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 5); // l // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 5); // l // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 241, 207); // b // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation]", 9, true, false, false, false, true, false); // n - Popup Trigger - Node selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_SETTINGS, "Simulation Settings..."); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_SETTINGS // Tcl Command: 'rdi::info_commands {device::*}' // Tcl Command: 'rdi::info_commands {debug::*}' // Tcl Command: 'rdi::info_commands {*}' // WARNING: HEventQueue.dispatchEvent() is taking 1449 ms. // Elapsed time: 18 seconds dismissDialog("Settings"); // d // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 5, true); // l - Node // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, a[7:-6]]", 5, true, false, false, false, true, false); // l - Popup Trigger - Node selectMenu("Name"); // al selectMenu("Waveform Style"); // al selectMenu("Signal Color"); // al selectMenu("Radix"); // al selectMenu("Radix"); // al selectMenuItem((HResource) null, "Real Settings..."); // ao selectRadioButton(RDIResource.WaveformRealSettingsDialog_FIXED_POINT, "Fixed point"); // a selectRadioButton(RDIResource.WaveformRealSettingsDialog_SIGNED, "Signed"); // a setSpinner(RDIResource.WaveformRealSettingsDialog_BINARY_POINT, "28"); // V selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_TITLE dismissDialog("Real Settings"); // h // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectMenu("Waveform Style"); // al selectMenu("Signal Color"); // al selectMenu("Radix"); // al selectMenu("Radix"); // al selectMenuItem((HResource) null, "Real Settings..."); // ao selectRadioButton(RDIResource.WaveformRealSettingsDialog_FIXED_POINT, "Fixed point"); // a selectRadioButton(RDIResource.WaveformRealSettingsDialog_SIGNED, "Signed"); // a setSpinner(RDIResource.WaveformRealSettingsDialog_BINARY_POINT, "28"); // V selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_TITLE dismissDialog("Real Settings"); // h // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // [GUI Memory]: 175 MB (+3967kb) [01:09:21] selectMenu("Waveform Style"); // al selectMenu("Signal Color"); // al selectMenu("Radix"); // al selectMenu("Radix"); // al selectMenuItem((HResource) null, "Real Settings..."); // ao selectRadioButton(RDIResource.WaveformRealSettingsDialog_FIXED_POINT, "Fixed point"); // a selectRadioButton(RDIResource.WaveformRealSettingsDialog_SIGNED, "Signed"); // a setSpinner(RDIResource.WaveformRealSettingsDialog_BINARY_POINT, "28"); // V selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_UPDATE_TITLE dismissDialog("Real Settings"); // h // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 25, 444); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 67, 397); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // Run Command: RDIResourceCommand.RDICommands_WAVEFORM_SAVE_CONFIGURATION // TclEventType: WAVEFORM_UPDATE_TITLE // Tcl Message: save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} // TclEventType: FILE_SET_CHANGE // Elapsed time: 15 seconds selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 214, 544); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:23 PM CEST // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 70, 401); // b // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:24 PM CEST // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:25 PM CEST // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:25 PM CEST // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:25 PM CEST // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 119 MB. Current time: 5/13/22, 12:43:26 PM CEST selectButton(RDIResource.WaveformView_NEXT_TRANSITION, "Waveform Viewer_waveformNextTransition"); // D selectButton(RDIResource.WaveformView_PREVIOUS_TRANSITION, "Waveform Viewer_waveformPreviousTransition"); // D // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // Elapsed time: 31 seconds selectTab((HResource) null, (HResource) null, "Sources", 1); // aL selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008]", 21); // D collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File]", 24); // D expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File]", 24); // D // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: WAVEFORM_UPDATE_WAVEFORM // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 114 MB. Current time: 5/13/22, 12:44:14 PM CEST selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false, false, false, false, true, false); // D - Popup Trigger selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false, false, false, false, false, true); // D - Double Click selectButton(PAResourceOtoP.OpenFileAction_CANCEL, "Cancel"); // a dismissDialog("Unable to Open File"); // ag // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 115 MB. Current time: 5/13/22, 12:44:23 PM CEST selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false, false, false, false, false, true); // D - Double Click dismissDialog("Opening Editor"); // bA selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D selectTab((HResource) null, (HResource) null, "Messages", 1); // aL selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Compile Order", 3); // i selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false, false, false, false, true, false); // D - Popup Trigger selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008, xil_defaultlib, pwm_test_db.vhd]", 23, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, Waveform Configuration File, pwm_test_db_func_synth.wcfg]", 25, false, false, false, false, true, false); // D - Popup Trigger // Elapsed time: 148 seconds selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i // Elapsed time: 10 seconds expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Utility Sources, utils_1, Design Checkpoint]", 21); // D selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Utility Sources, utils_1, Design Checkpoint, pwm_test.dcp]", 22, false); // D // Elapsed time: 22 seconds selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 5, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 5, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 5, true, false, false, false, false, true); // ah - Double Click - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 7, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 7, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 7, true, false, false, false, false, true); // ah - Double Click - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. , [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 8, false); // ah selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. , [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 8, false, false, false, false, false, true); // ah - Double Click selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. , [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 8, false); // ah selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. , [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.. ]", 8, false, false, false, false, false, true); // ah - Double Click selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2); // ah selectCheckBox(PAResourceItoN.MsgView_ERROR_MESSAGES, (String) null, true); // g: TRUE // Elapsed time: 17 seconds selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. ]", 2, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Vivado Commands, General Messages, [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. - . while executing. source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]. , [Ip 78-89] Error in evaluating command source init.tcl. - . while executing. source init.tcl. ]", 3, false, false, false, false, false, true); // ah - Double Click // Elapsed time: 11 seconds selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages]", 33, true); // ah - Node selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 34, true); // ah - Node // Elapsed time: 12 seconds expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 34); // ah // Elapsed time: 26 seconds selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, design_1, General Messages, [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.. ]", 34, true); // ah - Node // Elapsed time: 69 seconds selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test.vhd", 1); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "wendeTangente.vhd", 2); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pt1.vhd", 3); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Cora-Z7-10-Master.xdc", 0); // m selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation-Only Sources, sim_1, VHDL 2008]", 21); // D selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db_func_synth.wcfg", 5); // m selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 165, 131); // b // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 93, 160); // b // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aL // Elapsed time: 91 seconds selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 221, 277); // b // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_UPDATE_COMMANDS // TclEventType: WAVEFORM_MOVE_CURSOR // TclEventType: WAVEFORM_UPDATE_WAVEFORM selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 13, false); // n // Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS selectButton("OptionPane.button", "OK"); // JButton // TclEventType: RUN_MODIFY // TclEventType: RUN_RESET // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_RESET // TclEventType: RUN_MODIFY // Tcl Message: reset_run synth_1 // Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp // TclEventType: FILE_SET_CHANGE selectButton(RDIResource.BaseDialog_OK, "OK"); // a dismissDialog("Launch Runs"); // f // TclEventType: RUN_LAUNCH // TclEventType: RUN_MODIFY // Tcl Message: launch_runs synth_1 -jobs 6 // Tcl Message: [Fri May 13 12:52:54 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log // 'k' command handler elapsed time: 3 seconds dismissDialog("Starting Design Runs"); // bA // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_COMPLETED // TclEventType: RUN_STATUS_CHANGE // TclEventType: RUN_STEP_COMPLETED // Elapsed time: 57 seconds selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a dismissDialog("Synthesis Completed"); // ag // Elapsed time: 32 seconds selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "pwm_test_db.vhd", 4); // m // Elapsed time: 37 seconds selectCodeEditor("pwm_test_db.vhd", 6, 121); // be selectCodeEditor("pwm_test_db.vhd", 232, 120); // be selectCodeEditor("pwm_test_db.vhd", 281, 184); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 42, 123); // be typeControlKey((HResource) null, "pwm_test_db.vhd", 'v'); // be selectCodeEditor("pwm_test_db.vhd", 2, 118); // be selectCodeEditor("pwm_test_db.vhd", 0, 126); // be selectCodeEditor("pwm_test_db.vhd", 244, 215); // be // Elapsed time: 14 seconds selectCodeEditor("pwm_test_db.vhd", 11, 109); // be selectCodeEditor("pwm_test_db.vhd", 3, 205); // be selectCodeEditor("pwm_test_db.vhd", 468, 130); // be selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Run Implementation]", 16, false); // n // Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION selectButton(PAResourceQtoS.SaveProjectUtils_CANCEL, "Cancel"); // a dismissDialog("Save Project"); // al selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation]", 9, true); // n - Node selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL selectButton("OptionPane.button", "Yes"); // JButton selectButton(RDIResource.BaseDialog_OK, "OK"); // a // TclEventType: DG_GRAPH_STALE // WARNING: HEventQueue.dispatchEvent() is taking 2453 ms. // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // TclEventType: WAVEFORM_CLOSE_WCFG // TclEventType: FILE_SET_CHANGE dismissDialog("Save Simulation Sources"); // c // TclEventType: WAVEFORM_CLOSE_WCFG // TclEventType: SIMULATION_CLOSE_SIMULATION // WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 1089 ms. Increasing delay to 3267 ms. // Tcl Message: close_sim // Tcl Message: INFO: [Simtcl 6-16] Simulation closed dismissDialog("Close"); // bA // TclEventType: LAUNCH_SIM // TclEventType: FILE_SET_OPTIONS_CHANGE // Tcl Message: launch_simulation // Tcl Message: Command: launch_simulation // Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' // Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" // Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' // Tcl Message: ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. // Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. // CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. // HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. (Run Simulation)' // 'd' command handler elapsed time: 15 seconds selectButton("OptionPane.button", "OK"); // JButton selectList(PAResourceAtoD.CmdMsgDialog_MESSAGES, "[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.", 0); // b selectList(PAResourceAtoD.CmdMsgDialog_MESSAGES, "[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.", 0); // b selectList(PAResourceAtoD.CmdMsgDialog_MESSAGES, "[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.", 0, false, false, false, false, true); // b - Double Click // Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW dismissDialog("Critical Messages"); // a selectCodeEditor("pwm_test_db.vhd", 15, 109); // be selectCodeEditor("pwm_test_db.vhd", 17, 128); // be selectCodeEditor("pwm_test_db.vhd", 249, 176); // be // Elapsed time: 17 seconds selectCodeEditor("pwm_test_db.vhd", 236, 152); // be selectCodeEditor("pwm_test_db.vhd", 167, 202); // be selectCodeEditor("pwm_test_db.vhd", 14, 126); // be selectCodeEditor("pwm_test_db.vhd", 301, 169); // be selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // n selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ao // Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a // TclEventType: DG_GRAPH_STALE // WARNING: HEventQueue.dispatchEvent() is taking 3243 ms. dismissDialog("Save Project"); // al // TclEventType: DG_GRAPH_STALE // TclEventType: FILE_SET_CHANGE // WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 2972 ms. Increasing delay to 8916 ms. // TclEventType: LAUNCH_SIM // TclEventType: FILE_SET_OPTIONS_CHANGE // Tcl Message: launch_simulation // Tcl Message: Command: launch_simulation // Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' // Tcl Message: "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" // TclEventType: LAUNCH_SIM_LOG // Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' // Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' // Tcl Message: "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" // TclEventType: LAUNCH_SIM // Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim // Tcl Message: with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" // Tcl Message: INFO: [USF-XSim-8] Loading simulator feature // TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_UPDATE_TITLE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // Tcl Message: Time resolution is 1 ps // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE // TclEventType: WAVEFORM_OPEN_WCFG // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_CLEAR_CURRENT_LINE // TclEventType: WAVEFORM_DELAYED_MODEL_EVENT // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: SIMULATION_OBJECT_TREE_RESTORED // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: SIMULATION_UPDATE_LATEST_TIME // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED // TclEventType: SIMULATION_CURRENT_STACK_CHANGED // TclEventType: SIMULATION_UPDATE_STACK_FRAMES // TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED // TclEventType: SIMULATION_UPDATE_LOCALS // TclEventType: SIMULATION_UPDATE_SCOPE_TREE // TclEventType: SIMULATION_UPDATE_STACKS // TclEventType: SIMULATION_UPDATE_OBJECT_TREE // TclEventType: SIMULATION_STOPPED // TclEventType: SIMULATION_UPDATE_SIMULATION_STATE // Tcl Message: open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg // Tcl Message: source pwm_test_db.tcl // Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 5 s // Tcl Message: ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 // Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 5 s // Tcl Message: launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 // 'd' command handler elapsed time: 12 seconds // Elapsed time: 11 seconds dismissDialog("Run Simulation"); // e // TclEventType: WAVEFORM_MODEL_EVENT // TclEventType: WAVEFORM_UPDATE_WAVEFORM // TclEventType: WAVEFORM_MODEL_EVENT // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 118 MB. Current time: 5/13/22, 1:14:23 PM CEST