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FPGA_Projekt_Regler
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  1. # ---> XilinxISE

  2. # intermediate build files

  3. *.bgn

  4. *.bit

  5. *.bld

  6. *.cmd_log

  7. *.drc

  8. *.ll

  9. *.lso

  10. *.msd

  11. *.msk

  12. *.ncd

  13. *.ngc

  14. *.ngd

  15. *.ngr

  16. *.pad

  17. *.par

  18. *.pcf

  19. *.prj

  20. *.ptwx

  21. *.rbb

  22. *.rbd

  23. *.stx

  24. *.syr

  25. *.twr

  26. *.twx

  27. *.unroutes

  28. *.ut

  29. *.xpi

  30. *.xst

  31. *_bitgen.xwbt

  32. *_envsettings.html

  33. *_map.map

  34. *_map.mrp

  35. *_map.ngm

  36. *_map.xrpt

  37. *_ngdbuild.xrpt

  38. *_pad.csv

  39. *_pad.txt

  40. *_par.xrpt

  41. *_summary.html

  42. *_summary.xml

  43. *_usage.xml

  44. *_xst.xrpt

  45. 

  46. # iMPACT generated files

  47. _impactbatch.log

  48. impact.xsl

  49. impact_impact.xwbt

  50. ise_impact.cmd

  51. webtalk_impact.xml

  52. 

  53. # Core Generator generated files

  54. xaw2verilog.log

  55. 

  56. # project-wide generated files

  57. *.gise

  58. par_usage_statistics.html

  59. usage_statistics_webtalk.html

  60. webtalk.log

  61. webtalk_pn.xml

  62. 

  63. # generated folders

  64. iseconfig/

  65. xlnx_auto_0_xdb/

  66. xst/

  67. _ngo/

  68. _xmsgs/