stammfe87185
/
FPGA_Projekt_Regler
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
3 Commits
2 Branches
Tree: 8ace88585e
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '8ace88585e'
${ noResults }
FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds

regler.vds 18KB
Raw Blame History

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233 
  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Fri May 13 12:52:57 2022

  6. # Process ID: 2508

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  8. # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. source regler.tcl -notrace

  14. create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1260.457 ; gain = 7.594

  15. Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp

  16. INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis

  17. INFO: [Vivado 12-7989] Please ensure there are no constraint changes

  18. Command: synth_design -top regler -part xc7z010clg400-1

  19. Starting synth_design

  20. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'

  21. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'

  22. INFO: [Device 21-403] Loading part xc7z010clg400-1

  23. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  24. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  25. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.

  26. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes

  27. INFO: [Synth 8-7075] Helper process launched with PID 12584

  28. ---------------------------------------------------------------------------------

  29. Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.457 ; gain = 0.000

  30. ---------------------------------------------------------------------------------

  31. INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43]

  32. WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:97]

  33. WARNING: [Synth 8-6014] Unused sequential element e_k2_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:98]

  34. INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43]

  35. ---------------------------------------------------------------------------------

  36. Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.457 ; gain = 0.000

  37. ---------------------------------------------------------------------------------

  38. ---------------------------------------------------------------------------------

  39. Start Handling Custom Attributes

  40. ---------------------------------------------------------------------------------

  41. ---------------------------------------------------------------------------------

  42. Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000

  43. ---------------------------------------------------------------------------------

  44. ---------------------------------------------------------------------------------

  45. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000

  46. ---------------------------------------------------------------------------------

  47. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1260.457 ; gain = 0.000

  48. INFO: [Project 1-570] Preparing netlist for logic optimization

  49. 

  50. Processing XDC Constraints

  51. Initializing timing engine

  52. Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  53. Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  54. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/regler_propImpl.xdc].

  55. Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.

  56. Completed Processing XDC Constraints

  57. 

  58. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1260.457 ; gain = 0.000

  59. INFO: [Project 1-111] Unisim Transformation Summary:

  60. No Unisim elements were transformed.

  61. 

  62. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1260.457 ; gain = 0.000

  63. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  64. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  65. ---------------------------------------------------------------------------------

  66. Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000

  67. ---------------------------------------------------------------------------------

  68. ---------------------------------------------------------------------------------

  69. Start Loading Part and Timing Information

  70. ---------------------------------------------------------------------------------

  71. Loading part: xc7z010clg400-1

  72. ---------------------------------------------------------------------------------

  73. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000

  74. ---------------------------------------------------------------------------------

  75. ---------------------------------------------------------------------------------

  76. Start Applying 'set_property' XDC Constraints

  77. ---------------------------------------------------------------------------------

  78. ---------------------------------------------------------------------------------

  79. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000

  80. ---------------------------------------------------------------------------------

  81. ---------------------------------------------------------------------------------

  82. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1260.457 ; gain = 0.000

  83. ---------------------------------------------------------------------------------

  84. ---------------------------------------------------------------------------------

  85. Start RTL Component Statistics 

  86. ---------------------------------------------------------------------------------

  87. Detailed RTL Component Info : 

  88. +---Adders : 

  89. 	   3 Input   32 Bit       Adders := 2     

  90. 	   2 Input   32 Bit       Adders := 1     

  91. 	   2 Input   31 Bit       Adders := 1     

  92. +---Registers : 

  93. 	               32 Bit    Registers := 2     

  94. +---Multipliers : 

  95. 	               1x32  Multipliers := 1     

  96. +---Muxes : 

  97. 	   2 Input   32 Bit        Muxes := 1     

  98. 	   2 Input   31 Bit        Muxes := 1     

  99. ---------------------------------------------------------------------------------

  100. Finished RTL Component Statistics 

  101. ---------------------------------------------------------------------------------

  102. ---------------------------------------------------------------------------------

  103. Start Part Resource Summary

  104. ---------------------------------------------------------------------------------

  105. Part Resources:

  106. DSPs: 80 (col length:40)

  107. BRAMs: 120 (col length: RAMB18 40 RAMB36 20)

  108. ---------------------------------------------------------------------------------

  109. Finished Part Resource Summary

  110. ---------------------------------------------------------------------------------

  111. ---------------------------------------------------------------------------------

  112. Start Cross Boundary and Area Optimization

  113. ---------------------------------------------------------------------------------

  114. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met

  115. ---------------------------------------------------------------------------------

  116. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1260.457 ; gain = 0.000

  117. ---------------------------------------------------------------------------------

  118. ---------------------------------------------------------------------------------

  119. Start Applying XDC Timing Constraints

  120. ---------------------------------------------------------------------------------

  121. ---------------------------------------------------------------------------------

  122. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000

  123. ---------------------------------------------------------------------------------

  124. ---------------------------------------------------------------------------------

  125. Start Timing Optimization

  126. ---------------------------------------------------------------------------------

  127. ---------------------------------------------------------------------------------

  128. Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000

  129. ---------------------------------------------------------------------------------

  130. ---------------------------------------------------------------------------------

  131. Start Technology Mapping

  132. ---------------------------------------------------------------------------------

  133. ---------------------------------------------------------------------------------

  134. Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1260.457 ; gain = 0.000

  135. ---------------------------------------------------------------------------------

  136. ---------------------------------------------------------------------------------

  137. Start IO Insertion

  138. ---------------------------------------------------------------------------------

  139. ---------------------------------------------------------------------------------

  140. Start Flattening Before IO Insertion

  141. ---------------------------------------------------------------------------------

  142. ---------------------------------------------------------------------------------

  143. Finished Flattening Before IO Insertion

  144. ---------------------------------------------------------------------------------

  145. ---------------------------------------------------------------------------------

  146. Start Final Netlist Cleanup

  147. ---------------------------------------------------------------------------------

  148. ---------------------------------------------------------------------------------

  149. Finished Final Netlist Cleanup

  150. ---------------------------------------------------------------------------------

  151. ---------------------------------------------------------------------------------

  152. Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  153. ---------------------------------------------------------------------------------

  154. ---------------------------------------------------------------------------------

  155. Start Renaming Generated Instances

  156. ---------------------------------------------------------------------------------

  157. ---------------------------------------------------------------------------------

  158. Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  159. ---------------------------------------------------------------------------------

  160. ---------------------------------------------------------------------------------

  161. Start Rebuilding User Hierarchy

  162. ---------------------------------------------------------------------------------

  163. ---------------------------------------------------------------------------------

  164. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  165. ---------------------------------------------------------------------------------

  166. ---------------------------------------------------------------------------------

  167. Start Renaming Generated Ports

  168. ---------------------------------------------------------------------------------

  169. ---------------------------------------------------------------------------------

  170. Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  171. ---------------------------------------------------------------------------------

  172. ---------------------------------------------------------------------------------

  173. Start Handling Custom Attributes

  174. ---------------------------------------------------------------------------------

  175. ---------------------------------------------------------------------------------

  176. Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  177. ---------------------------------------------------------------------------------

  178. ---------------------------------------------------------------------------------

  179. Start Renaming Generated Nets

  180. ---------------------------------------------------------------------------------

  181. ---------------------------------------------------------------------------------

  182. Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  183. ---------------------------------------------------------------------------------

  184. ---------------------------------------------------------------------------------

  185. Start Writing Synthesis Report

  186. ---------------------------------------------------------------------------------

  187. 

  188. Report BlackBoxes: 

  189. +-+--------------+----------+

  190. | |BlackBox name |Instances |

  191. +-+--------------+----------+

  192. +-+--------------+----------+

  193. 

  194. Report Cell Usage: 

  195. +------+-------+------+

  196. |      |Cell   |Count |

  197. +------+-------+------+

  198. |1     |BUFG   |     1|

  199. |2     |CARRY4 |   104|

  200. |3     |LUT1   |    66|

  201. |4     |LUT2   |    59|

  202. |5     |LUT3   |   182|

  203. |6     |LUT4   |   138|

  204. |7     |LUT5   |    49|

  205. |8     |LUT6   |   186|

  206. |9     |FDRE   |    64|

  207. |10    |IBUF   |    65|

  208. |11    |OBUF   |    32|

  209. +------+-------+------+

  210. ---------------------------------------------------------------------------------

  211. Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  212. ---------------------------------------------------------------------------------

  213. Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.

  214. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1274.391 ; gain = 13.934

  215. Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  216. INFO: [Project 1-571] Translating synthesized netlist

  217. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1286.504 ; gain = 0.000

  218. INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement

  219. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  220. INFO: [Project 1-570] Preparing netlist for logic optimization

  221. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  222. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1290.160 ; gain = 0.000

  223. INFO: [Project 1-111] Unisim Transformation Summary:

  224. No Unisim elements were transformed.

  225. 

  226. Synth Design complete, checksum: 235c9ea4

  227. INFO: [Common 17-83] Releasing license: Synthesis

  228. 21 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.

  229. synth_design completed successfully

  230. synth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.160 ; gain = 29.703

  231. INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.

  232. INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb

  233. INFO: [Common 17-206] Exiting Vivado at Fri May 13 12:53:45 2022...