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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

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  1. 

  2. *** Running vivado

  3.     with args -log regler.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl

  4. 

  5. 

  6. 

  7. ****** Vivado v2021.2 (64-bit)

  8.   **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  9.   **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  10.     ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

  11. 

  12. source regler.tcl -notrace

  13. create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1260.457 ; gain = 7.594

  14. Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp

  15. INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis

  16. INFO: [Vivado 12-7989] Please ensure there are no constraint changes

  17. Command: synth_design -top regler -part xc7z010clg400-1

  18. Starting synth_design

  19. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'

  20. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'

  21. INFO: [Device 21-403] Loading part xc7z010clg400-1

  22. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  23. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  24. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.

  25. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes

  26. INFO: [Synth 8-7075] Helper process launched with PID 12584

  27. ---------------------------------------------------------------------------------

  28. Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.457 ; gain = 0.000

  29. ---------------------------------------------------------------------------------

  30. INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43]

  31. WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:97]

  32. WARNING: [Synth 8-6014] Unused sequential element e_k2_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:98]

  33. INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43]

  34. ---------------------------------------------------------------------------------

  35. Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.457 ; gain = 0.000

  36. ---------------------------------------------------------------------------------

  37. ---------------------------------------------------------------------------------

  38. Start Handling Custom Attributes

  39. ---------------------------------------------------------------------------------

  40. ---------------------------------------------------------------------------------

  41. Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000

  42. ---------------------------------------------------------------------------------

  43. ---------------------------------------------------------------------------------

  44. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000

  45. ---------------------------------------------------------------------------------

  46. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1260.457 ; gain = 0.000

  47. INFO: [Project 1-570] Preparing netlist for logic optimization

  48. 

  49. Processing XDC Constraints

  50. Initializing timing engine

  51. Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  52. Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  53. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/regler_propImpl.xdc].

  54. Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.

  55. Completed Processing XDC Constraints

  56. 

  57. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1260.457 ; gain = 0.000

  58. INFO: [Project 1-111] Unisim Transformation Summary:

  59. No Unisim elements were transformed.

  60. 

  61. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1260.457 ; gain = 0.000

  62. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  63. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  64. ---------------------------------------------------------------------------------

  65. Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000

  66. ---------------------------------------------------------------------------------

  67. ---------------------------------------------------------------------------------

  68. Start Loading Part and Timing Information

  69. ---------------------------------------------------------------------------------

  70. Loading part: xc7z010clg400-1

  71. ---------------------------------------------------------------------------------

  72. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000

  73. ---------------------------------------------------------------------------------

  74. ---------------------------------------------------------------------------------

  75. Start Applying 'set_property' XDC Constraints

  76. ---------------------------------------------------------------------------------

  77. ---------------------------------------------------------------------------------

  78. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000

  79. ---------------------------------------------------------------------------------

  80. ---------------------------------------------------------------------------------

  81. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1260.457 ; gain = 0.000

  82. ---------------------------------------------------------------------------------

  83. ---------------------------------------------------------------------------------

  84. Start RTL Component Statistics 

  85. ---------------------------------------------------------------------------------

  86. Detailed RTL Component Info : 

  87. +---Adders : 

  88. 	   3 Input   32 Bit       Adders := 2     

  89. 	   2 Input   32 Bit       Adders := 1     

  90. 	   2 Input   31 Bit       Adders := 1     

  91. +---Registers : 

  92. 	               32 Bit    Registers := 2     

  93. +---Multipliers : 

  94. 	               1x32  Multipliers := 1     

  95. +---Muxes : 

  96. 	   2 Input   32 Bit        Muxes := 1     

  97. 	   2 Input   31 Bit        Muxes := 1     

  98. ---------------------------------------------------------------------------------

  99. Finished RTL Component Statistics 

  100. ---------------------------------------------------------------------------------

  101. ---------------------------------------------------------------------------------

  102. Start Part Resource Summary

  103. ---------------------------------------------------------------------------------

  104. Part Resources:

  105. DSPs: 80 (col length:40)

  106. BRAMs: 120 (col length: RAMB18 40 RAMB36 20)

  107. ---------------------------------------------------------------------------------

  108. Finished Part Resource Summary

  109. ---------------------------------------------------------------------------------

  110. ---------------------------------------------------------------------------------

  111. Start Cross Boundary and Area Optimization

  112. ---------------------------------------------------------------------------------

  113. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met

  114. ---------------------------------------------------------------------------------

  115. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1260.457 ; gain = 0.000

  116. ---------------------------------------------------------------------------------

  117. ---------------------------------------------------------------------------------

  118. Start Applying XDC Timing Constraints

  119. ---------------------------------------------------------------------------------

  120. ---------------------------------------------------------------------------------

  121. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000

  122. ---------------------------------------------------------------------------------

  123. ---------------------------------------------------------------------------------

  124. Start Timing Optimization

  125. ---------------------------------------------------------------------------------

  126. ---------------------------------------------------------------------------------

  127. Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000

  128. ---------------------------------------------------------------------------------

  129. ---------------------------------------------------------------------------------

  130. Start Technology Mapping

  131. ---------------------------------------------------------------------------------

  132. ---------------------------------------------------------------------------------

  133. Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1260.457 ; gain = 0.000

  134. ---------------------------------------------------------------------------------

  135. ---------------------------------------------------------------------------------

  136. Start IO Insertion

  137. ---------------------------------------------------------------------------------

  138. ---------------------------------------------------------------------------------

  139. Start Flattening Before IO Insertion

  140. ---------------------------------------------------------------------------------

  141. ---------------------------------------------------------------------------------

  142. Finished Flattening Before IO Insertion

  143. ---------------------------------------------------------------------------------

  144. ---------------------------------------------------------------------------------

  145. Start Final Netlist Cleanup

  146. ---------------------------------------------------------------------------------

  147. ---------------------------------------------------------------------------------

  148. Finished Final Netlist Cleanup

  149. ---------------------------------------------------------------------------------

  150. ---------------------------------------------------------------------------------

  151. Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  152. ---------------------------------------------------------------------------------

  153. ---------------------------------------------------------------------------------

  154. Start Renaming Generated Instances

  155. ---------------------------------------------------------------------------------

  156. ---------------------------------------------------------------------------------

  157. Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  158. ---------------------------------------------------------------------------------

  159. ---------------------------------------------------------------------------------

  160. Start Rebuilding User Hierarchy

  161. ---------------------------------------------------------------------------------

  162. ---------------------------------------------------------------------------------

  163. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  164. ---------------------------------------------------------------------------------

  165. ---------------------------------------------------------------------------------

  166. Start Renaming Generated Ports

  167. ---------------------------------------------------------------------------------

  168. ---------------------------------------------------------------------------------

  169. Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  170. ---------------------------------------------------------------------------------

  171. ---------------------------------------------------------------------------------

  172. Start Handling Custom Attributes

  173. ---------------------------------------------------------------------------------

  174. ---------------------------------------------------------------------------------

  175. Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  176. ---------------------------------------------------------------------------------

  177. ---------------------------------------------------------------------------------

  178. Start Renaming Generated Nets

  179. ---------------------------------------------------------------------------------

  180. ---------------------------------------------------------------------------------

  181. Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  182. ---------------------------------------------------------------------------------

  183. ---------------------------------------------------------------------------------

  184. Start Writing Synthesis Report

  185. ---------------------------------------------------------------------------------

  186. 

  187. Report BlackBoxes: 

  188. +-+--------------+----------+

  189. | |BlackBox name |Instances |

  190. +-+--------------+----------+

  191. +-+--------------+----------+

  192. 

  193. Report Cell Usage: 

  194. +------+-------+------+

  195. |      |Cell   |Count |

  196. +------+-------+------+

  197. |1     |BUFG   |     1|

  198. |2     |CARRY4 |   104|

  199. |3     |LUT1   |    66|

  200. |4     |LUT2   |    59|

  201. |5     |LUT3   |   182|

  202. |6     |LUT4   |   138|

  203. |7     |LUT5   |    49|

  204. |8     |LUT6   |   186|

  205. |9     |FDRE   |    64|

  206. |10    |IBUF   |    65|

  207. |11    |OBUF   |    32|

  208. +------+-------+------+

  209. ---------------------------------------------------------------------------------

  210. Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  211. ---------------------------------------------------------------------------------

  212. Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.

  213. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1274.391 ; gain = 13.934

  214. Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934

  215. INFO: [Project 1-571] Translating synthesized netlist

  216. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1286.504 ; gain = 0.000

  217. INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement

  218. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  219. INFO: [Project 1-570] Preparing netlist for logic optimization

  220. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  221. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1290.160 ; gain = 0.000

  222. INFO: [Project 1-111] Unisim Transformation Summary:

  223. No Unisim elements were transformed.

  224. 

  225. Synth Design complete, checksum: 235c9ea4

  226. INFO: [Common 17-83] Releasing license: Synthesis

  227. 21 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.

  228. synth_design completed successfully

  229. synth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.160 ; gain = 29.703

  230. INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.

  231. INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb

  232. INFO: [Common 17-206] Exiting Vivado at Fri May 13 12:53:45 2022...