| 123456789101112131415161718192021222324 |
- Vivado Simulator v2021.2
- Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
- WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
- WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.numeric_std
- Compiling package ieee.fixed_float_types
- Compiling package ieee.fixed_pkg
- Compiling package ieee.math_real
- Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
- Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
- Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]
- Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
- Built simulation snapshot pwm_test_db_behav
|
