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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/Compile_Options.txt

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  1. --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "ieee_proposed" -L "secureip" -L "xpm" --snapshot "pwm_test_db_behav" "xil_defaultlib.pwm_test_db" -log "elaborate.log"