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FPGA_Projekt_Regler
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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log

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  1. Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 53693

  2. Design successfully loaded

  3. Design Loading Memory Usage: 7256 KB (Peak: 7256 KB)

  4. Design Loading CPU Usage: 15 ms