FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.03.2022 20:07:22
-- Design Name: 
-- Module Name: pwm_test_db - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;


--use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pwm_test_db is
--  Port ( );
end pwm_test_db;

architecture Behavioral of pwm_test_db is

component regler is
    Port ( clk : in STD_LOGIC;      --Clk -> Gibt Abtastzeit vor
           w : in integer := 0;     --Sollwert
           y : in integer := 0;     --Istwert
           u : inout integer := 0); --Stellgöße
end component;

component pt1 is
    Port ( clk : in STD_LOGIC;
           u : in integer;
           y : inout integer);
end component;


component wendeTangente is
    Port ( a : in sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen
           b : in sfixed (7 downto -6);
           c : out sfixed (7 downto -6));
end component;

signal clk : std_logic := '0';
signal clk_100 : std_logic := '0';

signal w : integer := 1000000;
signal u  : integer := 0;
signal y  : integer := 0;
signal cnt : integer := 0;
signal risingEdge : std_logic := '0';


--wendetangenten test
signal a : sfixed(7 downto -6) := to_sfixed (-3.125, 7, -6);
signal b : sfixed(7 downto -6) := to_sfixed (5.1111, 7, -6);
signal c : sfixed(7 downto -6);

begin

uut_regler: regler PORT MAP (
    clk => clk,
    w => w,
    y => y,
    u => u
);

uut_pt1: pt1 PORT MAP (
    clk => clk,
    u => u,
    y => y
);

uutWendeTangente: wendeTangente PORT MAP(
    a => a,
    b => b,
    c => c
);

--generate clock
clk <= not clk after 5 us;


process 
begin
    w <= 1000000;
    
--    if rising_edge(clk) and ( cnt >= 100) then
--        clk_100 <= not clk_100;
--        cnt <= 0;
--    end if;
    
    if clk = '1' and risingEdge = '0' then
        cnt <= cnt+1;
        risingEdge <= '1';
        clk_100 <= '0';
        a <= a + to_sfixed(1.111, 7, -6);
    end if;
    
    if clk = '0' then
        risingEdge <= '0';
    end if;
        
    if cnt >= 99 then
        clk_100 <= '1';
        cnt <= 0;
    end if;
    
    wait for 1 us;
--    cnt <= cnt+1;

end process;


end Behavioral;