FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.05.2022 11:46:14
-- Design Name: 
-- Module Name: wendeTangente - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity wendeTangente is
    Port ( a : in sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen
           b : in sfixed (7 downto -6);
           c : out sfixed (7 downto -6));
end wendeTangente;

architecture Behavioral of wendeTangente is


--signal a, b, c : sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen


begin

process(a,b)

begin

    c <= a+b;


end process;


end Behavioral;