stammfe87185
/
FPGA_Projekt_Regler
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
4 Commits
2 Branches
Tree: 93029627da
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '93029627da'
${ noResults }
FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log

xsimkernel.log 323B
Raw Blame History

1234567 
  1. Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 53693

  2. Design successfully loaded

  3. Design Loading Memory Usage: 7256 KB (Peak: 7256 KB)

  4. Design Loading CPU Usage: 15 ms

  5. Simulation completed

  6. Simulation Memory Usage: 7792 KB (Peak: 7792 KB)

  7. Simulation CPU Usage: 15 ms