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- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
- ---------------------------------------------------------------------------------------------------------------------------------
- | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
- | Date : Fri May 13 14:41:51 2022
- | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
- | Command : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
- | Design : fixedPointTest
- | Device : xc7z010clg400-1
- | Speed File : -1
- | Design State : Synthesized
- ---------------------------------------------------------------------------------------------------------------------------------
-
- Report DRC
-
- Table of Contents
- -----------------
- 1. REPORT SUMMARY
- 2. REPORT DETAILS
-
- 1. REPORT SUMMARY
- -----------------
- Netlist: netlist
- Floorplan: design_1
- Design limits: <entire design considered>
- Ruledeck: default
- Max violations: <unlimited>
- Violations found: 3
- +--------+------------------+----------------------------+------------+
- | Rule | Severity | Description | Violations |
- +--------+------------------+----------------------------+------------+
- | NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
- | UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
- | ZPS7-1 | Warning | PS7 block required | 1 |
- +--------+------------------+----------------------------+------------+
-
- 2. REPORT DETAILS
- -----------------
- NSTD-1#1 Critical Warning
- Unspecified I/O Standard
- 43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], c[8:-6].
- Related violations: <none>
-
- UCIO-1#1 Critical Warning
- Unconstrained Logical Port
- 43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], c[8:-6].
- Related violations: <none>
-
- ZPS7-1#1 Warning
- PS7 block required
- The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
- Related violations: <none>
-
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