FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_power_routed.rpt

Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
| Date             : Fri May 13 14:42:10 2022
| Host             : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
| Command          : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
| Design           : fixedPointTest
| Device           : xc7z010clg400-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+----------------------------------+
| Total On-Chip Power (W)  | 10.945 (Junction temp exceeded!) |
| Design Power Budget (W)  | Unspecified*                     |
| Power Budget Margin (W)  | NA                               |
| Dynamic (W)              | 10.198                           |
| Device Static (W)        | 0.747                            |
| Effective TJA (C/W)      | 11.5                             |
| Max Ambient (C)          | 0.0                              |
| Junction Temperature (C) | 125.0                            |
| Confidence Level         | Low                              |
| Setting File             | ---                              |
| Simulation Activity File | ---                              |
| Design Nets Matched      | NA                               |
+--------------------------+----------------------------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+----------------+-----------+----------+-----------+-----------------+
| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic    |     0.051 |       21 |       --- |             --- |
|   LUT as Logic |     0.032 |       14 |     17600 |            0.08 |
|   CARRY4       |     0.019 |        4 |      4400 |            0.09 |
|   Others       |     0.000 |        2 |       --- |             --- |
| Signals        |     0.294 |       46 |       --- |             --- |
| I/O            |     9.853 |       43 |       100 |           43.00 |
| Static Power   |     0.747 |          |           |                 |
| Total          |    10.945 |          |           |                 |
+----------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.586 |       0.457 |      0.129 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.838 |       0.797 |      0.040 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     4.615 |       4.614 |      0.001 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.011 |       0.000 |      0.011 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccpint   |       1.000 |     0.473 |       0.000 |      0.473 |       NA    | Unspecified | NA         |
| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |       NA    | Unspecified | NA         |
| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |       NA    | Unspecified | NA         |
| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+----------------+-----------+
| Name           | Power (W) |
+----------------+-----------+
| fixedPointTest |    10.198 |
+----------------+-----------+