FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.rpt

Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
| Date         : Fri May 13 14:42:10 2022
| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation
| Design       : fixedPointTest
| Device       : 7z010-clg400
| Speed File   : -1  PRODUCTION 1.12 2019-11-22
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule  Severity  Description  Violations  
----  --------  -----------  ----------  

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (0)
6. checking no_output_delay (0)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (0)
------------------------------
 There are 0 input ports with no input delay specified.

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (0)
-------------------------------
 There are 0 ports with no output delay specified.

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
        inf        0.000                      0                   15          inf        0.000                      0                   15           NA           NA                      NA                    NA  


There are no user specified timing constraints.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock    
----------    ----------    --------    


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock    
----------    ----------    --------    
(none)                                    


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  

Max Delay            15 Endpoints
Min Delay            15 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[7]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        9.462ns  (logic 4.925ns (52.050%)  route 4.537ns (47.950%))
  Logic Levels:           7  (CARRY4=4 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.825 r  c_OBUF[5]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.825    c_OBUF[5]_inst_i_1_n_0
    SLICE_X43Y21         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     4.159 r  c_OBUF[8]_inst_i_1/O[1]
                         net (fo=1, routed)           2.437     6.596    c_OBUF[7]
    W13                  OBUF (Prop_obuf_I_O)         2.866     9.462 r  c_OBUF[7]_inst/O
                         net (fo=0)                   0.000     9.462    c[7]
    W13                                                               r  c[7] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[8]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        9.266ns  (logic 4.823ns (52.047%)  route 4.443ns (47.953%))
  Logic Levels:           7  (CARRY4=4 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.825 r  c_OBUF[5]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.825    c_OBUF[5]_inst_i_1_n_0
    SLICE_X43Y21         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     4.064 r  c_OBUF[8]_inst_i_1/O[2]
                         net (fo=1, routed)           2.343     6.407    c_OBUF[8]
    V12                  OBUF (Prop_obuf_I_O)         2.858     9.266 r  c_OBUF[8]_inst/O
                         net (fo=0)                   0.000     9.266    c[8]
    V12                                                               r  c[8] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[6]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        9.175ns  (logic 4.778ns (52.082%)  route 4.396ns (47.918%))
  Logic Levels:           7  (CARRY4=4 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.825 r  c_OBUF[5]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.825    c_OBUF[5]_inst_i_1_n_0
    SLICE_X43Y21         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222     4.047 r  c_OBUF[8]_inst_i_1/O[0]
                         net (fo=1, routed)           2.296     6.343    c_OBUF[6]
    T14                  OBUF (Prop_obuf_I_O)         2.831     9.175 r  c_OBUF[6]_inst/O
                         net (fo=0)                   0.000     9.175    c[6]
    T14                                                               r  c[6] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        9.173ns  (logic 4.784ns (52.155%)  route 4.389ns (47.845%))
  Logic Levels:           6  (CARRY4=3 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     4.045 r  c_OBUF[5]_inst_i_1/O[1]
                         net (fo=1, routed)           2.289     6.334    c_OBUF[3]
    R14                  OBUF (Prop_obuf_I_O)         2.839     9.173 r  c_OBUF[3]_inst/O
                         net (fo=0)                   0.000     9.173    c[3]
    R14                                                               r  c[3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        9.153ns  (logic 4.765ns (52.061%)  route 4.388ns (47.939%))
  Logic Levels:           6  (CARRY4=3 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     4.024 r  c_OBUF[5]_inst_i_1/O[3]
                         net (fo=1, routed)           2.288     6.312    c_OBUF[5]
    T15                  OBUF (Prop_obuf_I_O)         2.841     9.153 r  c_OBUF[5]_inst/O
                         net (fo=0)                   0.000     9.153    c[5]
    T15                                                               r  c[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[1]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        9.090ns  (logic 4.700ns (51.703%)  route 4.390ns (48.297%))
  Logic Levels:           5  (CARRY4=2 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     3.910 r  c_OBUF[1]_inst_i_1/O[3]
                         net (fo=1, routed)           2.290     6.201    c_OBUF[1]
    Y17                  OBUF (Prop_obuf_I_O)         2.890     9.090 r  c_OBUF[1]_inst/O
                         net (fo=0)                   0.000     9.090    c[1]
    Y17                                                               r  c[1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[-1]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        9.079ns  (logic 4.743ns (52.242%)  route 4.336ns (47.758%))
  Logic Levels:           5  (CARRY4=2 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     3.931 r  c_OBUF[1]_inst_i_1/O[1]
                         net (fo=1, routed)           2.236     6.167    c_OBUF[-1]
    Y14                  OBUF (Prop_obuf_I_O)         2.912     9.079 r  c_OBUF[-1]_inst/O
                         net (fo=0)                   0.000     9.079    c[-1]
    Y14                                                               r  c[-1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[4]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        9.079ns  (logic 4.693ns (51.693%)  route 4.386ns (48.307%))
  Logic Levels:           6  (CARRY4=3 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     3.950 r  c_OBUF[5]_inst_i_1/O[2]
                         net (fo=1, routed)           2.286     6.236    c_OBUF[4]
    P14                  OBUF (Prop_obuf_I_O)         2.843     9.079 r  c_OBUF[4]_inst/O
                         net (fo=0)                   0.000     9.079    c[4]
    P14                                                               r  c[4] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        8.971ns  (logic 4.723ns (52.647%)  route 4.248ns (47.353%))
  Logic Levels:           6  (CARRY4=3 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.711 r  c_OBUF[1]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.711    c_OBUF[1]_inst_i_1_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222     3.933 r  c_OBUF[5]_inst_i_1/O[0]
                         net (fo=1, routed)           2.148     6.081    c_OBUF[2]
    Y16                  OBUF (Prop_obuf_I_O)         2.890     8.971 r  c_OBUF[2]_inst/O
                         net (fo=0)                   0.000     8.971    c[2]
    Y16                                                               r  c[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[-3]
                            (input port)
  Destination:            c[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        8.884ns  (logic 4.645ns (52.282%)  route 4.239ns (47.718%))
  Logic Levels:           5  (CARRY4=2 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  a[-3] (IN)
                         net (fo=0)                   0.000     0.000    a[-3]
    P18                  IBUF (Prop_ibuf_I_O)         0.972     0.972 r  a_IBUF[-3]_inst/O
                         net (fo=2, routed)           2.100     3.072    a_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I0_O)        0.124     3.196 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     3.196    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401     3.597 r  c_OBUF[-3]_inst_i_1/CO[3]
                         net (fo=1, routed)           0.000     3.597    c_OBUF[-3]_inst_i_1_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     3.836 r  c_OBUF[1]_inst_i_1/O[2]
                         net (fo=1, routed)           2.139     5.975    c_OBUF[0]
    W14                  OBUF (Prop_obuf_I_O)         2.909     8.884 r  c_OBUF[0]_inst/O
                         net (fo=0)                   0.000     8.884    c[0]
    W14                                                               r  c[0] (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 b[-3]
                            (input port)
  Destination:            c[-3]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.431ns  (logic 1.568ns (64.485%)  route 0.863ns (35.515%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    W20                                               0.000     0.000 r  b[-3] (IN)
                         net (fo=0)                   0.000     0.000    b[-3]
    W20                  IBUF (Prop_ibuf_I_O)         0.206     0.206 r  b_IBUF[-3]_inst/O
                         net (fo=1, routed)           0.329     0.534    b_IBUF[-3]
    SLICE_X43Y18         LUT2 (Prop_lut2_I1_O)        0.045     0.579 r  c_OBUF[-3]_inst_i_2/O
                         net (fo=1, routed)           0.000     0.579    c_OBUF[-3]_inst_i_2_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.063     0.642 r  c_OBUF[-3]_inst_i_1/O[3]
                         net (fo=1, routed)           0.535     1.177    c_OBUF[-3]
    U17                  OBUF (Prop_obuf_I_O)         1.254     2.431 r  c_OBUF[-3]_inst/O
                         net (fo=0)                   0.000     2.431    c[-3]
    U17                                                               r  c[-3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 b[-5]
                            (input port)
  Destination:            c[-5]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.505ns  (logic 1.604ns (64.018%)  route 0.901ns (35.982%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    Y19                                               0.000     0.000 r  b[-5] (IN)
                         net (fo=0)                   0.000     0.000    b[-5]
    Y19                  IBUF (Prop_ibuf_I_O)         0.205     0.205 r  b_IBUF[-5]_inst/O
                         net (fo=1, routed)           0.375     0.580    b_IBUF[-5]
    SLICE_X43Y18         LUT2 (Prop_lut2_I1_O)        0.045     0.625 r  c_OBUF[-3]_inst_i_4/O
                         net (fo=1, routed)           0.000     0.625    c_OBUF[-3]_inst_i_4_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.065     0.690 r  c_OBUF[-3]_inst_i_1/O[1]
                         net (fo=1, routed)           0.527     1.217    c_OBUF[-5]
    W15                  OBUF (Prop_obuf_I_O)         1.288     2.505 r  c_OBUF[-5]_inst/O
                         net (fo=0)                   0.000     2.505    c[-5]
    W15                                                               r  c[-5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 b[-6]
                            (input port)
  Destination:            c[-6]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.520ns  (logic 1.587ns (62.965%)  route 0.933ns (37.035%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    V16                                               0.000     0.000 r  b[-6] (IN)
                         net (fo=0)                   0.000     0.000    b[-6]
    V16                  IBUF (Prop_ibuf_I_O)         0.185     0.185 r  b_IBUF[-6]_inst/O
                         net (fo=1, routed)           0.461     0.646    b_IBUF[-6]
    SLICE_X43Y18         LUT2 (Prop_lut2_I1_O)        0.045     0.691 r  c_OBUF[-3]_inst_i_5/O
                         net (fo=1, routed)           0.000     0.691    c_OBUF[-3]_inst_i_5_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.070     0.761 r  c_OBUF[-3]_inst_i_1/O[0]
                         net (fo=1, routed)           0.473     1.233    c_OBUF[-6]
    U14                  OBUF (Prop_obuf_I_O)         1.287     2.520 r  c_OBUF[-6]_inst/O
                         net (fo=0)                   0.000     2.520    c[-6]
    U14                                                               r  c[-6] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 b[-2]
                            (input port)
  Destination:            c[-2]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.529ns  (logic 1.573ns (62.198%)  route 0.956ns (37.802%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    V20                                               0.000     0.000 r  b[-2] (IN)
                         net (fo=0)                   0.000     0.000    b[-2]
    V20                  IBUF (Prop_ibuf_I_O)         0.204     0.204 r  b_IBUF[-2]_inst/O
                         net (fo=1, routed)           0.419     0.622    b_IBUF[-2]
    SLICE_X43Y19         LUT2 (Prop_lut2_I1_O)        0.045     0.667 r  c_OBUF[1]_inst_i_5/O
                         net (fo=1, routed)           0.000     0.667    c_OBUF[1]_inst_i_5_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.070     0.737 r  c_OBUF[1]_inst_i_1/O[0]
                         net (fo=1, routed)           0.537     1.275    c_OBUF[-2]
    T16                  OBUF (Prop_obuf_I_O)         1.254     2.529 r  c_OBUF[-2]_inst/O
                         net (fo=0)                   0.000     2.529    c[-2]
    T16                                                               r  c[-2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 b[-1]
                            (input port)
  Destination:            c[-1]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.576ns  (logic 1.613ns (62.626%)  route 0.963ns (37.374%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    U20                                               0.000     0.000 r  b[-1] (IN)
                         net (fo=0)                   0.000     0.000    b[-1]
    U20                  IBUF (Prop_ibuf_I_O)         0.193     0.193 r  b_IBUF[-1]_inst/O
                         net (fo=1, routed)           0.375     0.567    b_IBUF[-1]
    SLICE_X43Y19         LUT2 (Prop_lut2_I1_O)        0.045     0.612 r  c_OBUF[1]_inst_i_4/O
                         net (fo=1, routed)           0.000     0.612    c_OBUF[1]_inst_i_4_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.065     0.677 r  c_OBUF[1]_inst_i_1/O[1]
                         net (fo=1, routed)           0.588     1.265    c_OBUF[-1]
    Y14                  OBUF (Prop_obuf_I_O)         1.311     2.576 r  c_OBUF[-1]_inst/O
                         net (fo=0)                   0.000     2.576    c[-1]
    Y14                                                               r  c[-1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 b[0]
                            (input port)
  Destination:            c[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.593ns  (logic 1.617ns (62.342%)  route 0.977ns (37.658%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    T20                                               0.000     0.000 r  b[0] (IN)
                         net (fo=0)                   0.000     0.000    b[0]
    T20                  IBUF (Prop_ibuf_I_O)         0.196     0.196 r  b_IBUF[0]_inst/O
                         net (fo=1, routed)           0.420     0.616    b_IBUF[0]
    SLICE_X43Y19         LUT2 (Prop_lut2_I1_O)        0.045     0.661 r  c_OBUF[1]_inst_i_3/O
                         net (fo=1, routed)           0.000     0.661    c_OBUF[1]_inst_i_3_n_0
    SLICE_X43Y19         CARRY4 (Prop_carry4_S[2]_O[2])
                                                      0.066     0.727 r  c_OBUF[1]_inst_i_1/O[2]
                         net (fo=1, routed)           0.557     1.284    c_OBUF[0]
    W14                  OBUF (Prop_obuf_I_O)         1.309     2.593 r  c_OBUF[0]_inst/O
                         net (fo=0)                   0.000     2.593    c[0]
    W14                                                               r  c[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[5]
                            (input port)
  Destination:            c[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.595ns  (logic 1.510ns (58.186%)  route 1.085ns (41.814%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    R17                                               0.000     0.000 r  a[5] (IN)
                         net (fo=0)                   0.000     0.000    a[5]
    R17                  IBUF (Prop_ibuf_I_O)         0.161     0.161 r  a_IBUF[5]_inst/O
                         net (fo=2, routed)           0.467     0.628    a_IBUF[5]
    SLICE_X43Y20         LUT2 (Prop_lut2_I0_O)        0.045     0.673 r  c_OBUF[5]_inst_i_2/O
                         net (fo=1, routed)           0.000     0.673    c_OBUF[5]_inst_i_2_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.063     0.736 r  c_OBUF[5]_inst_i_1/O[3]
                         net (fo=1, routed)           0.618     1.354    c_OBUF[5]
    T15                  OBUF (Prop_obuf_I_O)         1.241     2.595 r  c_OBUF[5]_inst/O
                         net (fo=0)                   0.000     2.595    c[5]
    T15                                                               r  c[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 b[-5]
                            (input port)
  Destination:            c[-4]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.603ns  (logic 1.698ns (65.228%)  route 0.905ns (34.772%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    Y19                                               0.000     0.000 r  b[-5] (IN)
                         net (fo=0)                   0.000     0.000    b[-5]
    Y19                  IBUF (Prop_ibuf_I_O)         0.205     0.205 r  b_IBUF[-5]_inst/O
                         net (fo=1, routed)           0.375     0.580    b_IBUF[-5]
    SLICE_X43Y18         LUT2 (Prop_lut2_I1_O)        0.045     0.625 r  c_OBUF[-3]_inst_i_4/O
                         net (fo=1, routed)           0.000     0.625    c_OBUF[-3]_inst_i_4_n_0
    SLICE_X43Y18         CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.152     0.777 r  c_OBUF[-3]_inst_i_1/O[2]
                         net (fo=1, routed)           0.531     1.307    c_OBUF[-4]
    V15                  OBUF (Prop_obuf_I_O)         1.296     2.603 r  c_OBUF[-4]_inst/O
                         net (fo=0)                   0.000     2.603    c[-4]
    V15                                                               r  c[-4] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 b[2]
                            (input port)
  Destination:            c[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.608ns  (logic 1.615ns (61.934%)  route 0.993ns (38.066%))
  Logic Levels:           4  (CARRY4=1 IBUF=1 LUT2=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    N20                                               0.000     0.000 r  b[2] (IN)
                         net (fo=0)                   0.000     0.000    b[2]
    N20                  IBUF (Prop_ibuf_I_O)         0.208     0.208 r  b_IBUF[2]_inst/O
                         net (fo=1, routed)           0.435     0.643    b_IBUF[2]
    SLICE_X43Y20         LUT2 (Prop_lut2_I1_O)        0.045     0.688 r  c_OBUF[5]_inst_i_5/O
                         net (fo=1, routed)           0.000     0.688    c_OBUF[5]_inst_i_5_n_0
    SLICE_X43Y20         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.070     0.758 r  c_OBUF[5]_inst_i_1/O[0]
                         net (fo=1, routed)           0.558     1.316    c_OBUF[2]
    Y16                  OBUF (Prop_obuf_I_O)         1.293     2.608 r  c_OBUF[2]_inst/O
                         net (fo=0)                   0.000     2.608    c[2]
    Y16                                                               r  c[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 a[2]
                            (input port)
  Destination:            c[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.631ns  (logic 1.552ns (58.994%)  route 1.079ns (41.006%))
  Logic Levels:           3  (CARRY4=1 IBUF=1 OBUF=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    V17                                               0.000     0.000 r  a[2] (IN)
                         net (fo=0)                   0.000     0.000    a[2]
    V17                  IBUF (Prop_ibuf_I_O)         0.190     0.190 r  a_IBUF[2]_inst/O
                         net (fo=2, routed)           0.467     0.657    a_IBUF[2]
    SLICE_X43Y20         CARRY4 (Prop_carry4_DI[0]_O[1])
                                                      0.124     0.781 r  c_OBUF[5]_inst_i_1/O[1]
                         net (fo=1, routed)           0.612     1.393    c_OBUF[3]
    R14                  OBUF (Prop_obuf_I_O)         1.239     2.631 r  c_OBUF[3]_inst/O
                         net (fo=0)                   0.000     2.631    c[3]
    R14                                                               r  c[3] (OUT)
  -------------------------------------------------------------------    -------------------