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-
- *** Running vivado
- with args -log fixedPointTest.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
-
-
-
- ****** Vivado v2021.2 (64-bit)
- **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
- **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
- ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-
- source fixedPointTest.tcl -notrace
- create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 10.250
- Command: link_design -top fixedPointTest -part xc7z010clg400-1
- Design is defaulting to srcset: sources_1
- Design is defaulting to constrset: constrs_1
- INFO: [Device 21-403] Loading part xc7z010clg400-1
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.340 ; gain = 0.000
- INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
- INFO: [Project 1-479] Netlist was created with Vivado 2021.2
- INFO: [Project 1-570] Preparing netlist for logic optimization
- Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
- WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
- CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]
- Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
- WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
- CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]
- Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
- WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
- CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]
- Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
- WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
- CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]
- Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
- WARNING: [Vivado 12-584] No ports matched 'led1_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
- CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15]
- Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
- WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
- CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]
- Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
- WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
- CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]
- Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
- Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.340 ; gain = 0.000
- INFO: [Project 1-111] Unisim Transformation Summary:
- No Unisim elements were transformed.
-
- 7 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
- link_design completed successfully
- link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 0.000
- Command: opt_design
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
- Running DRC as a precondition to command opt_design
-
- Starting DRC Task
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Project 1-461] DRC finished with 0 Errors
- INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.340 ; gain = 0.000
-
- Starting Cache Timing Information Task
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- Ending Cache Timing Information Task | Checksum: d688f8fa
-
- Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1387.457 ; gain = 126.117
-
- Starting Logic Optimization Task
-
- Phase 1 Retarget
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- INFO: [Opt 31-49] Retargeted 0 cell(s).
- Phase 1 Retarget | Checksum: d688f8fa
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1683.215 ; gain = 0.000
- INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
-
- Phase 2 Constant propagation
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- Phase 2 Constant propagation | Checksum: d688f8fa
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1683.215 ; gain = 0.000
- INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
-
- Phase 3 Sweep
- Phase 3 Sweep | Checksum: 9d9fcb97
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1683.215 ; gain = 0.000
- INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
-
- Phase 4 BUFG optimization
- Phase 4 BUFG optimization | Checksum: 9d9fcb97
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1683.215 ; gain = 0.000
- INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
- Phase 5 Shift Register Optimization
- INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
- Phase 5 Shift Register Optimization | Checksum: 9d9fcb97
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
- INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
- Phase 6 Post Processing Netlist
- Phase 6 Post Processing Netlist | Checksum: 9d9fcb97
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
- INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
- Opt_design Change Summary
- =========================
-
-
- -------------------------------------------------------------------------------------------------------------------------
- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
- -------------------------------------------------------------------------------------------------------------------------
- | Retarget | 0 | 0 | 0 |
- | Constant propagation | 0 | 0 | 0 |
- | Sweep | 0 | 0 | 0 |
- | BUFG optimization | 0 | 0 | 0 |
- | Shift Register Optimization | 0 | 0 | 0 |
- | Post Processing Netlist | 0 | 0 | 0 |
- -------------------------------------------------------------------------------------------------------------------------
-
-
-
- Starting Connectivity Check Task
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1683.215 ; gain = 0.000
- Ending Logic Optimization Task | Checksum: f158031e
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1683.215 ; gain = 0.000
-
- Starting Power Optimization Task
- INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
- Ending Power Optimization Task | Checksum: f158031e
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000
-
- Starting Final Cleanup Task
- Ending Final Cleanup Task | Checksum: f158031e
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
-
- Starting Netlist Obfuscation Task
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
- Ending Netlist Obfuscation Task | Checksum: f158031e
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000
- INFO: [Common 17-83] Releasing license: Implementation
- 24 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
- opt_design completed successfully
- opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1683.215 ; gain = 421.875
- INFO: [Timing 38-480] Writing timing data to binary archive.
- INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp' has been generated.
- INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
- Command: report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx
- INFO: [IP_Flow 19-234] Refreshing IP repositories
- INFO: [IP_Flow 19-1704] No user IP repositories specified
- INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt.
- report_drc completed successfully
- Command: place_design
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
- Running DRC as a precondition to command place_design
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-
- Starting Placer Task
- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
-
- Phase 1 Placer Initialization
-
- Phase 1.1 Placer Initialization Netlist Sorting
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c5371e47
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170083491
-
- Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 1.3 Build Placer Netlist Model
- Phase 1.3 Build Placer Netlist Model | Checksum: 1e3fab18a
-
- Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.149 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 1.4 Constrain Clocks/Macros
- Phase 1.4 Constrain Clocks/Macros | Checksum: 1e3fab18a
-
- Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Phase 1 Placer Initialization | Checksum: 1e3fab18a
-
- Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.152 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 2 Global Placement
-
- Phase 2.1 Floorplanning
- Phase 2.1 Floorplanning | Checksum: 1e3fab18a
-
- Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 2.2 Update Timing before SLR Path Opt
- Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e3fab18a
-
- Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 2.3 Post-Processing in Floorplanning
- Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e3fab18a
-
- Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 2.4 Global Placement Core
- WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
- Phase 2.4 Global Placement Core | Checksum: 17701980b
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Phase 2 Global Placement | Checksum: 17701980b
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 3 Detail Placement
-
- Phase 3.1 Commit Multi Column Macros
- Phase 3.1 Commit Multi Column Macros | Checksum: 17701980b
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 3.2 Commit Most Macros & LUTRAMs
- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.699 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 3.3 Area Swap Optimization
- Phase 3.3 Area Swap Optimization | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 3.4 Pipeline Register Optimization
- Phase 3.4 Pipeline Register Optimization | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 3.5 Small Shape Detail Placement
- Phase 3.5 Small Shape Detail Placement | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 3.6 Re-assign LUT pins
- Phase 3.6 Re-assign LUT pins | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 3.7 Pipeline Register Optimization
- Phase 3.7 Pipeline Register Optimization | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Phase 3 Detail Placement | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 4 Post Placement Optimization and Clean-Up
-
- Phase 4.1 Post Commit Optimization
- Phase 4.1 Post Commit Optimization | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 4.2 Post Placement Cleanup
- Phase 4.2 Post Placement Cleanup | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.773 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 4.3 Placer Reporting
-
- Phase 4.3.1 Print Estimated Congestion
- INFO: [Place 30-612] Post-Placement Estimated Congestion
- ____________________________________________________
- | | Global Congestion | Short Congestion |
- | Direction | Region Size | Region Size |
- |___________|___________________|___________________|
- | North| 1x1| 1x1|
- |___________|___________________|___________________|
- | South| 1x1| 1x1|
- |___________|___________________|___________________|
- | East| 1x1| 1x1|
- |___________|___________________|___________________|
- | West| 1x1| 1x1|
- |___________|___________________|___________________|
-
- Phase 4.3.1 Print Estimated Congestion | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Phase 4.3 Placer Reporting | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Phase 4.4 Final Placement Cleanup
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236ae8e9c
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Ending Placer Task | Checksum: 1c0019b8b
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000
- INFO: [Common 17-83] Releasing license: Implementation
- 43 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
- place_design completed successfully
- INFO: [Timing 38-480] Writing timing data to binary archive.
- Writing placer database...
- Writing XDEF routing.
- Writing XDEF routing logical nets.
- Writing XDEF routing special nets.
- Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1722.266 ; gain = 0.000
- INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp' has been generated.
- INFO: [runtcl-4] Executing : report_io -file fixedPointTest_io_placed.rpt
- report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1722.266 ; gain = 0.000
- INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb
- INFO: [runtcl-4] Executing : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt
- report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1722.266 ; gain = 0.000
- Command: phys_opt_design
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
- INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
- INFO: [Common 17-83] Releasing license: Implementation
- 51 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
- phys_opt_design completed successfully
- INFO: [Timing 38-480] Writing timing data to binary archive.
- Writing placer database...
- Writing XDEF routing.
- Writing XDEF routing logical nets.
- Writing XDEF routing special nets.
- Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1722.266 ; gain = 0.000
- INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp' has been generated.
- Command: route_design
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
- Running DRC as a precondition to command route_design
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-
-
- Starting Routing Task
- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
-
- Phase 1 Build RT Design
- Checksum: PlaceDB: faca7d44 ConstDB: 0 ShapeSum: c5371e47 RouteDB: 0
- Post Restoration Checksum: NetGraph: 54150718 NumContArr: b3d68f27 Constraints: 0 Timing: 0
- Phase 1 Build RT Design | Checksum: 107eb963f
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1757.188 ; gain = 23.668
-
- Phase 2 Router Initialization
- INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
-
- Phase 2.1 Fix Topology Constraints
- Phase 2.1 Fix Topology Constraints | Checksum: 107eb963f
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699
-
- Phase 2.2 Pre Route Cleanup
- Phase 2.2 Pre Route Cleanup | Checksum: 107eb963f
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699
- Number of Nodes with overlaps = 0
-
- Router Utilization Summary
- Global Vertical Routing Utilization = 0 %
- Global Horizontal Routing Utilization = 0 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 46
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 46
- Number of Partially Routed Nets = 0
- Number of Node Overlaps = 0
-
- Phase 2 Router Initialization | Checksum: d7f76c92
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
-
- Phase 3 Initial Routing
-
- Phase 3.1 Global Routing
- Phase 3.1 Global Routing | Checksum: d7f76c92
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
- Phase 3 Initial Routing | Checksum: aa1bb3ea
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
-
- Phase 4 Rip-up And Reroute
-
- Phase 4.1 Global Iteration 0
- Number of Nodes with overlaps = 0
- Phase 4.1 Global Iteration 0 | Checksum: 1a2c45faa
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
- Phase 4 Rip-up And Reroute | Checksum: 1a2c45faa
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
-
- Phase 5 Delay and Skew Optimization
- Phase 5 Delay and Skew Optimization | Checksum: 1a2c45faa
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
-
- Phase 6 Post Hold Fix
-
- Phase 6.1 Hold Fix Iter
- Phase 6.1 Hold Fix Iter | Checksum: 1a2c45faa
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
- Phase 6 Post Hold Fix | Checksum: 1a2c45faa
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
-
- Phase 7 Route finalize
-
- Router Utilization Summary
- Global Vertical Routing Utilization = 0.0663007 %
- Global Horizontal Routing Utilization = 0.0248162 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 0
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 0
- Number of Partially Routed Nets = 0
- Number of Node Overlaps = 0
-
- Congestion Report
- North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
- South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions.
- East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
- West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions.
-
- ------------------------------
- Reporting congestion hotspots
- ------------------------------
- Direction: North
- ----------------
- Congested clusters found at Level 0
- Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
- Direction: South
- ----------------
- Congested clusters found at Level 0
- Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
- Direction: East
- ----------------
- Congested clusters found at Level 0
- Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
- Direction: West
- ----------------
- Congested clusters found at Level 0
- Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-
- Phase 7 Route finalize | Checksum: 1a2c45faa
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805
-
- Phase 8 Verifying routed nets
-
- Verification completed successfully
- Phase 8 Verifying routed nets | Checksum: 1a2c45faa
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
-
- Phase 9 Depositing Routes
- Phase 9 Depositing Routes | Checksum: 156fe757f
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
- INFO: [Route 35-16] Router Completed Successfully
-
- Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910
-
- Routing Is Done.
- INFO: [Common 17-83] Releasing license: Implementation
- 61 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered.
- route_design completed successfully
- route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1765.430 ; gain = 43.164
- INFO: [Timing 38-480] Writing timing data to binary archive.
- Writing placer database...
- Writing XDEF routing.
- Writing XDEF routing logical nets.
- Writing XDEF routing special nets.
- Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1775.246 ; gain = 9.816
- INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp' has been generated.
- INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
- Command: report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx
- INFO: [IP_Flow 19-1839] IP Catalog is up to date.
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt.
- report_drc completed successfully
- INFO: [runtcl-4] Executing : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
- Command: report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- INFO: [DRC 23-133] Running Methodology with 2 threads
- INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt.
- report_methodology completed successfully
- INFO: [runtcl-4] Executing : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
- Command: report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
- Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
- Running Vector-less Activity Propagation...
-
- Finished Running Vector-less Activity Propagation
- 73 Infos, 9 Warnings, 7 Critical Warnings and 0 Errors encountered.
- report_power completed successfully
- INFO: [runtcl-4] Executing : report_route_status -file fixedPointTest_route_status.rpt -pb fixedPointTest_route_status.pb
- INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation
- INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
- INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
- WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
- INFO: [runtcl-4] Executing : report_incremental_reuse -file fixedPointTest_incremental_reuse_routed.rpt
- INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
- INFO: [runtcl-4] Executing : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt
- INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx
- INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
- INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
- INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:42:11 2022...
-
- *** Running vivado
- with args -log fixedPointTest.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace
-
-
-
- ****** Vivado v2021.2 (64-bit)
- **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
- **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
- ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-
- source fixedPointTest.tcl -notrace
- Command: open_checkpoint fixedPointTest_routed.dcp
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1251.590 ; gain = 0.000
- INFO: [Device 21-403] Loading part xc7z010clg400-1
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1251.590 ; gain = 0.000
- INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
- INFO: [Project 1-479] Netlist was created with Vivado 2021.2
- INFO: [Project 1-570] Preparing netlist for logic optimization
- INFO: [Timing 38-478] Restoring timing data from binary archive.
- INFO: [Timing 38-479] Binary timing data restore complete.
- INFO: [Project 1-856] Restoring constraints from binary archive.
- INFO: [Project 1-853] Binary constraint restore complete.
- Reading XDEF placement.
- Reading placer database...
- Reading XDEF routing.
- Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1387.207 ; gain = 17.668
- Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
- Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1387.207 ; gain = 17.668
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1387.207 ; gain = 0.000
- INFO: [Project 1-111] Unisim Transformation Summary:
- No Unisim elements were transformed.
-
- INFO: [Project 1-604] Checkpoint was created with Vivado v2021.2 (64-bit) build 3367213
- open_checkpoint: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1387.207 ; gain = 135.617
- Command: write_bitstream -force fixedPointTest.bit
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
- Running DRC as a precondition to command write_bitstream
- INFO: [IP_Flow 19-234] Refreshing IP repositories
- INFO: [IP_Flow 19-1704] No user IP repositories specified
- INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
- INFO: [DRC 23-27] Running DRC with 2 threads
- ERROR: [DRC NSTD-1] Unspecified I/O Standard: 43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], and c[8:-6].
- ERROR: [DRC UCIO-1] Unconstrained Logical Port: 43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], and c[8:-6].
- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
- INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings
- INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
- ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
- INFO: [Common 17-83] Releasing license: Implementation
- 19 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered.
- write_bitstream failed
- ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
-
- INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:43:07 2022...
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