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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_10280.backup.log

vivado_10280.backup.log 26KB
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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Tue Mar 29 10:43:14 2022

  6. # Process ID: 10280

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test

  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18072 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. start_gui

  14. open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr

  15. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  16. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  17. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  18. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  19. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  20. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available

  21. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available

  22. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available

  23. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  24. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  25. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  26. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  27. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available

  28. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  29. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  30. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  31. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available

  32. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available

  33. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available

  34. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available

  35. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available

  36. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  37. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  38. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available

  39. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available

  40. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  41. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  42. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  43. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  44. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  45. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  46. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  47. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available

  48. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  49. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  50. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  51. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available

  52. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available

  53. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  54. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  55. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  56. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  57. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  58. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available

  59. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available

  60. INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'.

  61. Scanning sources...

  62. Finished scanning sources

  63. INFO: [IP_Flow 19-234] Refreshing IP repositories

  64. INFO: [IP_Flow 19-1704] No user IP repositories specified

  65. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.

  66. open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 1251.211 ; gain = 0.000

  67. update_compile_order -fileset sources_1

  68. launch_simulation

  69. Command: launch_simulation 

  70. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  71. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  72. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  73. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  74. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  75. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  76. INFO: [USF-XSim-97] Finding global include files...

  77. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  78. INFO: [USF-XSim-2] XSim::Compile design

  79. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  80. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  81. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  82. INFO: [VRFC 10-3107] analyzing entity 'pwm_test'

  83. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  84. INFO: [USF-XSim-3] XSim::Elaborate design

  85. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  86. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  87. Vivado Simulator v2021.2

  88. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  89. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  90. Using 2 slave threads.

  91. Starting static elaboration

  92. Completed static elaboration

  93. Starting simulation data flow analysis

  94. Completed simulation data flow analysis

  95. Time Resolution for simulation is 1ps

  96. Compiling package std.standard

  97. Compiling package std.textio

  98. Compiling package ieee.std_logic_1164

  99. Compiling architecture behavioral of entity xil_defaultlib.pwm_test [pwm_test_default]

  100. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  101. Built simulation snapshot pwm_test_db_behav

  102. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  103. INFO: [USF-XSim-4] XSim::Simulate design

  104. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  105. INFO: [USF-XSim-98] *** Running xsim

  106.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  107. INFO: [USF-XSim-8] Loading simulator feature

  108. Time resolution is 1 ps

  109. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg

  110. source pwm_test_db.tcl

  111. # set curr_wave [current_wave_config]

  112. # if { [string length $curr_wave] == 0 } {

  113. #   if { [llength [get_objects]] > 0} {

  114. #     add_wave /

  115. #     set_property needs_save false [current_wave_config]

  116. #   } else {

  117. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  118. #   }

  119. # }

  120. # run 5 ms

  121. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  122. INFO: [USF-XSim-97] XSim simulation ran for 5 ms

  123. launch_simulation: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1251.211 ; gain = 0.000

  124. reset_run synth_1

  125. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp

  126. WARNING: [Vivado 12-1017] Problems encountered:

  127. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

  128. 

  129. launch_runs synth_1 -jobs 6

  130. [Tue Mar 29 11:00:35 2022] Launched synth_1...

  131. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log

  132. open_run synth_1 -name synth_1

  133. Design is defaulting to impl run constrset: constrs_1

  134. Design is defaulting to synth run part: xc7z010clg400-1

  135. INFO: [Device 21-403] Loading part xc7z010clg400-1

  136. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1532.922 ; gain = 0.000

  137. INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement

  138. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  139. INFO: [Project 1-479] Netlist was created with Vivado 2021.2

  140. INFO: [Project 1-570] Preparing netlist for logic optimization

  141. Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  142. WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]

  143. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:11]

  144. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

  145. WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]

  146. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:12]

  147. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

  148. WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]

  149. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:13]

  150. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

  151. WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]

  152. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:16]

  153. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

  154. WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]

  155. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc:17]

  156. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

  157. Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  158. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  159. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1627.844 ; gain = 0.000

  160. INFO: [Project 1-111] Unisim Transformation Summary:

  161. No Unisim elements were transformed.

  162. 

  163. open_run: Time (s): cpu = 00:00:16 ; elapsed = 00:00:08 . Memory (MB): peak = 1746.418 ; gain = 495.207

  164. set_property IOSTANDARD LVCMOS33 [get_ports [list clk]]

  165. save_constraints

  166. launch_runs impl_1 -jobs 6

  167. INFO: [Timing 38-480] Writing timing data to binary archive.

  168. Writing placer database...

  169. Writing XDEF routing.

  170. Writing XDEF routing logical nets.

  171. Writing XDEF routing special nets.

  172. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2221.637 ; gain = 0.000

  173. [Tue Mar 29 11:09:22 2022] Launched impl_1...

  174. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log

  175. launch_runs impl_1 -to_step write_bitstream -jobs 6

  176. [Tue Mar 29 11:10:24 2022] Launched impl_1...

  177. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log

  178. close_design

  179. open_run impl_1

  180. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2222.562 ; gain = 0.000

  181. INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement

  182. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  183. INFO: [Project 1-479] Netlist was created with Vivado 2021.2

  184. INFO: [Project 1-570] Preparing netlist for logic optimization

  185. INFO: [Timing 38-478] Restoring timing data from binary archive.

  186. INFO: [Timing 38-479] Binary timing data restore complete.

  187. INFO: [Project 1-856] Restoring constraints from binary archive.

  188. INFO: [Project 1-853] Binary constraint restore complete.

  189. Reading XDEF placement.

  190. Reading placer database...

  191. Reading XDEF routing.

  192. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 2253.348 ; gain = 0.000

  193. Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |

  194. Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 2253.348 ; gain = 0.000

  195. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2253.348 ; gain = 0.000

  196. INFO: [Project 1-111] Unisim Transformation Summary:

  197. No Unisim elements were transformed.

  198. 

  199. WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.

  200. open_hw_manager

  201. connect_hw_server -allow_non_jtag

  202. INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121

  203. INFO: [Labtools 27-2222] Launching hw_server...

  204. INFO: [Labtools 27-2221] Launch Output:

  205. 

  206. ****** Xilinx hw_server v2021.2

  207.   **** Build date : Oct 19 2021 at 03:13:30

  208.     ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

  209. 

  210. 

  211. INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042

  212. INFO: [Labtools 27-3417] Launching cs_server...

  213. INFO: [Labtools 27-2221] Launch Output:

  214. 

  215. 

  216. ******** Xilinx cs_server v2021.2.0

  217.   ****** Build date   : Sep 27 2021-23:44:20

  218.     **** Build number : 2021.2.1632779060

  219.       ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.

  220. 

  221. 

  222. 

  223. connect_hw_server: Time (s): cpu = 00:00:08 ; elapsed = 00:00:29 . Memory (MB): peak = 2403.906 ; gain = 14.949

  224. open_hw_target

  225. INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210370A9326CA

  226. open_hw_target: Time (s): cpu = 00:00:22 ; elapsed = 00:00:58 . Memory (MB): peak = 4174.812 ; gain = 1770.906

  227. set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]

  228. current_hw_device [get_hw_devices xc7z010_1]

  229. refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0]

  230. INFO: [Labtools 27-1435] Device xc7z010 (JTAG device index = 1) is not programmed (DONE status = 0).

  231. refresh_hw_device: Time (s): cpu = 00:00:06 ; elapsed = 00:00:19 . Memory (MB): peak = 4201.266 ; gain = 24.125

  232. set_property PROBES.FILE {} [get_hw_devices xc7z010_1]

  233. set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]

  234. set_property PROGRAM.FILE {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.bit} [get_hw_devices xc7z010_1]

  235. program_hw_devices [get_hw_devices xc7z010_1]

  236. INFO: [Labtools 27-3164] End of startup status: HIGH

  237. program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 4201.266 ; gain = 0.000

  238. refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]

  239. INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.

  240. refresh_hw_device: Time (s): cpu = 00:00:07 ; elapsed = 00:00:26 . Memory (MB): peak = 4201.598 ; gain = 0.332

  241. ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210370A9326CA

  242. close_sim

  243. INFO: [Simtcl 6-16] Simulation closed

  244. exit

  245. INFO: [Common 17-206] Exiting Vivado at Tue Mar 29 12:45:07 2022...