FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt/webtalk_pa.xml

<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Fri May 13 15:07:11 2022">
<section name="Project Information" visible="false">
<property name="ProjectID" value="7a8e7c8ef7e84daa83c28bbcb851b3c5" type="ProjectID"/>
<property name="ProjectIteration" value="7" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
</section>
</application>
</document>