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FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.vds

fixedPointTest.vds 19KB
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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Mon May 16 13:47:39 2022

  6. # Process ID: 13868

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1

  8. # Command line: vivado.exe -log fixedPointTest.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fixedPointTest.tcl

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.vds

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. source fixedPointTest.tcl -notrace

  14. create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.980 ; gain = 10.180

  15. Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp

  16. INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp for incremental synthesis

  17. INFO: [Vivado 12-7989] Please ensure there are no constraint changes

  18. Command: synth_design -top fixedPointTest -part xc7z010clg400-1

  19. Starting synth_design

  20. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'

  21. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'

  22. INFO: [Device 21-403] Loading part xc7z010clg400-1

  23. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  24. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  25. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.

  26. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes

  27. INFO: [Synth 8-7075] Helper process launched with PID 9900

  28. ---------------------------------------------------------------------------------

  29. Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.980 ; gain = 0.000

  30. ---------------------------------------------------------------------------------

  31. INFO: [Synth 8-638] synthesizing module 'fixedPointTest' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd:44]

  32. INFO: [Synth 8-256] done synthesizing module 'fixedPointTest' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd:44]

  33. ---------------------------------------------------------------------------------

  34. Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.980 ; gain = 0.000

  35. ---------------------------------------------------------------------------------

  36. ---------------------------------------------------------------------------------

  37. Start Handling Custom Attributes

  38. ---------------------------------------------------------------------------------

  39. ---------------------------------------------------------------------------------

  40. Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.980 ; gain = 0.000

  41. ---------------------------------------------------------------------------------

  42. ---------------------------------------------------------------------------------

  43. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.980 ; gain = 0.000

  44. ---------------------------------------------------------------------------------

  45. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.980 ; gain = 0.000

  46. INFO: [Project 1-570] Preparing netlist for logic optimization

  47. 

  48. Processing XDC Constraints

  49. Initializing timing engine

  50. Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  51. WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]

  52. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]

  53. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

  54. Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  55. Completed Processing XDC Constraints

  56. 

  57. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.980 ; gain = 0.000

  58. INFO: [Project 1-111] Unisim Transformation Summary:

  59. No Unisim elements were transformed.

  60. 

  61. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1261.980 ; gain = 0.000

  62. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  63. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  64. ---------------------------------------------------------------------------------

  65. Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.980 ; gain = 0.000

  66. ---------------------------------------------------------------------------------

  67. ---------------------------------------------------------------------------------

  68. Start Loading Part and Timing Information

  69. ---------------------------------------------------------------------------------

  70. Loading part: xc7z010clg400-1

  71. ---------------------------------------------------------------------------------

  72. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.980 ; gain = 0.000

  73. ---------------------------------------------------------------------------------

  74. ---------------------------------------------------------------------------------

  75. Start Applying 'set_property' XDC Constraints

  76. ---------------------------------------------------------------------------------

  77. ---------------------------------------------------------------------------------

  78. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.980 ; gain = 0.000

  79. ---------------------------------------------------------------------------------

  80. ---------------------------------------------------------------------------------

  81. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.980 ; gain = 0.000

  82. ---------------------------------------------------------------------------------

  83. ---------------------------------------------------------------------------------

  84. Start RTL Component Statistics 

  85. ---------------------------------------------------------------------------------

  86. Detailed RTL Component Info : 

  87. ---------------------------------------------------------------------------------

  88. Finished RTL Component Statistics 

  89. ---------------------------------------------------------------------------------

  90. ---------------------------------------------------------------------------------

  91. Start Part Resource Summary

  92. ---------------------------------------------------------------------------------

  93. Part Resources:

  94. DSPs: 80 (col length:40)

  95. BRAMs: 120 (col length: RAMB18 40 RAMB36 20)

  96. ---------------------------------------------------------------------------------

  97. Finished Part Resource Summary

  98. ---------------------------------------------------------------------------------

  99. ---------------------------------------------------------------------------------

  100. Start Cross Boundary and Area Optimization

  101. ---------------------------------------------------------------------------------

  102. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met

  103. DSP Report: Generating DSP arg, operation Mode is: A*B.

  104. DSP Report: operator arg is absorbed into DSP arg.

  105. ---------------------------------------------------------------------------------

  106. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1261.980 ; gain = 0.000

  107. ---------------------------------------------------------------------------------

  108. ---------------------------------------------------------------------------------

  109. Start ROM, RAM, DSP, Shift Register and Retiming Reporting

  110. ---------------------------------------------------------------------------------

  111. 

  112. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)

  113. +---------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  114. |Module Name    | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 

  115. +---------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  116. |fixedPointTest | A*B         | 14     | 14     | -      | -      | 28     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  117. +---------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  118. 

  119. Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.

  120. ---------------------------------------------------------------------------------

  121. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting

  122. ---------------------------------------------------------------------------------

  123. ---------------------------------------------------------------------------------

  124. Start Applying XDC Timing Constraints

  125. ---------------------------------------------------------------------------------

  126. ---------------------------------------------------------------------------------

  127. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 1277.898 ; gain = 15.918

  128. ---------------------------------------------------------------------------------

  129. ---------------------------------------------------------------------------------

  130. Start Timing Optimization

  131. ---------------------------------------------------------------------------------

  132. ---------------------------------------------------------------------------------

  133. Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 1277.898 ; gain = 15.918

  134. ---------------------------------------------------------------------------------

  135. ---------------------------------------------------------------------------------

  136. Start Technology Mapping

  137. ---------------------------------------------------------------------------------

  138. ---------------------------------------------------------------------------------

  139. Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 1297.012 ; gain = 35.031

  140. ---------------------------------------------------------------------------------

  141. ---------------------------------------------------------------------------------

  142. Start IO Insertion

  143. ---------------------------------------------------------------------------------

  144. ---------------------------------------------------------------------------------

  145. Start Flattening Before IO Insertion

  146. ---------------------------------------------------------------------------------

  147. ---------------------------------------------------------------------------------

  148. Finished Flattening Before IO Insertion

  149. ---------------------------------------------------------------------------------

  150. ---------------------------------------------------------------------------------

  151. Start Final Netlist Cleanup

  152. ---------------------------------------------------------------------------------

  153. ---------------------------------------------------------------------------------

  154. Finished Final Netlist Cleanup

  155. ---------------------------------------------------------------------------------

  156. ---------------------------------------------------------------------------------

  157. Finished IO Insertion : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  158. ---------------------------------------------------------------------------------

  159. ---------------------------------------------------------------------------------

  160. Start Renaming Generated Instances

  161. ---------------------------------------------------------------------------------

  162. ---------------------------------------------------------------------------------

  163. Finished Renaming Generated Instances : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  164. ---------------------------------------------------------------------------------

  165. ---------------------------------------------------------------------------------

  166. Start Rebuilding User Hierarchy

  167. ---------------------------------------------------------------------------------

  168. ---------------------------------------------------------------------------------

  169. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  170. ---------------------------------------------------------------------------------

  171. ---------------------------------------------------------------------------------

  172. Start Renaming Generated Ports

  173. ---------------------------------------------------------------------------------

  174. ---------------------------------------------------------------------------------

  175. Finished Renaming Generated Ports : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  176. ---------------------------------------------------------------------------------

  177. ---------------------------------------------------------------------------------

  178. Start Handling Custom Attributes

  179. ---------------------------------------------------------------------------------

  180. ---------------------------------------------------------------------------------

  181. Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  182. ---------------------------------------------------------------------------------

  183. ---------------------------------------------------------------------------------

  184. Start Renaming Generated Nets

  185. ---------------------------------------------------------------------------------

  186. ---------------------------------------------------------------------------------

  187. Finished Renaming Generated Nets : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  188. ---------------------------------------------------------------------------------

  189. ---------------------------------------------------------------------------------

  190. Start Writing Synthesis Report

  191. ---------------------------------------------------------------------------------

  192. 

  193. Report BlackBoxes: 

  194. +-+--------------+----------+

  195. | |BlackBox name |Instances |

  196. +-+--------------+----------+

  197. +-+--------------+----------+

  198. 

  199. Report Cell Usage: 

  200. +------+--------+------+

  201. |      |Cell    |Count |

  202. +------+--------+------+

  203. |1     |DSP48E1 |     1|

  204. |2     |IBUF    |    28|

  205. |3     |OBUF    |    28|

  206. +------+--------+------+

  207. ---------------------------------------------------------------------------------

  208. Finished Writing Synthesis Report : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  209. ---------------------------------------------------------------------------------

  210. Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.

  211. Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1303.738 ; gain = 41.758

  212. Synthesis Optimization Complete : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 1303.738 ; gain = 41.758

  213. INFO: [Project 1-571] Translating synthesized netlist

  214. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1315.801 ; gain = 0.000

  215. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement

  216. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  217. INFO: [Project 1-570] Preparing netlist for logic optimization

  218. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  219. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.461 ; gain = 0.000

  220. INFO: [Project 1-111] Unisim Transformation Summary:

  221. No Unisim elements were transformed.

  222. 

  223. Synth Design complete, checksum: acd46f8c

  224. INFO: [Common 17-83] Releasing license: Synthesis

  225. 20 Infos, 4 Warnings, 1 Critical Warnings and 0 Errors encountered.

  226. synth_design completed successfully

  227. synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 1322.461 ; gain = 60.480

  228. INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING

  229. INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.dcp' has been generated.

  230. INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_synth.rpt -pb fixedPointTest_utilization_synth.pb

  231. INFO: [Common 17-206] Exiting Vivado at Mon May 16 13:48:36 2022...