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- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
- -----------------------------------------------------------------------------------------------------------------------
- | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
- | Date : Mon May 16 13:48:36 2022
- | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
- | Command : report_utilization -file fixedPointTest_utilization_synth.rpt -pb fixedPointTest_utilization_synth.pb
- | Design : fixedPointTest
- | Device : xc7z010clg400-1
- | Speed File : -1
- | Design State : Synthesized
- -----------------------------------------------------------------------------------------------------------------------
-
- Utilization Design Information
-
- Table of Contents
- -----------------
- 1. Slice Logic
- 1.1 Summary of Registers by Type
- 2. Memory
- 3. DSP
- 4. IO and GT Specific
- 5. Clocking
- 6. Specific Feature
- 7. Primitives
- 8. Black Boxes
- 9. Instantiated Netlists
-
- 1. Slice Logic
- --------------
-
- +-------------------------+------+-------+------------+-----------+-------+
- | Site Type | Used | Fixed | Prohibited | Available | Util% |
- +-------------------------+------+-------+------------+-----------+-------+
- | Slice LUTs* | 0 | 0 | 0 | 17600 | 0.00 |
- | LUT as Logic | 0 | 0 | 0 | 17600 | 0.00 |
- | LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
- | Slice Registers | 0 | 0 | 0 | 35200 | 0.00 |
- | Register as Flip Flop | 0 | 0 | 0 | 35200 | 0.00 |
- | Register as Latch | 0 | 0 | 0 | 35200 | 0.00 |
- | F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
- | F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
- +-------------------------+------+-------+------------+-----------+-------+
- * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
-
-
- 1.1 Summary of Registers by Type
- --------------------------------
-
- +-------+--------------+-------------+--------------+
- | Total | Clock Enable | Synchronous | Asynchronous |
- +-------+--------------+-------------+--------------+
- | 0 | _ | - | - |
- | 0 | _ | - | Set |
- | 0 | _ | - | Reset |
- | 0 | _ | Set | - |
- | 0 | _ | Reset | - |
- | 0 | Yes | - | - |
- | 0 | Yes | - | Set |
- | 0 | Yes | - | Reset |
- | 0 | Yes | Set | - |
- | 0 | Yes | Reset | - |
- +-------+--------------+-------------+--------------+
-
-
- 2. Memory
- ---------
-
- +----------------+------+-------+------------+-----------+-------+
- | Site Type | Used | Fixed | Prohibited | Available | Util% |
- +----------------+------+-------+------------+-----------+-------+
- | Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 |
- | RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
- | RAMB18 | 0 | 0 | 0 | 120 | 0.00 |
- +----------------+------+-------+------------+-----------+-------+
- * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
- 3. DSP
- ------
-
- +----------------+------+-------+------------+-----------+-------+
- | Site Type | Used | Fixed | Prohibited | Available | Util% |
- +----------------+------+-------+------------+-----------+-------+
- | DSPs | 1 | 0 | 0 | 80 | 1.25 |
- | DSP48E1 only | 1 | | | | |
- +----------------+------+-------+------------+-----------+-------+
-
-
- 4. IO and GT Specific
- ---------------------
-
- +-----------------------------+------+-------+------------+-----------+-------+
- | Site Type | Used | Fixed | Prohibited | Available | Util% |
- +-----------------------------+------+-------+------------+-----------+-------+
- | Bonded IOB | 56 | 0 | 0 | 100 | 56.00 |
- | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
- | Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
- | PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
- | PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
- | OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
- | IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
- | IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
- | IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
- | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
- | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
- | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
- | ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
- | OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
- +-----------------------------+------+-------+------------+-----------+-------+
-
-
- 5. Clocking
- -----------
-
- +------------+------+-------+------------+-----------+-------+
- | Site Type | Used | Fixed | Prohibited | Available | Util% |
- +------------+------+-------+------------+-----------+-------+
- | BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
- | BUFIO | 0 | 0 | 0 | 8 | 0.00 |
- | MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
- | PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
- | BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
- | BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
- | BUFR | 0 | 0 | 0 | 8 | 0.00 |
- +------------+------+-------+------------+-----------+-------+
-
-
- 6. Specific Feature
- -------------------
-
- +-------------+------+-------+------------+-----------+-------+
- | Site Type | Used | Fixed | Prohibited | Available | Util% |
- +-------------+------+-------+------------+-----------+-------+
- | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
- | CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
- | DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
- | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
- | FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
- | ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
- | STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
- | XADC | 0 | 0 | 0 | 1 | 0.00 |
- +-------------+------+-------+------------+-----------+-------+
-
-
- 7. Primitives
- -------------
-
- +----------+------+---------------------+
- | Ref Name | Used | Functional Category |
- +----------+------+---------------------+
- | OBUF | 28 | IO |
- | IBUF | 28 | IO |
- | DSP48E1 | 1 | Block Arithmetic |
- +----------+------+---------------------+
-
-
- 8. Black Boxes
- --------------
-
- +----------+------+
- | Ref Name | Used |
- +----------+------+
-
-
- 9. Instantiated Netlists
- ------------------------
-
- +----------+------+
- | Ref Name | Used |
- +----------+------+
-
|